Millimeter wave antenna with novel interface and application device design

Abstract

The millimeter wave antenna and application device design comprises a millimeter wave antenna, the millimeter wave antenna is provided with an espi-to-AXI interface, conversion between the espi interface and the AXI interface is achieved through an antenna internal programmable logic, direct access of a CPU to antenna internal logic register is achieved, and therefore the antenna is directly controlled to work, the antenna state is obtained, and the service life of the antenna is prolonged. The programmable logic is divided into SOC internal FPGA logic and antenna internal logic, and the SOC internal FPGA logic and the antenna internal logic respectively correspond to the SOC internal programmable logic implementation module and the antenna internal programmable logic implementation module. The method has the advantages that the CPU is supported to directly access a hardware register in the antenna, the packaging and de-packaging software overhead of a software protocol layer is removed, and the efficiency of controlling the antenna by the software is greatly improved. When an antenna fault occurs, a hardware state register in the antenna can be directly and quickly read, and the problem positioning efficiency is improved. The antenna control message is removed, and the software development workload is reduced.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a millimeter wave antenna with a novel interface and an application device design, which can be widely used in embedded products. Background Art

[0002] In millimeter-wave terminal equipment, the millimeter-wave antenna is the main module of the RF hardware. Its main function is to receive and send RF signals, realize beamforming, power control management and other functions. At this stage, millimeter-wave antennas are cutting-edge research. The development and verification of antenna functions and the development of antenna control algorithms require the cooperation of millimeter-wave equipment manufacturers and antenna manufacturers in terms of hardware and software. Currently, millimeter-wave antenna manufacturers generally use custom protocol messages for antenna message communication. This means that when millimeter-wave equipment manufacturers use antennas from different manufacturers, their software needs to be developed based on the control protocol messages of the antenna manufacturer. Its disadvantages:

[0003] First, the equipment manufacturer's software development manpower needs to be increased to adapt to antenna message protocols from multiple manufacturers, and protocol message processing efficiency is low;

[0004] Second, when manufacturers modify communication protocol messages, the terminal manufacturer's software also needs to be modified accordingly, which reduces development efficiency;

[0005] Third, when errors occur in antenna message interaction, it is difficult to locate millimeter wave antenna problems.

[0006] The present invention proposes a new millimeter wave antenna design, which eliminates antenna message packets through espi to axi interface design, and allows the device terminal to directly access the registers of the antenna internal hardware like accessing an internal module.

[0007] The present invention also proposes a terminal application design for this new interface antenna, aiming to provide a standard, unified millimeter-wave antenna terminal application design, improve R&D efficiency, and reduce software development costs. Summary of the Invention

[0008] (1) Technical problems solved

[0009] In response to the shortcomings of the existing technology, the present invention provides a millimeter wave antenna and application device design with a new interface, and provides a standard, unified millimeter wave antenna terminal application design, which improves R&D efficiency, reduces software development costs, and solves the current problems of low protocol message processing efficiency, low development efficiency, and difficulty in locating millimeter wave antenna problems when antenna message interaction errors occur.

[0010] (2) Technical solution

[0011] To achieve the above-mentioned purpose of providing a standard, unified millimeter wave antenna terminal application design, improving R&D efficiency, and reducing software development costs, the present invention provides the following technical solution: including a millimeter wave antenna, wherein the millimeter wave antenna has an ESP100 to AXI interface, which realizes the conversion between the ESP100 and AXI interfaces through the programmable logic inside the antenna, and enables the CPU to directly access the internal logic registers of the antenna, thereby directly controlling the antenna operation and obtaining the antenna status;

[0012] The programmable logic is divided into SOC internal FPGA logic and antenna internal logic. The SOC internal FPGA logic and the antenna internal logic correspond to the SOC internal programmable logic implementation module and the antenna internal programmable logic implementation module respectively. The SOC internal programmable logic implementation module includes: AXI interface module, AXI message and ESPI message conversion module, address window mapping module, ESPI bus interface module, and the antenna internal programmable logic implementation module includes: EPSI interface, AXI message and ESPI message conversion module, and antenna AXI bus interface module.

[0013] Preferably, the AXI interface module: AXI protocol processing, sending direction, parsing AXI bus messages, obtaining instruction operation type, operation address, and data information; receiving side, converting AXI operation data into AXI signals.

[0014] Preferably, the AXI message and EPSI message conversion module converts the AXI operation data into the ESPI message data after sending, and converts the ESPI message into the AXI operation data after receiving.

[0015] Preferably, the address window mapping module completes the window mapping of the FPGA logic physical address inside the SOC and the physical address of the antenna internal register, completes the FPGA physical legitimacy check, and converts the FPGA physical address into the antenna internal logical address.

[0016] Preferably, the ESPI bus interface module data: in the sending direction, completes the conversion of ESPI message data into ESPI electrical signals; in the receiving direction, completes the conversion of ESPI electrical signals into message data.

[0017] Preferably, the antenna control process is as follows:

[0018] 1. SOC interface workflow:

[0019] 1) Initialize the antenna interface and configure the mapping relationship between the SOC internal address window and the antenna internal hardware address window. Multiple mappings can be configured.

[0020] 2) The CPU sends an instruction to access the antenna's internal hardware address through the AXI interface;

[0021] 3) The AXI bus interface module parses the AXI bus message and obtains the AXI operation type, read or write, operation address, and operation data;

[0022] 4) The AXI bus interface sends the operation address to the address window mapping module;

[0023] 5) The address window mapping module checks whether the address belongs to the configured address mapping window and returns the corresponding mapping address;

[0024] 6) The AXI bus interface module sends the mapped address, operation type, and operand to the AXI and ESPI message conversion module;

[0025] 7) AXI message and ESPI conversion module converts the corresponding AXI operation into ESPI message, and sends the data to the ESPI bus interface after the conversion is completed;

[0026] 8) The ESPI bus interface converts the data message data into ESPI electrical signals;

[0027] Antenna FPGA logic workflow:

[0028] 1) The ESPI main interface converts the electrical signal into ESPI message data and transmits the data to the AXI message and ESPI message conversion module;

[0029] 2) The AXI message and ESPI message conversion module parses the ESPI message to obtain the operation type, operation address, and operation data in the protocol;

[0030] 3) The AXI message and ESPI message conversion module converts the acquired operation data into an AXI bus message, and sends the AXI bus message to the antenna internal hardware module via the AXI bus;

[0031] 4) The hardware module inside the antenna performs the corresponding operation. If it is writing data, the data is written to the corresponding address; if it is reading data, the corresponding address data is returned.

[0032] A method for antenna application. The antenna application system device of the present invention includes components such as a CPU, a system-on-chip (SOC) FPGA programmable logic, antenna internal programmable logic, and antenna internal logic hardware. The SOC internal FPGA implementation module includes: an AXI interface module, an AXI message and ESPI message conversion module, an address window mapping module, and an ESPI bus interface module. The antenna internal programmable logic implementation module includes: an EPSI interface module, an AXI message and ESPI message conversion module, and an antenna internal AXI bus module. The specific working method is as follows:

[0033] 1) The CPU completes the initialization of the antenna interface path, mainly completing the mapping of the FPGA physical address window and the antenna internal physical address window. The way to configure a mapping window is to use the FPGA physical starting address fpga_addr, the antenna internal starting physical address ant_addr, and the mapping window size size. Multiple window mappings can be configured;

[0034] 2) AXI interface module. When the CPU sends an access operation, the AXI interface module parses the AXI bus message and obtains the AXI operation parameters, including the AXI operation type (read or write), the operation address, and the operation data. The address obtained by this module is the physical address of the FPGA in the SOC. Then, the obtained AXI operation parameters are sent to the next level module and wait for the result of this operation. If the result of this operation is successful, the AXI interface module responds successfully to the AXI bus, otherwise the response fails.

[0035] 3) Implementation of AXI message and ESPI message conversion module, sending direction: this module sends the obtained FPGA operation address to the address window mapping module, starts the address mapping query conversion, and waits for the operation result. If the operation fails, the corresponding error information is recorded and the operation failure is returned to the AXI interface. If the operation is successful, the converted internal physical address of the antenna is obtained. The module converts the operation type, converted address, and operation data into an ESPI protocol message, sends the message to the next module, and waits for the operation result. If the operation fails, the failure information is recorded and a failure flag is returned to the AXI interface. If the operation is successful, if the operation is a write operation, a success flag is returned to the AXI interface; if the operation is a read operation, the readback data and the success flag are returned at the same time. Receiving direction: Receive ESPI interface message data, judge the legitimacy of the ESPI message, parse the ESPI message, obtain EPSI operation parameters, including operation type, operation address, and operation data, convert the ESPI operation parameters into AXI operation parameters, and send the AXI operation to the AXI interface module;

[0036] 4). Implementation of the address window mapping module, which internally includes a register array for address window mapping, an address query module, and a status recording module. One register data contains three 64-bit elements, respectively recording the starting physical address fpga_addr of the FPGA within this window, the starting address ant_addr of the antenna, and the address size size. Multiple register data can record multiple segments of address mapping windows. The address query module sequentially retrieves the register data and queries whether the input address belongs to the address mapping window of this segment. The query method is as follows: when the condition fapg_addr <= <addr && addr < fapg_addr + size is satisfied, it belongs to this segment. The method for calculating the converted address is: offset = addr - fpga_addr, new_addr = ant_addr + offset. After querying and completing the address conversion, the converted address and a success flag are returned. When the query for this segment fails, other configured address window mapping segments are sequentially queried; if all queries fail, the failure information is recorded and a conversion failure flag is returned.

[0037] 5). Implementation of the ESPI interface module. In the transmission direction: receive the ESPI message data from the upper-level module and convert the data into ESPI electrical signals. In the reception direction: convert the received ESPI electrical signals into data and send the data to the lower-level module.

[0038] 6). The internal hardware module of the antenna: controls the operation of the antenna, records the working status, and when receiving an AXI write operation, writes the operation data into the corresponding physical address register; when receiving a read operation, retrieves the data from the corresponding address register.

[0039] (III) Beneficial effects

[0040] Compared with the prior art, the present invention provides a design of a millimeter-wave antenna and an application device with a new interface, having the following beneficial effects:

[0041] 1. For the design of the millimeter-wave antenna and the application device with this new interface, the advantage of the present invention is that it supports the CPU to directly access the internal hardware registers of the antenna, eliminates the software overhead of encapsulation and de-encapsulation in the software protocol layer, and greatly improves the efficiency of software control of the antenna. When an antenna failure occurs, the internal hardware status register of the antenna can be directly and quickly read, improving the efficiency of problem location. Removing the antenna control message reduces the software development workload.

[0042] 2. Design a millimeter-wave antenna with a new interface, support external direct access to the internal hardware of the antenna through the espi bus, replace the message communication method, reduce the software development cost and enhance the antenna problem location ability; propose a design of an application device with a new interface antenna; propose a millimeter-wave antenna interface standard that can be promoted. Brief description of the drawings

[0043] Figure 1 This is a diagram of the overall architecture of the present invention;

[0044] Figure 2 This is a schematic diagram of the workflow of the AXI message and ESPI message conversion module of the present invention;

[0045] Figure 3 This is a flowchart of the address mapping unit of the present invention;

[0046] Figure 4 Schematic diagram of the working process of the antenna operation method of the present invention. DETAILED DESCRIPTION

[0047] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0048] See also Figure 1-4 A millimeter wave antenna and application device with a new interface is designed, including a millimeter wave antenna. The millimeter wave antenna has an espi to axi interface, which realizes the conversion between the espi and axi interfaces through the programmable logic inside the antenna, and enables the CPU to directly access the internal logic registers of the antenna, thereby directly controlling the antenna operation and obtaining the antenna status;

[0049] The programmable logic is divided into the FPGA logic inside the SOC and the logic inside the antenna. The FPGA logic inside the SOC and the logic inside the antenna correspond to the programmable logic implementation module inside the SOC and the programmable logic implementation module inside the antenna respectively. The programmable logic implementation module inside the SOC includes: AXI interface module, AXI message and ESPI message conversion module, address window mapping module, and ESPI bus interface module. The programmable logic implementation module inside the antenna includes: EPSI interface, AXI message and ESPI message conversion module, and antenna AXI bus interface module.

[0050] Example 1: AXI interface module: AXI protocol processing, sending direction, parsing AXI bus messages, obtaining instruction operation type, operation address, and data information; receiving side, converting AXI operation data into AXI signals.

[0051] Embodiment 2: AXI message and EPSI message conversion module: converts the sending AXI operation data into ESPI message data, and converts the receiving ESPI message into AXI operation data.

[0052] Embodiment 3: Address window mapping module: completes the window mapping between the SOC internal FPGA logic physical address and the antenna internal register physical address, completes the FPGA physical legality check, and converts the FPGA physical address into the antenna internal logical address.

[0053] Embodiment 4: ESPI bus interface module data: In the sending direction, ESPI message data is converted into ESPI electrical signals, and in the receiving direction, ESPI electrical signals are converted into message data.

[0054] Example 5: The antenna control process is as follows:

[0055] 1. SOC interface workflow:

[0056] 1) Initialize the antenna interface and configure the mapping relationship between the SOC internal address window and the antenna internal hardware address window. Multiple mappings can be configured.

[0057] 2) The CPU sends an instruction to access the antenna's internal hardware address through the AXI interface;

[0058] 3) The AXI bus interface module parses the AXI bus message and obtains the AXI operation type, read or write, operation address, and operation data;

[0059] 4) The AXI bus interface sends the operation address to the address window mapping module;

[0060] 5) The address window mapping module checks whether the address belongs to the configured address mapping window and returns the corresponding mapping address;

[0061] 6) The AXI bus interface module sends the mapped address, operation type, and operand to the AXI and ESPI message conversion module;

[0062] 7) AXI message and ESPI conversion module converts the corresponding AXI operation into ESPI message, and sends the data to the ESPI bus interface after the conversion is completed;

[0063] 8) The ESPI bus interface converts the data message data into ESPI electrical signals;

[0064] Antenna FPGA logic workflow:

[0065] 1) The ESPI main interface converts the electrical signal into ESPI message data and transmits the data to the AXI message and ESPI message conversion module;

[0066] 2) The AXI message and ESPI message conversion module parses the ESPI message to obtain the operation type, operation address, and operation data in the protocol;

[0067] 3) The AXI message and ESPI message conversion module converts the acquired operation data into an AXI bus message, and sends the AXI bus message to the antenna internal hardware module via the AXI bus;

[0068] 4) The hardware module inside the antenna performs the corresponding operation. If it is writing data, the data is written to the corresponding address; if it is reading data, the corresponding address data is returned.

[0069] Example 6: A method for antenna application. The antenna application system device of the present invention includes components such as a CPU, a SOC FPGA programmable logic, an antenna internal programmable logic, and antenna internal logic hardware. The SOC internal FPGA implementation module includes: an AXI interface module, an AXI message and ESPI message conversion module, an address window mapping module, and an ESPI bus interface module. The antenna internal programmable logic implementation module includes: an EPSI interface module, an AXI message and ESPI message conversion module, and an antenna internal AXI bus module. The specific working method is as follows:

[0070] 1) The CPU completes the initialization of the antenna interface path, mainly completing the mapping of the FPGA physical address window and the antenna internal physical address window. The way to configure a mapping window is to use the FPGA physical starting address fpga_addr, the antenna internal starting physical address ant_addr, and the mapping window size size. Multiple window mappings can be configured;

[0071] 2) AXI interface module. When the CPU sends an access operation, the AXI interface module parses the AXI bus message and obtains the AXI operation parameters, including the AXI operation type (read or write), the operation address, and the operation data. The address obtained by this module is the physical address of the FPGA in the SOC. Then, the obtained AXI operation parameters are sent to the next level module and wait for the result of this operation. If the result of this operation is successful, the AXI interface module responds successfully to the AXI bus, otherwise the response fails.

[0072] 3) Implementation of the AXI message and ESPI message conversion module. Sending direction: This module sends the obtained FPGA operation address to the address window mapping module, initiates address mapping query conversion, and waits for the operation result. If the operation fails, record the corresponding error information and return the failure of this operation to the AXI interface. If the operation is successful, obtain the converted internal physical address of the antenna. The module converts the operation type, the converted address, and the operation data into an ESPI protocol message, sends the message to the next module, and waits for the operation result. If the operation result fails, record the failure information and return the failure flag to the AXI interface. If the operation is successful, if this operation is a write operation, return the success flag to the AXI interface; if this operation is a read operation, return the read-back data and the success flag simultaneously. Receiving direction: Receive the ESPI interface message data, perform a legality check on the ESPI message, parse the ESPI message, obtain the EPSI operation parameters, including the operation type, operation address, and operation data, convert the ESPI operation parameters into AXI operation parameters, and send the AXI operation to the AXI interface module;

[0073] 4) Implementation of the address window mapping module. It internally includes a register array for address window mapping, an address query, and a status recording module. One register data contains 3 64-bit elements, which respectively record the FPGA start physical address fpga_addr, the antenna start address ant_addr, and the address size size within this window. Multiple register data can record multiple address mapping windows. The address query module sequentially searches for the register data and checks whether the input address belongs to the address mapping window of this segment. Query method: When the condition fapg_addr <= <addr && addr < fapg_addr + size is satisfied, it belongs to this segment. Method for calculating the converted address: offset = addr – fpga_addr, new_addr = ant_addr + offset. After querying and completing the address conversion, return the converted address and the success flag. When the query of this segment fails, sequentially query other configured address window mapping segments; if all queries fail, record the failure information and return the conversion failure flag;

[0074] 5) Implementation of the ESPI interface module. Sending direction: Receive the ESPI message data from the upper-level module and convert the data into an ESPI electrical signal. Receiving direction: Convert the received ESPI electrical signal into data and send the data to the lower-level module;

[0075] 6) Antenna internal hardware module: Controls the antenna operation and records the working status. When receiving an AXI write operation, write the operation data into the corresponding physical address register; when receiving a read operation, retrieve the data from the corresponding address register.

[0076] In summary, the advantages of this novel millimeter-wave antenna and device design include enabling direct CPU access to the antenna's internal hardware registers, eliminating the encapsulation and decapsulation software overhead of the software protocol layer, and significantly improving the efficiency of software-controlled antennas. When an antenna fault occurs, the antenna's internal hardware status registers can be directly and quickly read, improving problem location efficiency. Antenna control messages are eliminated, reducing software development workload. Direct external access to the antenna's internal hardware via the ESP100 bus replaces message communication, reducing software development costs and enhancing antenna problem location capabilities. A device design utilizing the novel interface antenna is proposed, along with a generalizable millimeter-wave antenna interface standard.

[0077] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0078] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A millimeter wave antenna and application device design with a new interface, characterized in that: The millimeter wave antenna includes an espi to axi interface, which realizes the conversion between the espi and axi interfaces through the programmable logic inside the antenna, and enables the CPU to directly access the internal logic registers of the antenna, thereby directly controlling the antenna operation and obtaining the antenna status; The programmable logic is divided into SOC internal FPGA logic and antenna internal logic. The SOC internal FPGA logic and the antenna internal logic correspond to the SOC internal programmable logic implementation module and the antenna internal programmable logic implementation module respectively. The SOC internal programmable logic implementation module includes: AXI interface module, AXI message and ESPI message conversion module, address window mapping module, ESPI bus interface module, and the antenna internal programmable logic implementation module includes: EPSI interface, AXI message and ESPI message conversion module, and antenna AXI bus interface module.

2. The millimeter wave antenna and application device design of a novel interface according to claim 1 is characterized by: The AXI interface module: AXI protocol processing, sending direction, parsing AXI bus messages, obtaining instruction operation type, operation address, and data information; receiving side, converting AXI operation data into AXI signals.

3. The millimeter wave antenna and application device design of a novel interface according to claim 1 is characterized by: The AXI message and EPSI message conversion module converts AXI operation data into ESPI message data after sending, and converts ESPI message into AXI operation data after receiving.

4. The millimeter wave antenna and application device design of a novel interface according to claim 1 is characterized by: The address window mapping module completes the mapping between the FPGA logic physical address inside the SOC and the physical address window of the antenna internal register, completes the FPGA physical legality check, and converts the FPGA physical address into the antenna internal logical address.

5. The millimeter wave antenna and application device design of a novel interface according to claim 1 is characterized by: The ESPI bus interface module data: in the sending direction, the ESPI message data is converted into an ESPI electrical signal; in the receiving direction, the ESPI electrical signal is converted into message data.

6. The millimeter wave antenna and application device design of a novel interface according to claim 1 is characterized by: The antenna control process is as follows:

1. SOC interface workflow: 1) Initialize the antenna interface and configure the mapping relationship between the SOC internal address window and the antenna internal hardware address window. Multiple mappings can be configured. 2) The CPU sends an instruction to access the antenna's internal hardware address through the AXI interface; 3) The AXI bus interface module parses the AXI bus message and obtains the AXI operation type, read or write, operation address, and operation data; 4) The AXI bus interface sends the operation address to the address window mapping module; 5) The address window mapping module checks whether the address belongs to the configured address mapping window and returns the corresponding mapping address; 6) The AXI bus interface module sends the mapped address, operation type, and operand to the AXI and ESPI message conversion module; 7) AXI message and ESPI conversion module converts the corresponding AXI operation into ESPI message, and sends the data to the ESPI bus interface after the conversion is completed; 8) The ESPI bus interface converts the data message data into ESPI electrical signals; Antenna FPGA logic workflow: 1) The ESPI main interface converts the electrical signal into ESPI message data and transmits the data to the AXI message and ESPI message conversion module; 2) The AXI message and ESPI message conversion module parses the ESPI message to obtain the operation type, operation address, and operation data in the protocol; 3) The AXI message and ESPI message conversion module converts the acquired operation data into an AXI bus message, and sends the AXI bus message to the antenna internal hardware module via the AXI bus; 4) The hardware module inside the antenna performs the corresponding operation. If it is writing data, it writes the data to the corresponding address; If it is reading data, the corresponding address data is returned.

7. A method for antenna application, characterized in that: The antenna application system device of the present invention includes components such as a CPU, a SOC FPGA programmable logic, an antenna internal programmable logic, and antenna internal logic hardware. The SOC internal FPGA implementation module includes: an AXI interface module, an AXI message and ESPI message conversion module, an address window mapping module, and an ESPI bus interface module. The antenna internal programmable logic implementation module includes: an EPSI interface module, an AXI message and ESPI message conversion module, and an antenna internal AXI bus module. The specific working method is as follows: 1) The CPU completes the initialization of the antenna interface path, mainly completing the mapping of the FPGA physical address window and the antenna internal physical address window. The way to configure a mapping window is to use the FPGA physical starting address fpga_addr, the antenna internal starting physical address ant_addr, and the mapping window size size. Multiple window mappings can be configured; 2) AXI interface module. When the CPU sends an access operation, the AXI interface module parses the AXI bus message and obtains the AXI operation parameters, including the AXI operation type (read or write), the operation address, and the operation data. The address obtained by this module is the physical address of the FPGA in the SOC. Then, the obtained AXI operation parameters are sent to the next level module and wait for the result of this operation. If the result of this operation is successful, the AXI interface module responds successfully to the AXI bus, otherwise the response fails. 3) Implementation of AXI message and ESPI message conversion module, sending direction: this module sends the obtained FPGA operation address to the address window mapping module, starts the address mapping query conversion, and waits for the operation result. If the operation fails, the corresponding error information is recorded and the operation failure is returned to the AXI interface. If the operation is successful, the converted internal physical address of the antenna is obtained. The module converts the operation type, converted address, and operation data into an ESPI protocol message, sends the message to the next module, and waits for the operation result. If the operation fails, the failure information is recorded and a failure flag is returned to the AXI interface. If the operation is successful, if the operation is a write operation, a success flag is returned to the AXI interface; if the operation is a read operation, the readback data and the success flag are returned at the same time. Receiving direction: Receive ESPI interface message data, judge the legitimacy of the ESPI message, parse the ESPI message, obtain EPSI operation parameters, including operation type, operation address, and operation data, convert the ESPI operation parameters into AXI operation parameters, and send the AXI operation to the AXI interface module; 4) Implementation of the address window mapping module, which internally includes a register array for address window mapping, an address query module, and a status recording module. One register data contains 3 64-bit elements, which respectively record the starting physical address fpga_addr of the FPGA within this window, the starting address ant_addr of the antenna, and the address size size. Multiple register data can record multiple address mapping windows. The address query module sequentially searches for register data to check whether the input address belongs to the address mapping window of this segment. The query method is as follows: when the condition fapg_addr <= <addr && addr < fapg_addr + size is satisfied, it belongs to this segment. The method for calculating the converted address is: offset = addr – fpga_addr, new_addr = ant_addr + offset. After querying and completing the address conversion, the converted address and a success flag are returned. When the query for this segment fails, other configured address window mapping segments are sequentially queried; if all queries fail, the failure information is recorded and a conversion failure flag is returned; 5) Implementation of the ESPI interface module. In the transmission direction: receive the ESPI message data from the upper-level module and convert the data into an ESPI electrical signal. In the reception direction: convert the received ESPI electrical signal into data and send the data to the lower-level module; 6) Antenna internal hardware module: control the operation of the antenna, record the working status, and when an AXI write operation is received, write the operation data into the corresponding physical address register; when a read operation is received, retrieve the data from the corresponding address register.

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