Design rule detection and model training method and device, and electronic device

Abstract

The application provides a design rule detection and model training method and device and electronic equipment, comprising: constructing an initial design rule detection model; the design rule detection model comprises a multi-scale feature extraction module and an attention mechanism module; obtaining a data set of a design rule detection task; the data set contains feature maps corresponding to each feature area in the layout and real violation labels; after the design rule detection model obtains each feature map, the multi-scale feature extraction module and the attention mechanism module are combined to obtain optimized multi-scale features, and the multi-scale features are used to predict the predicted violation labels of each feature area; the parameters of the detection model are optimized according to the error of the real violation labels and the predicted violation labels until the loss function value of the design rule detection model is minimum. The application can improve the violation detection accuracy of the design rule detection model in a complex physical design layout, and has stronger robustness and generalization ability in the identification of small-scale violations and boundary details.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic design automation (EDA), and in particular to a design rule detection and model training method, device, and electronic equipment. Background Art

[0002] Design Rule Check (DRC) is a key step in the integrated circuit design process. Its primary purpose is to ensure that the chip layout meets process requirements during manufacturing, preventing chip functional failure or manufacturing defects caused by design violations. With the continuous advancement of semiconductor manufacturing technology, chip process nodes have entered the 5nm, 3nm, and higher levels. The increase in design complexity has placed higher requirements on DRC efficiency and accuracy.

[0003] Traditional design rule checking methods rely primarily on rule-based checking mechanisms and Boolean logic operations, employing a predefined rule base to perform layer-by-layer scanning and logical analysis of the chip layout. This approach suffers from high computational overhead, high false positive rates, and low detection efficiency when dealing with large-scale, highly complex chip designs. Furthermore, the compilation and maintenance of the rule base relies heavily on manual experience, making it difficult to adapt to ever-changing process requirements. Consequently, the applicability of traditional design rule checking methods in advanced process technologies has been limited, making it difficult to adapt to rapidly evolving process requirements and the expansion of design scale.

[0004] In recent years, deep learning technology has been gradually applied to the field of EDA technology, involving multiple stages of the integrated circuit design process, effectively improving the level of design automation, computational efficiency, and prediction accuracy, and providing new solutions for design rule checking. Compared with traditional methods, the design rule detection model based on deep learning can adaptively extract layout features and automatically detect possible violation areas through end-to-end learning. However, relying solely on basic models such as convolutional neural networks (CNN) may not be able to effectively capture violation patterns at different levels, especially when dealing with complex physical design layouts. Problems such as inaccurate small-scale violation detection and blurred boundaries are prone to occur. Therefore, how to improve the performance of deep learning models in design rule checking is a technical problem that needs to be solved. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a design rule detection and model training method, device, and electronic device, which can improve the accuracy of violation detection of the DRC model in complex physical design layouts, and have stronger robustness and generalization capabilities in identifying small-scale violations and boundary details, thereby effectively solving the problems in the existing technology such as difficulty in capturing multi-level violation patterns, inaccurate detection, and blurred boundaries.

[0006] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0007] In a first aspect, the present invention provides a design rule checking model training method, the method comprising: constructing an initial design rule detection model; wherein the design rule detection model includes a multi-scale feature extraction module and an attention mechanism module; obtaining a data set for a design rule detection task; wherein the data set includes feature maps and true violation labels corresponding to each feature area in the layout; after the design rule detection model obtains each feature map, the multi-scale feature extraction module and the attention mechanism module jointly obtain optimized multi-scale features, and use the multi-scale features to predict predicted violation labels for each feature area; and optimizing the parameters of the detection model according to the error between the true violation label and the predicted violation label until the loss function value of the design rule detection model is minimized.

[0008] In a second aspect, the present invention provides a design rule detection method, which includes: obtaining layout data to be detected; wherein, the layout data to be detected includes multidimensional feature data corresponding to each feature area in the layout to be detected; performing image-like feature mapping on the multidimensional feature data in each feature area, and inputting the feature mapping corresponding to each feature area into a trained design rule detection model to obtain violation detection results corresponding to each feature area; wherein, the design rule detection model is obtained according to the design rule detection model training method described in any one of the aforementioned embodiments.

[0009] In a third aspect, the present invention provides a design rule detection model training device, comprising: a model construction module, used to construct an initial design rule detection model; wherein the design rule detection model includes a multi-scale feature extraction module and an attention mechanism module; a data acquisition module, used to obtain a data set for the design rule detection task; wherein the data set includes feature maps and true violation labels corresponding to each feature area in the layout; a model training module, used to obtain optimized multi-scale features by combining the multi-scale feature extraction module and the attention mechanism module after the design rule detection model obtains each feature map, and use the multi-scale features to predict predicted violation labels for each feature area; optimize the parameters of the detection model according to the error between the true violation label and the predicted violation label until the loss function value of the design rule detection model is minimized.

[0010] In a fourth aspect, the present invention provides a design rule detection device, comprising: an acquisition module for acquiring layout data to be detected; wherein the layout data to be detected includes multidimensional feature data corresponding to each feature area in the layout to be detected; a preprocessing module for performing image-like feature mapping on the multidimensional feature data in each feature area; a detection module for inputting the feature mapping corresponding to each feature area into a trained design rule detection model to obtain violation detection results corresponding to each feature area; wherein the design rule detection model is obtained according to the design rule detection model training method described in any one of the aforementioned embodiments.

[0011] In a fifth aspect, the present invention provides an electronic device comprising a processor and a memory, wherein the memory stores machine-executable instructions that can be executed by the processor, and the processor can execute the machine-executable instructions to implement any of the methods described in the foregoing embodiments.

[0012] The design rule detection and model training method, device, and electronic device provided by the embodiments of the present invention first construct an initial design rule detection model, which includes a multi-scale feature extraction module and an attention mechanism module. Then, after obtaining a data set for the design rule detection task, the data set includes feature maps corresponding to each feature area in the layout and manually annotated real violation labels, providing high-quality learning samples for model training. After the design rule detection model receives these feature maps, the multi-scale feature extraction module and the attention mechanism model jointly obtain optimized multi-scale features. This process effectively enhances the model's ability to capture small-scale violation areas, enables the model to focus on key violation areas, and suppresses irrelevant or interfering information, thereby improving the problem of traditional convolutional networks' insufficient recognition ability in areas with blurred boundaries. On this basis, the model uses the optimized multi-scale features to predict the predicted violation label for each feature area, and dynamically adjusts the model parameters to minimize the loss function value based on the error between the actual violation label and the predicted result. The design rule detection model obtained at this time has significantly improved the accuracy of violation detection in complex physical design layouts, especially in the identification of small-scale violations and boundary details. It has stronger robustness and generalization ability, thus effectively solving the problems of difficulty in capturing multi-level violation patterns, inaccurate detection and blurred boundaries in existing technologies.

[0013] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0015] Figure 1 A schematic flow chart of a design rule detection model training method provided in an embodiment of the present invention;

[0016] Figure 2 A functional module diagram of a DRC detection model provided by an embodiment of the present invention;

[0017] Figure 3 A schematic diagram of the structure of a Bottleneck residual block provided in an embodiment of the present invention;

[0018] Figure 4 Schematic diagram of comparison between the predicted violation results and the actual violation situation of the DRC detection model in an embodiment of the present invention;

[0019] Figure 5 A schematic flow chart of a design rule detection method provided in an embodiment of the present invention;

[0020] Figure 6 A functional module diagram of a design rule detection model training device provided by an embodiment of the present invention;

[0021] Figure 7 A functional module diagram of a design rule detection device provided by an embodiment of the present invention;

[0022] Figure 8 This is a structural block diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0024] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but is merely intended to represent selected embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative work are within the scope of protection of the present invention.

[0025] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0026] Considering that relying solely on the basic convolutional neural network model may not be able to effectively capture violation patterns at different levels, and even when processing complex layouts, it is prone to problems such as inaccurate detection of small-scale violations and blurred boundaries. To address this problem, an embodiment of the present invention provides a design rule detection model training method that can enhance the design rule detection model (referred to as the DRC detection model in the subsequent description)'s ability to detect violation patterns of different scales, especially improving the problem of inaccurate detection of small-scale violations and effectively solving the problem of blurred boundaries, enabling the model to more accurately identify violation patterns.

[0027] See Figure 1 , Figure 1 This is a schematic flow chart of a design rule detection model training method provided in an embodiment of the present invention. The execution subject of the method can be an electronic device with model training capabilities. The method includes steps S101 to S104, which are described as follows:

[0028] S101: Constructing an initial design rule detection model; wherein the design rule detection model includes a multi-scale feature extraction module and an attention mechanism module;

[0029] S102: Obtaining a data set for a design rule detection task; wherein the data set includes feature maps and true violation labels corresponding to each feature region in the layout;

[0030] S103: After designing the rule detection model to obtain each feature map, the multi-scale feature extraction module and the attention mechanism module are combined to obtain optimized multi-scale features, and the multi-scale features are used to predict the predicted violation label of each feature area;

[0031] S104: Optimize the parameters of the detection model according to the error between the actual violation label and the predicted violation label until the loss function value of the design rule detection model is minimized.

[0032] In the design rule detection model training method provided by an embodiment of the present invention, an initial design rule detection model is first constructed, which includes a multi-scale feature extraction module and an attention mechanism module. Then, after obtaining a data set for the design rule detection task, the data set contains feature maps corresponding to each feature region in the layout and manually annotated real violation labels, providing high-quality learning samples for model training. After the design rule detection model receives these feature maps, the multi-scale feature extraction module and the attention mechanism model jointly obtain optimized multi-scale features. This process effectively enhances the model's ability to capture small-scale violation regions and enables the model to focus on key violation regions and suppress irrelevant or interference information, thereby improving the problem of traditional convolutional networks' insufficient recognition ability in fuzzy boundary regions. On this basis, the model uses the optimized multi-scale features to predict the predicted violation label for each feature region and dynamically adjusts the model parameters to minimize the loss function value based on the error between the real violation label and the predicted result. The resulting design rule detection model has significantly improved the violation detection accuracy in complex physical design layouts, especially in the recognition of small-scale violations and boundary details. It has stronger robustness and generalization ability, thus effectively solving the problems of difficulty in capturing multi-level violation patterns, inaccurate detection and fuzzy boundaries in the existing technology.

[0033] Next, the embodiment of the present invention will clearly and in detail illustrate the training process of the above-mentioned design rule checking model (hereinafter referred to as DRC checking model) with reference to relevant drawings.

[0034] In step S101, the DRC detection model of the embodiment of the present invention adopts an encoder-decoder structure, and the construction process includes steps a1 to a3:

[0035] Step a1: construct a feature fusion module based on the attention mechanism module, and construct an encoder based on the feature fusion module and the multi-scale feature extraction module;

[0036] Step a2: Build a detection module as a decoder;

[0037] Step a3: Build a design rule detection model based on the encoder and decoder.

[0038] To understand the above model structure and the functions of each module, please refer to Figure 2 , Figure 2 This is a functional module diagram of the DRC detection model provided by an embodiment of the present invention. It should be understood that Figure 2 This is only an example and omits some essential components of the DRC detection model. This is not a limitation on the structure of the DRC detection model.

[0039] Among them, the encoder is built based on the multi-scale feature extraction module and the feature fusion module. In this way, the DRC detection model can be based on the optimized multi-scale features extracted by the encoder, and then the decoder can perform violation detection based on the optimized multi-scale features to achieve accurate prediction of the violation results.

[0040] In the embodiments of the present invention, a multi-scale feature extraction module is used to extract rich feature information at different scales. Its feature extraction process primarily follows a bottom-up approach. During the feature extraction process, Bottleneck residual blocks are used for deep feature extraction, with feature maps downsampled by a factor of 2 at each layer. This design enables the acquisition of rich feature information at different scales layer by layer during the training phase, thereby constructing a pyramid-like feature representation. This provides a more comprehensive and hierarchical feature foundation for subsequent detection tasks.

[0041] To understand the above process, see Figure 3 , Figure 3 Schematic diagram of the structure of the Bottleneck residual block provided by the embodiment of the present invention. Figure 3 As shown in the figure, the Bottleneck residual block can be composed of three convolution modules in series. Each convolution layer is followed by a BN layer (BatchNormalization) and a ReLU activation function. A residual connection is performed after the three layers of convolution, and the convolution output is bitwise added to the input. If the dimensions are inconsistent, a 1×1 convolution is used to adjust the dimensions. The processing process of the Bottleneck residual block can be expressed by the following formula:

[0042] Block_out=ReLU(BN(Conv1(ReLU(BN(Conv3(ReLU(BN(Conv1(F))))))))+BN(Conv1(F)))

[0043] Among them, F is the feature map, Conv1 represents the convolution kernel with a size of 1×1 and a stride of 1, and Conv3 represents the convolution kernel with a size of 3×3 and a stride of 2.

[0044] It can be understood that in the embodiment of the present invention, feature extraction is performed through the Bottleneck residual block, and the features are downsampled by 2 times in each stage. Feature maps of different stages can be obtained by layer-by-layer extraction.

[0045] Optionally, the multi-scale feature extraction module can use the Feature Pyramid Network (FPN) architecture as the backbone network.

[0046] Continue to see Figure 2The feature fusion module is responsible for fusing rich feature information of different scales. It introduces an attention mechanism module, which can highlight important features and suppress unimportant features, thereby enhancing the expressiveness of features and making the extracted features more discriminative, which is beneficial to subsequent detection tasks.

[0047] In the embodiment of the present invention, the feature fusion module adopts a fusion structure that combines top-down and lateral connections. Top-down is the path from high-level features to low-level features, and lateral connections are to connect features at different levels horizontally in order to fuse information from different levels. Specifically:

[0048] In the top-down path, high-level features are scaled to the same size as lower-level feature maps through bilinear interpolation upsampling and then fused. The upsampled high-level features are fused with the lower-level features to enhance the detail capture of the lower-level features. Next, an attention mechanism module is used to deeply fuse the mapped feature maps with the feature maps of the current layer, highlighting important features and suppressing noise. Finally, a smoothed convolution operation is performed on the fused multi-scale feature maps to further optimize feature representation, reduce noise interference, and thus improve feature quality and effectiveness.

[0049] In this embodiment of the present invention, the attention mechanism module includes a channel attention submodule and a spatial attention submodule:

[0050] The channel attention submodule extracts global channel features and adaptively adjusts the channel distribution of the feature map. Its working principle can be expressed by the following formula:

[0051] M c (F)=σ(MLP(AvgPool(F)) + MLP(MaxPool(F)))

[0052] Among them, F is the feature map, AvgPool (F) is the average feature vector of the channel dimension generated by the average pooling layer, MaxPool (F) is the maximum feature vector of the channel dimension generated by the maximum pooling layer, and MLP is a shared multi-layer perceptron, which uses a two-layer fully connected network for feature transformation. is the Sigmoid activation function;

[0053] The spatial attention submodule weights the input features to enhance the extraction of spatial relationship information. Its working principle can be expressed by the following formula:

[0054] M s (F)=σ(conv([AvgPool(F) ,MLP(MaxPool(F)]))

[0055] Among them, conv is a convolution kernel with a size of 7×7.

[0056] From the above content, we can see that the attention mechanism module first calculates the channel attention, obtains the enhanced features, then calculates the spatial attention, further enhances the features, and finally outputs the feature map after attention optimization. Therefore, the working principle of the attention mechanism module is as follows:

[0057]

[0058] in, It is the feature map processed by the attention mechanism module.

[0059] Continue to see Figure 2 The decoder is constructed by the detection module. After obtaining the optimized multi-scale features output by the encoder, the detection module can use the multi-scale context information, starting from the deepest high-level features, and sequentially jump-connect the high-level features and low-level features, and perform three upsampling operations. Each upsampling operation includes deconvolution, BatchNorm, and ReLU, which can effectively integrate semantic information of different resolutions. The strategy is repeated for feature maps of different scales, and finally deconvolution is used to generate detection results with the same resolution as the original image.

[0060] Based on the above Figure 2 The DRC detection model shown is described below. Next, the training process of the DRC detection model provided by the embodiment of the present invention is introduced.

[0061] In step S102, the embodiment of the present invention first obtains a data set for the design rule detection task, and uses this data set to train, verify, and test a DRC detection model to obtain an accurate DRC detection model.

[0062] In one embodiment of the present invention, a data set related to the DRC detection task may be constructed based on the integrated circuit design data. That is, the implementation of step S102 includes steps b1 to b4, as described below:

[0063] Step b1: obtaining integrated circuit design data;

[0064] In this embodiment of the present invention, integrated circuit design data is derived from layout information in the integrated circuit design process. This layout information can include multi-dimensional feature data such as MacroRegion, Rectangular Uniform Density Analysis (RUDY), PinRUDY, Cell Density, and Congestion Map. This feature data constitutes the core input content of the DRC detection task.

[0065] Understandably, the complete layout data for integrated circuits is often very large. Directly processing the entire image would result in a massive computational load, impacting model training efficiency and inference speed. Therefore, a tile-level segmentation approach can be employed to divide the complete layout data into multiple fixed-size tiles, representing the feature regions in the embodiments of the present invention, such as a 2.25μm × 2.25μm grid.

[0066] Step b2: Perform image-like feature mapping on the multi-dimensional feature data in each feature area;

[0067] In this embodiment of the present invention, after tile-level segmentation, each tile can be converted into an image-like feature map. This abstracts the multidimensional feature data in each tile of the original layout into a multidimensional feature vector. This allows each layout to be divided into multiple feature regions, each corresponding to a feature map. This feature map is a multi-dimensional feature vector.

[0068] For example, the feature map corresponding to each tile can include five feature dimensions: MacroRegion, RUDY, PinRUDY, CellDensity, and CongestionMap. By integrating multi-dimensional features (e.g., MacroRegion, RUDY, PinRUDY, CellDensity, and CongestionMap) into feature engineering modeling, the DRC detection model's ability to understand complex DRC violation patterns can be enhanced. Of course, the above five feature dimensions are merely examples, and personnel are free to flexibly select different feature dimensions based on actual needs. This is not a limitation here.

[0069] Step b3: Determine the true violation label based on the violation status of each feature area;

[0070] In this embodiment of the present invention, the violation status includes violation and non-violation. For each feature region, a label is further required to mark whether each feature region has a violation issue. For example, if a feature region has a violation issue, it is marked as "1" (violation); otherwise, it is marked as "0" (normal or non-violation).

[0071] Through the above implementation, the true violation label corresponding to each feature area can be obtained.

[0072] Step b4: The feature maps corresponding to all feature areas and the actual violation labels are combined into a dataset.

[0073] In the embodiment of the present invention, the feature maps corresponding to all feature regions and the true violation labels are combined into a complete DRC detection task dataset for subsequent DRC detection model training, that is, step S103 to step S104 can be executed.

[0074] In step S103, to ensure effective model training and performance evaluation, embodiments of the present invention may further divide the dataset into three parts according to a preset ratio: a training set for learning model parameters; a validation set for tuning model hyperparameters and preventing overfitting; and a test set for ultimately evaluating the model's performance on unknown data.

[0075] For example, the data can be divided in a ratio of 8:1:1, with the training set accounting for 80%, the validation set accounting for 10%, and the test set accounting for 10%. Of course, this division is only an example, and relevant personnel can flexibly set the division ratio, which is not limited here.

[0076] Based on the divided training set, the embodiment of the present invention can input each feature map and the actual violation label in the training set into the DRC detection model to predict the violation label, that is, perform step S103. The process is as follows:

[0077] In the first step, after the feature maps and true violation labels in the training set are input into the DRC detection model, the multi-scale feature extraction module extracts multi-scale features;

[0078] The second step is to optimize the fused multi-scale features through the attention mechanism module during the fusion process of multi-scale features.

[0079] In the third step, the optimized multi-scale features are input into the detection module of the DRC detection model for prediction to obtain the predicted violation label corresponding to the feature area.

[0080] The predicted violation label of the feature area can be obtained in the above manner, and then step S104 can be executed, that is, the model parameters of the DRC detection model are optimized by the error between the real violation label and the predicted violation label until the loss function value is minimized and the training is stopped.

[0081] In the embodiment of the present invention, the loss function of the DRC detection model may adopt a cross entropy loss function, and the formula is as follows:

[0082]

[0083] Among them, L is the loss function value of the DRC detection model; N represents the number of feature regions, Indicates that the i-th feature area corresponds to the real violation label. When the i-th feature area has a design violation problem The value is 1, when there is no design violation The value is 0. It represents the predicted probability of a violation in the i-th feature region.

[0084] During the training process, the embodiment of the present invention can use the minimum loss function value as the training condition, update the model parameters through back propagation, and obtain the DRC detection model.

[0085] In one embodiment of the present invention, before model training, relevant personnel can flexibly set various hyperparameters such as learning rate, weight decay, batch size, etc. In the process of optimizing the model parameters of the DRC detection model using the cross-entropy loss function, the hyperparameters can also be dynamically adjusted and optimized.

[0086] In one embodiment of the present invention, after the DRC detection model is obtained through training with the training set, the model performance can also be evaluated based on the validation set. Therefore, after executing step S104, the following steps can also be performed:

[0087] Step c1: divide the validation set from the dataset;

[0088] Step c2: Use the validation set to evaluate the model accuracy of the trained DRC detection model;

[0089] Step c3: If the model accuracy does not meet the preset accuracy requirements and the number of iterations does not exceed the set maximum number of iterations, adjust the hyperparameters of the DRC detection model and continue training;

[0090] Step c4: When the model accuracy reaches the preset accuracy requirement or the number of iterations reaches the maximum number of iterations, stop training.

[0091] The above method can avoid the overfitting problem of the DRC detection model caused by overtraining, thereby effectively improving the generalization ability and final detection performance of the DRC detection model, so that it can perform design rule checking more stably and accurately in practical applications.

[0092] Furthermore, after completing the DRC detection model training, the generalization ability of the model can be evaluated, that is, the DRC detection model obtained after verification can be tested using the test set. Specifically, the test can be performed as follows:

[0093] Step d1: divide the test set from the dataset;

[0094] Step d2: Calculate the test index value of the verified DRC detection model using the test set;

[0095] Step d3: If the test index value does not meet the preset test index requirements, adjust the hyperparameters and continue training;

[0096] Step d4: When the test index value reaches the preset test index requirement, stop training.

[0097] Through the above method, the actual performance of the DRC detection model on data that has not participated in training can be more comprehensively evaluated, thereby ensuring the stability and reliability of the model, improving its accuracy and adaptability for design rule checking in practical applications, and better coping with various complex design scenarios.

[0098] In order to more intuitively demonstrate the detection effect of the DRC detection model provided by the embodiment of the present invention, please refer to Figure 4 . Figure 4 Schematic diagram of the comparison between the predicted violation results and the actual violation situation of the DRC detection model in an embodiment of the present invention.

[0099] The left side of the figure shows actual DRC violation areas manually annotated by the relevant designers. In this figure, violation areas are typically marked with a specific color (such as red or yellow) to indicate the specific location of design rule violations in the integrated circuit layout. The right side shows the prediction result automatically generated by the DRC detection model of the present invention, demonstrating the model's identification of potential DRC violation areas in the layout. The figure also uses color to mark the predicted violation locations, and different shades of color can be used to distinguish them based on the confidence level of the model's prediction, thereby reflecting the strength of the violation.

[0100] By comparing the left and right figures, it can be seen that the model's prediction results are highly consistent with the actual violation areas manually marked, indicating that the DRC detection model proposed in the embodiment of the present invention has high detection accuracy and good practicality, and can effectively assist the automated DRC inspection process in integrated circuit design.

[0101] Based on the DRC detection model trained by the embodiment of the present invention, the embodiment of the present invention also provides a DRC automatic detection process. Figure 5 , Figure 5 The schematic flow chart of the design rule detection method provided by the embodiment of the present invention includes steps S501 to S503, which are described as follows:

[0102] S501: Acquire layout data to be detected; wherein the layout data to be detected includes multi-dimensional feature data corresponding to each feature area in the layout to be detected;

[0103] S502: Performing image-like feature mapping on the multi-dimensional feature data in each feature area;

[0104] S503: Inputting the feature map corresponding to each feature area into the trained design rule detection model to obtain the violation detection result corresponding to each feature area;

[0105] The DRC detection model is obtained according to the DRC detection model training method provided by an embodiment of the present invention.

[0106] In the design rule detection method provided by the above steps S501 to S503, the DRC detection model provided by the embodiment of the present invention is used to perform violation detection on the layout to be detected. Since the model has the function of accurately identifying the violation areas in the layout during the training process, after the feature mapping of each feature area of ​​the layout to be detected is input into the model, the model outputs the violation detection results of each feature area. The entire process can quickly and accurately obtain the DRC detection results of the layout.

[0107] It can be understood that the DRC detection method provided by the present invention can be embedded in EDA tools to provide intelligent DRC detection in the integrated circuit design process, optimize the chip design process, improve design efficiency, and reduce later modification costs.

[0108] To execute Figure 1 The following is a method for implementing the DRC detection model training device 60, see Figure 6 , Figure 6 This is a functional module diagram of the design rule detection model training device provided by an embodiment of the present invention. It should be noted that the basic principles and technical effects of the design rule detection model training device 60 provided by the embodiment of the present invention are the same as those of the above-mentioned embodiment. For the sake of simplicity, any parts not mentioned in the embodiment of the present invention can be referred to the corresponding contents of the above-mentioned embodiment. The design rule detection model training device 60 includes:

[0109] A model construction module 601 is used to construct an initial design rule detection model; wherein the design rule detection model includes a multi-scale feature extraction module and an attention mechanism module;

[0110] The data acquisition module 602 is used to acquire a data set for the design rule detection task; wherein the data set includes a feature map and a true violation label corresponding to each feature area in the layout;

[0111] The model training module 603 is used to design a rule detection model. After obtaining each feature map, the multi-scale feature extraction module and the attention mechanism module jointly obtain optimized multi-scale features, and use the multi-scale features to predict the predicted violation labels of each feature area; the parameters of the detection model are optimized according to the error between the actual violation label and the predicted violation label until the loss function value of the designed rule detection model is minimized.

[0112] It is understandable that the model building module 601, the data acquisition module 602 and the model training module 603 can be executed in a coordinated manner. Figure 1 Each step in the process is performed to achieve the corresponding technical effects.

[0113] It should be noted that the design rule detection model training device 60 provided in the embodiment of the present invention can be specific hardware on the device or software or firmware installed on the device. The implementation principle and technical effects of the device provided in the embodiment of the present invention are the same as those in the aforementioned method embodiment. For the sake of brief description, for matters not mentioned in the device embodiment, reference can be made to the corresponding content in the aforementioned DRC detection model training method embodiment. Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the functional modules described above can all refer to the corresponding processes in the aforementioned DRC detection model training method embodiment, and will not be repeated here.

[0114] To execute Figure 5 The following is a corresponding step in the design rule detection device 70, see Figure 7 , Figure 7 This is a functional module diagram of a design rule detection device provided in an embodiment of the present invention. It should be noted that the basic principles and technical effects of the design rule detection device 70 provided in the embodiment of the present invention are the same as those of the above-mentioned embodiment. For the sake of simplicity, any parts not mentioned in the embodiment of the present invention can be referred to the corresponding contents in the above-mentioned embodiment. The design rule detection device 70 includes:

[0115] The acquisition module 701 is used to acquire the layout data to be detected; wherein the layout data to be detected includes multi-dimensional feature data corresponding to each feature area in the layout to be detected;

[0116] A pre-processing module 702 is used to perform image-like feature mapping on the multi-dimensional feature data in each feature area;

[0117] The detection module 703 is used to input the feature map corresponding to each feature area into the trained design rule detection model to obtain the violation detection result corresponding to each feature area; wherein the design rule detection model is obtained according to the design rule detection model training method provided by the embodiment of the present invention.

[0118] It is understandable that the acquisition module 701, the pre-processing module 702 and the detection module 703 can be executed in a coordinated manner. Figure 5 Each step in the process is performed to achieve the corresponding technical effects.

[0119] It should be noted that the design rule detection device 70 provided in the embodiment of the present invention can be specific hardware on the device, or software or firmware installed on the device. The implementation principles and technical effects of the device provided in the embodiment of the present invention are the same as those of the aforementioned design rule detection method embodiment. For the sake of simplicity, any details not mentioned in the device embodiment can be referred to the corresponding content in the aforementioned design rule detection method embodiment. Those skilled in the art will clearly understand this, and will not be elaborated on here.

[0120] Optionally, the above modules can be stored in the form of software or firmware. Figure 8 The memory shown in FIG. 8 or the operating system (OS) of the electronic device 80 may be fixed therein and may be Figure 8 Meanwhile, the data and program codes required to execute the above modules may be stored in the memory.

[0121] See Figure 8 , Figure 8 The electronic device provided in an embodiment of the present invention includes a memory 801, a processor 802, and a communication interface 803. The memory 801, processor 802, and communication interface 803 are electrically connected to each other, directly or indirectly, to enable data transmission or interaction. For example, these components may be electrically connected to each other via one or more communication buses or signal lines.

[0122] Optionally, the bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 8 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0123] In the embodiment of the present invention, the processor 802 can be a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, and can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiment of the present invention. A general-purpose processor can be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the embodiment of the present invention can be directly embodied as being executed by a hardware processor, or can be executed by a combination of hardware and software modules in the processor. The software module can be located in the memory 801, and the processor 802 reads the program instructions in the memory 801 and performs the steps of the above method in combination with its hardware.

[0124] In an embodiment of the present invention, the memory 801 may be a non-volatile memory, such as a hard disk drive (HDD) or a solid-state drive (SSD), or a volatile memory (Volatile Memory), such as RAM. The memory may also be any other medium that can be used to carry or store the desired program executable code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory in an embodiment of the present invention may also be a circuit or any other device that can implement a storage function, for storing instructions and / or data.

[0125] The memory 801 can be used to store software programs and modules, such as the instructions / modules of the design rule detection model training device 60 or the design rule detection device 70 provided in the embodiments of the present invention. These can be stored in the memory 801 in the form of software or firmware or embedded in the operating system (OS) of the electronic device 80. The processor 802 executes the software programs and modules stored in the memory 801 to perform various functional applications and data processing. The communication interface 803 can be used for signaling or data communication with other node devices.

[0126] I understand. Figure 8 The structure shown is for illustration only. The electronic device 8 may also include Figure 8 More or fewer components than shown, or with Figure 8 Different configurations shown. Figure 8 The components shown may be implemented in hardware, software, or a combination thereof.

[0127] Based on the above embodiments, the present invention also provides a readable storage medium, which stores a computer program. When the computer program is executed by a computer, the computer executes the design rule detection model training method or design rule detection method provided in the above embodiments. For specific implementation, please refer to the method embodiment and will not be repeated here.

[0128] An embodiment of the present invention can also provide a computer program product for executing a design rule detection model training method or a design rule detection method, including a computer-readable storage medium storing program code, and the instructions included in the program code can be used to execute the method in the previous method embodiment. The specific implementation can be found in the method embodiment, which will not be repeated here.

[0129] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interface, the indirect coupling or communication connection of the device or unit can be electrical, mechanical or other forms.

[0130] In addition, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiments of the present invention.

[0131] Furthermore, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0132] It should be noted that if the function is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, electronic device, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program code.

Claims

1. A design rule detection model training method, characterized in that: The method comprises: Constructing an initial design rule detection model; wherein the design rule detection model includes a multi-scale feature extraction module and an attention mechanism module; Obtaining a data set for a design rule checking task; wherein the data set includes feature maps and true violation labels corresponding to each feature region in a layout; obtaining a data set for a design rule checking task, comprising: obtaining integrated circuit design data; wherein the integrated circuit design data includes multidimensional feature data of the layout; performing image-like feature mapping on the multidimensional feature data in each feature region; determining the true violation label based on the violation status of each feature region; and combining the feature maps and true violation labels corresponding to all the feature regions into the data set; After the design rule detection model obtains each feature map, the multi-scale feature extraction module and the attention mechanism module jointly obtain optimized multi-scale features, and use the multi-scale features to predict the predicted violation label of each feature area; Optimizing parameters of the detection model according to the error between the true violation label and the predicted violation label until the loss function value of the design rule detection model is minimized.

2. The design rule detection model training method according to claim 1, characterized in that: After the design rule detection model obtains each feature map, the multi-scale feature extraction module and the attention mechanism module jointly obtain optimized multi-scale features, and use the multi-scale features to predict the predicted violation label of each feature area, including: A training set is divided from the data set; After inputting the feature maps and true violation labels in the training set into the design rule detection model, the multi-scale feature extraction module extracts multi-scale features; In the process of fusing the multi-scale features, optimizing the fused multi-scale features through the attention mechanism module; The optimized multi-scale features are input into the detection module of the design rule detection model for prediction, and the predicted violation labels corresponding to the feature areas are obtained.

3. The design rule detection model training method according to claim 1, characterized in that: The method further comprises: Separating a validation set from the dataset; Using the validation set to evaluate the model accuracy of the trained design rule detection model; If the model accuracy does not meet the preset accuracy requirement and the number of iterations does not exceed the set maximum number of iterations, adjusting the hyperparameters of the design rule detection model and continuing training; When the model accuracy reaches the preset accuracy requirement or the number of iterations reaches the maximum number of iterations, the training is stopped.

4. The design rule detection model training method according to claim 3, characterized in that: The method further comprises: Partitioning a test set from the dataset; Calculating a test index value of the verified design rule detection model using the test set; If the test index value does not meet the preset test index requirement, adjust the hyperparameter and continue training; When the test index value reaches the preset test index requirement, the training is stopped.

5. The design rule detection model training method according to any one of claims 1 to 4, characterized in that: Build an initial design rule checking model, including: Constructing a feature fusion module based on the attention mechanism module, and constructing an encoder based on the feature fusion module and the multi-scale feature extraction module; Build a detection module as a decoder; The design rule checking model is constructed based on the encoder and the decoder.

6. A design rule detection method, characterized in that: The method comprises: Acquire the layout data to be detected; wherein the layout data to be detected includes multi-dimensional feature data corresponding to each feature area in the layout to be detected; Performing image-like feature mapping on the multidimensional feature data in each feature area; Inputting the feature maps corresponding to the feature regions into the trained design rule detection model to obtain violation detection results corresponding to the feature regions; The design rule detection model is obtained according to the design rule detection model training method according to any one of claims 1 to 5.

7. A design rule detection model training device, characterized in that: include: A model building module, configured to build an initial design rule detection model; wherein the design rule detection model includes a multi-scale feature extraction module and an attention mechanism module; A data acquisition module is configured to acquire a data set for a design rule checking task; wherein the data set includes a feature map and a true violation label corresponding to each feature region within the layout; acquiring the data set for the design rule checking task comprises: acquiring integrated circuit design data; wherein the integrated circuit design data includes multidimensional feature data of the layout; performing image-like feature mapping on the multidimensional feature data within each feature region; determining the true violation label based on the violation status of each feature region; and assembling the feature maps and true violation labels corresponding to all the feature regions into the data set; A model training module is configured to, after the design rule detection model obtains each feature map, jointly obtain optimized multi-scale features by the multi-scale feature extraction module and the attention mechanism module, and use the multi-scale features to predict the predicted violation labels of each feature area; and optimize the parameters of the detection model based on the error between the true violation label and the predicted violation label until the loss function value of the design rule detection model is minimized.

8. A design rule detection device, characterized in that: include: An acquisition module is used to acquire the layout data to be detected; wherein the layout data to be detected includes multi-dimensional feature data corresponding to each feature area in the layout to be detected; A preprocessing module, configured to perform image-like feature mapping on the multidimensional feature data in each feature area; A detection module is used to input the feature maps corresponding to the feature areas into a trained design rule detection model to obtain violation detection results corresponding to the feature areas; wherein the design rule detection model is obtained according to the design rule detection model training method according to any one of claims 1 to 5.

9. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores machine-executable instructions that can be executed by the processor, and the processor can execute the machine-executable instructions to implement the method according to any one of claims 1 to 6.

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