Gate driver and display device including same

Abstract

The present disclosure relates to a gate driver and a display device including the same. According to an aspect of the present disclosure, a gate driver includes: a plurality of stages connected in relation to each other, each of the plurality of stages including: a node controller configured to control voltages of a Q node, a Q1 node, a Q2 node, a QB node, a QB1 node, and a QB2 node based on a first clock signal and a second clock signal; the carry signal output unit is configured to output a carry signal to a next stage based on the voltages of the Q1 node and the QB1 node; and a scan signal output unit configured to output a scan signal to a scan line based on voltages of the Q node and the QB node, and a width of the scan signal may be determined by a switching timing of the first clock signal and a switching timing of the second clock signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0026476 filed on January 23, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a gate driver and a display device including the gate driver. Background Art

[0004] With the advent of the information age, the field of displays that visually express electrical information signals has rapidly developed, and in response to this, various display devices having excellent performance such as thin thickness, light weight, and low power consumption have been developed. Examples of such display devices include liquid crystal display (LCD) devices, organic light emitting display (OLED) devices, and the like.

[0005] Such a display device includes a display panel having an array of pixels for displaying images, and driving circuits such as a data driver, a gate driver, and a timing controller. The data driver provides data signals to data lines provided in the display panel, the gate driver in turn provides gate signals to gate lines provided in an active area, and the timing controller controls the data driver and the gate driver. Summary of the Invention

[0006] One object to be achieved by the present disclosure is to provide a gate driver for driving an n-type transistor and a display device including the gate driver.

[0007] Another object to be achieved by the present disclosure is to provide a gate driver that modifies driving timing of a scan signal in various ways, and a display device including the gate driver.

[0008] The objects of the present disclosure are not limited to the above objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0009] To achieve the above-mentioned objectives, according to one aspect of the present disclosure, a gate driver includes: a plurality of stages, the plurality of stages being connected in relation to each other, each of the plurality of stages including: a node controller, the node controller being configured to control the voltages of a Q node, a Q1 node, a Q2 node, a QB node, a QB1 node, and a QB2 node based on a first clock signal and a second clock signal; a carry signal output unit, the carry signal output unit being configured to output a carry signal to a next stage based on the voltages of the Q1 node and the QB1 node; and a scan signal output unit, the scan signal output unit being configured to output a scan signal to a scan line based on the voltages of the Q node and the QB node, and a width of the scan signal can be determined by a toggling timing of the first clock signal and a toggling timing of the second clock signal.

[0010] To achieve the above-mentioned purpose, according to one aspect of the present disclosure, a display device includes: a display panel, the display panel including an active area in which a plurality of pixels are arranged; and a gate driver, the gate driver including: a plurality of stages, the plurality of stages being connected in relation to each other, each of the plurality of stages including: a node controller, the node controller being configured to control the voltages of a Q node, a Q1 node, a Q2 node, a QB node, a QB1 node, and a QB2 node based on a first clock signal and a second clock signal; a carry signal output unit, the carry signal output unit being configured to output a carry signal to a next stage based on the voltages of the Q1 node and the QB1 node; and a scan signal output unit, the scan signal output unit being configured to output a scan signal to a scan line based on the voltages of the Q node and the QB node, and the width of the scan signal can be determined by the switching timing of the first clock signal and the switching timing of the second clock signal.

[0011] Additional details of exemplary embodiments are included in the detailed description and accompanying drawings.

[0012] According to the present disclosure, the pulse width of the scanning signal can be set to 1H (horizontal period) or shorter, so that the scanning signal can be set according to various driving timings.

[0013] According to the present disclosure, the stability of the scan signal output is improved to enhance the driving reliability of the display device.

[0014] According to the present disclosure, a gate-on level scan signal of a high level is output to drive transistors including an n-type oxide semiconductor in a plurality of pixels.

[0015] According to the present disclosure, a separate power supply line for driving the inverter is not required, so that the bezel area can be reduced and an increase in separate power consumption can be suppressed.

[0016] The effects according to the present disclosure are not limited to those exemplified above, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0019] Figure 2 is a cross-sectional view illustrating a stacked shape of a display device according to an exemplary embodiment;

[0020] Figure 3 is a diagram illustrating a configuration of a gate driver in a display device according to an exemplary embodiment of the present disclosure;

[0021] Figure 4 is a diagram for illustrating a pixel circuit in a display device according to an exemplary embodiment of the present disclosure;

[0022] Figure 5A and Figure 5B Is used to illustrate Figure 4 FIG. 1 is a diagram illustrating operations of a scan signal and an emission control signal in a pixel circuit in a refresh period and a hold period;

[0023] Figure 6 is a circuit diagram of one stage of a gate driver of a display device according to an exemplary embodiment of the present disclosure;

[0024] Figure 7 1 is a waveform illustrating signals input to and output from a plurality of stages of a gate driver of a display device according to an exemplary embodiment of the present disclosure;

[0025] Figure 8A is a circuit diagram for explaining operations of a plurality of stages of a gate driver of a display device according to an exemplary embodiment of the present disclosure in a first period;

[0026] Figure 8B is a circuit diagram for explaining operations of a plurality of stages of a gate driver of a display device according to an exemplary embodiment of the present disclosure in a second period;

[0027] Figure 8Cis a circuit diagram for explaining operations of a plurality of stages of a gate driver of a display device according to an exemplary embodiment of the present disclosure in a third period;

[0028] Figure 8D is a circuit diagram for explaining operations of a plurality of stages of a gate driver of a display device according to an exemplary embodiment of the present disclosure in a fourth period; and

[0029] Figure 8E is a circuit diagram for explaining operations of a plurality of stages of a gate driver of a display device according to an exemplary embodiment of the present disclosure in a fifth period. DETAILED DESCRIPTION

[0030] The advantages and features of the present disclosure and the methods for achieving these advantages and features will be clear by reference to the exemplary embodiments described in detail below and the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only as examples so that those skilled in the art can fully understand the content disclosed by the present disclosure and the scope of the present disclosure.

[0031] The shapes, sizes, proportions, angles, quantities, etc. shown in the drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally represent the same elements. In addition, in the following description of the present disclosure, detailed explanations of known related arts may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including," "having," and "consisting of" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only." Unless expressly stated otherwise, any reference to the singular may include the plural.

[0032] Even if not explicitly stated, the components are interpreted as including the ordinary error range.

[0033] When terms such as "on," "over," "below," and "next to" are used to describe a positional relationship between two parts, one or more parts may be located between the two parts unless these terms are used together with the terms "immediately" or "directly."

[0034] When an element or layer is referred to as being “on” another element or layer, the other layer or other elements may be directly on the other element or interposed therebetween.

[0035] Although terms such as "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component mentioned below can be the second component in the technical concept of the present disclosure.

[0036] Throughout the specification, like reference numerals generally refer to like elements.

[0037] The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present disclosure is not limited to the size and thickness of the components shown.

[0038] The features of the various embodiments of the present disclosure may be partially or completely coupled or combined with each other and may be technically interlocked and operated in various ways, and the embodiments may be performed independently of or in association with each other.

[0039] Hereinafter, a display device according to exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0040] Figure 1 is a block diagram schematically illustrating a display device according to an exemplary embodiment of the present disclosure.

[0041] refer to Figure 1 The display device 10 includes a display panel 100, a controller 200, a gate driver 300, a data driver 400, and a power supply unit 500. The display panel 100 includes a plurality of pixels P. The gate driver 300 provides a gate signal to each of the plurality of pixels P. The data driver 400 provides a data signal to each of the plurality of pixels P. The power supply unit 500 provides power required for driving each of the plurality of pixels P.

[0042] The display panel 100 includes an active area AA (see Figure 2 ) and the non-active area NA (see Figure 2 ), the pixel P is located in the active area AA, and the non-active area NA is provided to surround the active area AA and includes the gate driver 300 and the data driver 400.

[0043] In the display panel 100, a plurality of gate lines GL and a plurality of data lines DL intersect each other, and a plurality of pixels P are respectively connected to the gate lines GL and the data lines DL. Specifically, a gate signal is supplied from the gate driver 300 to each pixel P via the gate line GL, a data signal is supplied from the data driver 400 to each pixel P via the data line DL, and a high-potential driving voltage EVDD and a low-potential driving voltage EVSS are supplied from the power supply unit 500 to each pixel P.

[0044] Here, the gate lines GL provide scan signals SC and emission control signals EM, and the data lines DL provide data voltages Vdata. Furthermore, according to various exemplary embodiments, the gate lines GL may include a plurality of gate lines SCL providing scan signals SC and emission control signal lines EML providing emission control signals EM. Furthermore, the plurality of pixels P further include a power line VL to which a bias voltage Vobs and initialization voltages Var and Vini are provided.

[0045] In addition, each pixel P includes a light emitting diode OLED and a pixel circuit configured to control driving of the light emitting diode OLED, such as Figure 2 Here, the light emitting diode OLED is composed of an anode electrode ANO, a cathode electrode CAT, and an emission layer EL between the anode electrode ANO and the cathode electrode CAT.

[0046] The pixel circuit includes multiple switching elements, driving elements, and capacitors. The switching elements and driving elements may be composed of thin-film transistors. In the pixel circuit, the driving element controls the amount of current supplied to the light-emitting diode (OLED) based on a data voltage to adjust the emission level of the light-emitting diode (OLED). Furthermore, the multiple switching elements receive scan signals SC provided via multiple gate lines SCL and emission control signals EM provided via emission control lines EML to operate the pixel circuit.

[0047] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel can be applied to a transparent display device in which an image is displayed on the screen and real objects in the background are visible. The display panel 100 can be manufactured as a flexible display panel. The flexible display panel can be implemented using an OLED panel using a plastic substrate.

[0048] Each pixel P can be divided into a red pixel, a green pixel, and a blue pixel for implementing colors. Each pixel P can also include a white pixel. Each pixel P includes a pixel circuit.

[0049] A touch sensor may be provided on the display panel 100. Touch input may be sensed using a separate touch sensor or by the pixel P. The touch sensor may be provided on the screen of the display panel in an on-cell type or an add-on type, or implemented as an in-cell type touch sensor to be embedded in the display panel 100.

[0050] The controller 200 processes the image data RGB input from the outside to a size and resolution suitable for the display panel 100 and provides the processed image data to the data driver 400. The controller 200 uses the synchronization signals (e.g., the dot clock signal CLK, the data enable signal DE, the horizontal synchronization signal Hsync, and the vertical synchronization signal Vsync) input from the outside to generate the gate control signal GCS and the data control signal DCS. The generated gate control signal GCS and data control signal DCS are provided to the gate driver 300 and the data driver 400, respectively, to control the gate driver 300 and the data driver 400.

[0051] The controller 200 may be configured to be coupled with various processors such as a microprocessor, a mobile processor, or an application processor, depending on the device to be installed.

[0052] The host system may be any one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, and a vehicle system.

[0053] The controller 200 multiplies the input frame rate by i and can control the operation timing of the display panel driver using the frame rate Hz of the input frame rate xi (i is a positive integer greater than 0). The input frame rate is 60 Hz in the National Television Standards Committee (NTSC) standard and 50 Hz in the Phase Alternation Line (PAL) standard.

[0054] The controller 200 generates signals that allow the pixels P to be driven at various refresh rates. That is, the controller 200 generates signals associated with driving to allow the pixels P to be driven in a variable refresh rate (VRR) mode or to be switchable between a first refresh rate and a second refresh rate. For example, the controller 200 can drive the pixels P at various refresh rates by simply changing the rate of the clock signal, or generating a synchronization signal to generate horizontal blanking or vertical blanking, or driving the gate driver 300 in a masked manner.

[0055] The controller 200 generates a gate control signal GCS for controlling the operation timing of the gate driver 300 and a data control signal DCS for controlling the operation timing of the data driver 400 based on the timing signals Vsync, Hsync, and DE received from the host system. The controller 200 controls the operation timing of the display panel driver to synchronize the gate driver 300 and the data driver 400.

[0056] The voltage level of the gate control signal GCS output from the controller 200 is converted into gate-on voltages VGL and VEL and gate-off voltages VGH and VEH by a level shifter (not shown) so as to be provided to the gate driver 300. The level shifter converts the low-level voltage of the gate control signal GCS into the gate low voltage VGL and converts the high-level voltage of the gate control signal GCS into the gate high voltage VGH. The gate control signal GCS includes a start pulse and a shift clock.

[0057] The gate driver 300 provides the scan signal SC to the gate line GL according to the gate control signal GCS provided from the controller 200. The gate driver 300 may be provided on one side or both sides of the display panel 100 in a gate-in-panel (GIP) manner.

[0058] The gate driver 300 sequentially outputs gate signals to the plurality of gate lines GL under the control of the controller 200. The gate driver 300 shifts the gate signals using a shift register to sequentially provide the signals to the gate lines GL.

[0059] The gate signal may include a scan signal SC and an emission control signal EM in an organic light-emitting display device. The scan signal SC includes a scan pulse that swings between a gate-on voltage VGL and a gate-off voltage VGH. The emission control signal EM may include an emission control signal pulse that swings between a gate-on voltage VGL and a gate-off voltage VGH.

[0060] The scan pulse is synchronized with the data voltage Vdata to select the pixels P of the row where data is written. The emission control signal EM defines the emission time of the pixels P.

[0061] The gate driver 300 may include an emission control signal driver 310 and at least one or more scan drivers 320 .

[0062] The emission control signal driver 310 outputs an emission control signal pulse in response to a start pulse and a shift clock from the controller 200 , and sequentially shifts the emission control signal pulse according to the shift clock.

[0063] At least one or more scan drivers 320 output a scan pulse in response to a start pulse and a shift clock from the controller 200 and shift the scan pulse according to the shift clock timing.

[0064] The data driver 400 converts the image data RGB into data voltages Vdata according to the data control signal DCS supplied from the controller 200 and supplies the converted data voltages Vdata to the pixels P through the data lines DL.

[0065] Despite Figure 11 and 2 show that one data driver 400 is disposed on one side of the display panel 100 , but the number of the data drivers 400 and their placement positions are not limited thereto.

[0066] That is, the data driver 400 is composed of a plurality of integrated circuits IC divided into a plurality of parts on one side of the display panel 100 .

[0067] The power supply unit 500 uses a DC-DC converter to generate the DC power required to drive the pixel array and display panel driver of the display panel 100. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply unit 500 receives a DC input voltage applied from a host system (not shown) to generate DC voltages such as gate-on voltages VGL and VEL, gate-off voltages VGH and VEH, a high-potential drive voltage EVDD, and a low-potential drive voltage EVSS. The gate-on voltages VGL and VEL and the gate-off voltages VGH and VEH are provided to a level shifter and gate driver 300 (not shown). The high-potential drive voltage EVDD and the low-potential drive voltage EVSS are jointly provided to the pixels P.

[0068] Figure 2 is a cross-sectional view illustrating a stacked shape of a display device according to an exemplary embodiment.

[0069] refer to Figure 2 , Figure 2 is a cross-sectional view of a device including two switching thin film transistors TFT1 and TFT2 and a storage capacitor CST. The two thin film transistors TFT1 and TFT2 include either a switching thin film transistor or a driving transistor containing a polycrystalline semiconductor material, and an oxide thin film transistor TFT2 containing an oxide semiconductor material. In this case, the thin film transistor containing a polycrystalline semiconductor material is referred to as a polycrystalline thin film transistor TFT1, and the thin film transistor containing an oxide semiconductor material is referred to as an oxide thin film transistor TFT2.

[0070] Figure 2 The illustrated polycrystalline thin film transistor TFT1 is an emission switching thin film transistor connected to the light emitting diode OLED, and the oxide thin film transistor TFT2 is any one switching thin film transistor connected to the storage capacitor CST.

[0071] Each pixel P includes a light-emitting diode (OLED) and a pixel driving circuit that applies a driving current to the light-emitting diode (OLED). The pixel driving circuit is disposed on a substrate 111, and the light-emitting diode (OLED) is disposed on the pixel driving circuit. An encapsulation layer 120 is disposed on the light-emitting diode (OLED). The encapsulation layer 120 protects the light-emitting diode (OLED).

[0072] The pixel driving circuit may refer to a pixel (P) array unit including a driving thin film transistor, a switching thin film transistor and a capacitor. The light emitting diode OLED may refer to an array unit including an anode electrode, a cathode electrode and an emission layer disposed between the anode electrode and the cathode electrode to emit light.

[0073] In one exemplary embodiment, the driver thin film transistor and at least one switching thin film transistor use oxide semiconductors as their active layers. Thin film transistors using oxide semiconductor materials as their active layers have excellent leakage current blocking effects and are more cost-effective to manufacture than thin film transistors using polycrystalline semiconductor materials as their active layers. Therefore, to reduce power consumption and manufacturing costs, a pixel driver circuit according to an exemplary embodiment includes a driver thin film transistor and at least one switching thin film transistor using oxide semiconductor materials.

[0074] All thin film transistors constituting the pixel driving circuit may be implemented using an oxide semiconductor material, or only some switching thin film transistors may be implemented using an oxide semiconductor material.

[0075] However, it is difficult to ensure the reliability of thin film transistors using oxide semiconductor materials, but thin film transistors using polycrystalline semiconductor materials have fast operating speeds and excellent reliability. Therefore, exemplary embodiments include both switching thin film transistors using oxide semiconductor materials and switching thin film transistors using polycrystalline semiconductor materials.

[0076] The substrate 111 may be configured as a multilayer structure in which organic films and inorganic films are alternately stacked. For example, in the substrate 111, an organic film such as polyimide and an inorganic film such as silicon oxide (SiO2) may be alternately stacked.

[0077] A lower buffer layer 112a is provided on the substrate 111. The lower buffer layer 112a is provided to block moisture and the like from penetrating from the outside, and can be used by stacking a plurality of silicon oxide (SiO2) films. An auxiliary buffer layer 112b may be further provided on the lower buffer layer 112a to protect the element from moisture penetration.

[0078] The polycrystalline thin film transistor TFT1 is formed on the substrate 111. The polycrystalline thin film transistor TFT1 may use a polycrystalline semiconductor as an active layer and includes a first active layer ACT1 having a channel through which electrons or holes move, a first gate electrode GE1, a first source electrode SD1, and a first drain electrode SD2.

[0079] The first active layer ACT1 includes a first channel region, a first source region disposed on one side of the first channel region, and a first drain region disposed on the other side thereof. The first source region and the first drain region are provided with the first channel region located therebetween.

[0080] The first source region and the first drain region are regions where an intrinsic polycrystalline semiconductor material is doped with a predetermined concentration of Group 5 or Group 3 impurity ions (e.g., phosphorus (P) or boron (B)) to conduct electricity. In the first channel region, the polycrystalline semiconductor material remains in an intrinsic state and provides a path through which electrons or holes move.

[0081] Meanwhile, the polycrystalline thin film transistor TFT1 includes a first gate electrode GE1 overlapping the first channel region of the first active region ACT1. A first gate insulating layer 113 is provided between the first gate electrode GE1 and the first active layer ACT1. The first gate insulating layer 113 can be formed by stacking an inorganic layer (e.g., a silicon oxide (SiO2) film or a silicon nitride (SiNx)) as a single layer or multiple layers.

[0082] In an exemplary embodiment, the polycrystalline thin-film transistor TFT1 has a top-gate structure in which the first gate electrode GE1 is located above the first active layer ACT1. Therefore, the first electrode CST1 included in the storage capacitor CST and the light shielding layer LS included in the oxide thin-film transistor TFT2 can be formed of the same material as the first gate electrode GE1. The first gate electrode GE1, the first electrode CST1, and the light shielding layer LS are formed using a single mask process, thereby reducing the number of mask processes.

[0083] The first gate electrode GE1 is made of a metal material. For example, the first gate electrode GE1 may be a single layer or multiple layers formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof, but is not limited thereto.

[0084] A first interlayer insulating layer 114 is disposed on the first gate electrode GE1 and may be formed of silicon oxide (SiO 2 ) or silicon nitride (SiNx).

[0085] The display panel 100 may further include an upper buffer layer 115, a second gate insulating layer 116, and a second interlayer insulating layer 117 sequentially disposed on the first interlayer insulating layer 114. The polycrystalline thin film transistor TFT1 includes a first source electrode SD1 and a first drain electrode SD2 formed on the second interlayer insulating layer 117 and connected to the first source region and the first drain region, respectively.

[0086] The first source electrode SD1 and the first drain electrode SD2 may be formed of a single layer or multiple layers formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof, but are not limited thereto.

[0087] The upper buffer layer 115 separates the second active layer ACT2 of the oxide thin film transistor TFT2 implemented with an oxide semiconductor material from the first active layer ACT1 implemented with a polycrystalline semiconductor material, and provides a base for forming the second active layer ACT2 .

[0088] The second gate insulating layer 116 covers the second active layer ACT2 of the oxide thin film transistor TFT2. The second gate insulating layer 116 is formed on the second active layer ACT2 implemented by the oxide semiconductor material, so that the second gate insulating layer is implemented by an inorganic film. For example, the second gate insulating layer 116 can be silicon oxide SiO2 or silicon nitride SiNx.

[0089] The second gate electrode GE2 is made of a metal material. For example, the second gate electrode GE2 may be a single layer or multiple layers formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof, but is not limited thereto.

[0090] Meanwhile, the oxide thin film transistor TFT2 includes a second active layer ACT2 formed on the upper buffer layer 115 and implemented with an oxide semiconductor material, a second gate electrode GE2 disposed on the second gate insulating layer 116, and a second source electrode SD3 and a second drain electrode SD4. The second source electrode SD3 and the second drain electrode SD4 are disposed on the second interlayer insulating layer 117.

[0091] The second active layer ACT2 includes an intrinsic second channel region which is implemented by an oxide semiconductor material and is not doped with impurities, and second source and second drain regions which are doped with impurities to become conductive.

[0092] The oxide thin-film transistor TFT2 further includes a light-shielding layer LS located below the upper buffer layer 115 and overlapping the second active layer ACT2. The light-shielding layer LS blocks light incident on the second active layer ACT2 to ensure the reliability of the oxide thin-film transistor TFT2. The light-shielding layer LS is formed of the same material as the first gate electrode GE1 and may be formed on the upper surface of the first gate insulating film 113. The light-shielding layer LS is electrically connected to the second gate electrode GE2 to form a dual-gate structure.

[0093] The second source electrode SD3 and the second drain electrode SD4 are simultaneously formed of the same material as the first source electrode SD1 and the first drain electrode SD2 on the second interlayer insulating layer 117 to reduce the number of mask processes.

[0094] Meanwhile, the second electrode CST2 is disposed on the first interlayer insulating layer 114 so as to overlap with the first electrode CST1, thereby implementing a storage capacitor CST. For example, the second electrode CST2 may be a single layer or a multilayer formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0095] The storage capacitor CST stores a data voltage applied through the data line DL for a predetermined period of time and then supplies the data voltage to the light emitting diode OLED. The storage capacitor CST includes two corresponding electrodes and a dielectric material disposed therebetween. A first interlayer insulating layer 114 is located between the first electrode CST1 and the second electrode CST2.

[0096] The first electrode CST1 or the second electrode CST2 of the storage capacitor CST may be electrically connected to the second source electrode SD3 or the second drain electrode SD4 of the oxide thin film transistor TFT2. However, this is not limited thereto, and the connection relationship of the storage capacitor CST may vary depending on the pixel driving circuit.

[0097] Meanwhile, a first planarization layer 118 and a second planarization layer 119 are sequentially disposed on the pixel driving circuit to flatten the upper end of the pixel driving circuit. The first planarization layer 118 and the second planarization layer 119 may be organic films such as polyimide or acrylic resin.

[0098] A light emitting diode OLED is formed on the second planarization layer 119 .

[0099] The light emitting diode OLED includes an anode electrode ANO, a cathode electrode CAT, and an emission layer EL disposed between the anode electrode ANO and the cathode electrode CAT. If a pixel driving circuit that generally uses a low potential voltage connected to the cathode electrode CAT is implemented, the anode electrode ANO is provided as a separate electrode in each sub-pixel. If a pixel driving circuit that generally uses a high potential voltage is implemented, the cathode electrode CAT may be provided as a separate electrode in each sub-pixel.

[0100] The light emitting diode OLED is electrically connected to the driving element through the intermediate electrode CNE provided on the first planarization layer 118. Specifically, the anode electrode ANO of the light emitting diode OLED and the first source electrode SD1 of the polycrystalline thin film transistor TFT1 constituting the pixel driving circuit are connected to each other through the intermediate electrode CNE.

[0101] The anode electrode ANO is connected to the intermediate electrode CNE exposed through a contact hole passing through the second planarization layer 119. In addition, the intermediate electrode CNE is connected to the first source electrode SD1 exposed through a contact hole passing through the first planarization layer 118.

[0102] The intermediate electrode CNE serves as a medium connecting the first source electrode SD1 and the anode electrode ANO. The intermediate electrode CNE may be formed of a conductive material, such as copper (Cu), silver (Ag), molybdenum (Mo), or titanium (Ti).

[0103] The anode electrode ANO can be formed to have a multilayer structure including a transparent conductive film and an opaque conductive film with high reflection efficiency. The transparent conductive film is made of a material with a relatively high work function, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The opaque conductive film can be configured to include a single layer or multilayer structure of aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti) or an alloy thereof. For example, the anode electrode ANO can be formed to have a structure in which a transparent conductive film, an opaque conductive film and a transparent conductive film are stacked in sequence, or the anode electrode ANO can be formed to have a structure in which a transparent conductive film and an opaque conductive film are stacked in sequence.

[0104] The emission layer EL may be formed by stacking a hole-related layer, an organic emission layer, and an electron-related layer on the anode electrode ANO in this order or in a reverse order.

[0105] The bank layer BNK may be a pixel-defining film that exposes the anode electrode ANO of each pixel P. The bank layer BNK may be formed of an opaque material (e.g., black) to suppress light interference between adjacent pixels P. In this case, the bank layer BNK includes a light-shielding material formed of at least any one of a color pigment, organic black, and carbon. A spacer may be further provided on the bank layer BNK.

[0106] The cathode electrode CAT is formed on the top and side surfaces of the emission layer EL so as to be opposite to the anode electrode ANO, with the emission layer EL located between the cathode electrode CAT and the anode electrode ANO. The cathode electrode CAT may be integrally formed over the entire active area AA. When the cathode electrode CAT is applied to a top-emission organic light-emitting display device, the cathode electrode may be formed of a transparent conductive film, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0107] An encapsulation layer 120 may be further disposed on the cathode electrode CAT to suppress moisture penetration.

[0108] The encapsulation layer 120 can prevent moisture or oxygen from penetrating into the light-emitting diode OLED, which is susceptible to moisture or oxygen from the outside. To this end, the encapsulation layer 120 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer, but is not limited thereto. In the present disclosure, the structure of the encapsulation layer 120 in which the first encapsulation layer 121, the second encapsulation layer 122, and the third encapsulation layer 123 are sequentially stacked will be described as an example.

[0109] The first encapsulating layer 121 is formed on the substrate 111 on which the cathode electrode CAT is formed. The third encapsulating layer 123 is formed on the substrate 111 on which the second encapsulating layer 122 is formed, and together with the first encapsulating layer 121, surrounds the top surface, bottom surface, and side surface of the second encapsulating layer 122. The first encapsulating layer 121 and the third encapsulating layer 123 can minimize or inhibit the penetration of external moisture or oxygen into the light-emitting diode OLED. The first encapsulating layer 121 and the third encapsulating layer 123 can be formed of an inorganic insulating material on which low-temperature deposition is allowed, such as silicon nitride SiNx, silicon oxide SiOx, silicon oxynitride SiON, or aluminum oxide Al2O3. The first encapsulating layer 121 and the third encapsulating layer 123 are deposited in a low-temperature atmosphere, so that damage to the light-emitting diode OLED, which is susceptible to high-temperature atmospheres, can be suppressed during the deposition process of the first encapsulating layer 121 and the third encapsulating layer 123.

[0110] The second encapsulating layer 122 acts as a buffer that reduces stress between layers caused by the bending of the display device 10 and can flatten the steps between the layers. The second encapsulating layer 122 can be formed on the substrate 111 on which the first encapsulating layer 121 is formed, using acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin and polyethylene, or a non-photosensitive organic insulating material (such as silicon oxycarbide (SiOC)) or a photosensitive organic insulating material (such as photoacryl), but is not limited thereto. When the second encapsulating layer 122 is formed using an inkjet method, a dam DAM can be provided to prevent the liquefied second encapsulating layer 122 from spreading to the edge of the substrate 111. The dam DAM can be provided closer to the edge of the substrate 111 than the second encapsulating layer 122. The dam DAM can prevent the second encapsulating layer 122 from spreading into the pad area, where a conductive pad provided at the outermost periphery of the substrate 111 is provided.

[0111] The dam DAM is designed to suppress diffusion of the second encapsulating layer 122. However, when the second encapsulating layer 122 is formed to exceed the height of the dam DAM during processing, the second encapsulating layer 122, which is an organic layer, may be exposed to the outside, so that moisture, etc. may easily penetrate into the light-emitting diode. Therefore, to avoid the above problem, at least ten dams DAM may be repeatedly formed.

[0112] A dam DAM may be disposed on the second interlayer insulating layer 117 of the non-active area NA.

[0113] In addition, the dam DAM may be formed simultaneously with the first planarization layer 118 and the second planarization layer 119. When the first planarization layer 118 is formed, the lower layer of the dam DAM is formed together, and when the second planarization layer 119 is formed, the upper layer of the dam DAM is formed together, so that the dam DAM may be stacked to have a double-layer structure.

[0114] Therefore, the dam DAM may be made of the same material as the first planarization layer 118 and the second planarization layer 119 , but is not limited thereto.

[0115] The dam DAM may be provided to overlap with the low potential driving power line VSS. For example, the low potential driving power line VSS may be formed on a lower layer of the area where the dam DAM is located in the non-display area NA.

[0116] The low-potential drive power line VSS and the gate driver 300 configured in a gate-in-panel (GIP) manner are formed to surround the periphery of the display panel, and the low-potential drive power line VSS can be located on the periphery further out than the gate driver 300. In addition, the low-potential drive power line VSS is connected to the cathode electrode CAT to apply a common voltage. Although the gate driver 300 is simply shown in the plan view and the cross-sectional view, the gate driver 300 can also be configured using thin film transistors having the same structure as the thin film transistors in the active area AA.

[0117] The low potential driving power line VSS is provided at a position further outward from the gate driver 300. The low potential driving power line VSS is provided at a position further outward from the gate driver 300 and surrounds the active area AA. For example, the low potential driving power line VSS may be formed of the same material as the first gate electrode GE1, but is not limited thereto, and may be formed of the same material as the second electrode CST2 or the first source electrode SD1 and the first drain electrode SD2, but is not limited thereto.

[0118] In addition, a low potential driving power line VSS may be electrically connected to the cathode electrode CAT. The low potential driving power line VSS may provide a low potential driving voltage EVSS to the plurality of pixels P of the active area AA.

[0119] The touch layer may be disposed on the encapsulation layer 120. The touch buffer film 151 may be disposed between the touch sensor metal including the touch electrode connection lines 152 and 154 and the touch electrodes 155 and 156 on the touch layer and the cathode electrode CAT of the light emitting diode OLED.

[0120] The touch buffer film 151 can prevent chemical solutions (developers or etchants) or moisture, etc., used in the manufacturing process of the touch sensor metal provided on the touch buffer film 151 from penetrating from the outside into the emission layer EL including the organic material. By doing so, the touch buffer film 151 can prevent damage to the emission layer EL, which is susceptible to chemical solutions or moisture.

[0121] The touch buffer film 151 can be formed of an organic insulating material formed at a temperature below a predetermined temperature (e.g., 10°C) to suppress damage to the emission layer EL, which includes organic materials susceptible to high temperatures. The organic insulating material has a low dielectric constant of 1 to 3. For example, the touch buffer film 151 can be formed of an acrylic, epoxy, or siloxane-based material. The touch buffer film 151, formed of an organic insulating material and having planarization properties, can suppress damage to the encapsulation layer 120 caused by bending of the organic light-emitting display device and fracture of the touch sensor metal formed on the touch buffer film 151.

[0122] According to a touch sensor structure based on mutual capacitance, the touch electrodes 155 and 156 are disposed on the touch buffer film 151 , and the touch electrodes 155 and 156 may be alternately disposed.

[0123] The touch electrode connection lines 152 and 154 may electrically connect the touch electrodes 155 and 156. The touch electrode connection lines 152 and 154 and the touch electrodes 155 and 156 may be provided on different layers with a touch insulation film 153 therebetween.

[0124] The touch electrode connection lines 152 and 154 are disposed to overlap with the bank layer BNK to suppress a decrease in aperture ratio.

[0125] Meanwhile, in the touch electrodes 155 and 156 , a portion of the touch electrode connection line 152 passes through the upper portion and side surface of the encapsulation layer 120 and the upper portion and side surface of the dam DAM to be electrically connected to a touch driving circuit (not shown) through the touch pad PAD.

[0126] The above touch pad PAD may have a multi-layer structure in which the same layer as the first gate electrode GE1 and the same layer as the first source electrode SD1 and the first drain electrode SD2 are stacked, but is not limited thereto and the structure of the touch pad PAD may vary.

[0127] A portion of the touch electrode connection lines 152 and 154 is provided with a touch drive signal from a touch drive circuit to transmit the touch drive signal to the touch electrodes 155 and 156, and a portion of the touch electrode connection lines 152 and 154 can transmit the touch sensing signal in the touch electrodes 155 and 156 to the touch drive circuit.

[0128] That is, portions of the touch electrode connection lines 152 and 154 disposed in the non-active area NA may have a double-line structure to have the touch insulation film 153 disposed therebetween.

[0129] The touch protection film 157 may be provided on the touch electrodes 155 and 156. In the drawings, although the touch protection film 157 is shown to be provided only on the touch electrodes 155 and 156, it is not limited thereto and extends before and after the dam DAM to be provided on the touch electrode connection line 152.

[0130] A color filter (not shown) may be further disposed on the encapsulation layer 120 , and the color filter may be disposed on the touch layer or between the encapsulation layer 120 and the touch layer.

[0131] Figure 3 is a diagram of a configuration of a gate driver in a display device according to an exemplary embodiment of the present disclosure.

[0132] refer to Figure 3 The gate driver 300 is composed of an emission control signal driver 310 and a scan driver 320. The scan driver 320 may be composed of first to fourth scan drivers 321, 322, 323, and 324. In addition, the second scan driver 322 may be composed of an odd-numbered second scan driver 322_O and an even-numbered second scan driver 322_E.

[0133] In the gate driver 300, the shift registers may be symmetrically arranged on both sides of the active area AA. Furthermore, in the gate driver 300, the shift registers on one side of the active area AA include the second scan drivers 322_O and 322_E, the fourth scan driver 324, and the emission control signal driver 310. The shift registers on the other side of the active area AA include the first scan driver 321, the second scan drivers 322_O and 322_E, and the third scan driver 323. However, the present disclosure is not limited thereto. According to exemplary embodiments, the emission control signal driver 310 and the first to fourth scan drivers 321, 322, 323, and 324 may be arranged in a different manner.

[0134] Each of the levels STG(1) to STG(n) of the shift register may include each of the first scan signal generator SC1(1) to SC1(n), the second scan signal generator SC2_O(1) to SC2_O(n), SC2_E(1) to SC2_E(n), the third scan signal generator SC3(1) to SC3(n), the fourth scan signal generator SC4(1) to SC4(n) and the emission control signal generator EM(1) to EM(n).

[0135] The first scan signal generators SC1(1) to SC1(n) output first scan signals SC1(1) to SC1(n) through the first gate line SCL1 of the display panel 100. The second scan signal generators SC2_O(1) to SC2_O(n) and SC2_E(1) to SC2_E(n) output second scan signals SC2(1) to SC2(n) through the second gate line SCL2 of the display panel 100. The third scan signal generators SC3(1) to SC3(n) output third scan signals SC3(1) to SC3(n) through the third gate line SCL3 of the display panel 100. The fourth scan signal generators SC4(1) to SC4(n) output fourth scan signals SC4(1) to SC4(n) through the fourth gate line SCL4 of the display panel 100. The emission control signal generators EM(1) to EM(n) output emission control signals EM(1) to EM(n) through the emission control line EML of the display panel 100.

[0136] Specifically, the odd-numbered second scan signal generators SC2_O(1) to SC2_O(n) output the second scan signals SC2(1) to SC2(n) to the odd-numbered pixel rows. Furthermore, the even-numbered second scan signal generators SC2_E(1) to SC2_E(n) output the second scan signals SC2(1) to SC2(n) to the even-numbered pixel rows. The same second scan signals SC2(1) to SC2(n) may be applied to odd-numbered pixel rows and even-numbered pixel rows adjacent to each other.

[0137] The first scan signals SC1(1) to SC1(n) can be used as signals for driving the Ath transistor (e.g., compensation transistor) included in the pixel circuit. The second scan signals SC2(1) to SC2(n) can be used as signals for driving the Bth transistor (e.g., data providing transistor) included in the pixel circuit. The third scan signals SC3(1) to SC3(n) can be used as signals for driving the Cth transistor (e.g., bias transistor) included in the pixel circuit. The fourth scan signals SC4(1) to SC4(n) can be used as signals for driving the Dth transistor (e.g., initialization transistor) included in the pixel circuit. The emission control signals EM(1) to EM(n) can be used as signals for driving the Eth transistor (e.g., emission control transistor) included in the pixel circuit. For example, when the emission control transistor of the pixel is controlled using the emission control signals EM(1) to EM(n), the emission time of the light emitting diode is variable.

[0138] refer to Figure 3 , a bias voltage bus VobsL, a first initialization voltage bus VarL, and a second initialization voltage bus ViniL may be provided between the gate driver 300 and the active area AA.

[0139] The bias voltage bus VobsL, the first initialization voltage bus VarL, and the second initialization voltage bus ViniL may provide the bias voltage Vobs, the first initialization voltage Var, and the second initialization voltage Vini from the power supply unit 500 to the pixel circuit.

[0140] In the accompanying drawings, the bias voltage bus VobsL, the first initialization voltage bus VarL, and the second initialization voltage bus ViniL are shown as being disposed only on one side, either the left side or the right side, of the active area AA. However, the present disclosure is not limited thereto and the bias voltage bus VobsL, the first initialization voltage bus VarL, and the second initialization voltage bus ViniL may be disposed on both sides. Furthermore, even if the bias voltage bus VobsL, the first initialization voltage bus VarL, and the second initialization voltage bus ViniL are disposed on one side, the left side or the right side is not limited thereto.

[0141] refer to Figure 3 In the active area AA, one or more optical areas OA1 and OA2 may be provided.

[0142] The one or more optical areas OA1 and OA2 may be provided to overlap with one or more optical electronic devices, such as an image capturing device such as a camera (image sensor) and a detection sensor such as a proximity sensor and an illumination sensor.

[0143] In one or more optical areas OA1 and OA2, the light-transmitting structure is formed to have a transmittance at a predetermined level or higher for operation of the optical electronic device. That is, the number of pixels P per unit area in the one or more optical areas OA1 and OA2 may be smaller than the number of pixels P per unit area in the active area AA, that is, smaller than the number of pixels P per unit area in a general area excluding the optical areas OA1 and OA2. That is, the resolution of the one or more optical areas OA1 and OA2 may be lower than the resolution of the general area in the active area AA.

[0144] The light-transmitting structure in one or more optical areas OA1 and OA2 may be configured by patterning a cathode electrode in a portion where no pixel P is provided. At this time, the cathode electrode to be patterned may be removed using a laser, or may be selectively formed using a material such as a cathode deposition stop layer.

[0145] Furthermore, in one or more optical areas OA1 and OA2, a light-transmitting structure can be configured by separately forming a light-emitting diode (OLED) and a pixel circuit in a pixel P. Specifically, the light-emitting diode (OLED) of the pixel P is located in the optical areas OA1 and OA2, and the plurality of transistors (TFTs) constituting the pixel circuit are disposed near the optical areas OA1 and OA2. Thus, the light-emitting diode (OLED) and the pixel circuit can be electrically connected via a transparent metal layer.

[0146] Figure 4 is a diagram for illustrating a pixel circuit in a display device according to an exemplary embodiment of the present disclosure.

[0147] Figure 4 The pixel circuit for description is shown as an example, and there is no particular limitation, as long as the structure can control the emission of the light-emitting diode ED by applying the EM signal EM(n). For example, the pixel circuit may include an additional scanning signal, a switching thin film transistor connected thereto, and a switching thin film transistor to which an additional initialization voltage is applied. In addition, the connection relationship of the switching element or the connection position of the capacitor can be set in various ways. In the following, for the convenience of description, the pixel circuit with Figure 4 A display device with a pixel circuit structure.

[0148] refer to Figure 4 , each of the plurality of pixels P may include a pixel circuit having a driving transistor DT and a light emitting diode ED connected to the pixel circuit.

[0149] The pixel circuit controls a driving current flowing through the light-emitting diode ED to drive the light-emitting diode ED. The pixel circuit may include a driving transistor DT, first to seventh transistors T1 to T7, and a storage capacitor Cst. Each of the transistors DT, T1 to T7 may include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other of the first electrode and the second electrode may be a drain electrode.

[0150] Each of the transistors DT, T1 to T7 may be a P-type thin film transistor or an N-type thin film transistor. Figure 4 In the exemplary embodiment of the present invention, the first transistor T1 and the seventh transistor T7 are N-type thin film transistors, and the remaining transistors DT, T2 to T6 are P-type thin film transistors. However, this is not limited to this, and according to exemplary embodiments, all or some of the transistors DT, T1 to T7 may be P-type thin film transistors or N-type thin film transistors. In addition, the N-type thin film transistor may be an oxide thin film transistor, and the P-type thin film transistor may be a polysilicon thin film transistor.

[0151] Hereinafter, it is illustrated that the first transistor T1 and the seventh transistor T7 are N-type thin film transistors, and the remaining transistors DT, T2 to T6 are P-type thin film transistors. Therefore, a high voltage is applied to the first transistor T1 and the seventh transistor T7 to be turned on, and a low voltage is applied to the remaining transistors D1, T2 to T6 to be turned on.

[0152] According to an exemplary embodiment, the first transistor T1 constituting the pixel circuit may be used as a compensation transistor, the second transistor T2 may be used as a data supply transistor, the third transistor T3 and the fourth transistor T4 may be used as emission control transistors, and the fifth transistor T5 may be used as a bias transistor. In addition, the sixth transistor T6 and the seventh transistor T7 may be used as initialization transistors.

[0153] The light emitting diode ED may include an anode electrode and a cathode electrode. The anode electrode of the light emitting diode ED may be connected to the fifth node N5, and the cathode electrode may be connected to the low potential driving voltage EVSS.

[0154] The driving transistor DT may include a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a gate electrode connected to the first node N1. The driving transistor DT may provide a driving current Id to the light emitting diode ED based on a voltage of the first node N1 (or a data voltage stored in the storage capacitor Cst described below).

[0155] The first transistor T1 may include a first electrode connected to the first node N1, a second electrode connected to the third node N3, and a gate electrode that receives a first scan signal SC1(n). The first transistor T1 is turned on in response to the first scan signal SC1(n) and is diode-connected between the first node N1 and the third node N3 to sample a threshold voltage Vth of the drive transistor DT. Such a first transistor T1 may be a compensation transistor.

[0156] The storage capacitor Cst may be connected or formed between the first node N1 and the fourth node N4. The storage capacitor Cst may store or maintain the supplied high-potential driving voltage EVDD.

[0157] The second transistor T2 may include a first electrode connected to the data line DL (or receiving the data voltage Vdata), a second electrode connected to the second node N2, and a gate electrode receiving the second scan signal SC2(n). The second transistor T2 is turned on in response to the second scan signal SC2(n) and may transmit the data voltage Vdata to the second node N2. Such a second transistor T2 may be a data supply transistor.

[0158] The third transistor T3 and the fourth transistor T4 (or the first emission control transistor and the second emission control transistor) are connected between the high potential driving voltage EVDD and the light emitting diode EL and may form a current moving path through which the driving current ID generated by the driving transistor DT moves.

[0159] The third transistor T3 may include a first electrode connected to the fourth node N4 to receive the high potential driving voltage EVDD, a second electrode connected to the second node N2, and a gate electrode receiving the emission control signal EM(n).

[0160] The fourth transistor T4 may include a first electrode connected to the third node N3, a second electrode connected to the fifth node N5 (or the anode electrode of the light emitting diode ED), and a gate electrode receiving the emission control signal EM(n).

[0161] The third transistor T3 and the fourth transistor T4 are turned on in response to the emission control signal EM(n), and in this case, the driving current Id is supplied to the light emitting diode ED, and the light emitting diode ED may emit light having brightness corresponding to the driving current Id.

[0162] The fifth transistor T5 may include a first electrode receiving the bias voltage Vobs, a second electrode connected to the second node N2, and a gate electrode receiving the third scan signal SC3(n). Such a fifth transistor T5 may be a bias transistor.

[0163] The sixth transistor T6 may include a first electrode receiving the first initialization voltage Var, a second electrode connected to the fifth node N5, and a gate electrode receiving the third scan signal SC3(n).

[0164] Before the light-emitting diode ED emits light (or after the light-emitting diode ED emits light), the sixth transistor T6 is turned on in response to the third scan signal SC3(n) and can initialize the anode electrode (or pixel electrode) of the light-emitting diode ED using the first initialization voltage Var. The light-emitting diode ED may have a parasitic capacitor formed between the anode electrode and the cathode electrode. When the light-emitting diode ED emits light, the parasitic capacitor is charged, so that the anode electrode of the light-emitting diode ED can have a specific voltage. Therefore, the first initialization voltage Var is applied to the anode electrode of the light-emitting diode ED through the sixth transistor T6 to initialize the amount of charge accumulated in the light-emitting diode ED.

[0165] In the present disclosure, the gate electrodes of the fifth transistor T5 and the sixth transistor T6 are configured to receive the third scan signal SC3(n) in common. However, the present disclosure is not necessarily limited thereto, and the gate electrodes of the fifth transistor T5 and the sixth transistor T6 may be configured to receive separate scan signals to be independently controlled.

[0166] The seventh transistor T7 may include a first electrode receiving the second initialization voltage Vini, a second electrode connected to the first node N1, and a gate electrode receiving the fourth scan signal SC4(n).

[0167] The seventh transistor T7 is turned on in response to the fourth scan signal SC4(n) and can initialize the gate electrode of the driving transistor DT using the second initialization voltage Vini. Unnecessary charge may remain in the gate electrode of the driving transistor DT due to the high potential driving voltage EVDD stored in the storage capacitor Cst. Therefore, the second initialization voltage Vini is applied to the gate electrode of the driving transistor DT through the seventh transistor T7 to initialize the amount of residual charge.

[0168] Figure 5A and Figure 5B Is used to illustrate Figure 4 A diagram showing the operation of scan signals and emission control signals in a pixel circuit in a refresh period and a hold period.

[0169] The display device according to an exemplary embodiment of the present disclosure can be operated as a variable refresh rate (VRR) mode display device. In VRR mode, pixels are driven at a constant frequency, and when high-speed driving is required, the refresh rate of the update data voltage Vdata is increased to operate the pixels, or when power consumption needs to be reduced or low-speed driving is required, the refresh rate is reduced to operate the pixels.

[0170] Each of the plurality of pixels P can be driven by a combination of a refresh frame and a hold frame within one second. In the present disclosure, a setup is defined in which a combination of a refresh period in which the data voltage Vdata is updated and a hold period in which the data voltage Vdata is not updated repeats within one second. A setup period is a cycle in which the combination of a refresh period and a hold period repeats.

[0171] When the refresh rate is driven at 120 Hz, it can be driven only in the refresh period. That is, the refresh period can be driven 120 times in one second. One refresh period is 1 / 120=8.33 ms, and one setup period is also 8.33 ms.

[0172] When the refresh rate is driven at 60 Hz, the refresh period and the hold period can be driven alternately. That is, the refresh period and the hold period can be driven alternately 60 times each within 1 second. One refresh period and one hold period are each 0.5 / 60 = 8.33 ms, and one setup period is 16.66 ms.

[0173] When the refresh rate is driven at 1 Hz, one frame can be driven with one refresh period and 119 hold periods after the refresh period. In addition, when the refresh rate is driven at 1 Hz, one frame can be driven with multiple refresh periods and multiple hold periods. In this case, one refresh period and one hold period are each 1 / 120 = 8.33 ms, and one setup period is 1 s.

[0174] In the refresh period, the new data voltage Vdata is charged to apply the new data voltage Vdata to the driving transistor DT, and in the hold period, the data voltage Vdata of the previous frame is retained for use as it is. At the same time, in the hold period, the process of applying the new data voltage Vdata to the driving transistor DT is omitted, so that the hold period is also called a skip period.

[0175] Each of the plurality of pixels P may initialize a voltage charged in or retained in the pixel circuit during the refresh period. Specifically, each of the plurality of pixels P may eliminate the influence of the data voltage Vdata and the high potential driving voltage EVDD stored in the previous frame during the refresh period. Therefore, each of the plurality of pixels P may display an image corresponding to the new data voltage Vdata during the hold period.

[0176] During the holding period, each of the plurality of pixels P may supply a driving current corresponding to the data voltage Vdata to the light emitting diode ED to display an image, and may maintain a turn-on state of the light emitting diode ED.

[0177] First, we will describe Figure 5A The refresh period may be operated to include at least one biasing portion Tobs1 and Tobs2, an initialization portion Ti, a sampling portion Ts, and an emission portion Te, but this is merely an exemplary embodiment and is not necessarily limited to this order.

[0178] refer to Figure 5A , the pixel circuit may operate during the refresh period to include at least one bias portion Tobs1 and Tobs2.

[0179] At least one bias portion Tobs1 and Tobs2 is a portion in which an on-bias stress operation OBS is performed to apply a bias voltage Vobs, the emission control signal EM(n) is a high voltage, and the third transistor T3 and the fourth transistor T4 are turned off. The first scan signal SC1(n) and the fourth scan signal SC4(n) are low voltages, and the first transistor T1 and the seventh transistor T7 are turned off. The second scan signal SC2 is a high voltage, and the second transistor T2 is turned off.

[0180] The third scan signal SC3 (n) is input as a low voltage, and the fifth transistor T5 and the sixth transistor T6 are turned on. When the fifth transistor T5 is turned on, the bias voltage Vobs is applied to the first electrode of the driving transistor DT connected to the second node N2.

[0181] Here, applying the bias voltage Vobs to the third node N3 as the drain electrode of the driving transistor DT reduces the charging time or charging delay of the voltage of the fifth node N5 as the anode electrode of the light emitting diode ED in the emission period. The driving transistor DT maintains a stronger saturation state.

[0182] For example, the higher the bias voltage Vobs is, the higher the voltage of the third node N3 as the drain electrode of the driving transistor DT is, and the lower the gate-source voltage or drain-source voltage of the driving transistor DT is. Therefore, the bias voltage Vobs is desirably higher than the data voltage Vdata.

[0183] At this time, the magnitude of the drain-source current Id through the driving transistor DT can be reduced, and in the case of positive bias stress, the stress of the driving transistor DT is reduced to solve the charging delay of the voltage of the third node N3. That is, before the threshold voltage Vth of the driving transistor DT is sampled, the on-bias stress operation OBS is performed to alleviate the hysteresis of the driving transistor DT.

[0184] Therefore, in at least one of the bias parts Tobs1 and Tobs2 , the on-bias stress operation OBS may be defined as an operation of directly applying an appropriate bias voltage to the driving transistor DT during the non-emission period.

[0185] In addition, in at least one of the bias portions Tobs1 and Tobs2 , the sixth transistor T6 is turned on so that the anode electrode (or pixel electrode) of the light emitting diode ED connected to the fifth node N5 is initialized with the first initialization voltage Var.

[0186] However, the gate electrodes of the fifth transistor T5 and the sixth transistor T6 may be configured to receive separate scan signals to be independently controlled. That is, it is not necessary to simultaneously apply bias voltages to the first electrode of the driving transistor DT and the anode electrode of the light emitting diode ED in the biasing section.

[0187] refer to Figure 5A , the pixel circuit may operate during the refresh period to include an initialization section Ti. The initialization section Ti is a section in which the voltage of the gate electrode of the driving transistor DT is initialized.

[0188] The first scan signal SC1(n) to the fourth scan signal SC4(n) and the emission control signal EM(n) are high voltages, and the first transistor T1 and the seventh transistor T7 are turned on. The second to sixth transistors T2, T3, T4, T5, and T6 are turned off. When the first transistor T1 and the seventh transistor T7 are turned on, the gate electrode of the driving transistor DT and the second electrode connected to the first node N1 are initialized with the second initialization voltage Vini.

[0189] refer to Figure 5A , the pixel circuit may operate during the refresh period to include a sampling portion Ts. The sampling portion is a portion that samples the threshold voltage Vth of the driving transistor DT.

[0190] The first scan signal SC1(n), the third scan signal SC3(n), and the emission control signal EM(n) are high voltages, and the second scan signal SC2(n) and the fourth scan signal SC4(n) are low voltages. Therefore, the third to seventh transistors T3, T4, T5, T6, and T7 are turned off, the first transistor T1 remains on, and the second transistor T2 is turned on. That is, the second transistor T2 is turned on to apply the data voltage Vdata to the drive transistor DT, and the first transistor T1 is diode-connected between the first node N1 and the third node N3 to sample the threshold voltage Vth of the drive transistor DT.

[0191] refer to Figure 5A , the pixel circuit may operate during the refresh period to include an emission portion Te. The emission portion Te is a portion in which the sampled threshold voltage Vth is offset and a driving current corresponding to the sampled data voltage allows the light emitting diode ED to emit light.

[0192] The emission control signal EM(n) is a low voltage, and the third transistor T3 and the fourth transistor T4 operate to be turned on.

[0193] When the third transistor T3 is turned on, the high potential driving voltage EVDD connected to the fourth node N4 is applied to the first electrode of the driving transistor DT connected to the second node N2 through the third transistor T3. The driving current Id supplied from the driving transistor DT to the light emitting diode ED via the fourth transistor T4 becomes independent of the value of the threshold voltage Vth of the driving transistor DT, so that the threshold voltage Vth of the driving transistor DT is compensated for operation.

[0194] Next, we will refer to Figure 5B Driving of the pixel circuit and the light emitting diode during the holding period is described.

[0195] The holding period may include at least one bias portion Tobs3 and Tobs4 and an emission portion Te′. The same operation of the pixel circuit as that of the refresh period will not be described.

[0196] As described above, in the refresh period, the new data voltage Vdata is charged to apply the new data voltage Vdata to the gate electrode of the driving transistor DT, but in the hold period, the data voltage Vdata of the refresh period is maintained and used as it is. Therefore, unlike the refresh period, the hold period does not require the initialization part Ti and the sampling part Ts.

[0197] In the operation of the hold period, even a single on-bias stress operation OBS may be sufficient. However, in an exemplary embodiment, for the convenience of the driving circuit, the third scan signal SC3(n) of the hold period is driven identically to the third scan signal SC3(n) of the refresh period, so that the on-bias stress operation OBS can be performed twice as in the refresh period.

[0198] refer to Figure 5A The driving signal in the refresh period described is Figure 5B The difference between the drive signals during the hold period is the second scan signal SC2(n) and the fourth scan signal SC4(n). During the hold period, the initialization portion Ti and the sampling portion Ts are not required. Therefore, unlike the refresh period, the second scan signal SC2(n) is always at a high voltage, and the fourth scan signal SC4(n) is always at a low voltage. That is, the second transistor T2 and the seventh transistor T7 are always turned off.

[0199] Figure 6 is a circuit diagram of one stage of a gate driver of a display device according to an exemplary embodiment of the present disclosure.

[0200] For example, in Figure 6 2 shows a circuit of the fourth scan driver 324 included in each of the plurality of stages of the gate driver. The circuit configuration of the other emission control signal driver 310 and the scan drivers 321, 322, and 323 included in each of the plurality of stages may be the same as that of the fourth scan driver 324. However, this is not limiting, and the circuits of the other emission control signal driver 310 and the scan drivers 321, 322, and 323 may be modified in various forms.

[0201] For example, the first scan driver 321 and the fourth scan driver 324 that generate scan signals for controlling oxide thin film transistors (including oxide semiconductor materials) may have the same structure. In addition, the second scan driver 322 and the third scan driver 323 that generate scan signals for controlling thin film transistors (including polycrystalline semiconductor materials) and the emission control signal driver 310 that generates emission control signals may be designed to have different circuit structures.

[0202] Each of the plurality of fourth scan drivers 324 of the gate driver of the display device according to an exemplary embodiment of the present disclosure includes first to thirteenth transistors Ta to Tm and first to fifth capacitors CQ, CQB, C_on, CQ1, and CS.

[0203] In the first transistor Ta, a first electrode is connected to a gate low voltage (VGL) supply line, a gate electrode is connected to the Q node Q, and a second electrode is connected to the output terminal. Therefore, the first transistor Ta is turned on / off according to the voltage of the Q node Q to output the gate low voltage VGL to the fourth scan signal SC4 as an output.

[0204] In the second transistor Tb, a first electrode is connected to a gate high voltage (VGH) supply line, a gate electrode is connected to the QB node QB, and a second electrode is connected to the output terminal. The second transistor Tb is turned on / off according to the voltage of the QB node QB to output the gate high voltage VGH to the fourth scan signal SC4 as an output.

[0205] In the third transistor Tc, a first electrode is connected to a start signal (VST) input terminal or an output terminal of the fourth scan signal SC4 in the previous stage, a gate electrode is connected to a first clock signal (CLK1) supply line, and a second electrode is connected to the Q2 node Q2. Therefore, the third transistor Tc is turned on / off according to the first clock signal CLK1 to apply the start signal VST or the fourth scan signal SC4 in the previous stage to the Q2 node Q2.

[0206] In the fourth transistor Td, a first electrode is connected to a gate high voltage (VGH) supply line, a gate electrode is connected to the Q2 node Q2, and a second electrode is connected to the QB1 node QB1. Therefore, the fourth transistor Td is turned on / off according to the voltage of the Q2 node Q2 to provide the gate high voltage VGH to the QB1 node QB1.

[0207] In the fifth transistor Te, a first electrode is connected to the first clock signal (CLK1) supply line, a gate electrode is connected to the QB2 node QB2, and a second electrode is connected to the QB1 node QB1. Therefore, the fifth transistor Te is turned on / off according to the voltage of the QB2 node QB2 to provide the first clock signal CLK1 to the QB1 node QB1.

[0208] In the sixth transistor Tf, a first electrode is connected to the Q2 node Q2, a gate electrode is connected to a gate low voltage (VGL) supply line, and a second electrode is connected to the Q1 node Q1. Therefore, the sixth transistor Tf is turned on / off according to the gate low voltage VGL to connect the Q2 node Q2 and the Q1 node Q1.

[0209] In the seventh transistor Tg, a first electrode is connected to a gate high voltage (VGH) supply line, a gate electrode is connected to a start signal (VST) input terminal or an output terminal of the fourth scan signal SC4 in the previous stage, and a second electrode is connected to the QB2 node QB2. Therefore, the seventh transistor Tg is turned on / off according to the start signal VST or the fourth scan signal in the previous stage to provide the gate high voltage VGH to the QB2 node QB2.

[0210] In the eighth transistor Th, a first electrode is connected to a gate low voltage (VGL) supply line, a gate electrode is connected to the Q1 node Q1, and a second electrode is connected to a carry signal (Carry) output terminal. Therefore, the eighth transistor Th is turned on / off according to the voltage of the Q1 node Q1 to output the gate low voltage VGL as the carry signal Carry.

[0211] In the ninth transistor Ti, a first electrode is connected to a gate high voltage (VGH) supply line, a gate electrode is connected to the QB1 node QB1, and a second electrode is connected to a carry signal (Carry) output terminal. The ninth transistor Ti is turned on / off according to the voltage of the QB1 node QB1 to output the gate high voltage VGH as the carry signal Carry.

[0212] In the tenth transistor Tj, the first electrode is connected to the Q1 node Q1, the gate electrode is connected to the first clock signal (CLK1) supply line, and the second electrode is connected to the Q node Q, so the tenth transistor Tj is turned on / off according to the first clock signal CLK1 to connect the Q1 node Q1 and the Q node Q.

[0213] In the eleventh transistor Tk, a first electrode is connected to the QB1 node QB1, a gate electrode is connected to the first clock signal (CLK1) supply line, and a second electrode is connected to the QB node QB. Therefore, the eleventh transistor Tk is turned on / off according to the first clock signal CLK1 to connect the QB1 node QB1 and the QB node QB.

[0214] In the twelfth transistor Tl, the first electrode is connected to the gate low voltage (VGL) supply line, the gate electrode is connected to the second clock signal (CLK2) supply line, and the second electrode is connected to the Q node Q, so the twelfth transistor Tl is turned on / off according to the second clock signal CLK2 to provide the gate low voltage VGL to the Q node Q.

[0215] In the thirteenth transistor Tm, a first electrode is connected to a gate high voltage (VGH) supply line, a gate electrode is connected to a second clock signal (CLK2) supply line, and a second electrode is connected to the QB node QB. Therefore, the thirteenth transistor Tm is turned on / off according to the second clock signal CLK2 to supply the gate high voltage VGH to the QB node QB.

[0216] The first capacitor CQ is connected between the gate electrode and the second electrode of the first transistor Ta to bootstrap the Q node Q.

[0217] The second capacitor CQB is connected between the gate high voltage (VGH) supply line and the QB1 node QB1 to maintain the voltage of the QB1 node QB1 even if the switching period of the clock signals CLK1 and CLK2 increases.

[0218] The third capacitor C_on is connected between the first clock signal supply line and the QB2 node QB2 to generate a kickback phenomenon by the first clock signal CLK1 , thereby turning on the fifth transistor Te.

[0219] The fourth capacitor CQ1 is connected between the gate electrode and the second electrode of the eighth transistor Th to bootstrap the Q1 node Q1.

[0220] The fifth capacitor Cs is connected between the gate low voltage (VGL) supply line and the carry signal (Carry) output terminal to stabilize the carry signal Carry.

[0221] The first capacitor CQ and the second capacitor CQB may be designed to have a larger capacitance than that of the third to fifth capacitors C_on, CQ1, and CS. Furthermore, the first capacitor CQ and the second capacitor CQB may be designed to have a larger area than that of the third to fifth capacitors C_on, CQ1, and CS.

[0222] Each of the above-mentioned first to fifth capacitors CQ, CQB, C_on, CQ1 and CS can be designed to have a capacitance of 50pF or higher, but is not limited thereto, and each of the capacitances of the first to fifth capacitors CQ, CQB, C_on, CQ1 and CS can vary according to design.

[0223] Meanwhile, the first transistor Ta, the second transistor Tb, and the first capacitor CQ connected to the output terminal of each of the plurality of fourth scan drivers 324 are directly associated with the output of the fourth scan signal SC4. Therefore, the first transistor Ta, the second transistor Tb, and the first capacitor CQ may be defined as a scan signal output unit.

[0224] The eighth transistor Th, the ninth transistor Ti, the second capacitor CQB, the fourth capacitor CQ1, and the fifth capacitor CS connected to the carry signal output terminal of each of the plurality of fourth scan drivers 324 are directly associated with the output of the carry signal Carry. Therefore, the eighth transistor Th, the ninth transistor Ti, the second capacitor CQB, the fourth capacitor CQ1, and the fifth capacitor CS may be defined as a carry signal output unit.

[0225] In addition, the third to seventh transistors Tc to Tg, the tenth to thirteenth transistors Tj to Tm, and the third capacitor C_on are components related to control of the Q node, Q1 node, Q2 node, QB node, QB1 node, and QB2 node, and are thus defined as a node controller.

[0226] Specifically, the third transistor Tc, the seventh transistor Tg, and the third capacitor C_on controlling the Q2 node and the QB2 node can be defined as a first node controller. The fourth transistor Td, the fifth transistor Te, the sixth transistor Tf, and the second capacitor CQB controlling the Q1 node and the QB1 node can be defined as a second node controller. The tenth transistor Tj, the eleventh transistor Tk, the twelfth transistor Tl, and the thirteenth transistor Tm controlling the Q node and the QB node can be defined as a third node controller.

[0227] The following reference Figures 7 to 8E The operation of each of the plurality of fourth scan drivers 324 configured as described above is described.

[0228] Figure 7 1 is a waveform illustrating signals input to and output from a plurality of stages of a gate driver of a display device according to an exemplary embodiment of the present disclosure.

[0229] Figure 8A is a circuit diagram for explaining operations of a plurality of stages of a gate driver of a display device according to an exemplary embodiment of the present disclosure in a first period.

[0230] Figure 8B is a circuit diagram for explaining operations of a plurality of stages of a gate driver of a display device according to an exemplary embodiment of the present disclosure in a second period.

[0231] Figure 8C is a circuit diagram for explaining operations of a plurality of stages of a gate driver of a display device according to an exemplary embodiment of the present disclosure in a third period.

[0232] Figure 8D is a circuit diagram for explaining operations of a plurality of stages of a gate driver of a display device according to an exemplary embodiment of the present disclosure in a fourth period.

[0233] Figure 8E is a circuit diagram for explaining operations of a plurality of stages of a gate driver of a display device according to an exemplary embodiment of the present disclosure in a fifth period.

[0234] like Figure 7 and Figure 8AAs shown, in the first period p1 , the start signal VST is input as a high level, so that the seventh transistor Tg is turned off and the gate electrode of the fifth transistor Te is floated.

[0235] The voltage of the Q2 node Q2 may be initially set to a low level. Therefore, the fourth transistor Td is turned on to output the gate high voltage VGH to the QB1 node QB1.

[0236] In addition, the voltage of the Q1 node Q1 may be initially set to a low level. Therefore, the eighth transistor Th is turned on to output the gate low voltage VGL as the carry signal Carry.

[0237] In addition, the voltage of the Q node Q may also be initially set to a low level. Therefore, the first transistor Ta is turned on to output the gate low voltage VGL as a scan signal.

[0238] like Figure 7 and Figure 8B As shown, in the second period p2 after the first period p1, the first clock signal CLK1 drops from a high level to a low level, turning on the third transistor Tc and the tenth transistor Tj. As a result, the Q node Q, the Q1 node Q1, and the Q2 node Q2 are all charged to a high level (which is the level of the start signal VST). As a result, the first transistor Ta and the eighth transistor Th are turned off.

[0239] Due to the kickback of the third capacitor C_on, the QB2 node QB2 is charged to a low level, so that the fifth transistor Te is turned on. Therefore, the QB1 node QB1 is charged to a low level (which is the level of the first clock signal CLK1).

[0240] Therefore, the ninth transistor Ti is turned on to output the gate high voltage VGH as the carry signal Carry.

[0241] In addition, the first clock signal CLK1 falls from a high level to a low level, so that the eleventh transistor Tk is also turned on to charge the QB node QB with a low level, which is the level of the first clock signal CLK1 .

[0242] As a result, the first transistor Ta is turned off and the second transistor Tb is turned on to output the gate high voltage VGH as the scan signal SC4 .

[0243] like Figure 7 and Figure 8CAs shown, in the third period p3 after the second period p2, the second clock signal CLK2 drops from a high level to a low level, turning on the twelfth transistor T1 and the thirteenth transistor Tm. As a result, the Q node Q is charged to the gate low voltage VGL, and the QB node QB is charged to the gate high voltage VGH. As a result, the first transistor Ta is turned on and the second transistor Tb is turned off to output the gate low voltage VGL as the scan signal.

[0244] Specifically, in the third period p3, the voltage applied to the gate of the first transistor Ta and the voltage applied to the first electrode (source) are at the same level. That is, the gate-source voltage Vgs of the first transistor Ta is 0V.

[0245] The Vgs of the first transistor Ta is 0V, so that the first transistor Ta is turned off and the Q node Q floats. The floating Q node Q is bootstrapped by the first capacitor CQ to maintain a voltage lower than the gate low voltage VGL.

[0246] Here, the pulse width of the scan signal SC4 may be determined by the switching timing of the first clock signal CLK1 and the switching timing of the second clock signal CLK2 .

[0247] That is, the scan signal SC4 switches from low level to high level when the first clock signal CLK1 switches from high level to low level, and switches from high level to low level when the second clock signal CLK2 switches from high level to low level.

[0248] In the third period p3, the first clock signal CLK1 rises from a low level to a high level, so that the tenth transistor Tj and the eleventh transistor Tk are turned off, and the Q1 node Q1 can be maintained at a high level, and the QB1 node QB1 can be maintained at a low level. Therefore, the ninth transistor Ti is turned on to output the gate high voltage VGH as the carry signal Carry.

[0249] like Figure 7 and Figure 8D As shown, in the fourth period p4 after the third period p3, the second clock signal CLK2 rises from a low level to a high level, turning off the twelfth transistor T1 and the thirteenth transistor Tm. As a result, the Q node Q is floated to be maintained at a voltage lower than the gate low voltage VGL, and the QB node QB is also floated to be maintained at the gate high voltage VGH. Therefore, the first transistor Ta is turned on and the second transistor Tb is turned off to output the gate low voltage VGL as the scan signal.

[0250] In the fourth period p4, the first clock signal CLK1 is maintained at a high level, so that the tenth transistor Tj and the eleventh transistor Tk are turned off, and the Q1 node Q1 can be maintained at a high level, while the QB1 node QB1 can be maintained at a low level. Therefore, the ninth transistor Ti is turned on to output the gate high voltage VGH as the carry signal Carry.

[0251] In the fourth period p4 , the start signal VST falls from the high level to the low level.

[0252] like Figure 7 and Figure 8E As shown, in the fifth period p5 after the fourth period p4, when the start signal VST is input at a low level, if the first clock signal CLK1 falls to a low level, the third transistor Tc is turned on, so that the Q2 node Q2 is charged to a low level. In addition, the sixth transistor Tf is turned on, so that the Q1 node Q1 is charged to a low level, and the tenth transistor Tj is turned on, so that the Q node Q is charged to a low level.

[0253] In addition, the Q2 node Q2 is charged to a low level, so that the fourth transistor Td is turned on to charge the QB1 node QB1 to a high level.

[0254] In addition, the Q1 node is charged to a low level, so that the eighth transistor Th is turned on to charge the QB1 node QB1 to a low level. Therefore, the ninth transistor Ti is turned off. Therefore, the gate low voltage VGL is output as the carry signal Carry.

[0255] Specifically, in the fifth period p5, the voltage applied to the gate of the eighth transistor Th and the voltage applied to the first electrode (source) are the same level. That is, the gate-source voltage Vgs of the eighth transistor Th is 0V.

[0256] The Vgs of the eighth transistor Th is 0 V, so that the eighth transistor Th is turned off and the Q1 node Q1 is floated. The floating Q1 node Q1 is bootstrapped by the fourth capacitor CQ1 to maintain a voltage lower than the gate low voltage VGL.

[0257] The clock signal CLK1 falls to a low level, so that the eleventh transistor Tk is turned on to output the gate high voltage VGH to the QB node QB.

[0258] Therefore, the first transistor Ta is turned on and the second transistor Tb is turned off to output the gate low voltage VGL as the scan signal.

[0259] As described above, the width of the carry signal Carry may be determined by the switching period of the first clock signal CLK1 .

[0260] That is, when the first clock signal CLK1 switches from a high level to a low level, the carry signal Carry may be switched.

[0261] As described above, in the display device according to the exemplary embodiment of the present disclosure, the pulse width of the scanning signal can be set by controlling the switching timing of the first clock signal CLK1 and the switching timing of the second clock signal CLK2. The pulse width of the scanning signal can be set to 1H (horizontal period) or shorter, so that the scanning signal can be set according to various driving timings.

[0262] Furthermore, the display device according to the exemplary embodiment of the present disclosure does not output a clock signal as a scan signal, but instead outputs a constant voltage (such as a gate high voltage or a gate low voltage) as a scan signal. Therefore, the stability of the scan signal output is improved, thereby improving the driving reliability of the display device.

[0263] The display device according to an exemplary embodiment of the present disclosure outputs a high-level gate-on level scan signal to drive transistors including an n-type oxide semiconductor in a plurality of pixels.

[0264] In addition, in an exemplary embodiment of the present disclosure, a high-level gate-on level scan signal can be output without separately including an inverter. That is, in order to output a high-level gate-on level scan signal using an inverter, a separate power supply line for operation of the output unit needs to be designed, but according to an exemplary embodiment of the present disclosure, a high-level gate-on level scan signal can be output without separately including an inverter.

[0265] Therefore, according to the exemplary embodiments of the present disclosure, a separate power supply line for driving the inverter is not required, so that the bezel area can be reduced and an increase in separate power consumption can be suppressed.

[0266] Exemplary embodiments of the present disclosure may also be described as follows:

[0267] To achieve the purpose described above, according to one aspect of the present disclosure, a gate driver may include: multiple stages, the multiple stages being connected to each other in relation to each other, each of the multiple stages may include: a node controller, the node controller being configured to control the voltages of the Q node, Q1 node, Q2 node, QB node, QB1 node and QB2 node based on a first clock signal and a second clock signal; a carry signal output unit, the carry signal output unit being configured to output a carry signal to a next stage based on the voltages of the Q1 node and the QB1 node; and a scan signal output unit, the scan signal output unit being configured to output a scan signal to a scan line based on the voltages of the Q node and the QB node, and the width of the scan signal may be determined by the switching timing of the first clock signal and the switching timing of the second clock signal.

[0268] The scan signal output unit may include: a first transistor, the first transistor including a first electrode connected to a gate low voltage supply line, a gate electrode connected to the Q node, and a second electrode connected to a scan signal output terminal; a second transistor, the second transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the QB node, and a second electrode connected to the scan signal output terminal; and a first capacitor, the first capacitor being connected between the gate electrode and the second electrode of the first transistor.

[0269] When the second clock signal switches from a high level to a low level, the first capacitor may bootstrap the Q node.

[0270] The carry signal output unit may include: an eighth transistor, the eighth transistor including a first electrode connected to a gate low voltage supply line, a gate electrode connected to the Q1 node, and a second electrode connected to the carry signal output terminal; a ninth transistor, the ninth transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the QB1 node, and a second electrode connected to the carry signal output terminal; a fourth capacitor, the fourth capacitor connected between the gate electrode and the second electrode of the eighth transistor; and a fifth capacitor, the fifth capacitor connected between the gate low voltage supply line and the carry signal output terminal.

[0271] When the first clock signal switches from a high level to a low level, the fourth capacitor may bootstrap the Q1 node.

[0272] The node controller may include: a first node controller, which is configured to control the Q2 node and the QB2 node; a second node controller, which is configured to control the Q1 node and the QB1 node; and a third node controller, which is configured to control the Q node and the QB node.

[0273] The first node controller may include: a third transistor, the third transistor including a first electrode connected to the start signal input terminal or the carry signal output terminal of the previous stage, a gate electrode connected to the first clock signal supply line, and a second electrode connected to the Q2 node; a seventh transistor, the seventh transistor including a first electrode connected to the gate high voltage supply line, a gate electrode connected to the start signal input terminal or the carry signal output terminal of the previous stage, and a second electrode connected to the QB2 node; and a third capacitor, the third capacitor being connected between the first clock signal supply line and the QB2 node.

[0274] The second node controller may include: a fourth transistor, the fourth transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the Q2 node, and a second electrode connected to the QB1 node; a fifth transistor, the fifth transistor including a first electrode connected to a first clock signal supply line, a gate electrode connected to the QB2 node, and a second electrode connected to the QB1 node; a sixth transistor, the sixth transistor including a first electrode connected to the Q2 node, a gate electrode connected to a gate low voltage supply line, and a second electrode connected to the Q1 node; and a second capacitor, the second capacitor being connected between the gate high voltage supply line and the QB1 node.

[0275] The third node controller may include: a tenth transistor, the tenth transistor including a first electrode connected to the Q1 node, a gate electrode connected to the first clock signal supply line, and a second electrode connected to the Q node; an eleventh transistor, the eleventh transistor including a first electrode connected to the QB1 node, a gate electrode connected to the first clock signal supply line, and a second electrode connected to the QB node; a twelfth transistor, the twelfth transistor including a first electrode connected to a gate low voltage supply line, a gate electrode connected to a second clock signal supply line, and a second electrode connected to the Q node; and a thirteenth transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the second clock signal supply line, and a second electrode connected to the QB node.

[0276] When the first clock signal switches from a high level to a low level, the scan signal switches from a low level to a high level, and when the second clock signal switches from a high level to a low level, the scan signal may switch from a high level to a low level.

[0277] The carry signal may be switched when the first clock signal switches from a high level to a low level.

[0278] The plurality of transistors included in each of the plurality of stages may be p-type transistors.

[0279] To achieve the above-mentioned purpose, according to one aspect of the present disclosure, a display device may include: a display panel, the display panel including an active area in which a plurality of pixels are arranged; and a gate driver, the gate driver including: a plurality of stages, the plurality of stages being connected to each other in relation to each other, each of the plurality of stages may include: a node controller, the node controller being configured to control the voltages of the Q node, the Q1 node, the Q2 node, the QB node, the QB1 node and the QB2 node based on a first clock signal and a second clock signal; a carry signal output unit, the carry signal output unit being configured to output a carry signal to the next stage based on the voltages of the Q1 node and the QB1 node; and a scan signal output unit, the scan signal output unit being configured to output a scan signal to a scan line based on the voltages of the Q node and the QB node, and the width of the scan signal may be determined by the switching timing of the first clock signal and the switching timing of the second clock signal.

[0280] The scan signal output unit may include: a first transistor, the first transistor including a first electrode connected to a gate low voltage supply line, a gate electrode connected to the Q node, and a second electrode connected to a scan signal output terminal; a second transistor, the second transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the QB node, and a second electrode connected to the scan signal output terminal; and a first capacitor, the first capacitor being connected between the gate electrode and the second electrode of the first transistor.

[0281] The carry signal output unit may include: an eighth transistor, the eighth transistor including a first electrode connected to a gate low voltage supply line, a gate electrode connected to the Q1 node, and a second electrode connected to the carry signal output terminal; a ninth transistor, the ninth transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the QB1 node, and a second electrode connected to the carry signal output terminal; a fourth capacitor, the fourth capacitor connected between the gate electrode and the second electrode of the eighth transistor; and a fifth capacitor, the fifth capacitor connected between the gate low voltage supply line and the carry signal output terminal.

[0282] The node controller may include: a first node controller, which is configured to control the Q2 node and the QB2 node; a second node controller, which is configured to control the Q1 node and the QB1 node; and a third node controller, which is configured to control the Q node and the QB node.

[0283] The first node controller may include: a third transistor, the third transistor including a first electrode connected to the start signal input terminal or the carry signal output terminal of the previous stage, a gate electrode connected to the first clock signal supply line, and a second electrode connected to the Q2 node; a seventh transistor, the seventh transistor including a first electrode connected to the gate high voltage supply line, a gate electrode connected to the start signal input terminal or the carry signal output terminal of the previous stage, and a second electrode connected to the QB2 node; and a third capacitor, the third capacitor being connected between the first clock signal supply line and the QB2 node.

[0284] The second node controller may include: a fourth transistor, the fourth transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the Q2 node, and a second electrode connected to the QB1 node; a fifth transistor, the fifth transistor including a first electrode connected to a first clock signal supply line, a gate electrode connected to the QB2 node, and a second electrode connected to the QB1 node; a sixth transistor, the sixth transistor including a first electrode connected to the Q2 node, a gate electrode connected to a gate low voltage supply line, and a second electrode connected to the Q1 node; and a second capacitor, the second capacitor being connected between the gate high voltage supply line and the QB1 node.

[0285] The third node controller may include: a tenth transistor, the tenth transistor including a first electrode connected to the Q1 node, a gate electrode connected to the first clock signal supply line, and a second electrode connected to the Q node; an eleventh transistor, the eleventh transistor including a first electrode connected to the QB1 node, a gate electrode connected to the first clock signal supply line, and a second electrode connected to the QB node; a twelfth transistor, the twelfth transistor including a first electrode connected to a gate low voltage supply line, a gate electrode connected to a second clock signal supply line, and a second electrode connected to the Q node; and a thirteenth transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the second clock signal supply line, and a second electrode connected to the QB node.

[0286] Each of the plurality of pixels may include both a p-type transistor and an n-type transistor.

[0287] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be interpreted as falling within the scope of the present disclosure.

Claims

1. A gate driver comprising: a plurality of stages, the plurality of stages being connected in relation to each other, Each of the multiple levels includes: a node controller configured to control voltages of the Q node, the Q1 node, the Q2 node, the QB node, the QB1 node, and the QB2 node based on a first clock signal and a second clock signal; a carry signal output unit configured to output a carry signal to a next stage based on voltages of the Q1 node and the QB1 node; and a scan signal output unit configured to output a scan signal to a scan line based on voltages of the Q node and the QB node, and The width of the scanning signal is determined by the switching timing of the first clock signal and the switching timing of the second clock signal.

2. The gate driver according to claim 1, wherein: The scanning signal output unit includes: a first transistor including a first electrode connected to a gate low voltage supply line, a gate electrode connected to the Q node, and a second electrode connected to a scan signal output terminal; a second transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the QB node, and a second electrode connected to the scan signal output terminal; and A first capacitor is connected between a gate electrode of the first transistor and a second electrode of the first transistor.

3. The gate driver according to claim 2, wherein: When the second clock signal switches from a high level to a low level, the first capacitor bootstraps the Q node.

4. The gate driver according to claim 1, wherein: The carry signal output unit includes: an eighth transistor including a first electrode connected to a gate low voltage supply line, a gate electrode connected to the Q1 node, and a second electrode connected to a carry signal output terminal; a ninth transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the QB1 node, and a second electrode connected to the carry signal output terminal; a fourth capacitor connected between the gate electrode of the eighth transistor and the second electrode of the eighth transistor; and A fifth capacitor is connected between the gate low voltage supply line and the carry signal output terminal.

5. The gate driver according to claim 4, wherein: When the first clock signal switches from a high level to a low level, the fourth capacitor bootstraps the Q1 node. The gate driver according to claim 1 , wherein: The node controller includes: a first node controller configured to control the Q2 node and the QB2 node; a second node controller configured to control the Q1 node and the QB1 node; and A third node controller is configured to control the Q node and the QB node.

7. The gate driver according to claim 6, wherein: The first node controller includes: a third transistor including a first electrode connected to a start signal input terminal or a carry signal output terminal of a previous stage, a gate electrode connected to a first clock signal supply line, and a second electrode connected to the Q2 node; a seventh transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the start signal input terminal or the carry signal output terminal of the previous stage, and a second electrode connected to the QB2 node; and A third capacitor is connected between the first clock signal supply line and the QB2 node.

8. The gate driver according to claim 6, wherein: The second node controller includes: a fourth transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the Q2 node, and a second electrode connected to the QB1 node; a fifth transistor including a first electrode connected to a first clock signal supply line, a gate electrode connected to the QB2 node, and a second electrode connected to the QB1 node; a sixth transistor including a first electrode connected to the Q2 node, a gate electrode connected to a gate low voltage supply line, and a second electrode connected to the Q1 node; and A second capacitor is connected between the gate high voltage supply line and the QB1 node.

9. The gate driver according to claim 6, wherein: The third node controller includes: a tenth transistor including a first electrode connected to the Q1 node, a gate electrode connected to a first clock signal supply line, and a second electrode connected to the Q node; an eleventh transistor including a first electrode connected to the QB1 node, a gate electrode connected to the first clock signal supply line, and a second electrode connected to the QB node; a twelfth transistor including a first electrode connected to the gate low voltage supply line, a gate electrode connected to a second clock signal supply line, and a second electrode connected to the Q node; and a thirteenth transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the second clock signal supply line, and a second electrode connected to the QB node.

10. The gate driver according to claim 1, wherein When the first clock signal switches from a high level to a low level, the scan signal switches from a low level to a high level, and when the second clock signal switches from a high level to a low level, the scan signal switches from a high level to a low level.

11. The gate driver according to claim 1, wherein When the first clock signal switches from a high level to a low level, the carry signal is switched.

12. The gate driver according to claim 1, wherein The plurality of transistors included in each of the plurality of stages are p-type transistors.

13. A display device comprising: A display panel, the display panel comprising an active area in which a plurality of pixels are arranged; as well as A gate driver comprising: a plurality of stages connected in relation to one another, wherein each of the plurality of stages comprises: a node controller configured to control voltages of the Q node, the Q1 node, the Q2 node, the QB node, the QB1 node, and the QB2 node based on a first clock signal and a second clock signal; a carry signal output unit configured to output a carry signal to a next stage based on voltages of the Q1 node and the QB1 node; and a scan signal output unit configured to output a scan signal to a scan line based on voltages of the Q node and the QB node, and The width of the scanning signal is determined by the switching timing of the first clock signal and the switching timing of the second clock signal.

14. The display device according to claim 13, wherein: The scanning signal output unit includes: a first transistor including a first electrode connected to a gate low voltage supply line, a gate electrode connected to the Q node, and a second electrode connected to a scan signal output terminal; a second transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the QB node, and a second electrode connected to the scan signal output terminal; and A first capacitor is connected between a gate electrode of the first transistor and a second electrode of the first transistor.

15. The display device according to claim 13, wherein The carry signal output unit includes: an eighth transistor including a first electrode connected to a gate low voltage supply line, a gate electrode connected to the Q1 node, and a second electrode connected to a carry signal output terminal; a ninth transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the QB1 node, and a second electrode connected to the carry signal output terminal; a fourth capacitor connected between the gate electrode of the eighth transistor and the second electrode of the eighth transistor; and A fifth capacitor is connected between the gate low voltage supply line and the carry signal output terminal.

16. The display device according to claim 13, wherein The node controller includes: a first node controller configured to control the Q2 node and the QB2 node; a second node controller configured to control the Q1 node and the QB1 node; and A third node controller is configured to control the Q node and the QB node.

17. The display device according to claim 16, wherein: The first node controller includes: a third transistor including a first electrode connected to a start signal input terminal or a carry signal output terminal of a previous stage, a gate electrode connected to a first clock signal supply line, and a second electrode connected to the Q2 node; a seventh transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the start signal input terminal or the carry signal output terminal of the previous stage, and a second electrode connected to the QB2 node; and A third capacitor is connected between the first clock signal supply line and the QB2 node.

18. The display device according to claim 16, wherein: The second node controller includes: a fourth transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the Q2 node, and a second electrode connected to the QB1 node; a fifth transistor including a first electrode connected to a first clock signal supply line, a gate electrode connected to the QB2 node, and a second electrode connected to the QB1 node; a sixth transistor including a first electrode connected to the Q2 node, a gate electrode connected to a gate low voltage supply line, and a second electrode connected to the Q1 node; and A second capacitor is connected between the gate high voltage supply line and the QB1 node.

19. The display device according to claim 16, wherein: The third node controller includes: a tenth transistor including a first electrode connected to the Q1 node, a gate electrode connected to a first clock signal supply line, and a second electrode connected to the Q node; an eleventh transistor including a first electrode connected to the QB1 node, a gate electrode connected to the first clock signal supply line, and a second electrode connected to the QB node; a twelfth transistor including a first electrode connected to a gate low voltage supply line, a gate electrode connected to a second clock signal supply line, and a second electrode connected to the Q node; and a thirteenth transistor including a first electrode connected to a gate high voltage supply line, a gate electrode connected to the second clock signal supply line, and a second electrode connected to the QB node.

20. The display device according to claim 16, wherein Each pixel of the plurality of pixels includes both a p-type transistor and an n-type transistor.

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