Method and system for keeping discharge MOS (Metal Oxide Semiconductor) tube closed during BMS (Battery Management System) reset period

Abstract

The invention provides a method and system for keeping a discharge MOS tube closed during a BMS reset period, and relates to the technical field of new energy battery management, and the method comprises the following steps: after MCU reset is completed, a communication interface between an MCU and an AFE is initialized preferentially; reading a discharge MOS tube control state of the AFE in a current state through a communication interface; if it is detected that the discharging MOS tube is in the closed state, a discharging state keeping flag bit is generated in the MCU, and flag bit keeping time counting is carried out; in the configuration logic execution process after the MCU is reset, when the real-time control logic of the discharge MOS tube is not generated, according to the discharge state holding flag bit and the holding time counting result, the AFE is continuously controlled to maintain the closed state of the discharge MOS tube; and when the flag bit retention time count reaches the preset threshold value or the real-time control logic of the discharge MOS tube is generated, state control based on the real-time control logic is switched, so that reliable retention of the closed state of the discharge MOS tube under the reset state of the BMS is realized, and higher flexibility and cost effectiveness are achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of new energy battery management, and in particular to a method and system for keeping a discharge MOS tube closed during a battery management system (BMS) reset. Background Art

[0002] In new energy battery systems, the BMS must ensure that the discharge MOS transistor remains closed during reset (such as power-on reset, watchdog reset, etc.) to prevent external power outages. Existing technical solutions mainly use the following two methods to ensure that the discharge MOS transistor of the BMS (battery management system) remains closed during reset, thereby avoiding external power outages:

[0003] (1) Hardware design: By designing an RC delay circuit, a hardware latch circuit, or using a MOS transistor driver chip with a self-holding function, the discharge MOS transistor is ensured not to be disconnected during the BMS reset period. However, this solution still requires the discharge MOS transistor to be closed immediately after reset, which adds additional hardware costs, resulting in increased system complexity and cost.

[0004] (2) Software backup solution: The state of the discharge MOS tube is backed up and stored in Flash. After reset, the backup state is read and control is restored. However, this solution has certain risks: when the system is subject to irresistible interference (such as power fluctuations or strong electromagnetic interference), the Flash data may be lost or damaged, and the state of the discharge MOS tube cannot be correctly restored, causing external power outages and even serious safety accidents.

[0005] Since existing technical solutions have obvious shortcomings in hardware costs and system reliability, a more efficient and reliable solution is urgently needed. Summary of the Invention

[0006] In light of this, the present invention aims to provide a method and system for keeping a discharge MOSFET closed during a BMS reset. This method, designed to achieve reliable closed control of the discharge MOSFET during a BMS reset through software logic, eliminates the need for additional hardware, reduces system costs, and improves anti-interference capabilities. This method eliminates the limitations of traditional solutions that rely on hardware delay circuits or software backups, and instead reliably maintains the closed state of the discharge MOSFET during a BMS reset through pure software logic, offering greater flexibility and cost-effectiveness.

[0007] To achieve the above object, the present invention provides the following technical solutions:

[0008] Based on the above objectives, in a first aspect, the present invention provides a method for keeping a discharge MOS tube closed during a BMS reset, comprising the following steps:

[0009] S1. After the MCU reset is completed, the communication interface between the MCU and AFE is initialized first;

[0010] S2 reads the discharge MOS tube control state of the AFE in the current state through the communication interface;

[0011] S3. If the discharge MOS tube is detected to be in the closed state, a discharge state holding flag is generated in the MCU, and the flag holding time count is performed;

[0012] S4. During the execution of the configuration logic after the MCU is reset, when the real-time control logic of the discharge MOS tube is not generated, the AFE is continuously controlled to maintain the closed state of the discharge MOS tube according to the discharge state holding flag and the hold time count result;

[0013] S5. When the flag holding time count reaches a preset threshold or the real-time control logic of the discharge MOS tube is generated, switch to state control based on the real-time control logic.

[0014] As a further solution of the present invention, the MCU reset includes any one of the triggering scenarios of power-on reset, watchdog reset or manual reset.

[0015] As a further solution of the present invention, the duration of the time count is set according to the maximum initialization delay time after the MCU is reset, and covers the entire initialization process after the MCU is reset.

[0016] As a further solution of the present invention, the preset threshold value of the flag bit holding time count is set to be greater than the maximum time value required to complete system initialization after the MCU is reset.

[0017] As a further solution of the present invention, the communication interface is an SPI or I2C interface, and the initialization priority of the communication interface in S1 is higher than other post-reset configuration tasks of the MCU.

[0018] As a further solution of the present invention, during the time counting operation, if the normal logic of the MCU determines that the discharge MOS tube needs to be disconnected, the execution of the disconnection instruction is delayed until the countdown ends.

[0019] As a further solution of the present invention, the real-time control logic includes a control signal generated by at least one state judgment logic in battery voltage detection, temperature detection or overcurrent protection control strategy.

[0020] As a further solution of the present invention, when reading the discharge MOS tube control state in the current state of the AFE, if it is detected that the AFE does not respond or the data is abnormal, the discharge MOS tube is maintained in the closed state by default.

[0021] As a further solution of the present invention, after the time counting is started, if the MCU is reset again during the countdown, the process is re-executed.

[0022] In a second aspect, the present invention further provides a system for keeping a discharge MOS tube closed during a BMS reset, comprising:

[0023] Microcontroller unit (MCU), used to execute initialization logic and control strategy after reset;

[0024] An analog front-end module (AFE), connected to the MCU via a communication interface, and used to control the on / off state of the discharge MOS tube;

[0025] The communication interface initialization module is configured to prioritize initializing the communication interface between the MCU and the AFE after the MCU is reset;

[0026] A status reading module is configured to obtain the control status of the current discharge MOS tube of the AFE in real time through the communication interface;

[0027] A flag generating module is configured to generate a discharge state holding flag when detecting that the discharge MOS tube is in a closed state;

[0028] A time counting module, linked with the flag bit generating module, for starting the flag bit to hold time counting;

[0029] The control logic execution module is configured to:

[0030] If the real-time control logic is not generated, the discharge MOS tube is kept closed according to the flag bit and the time counting result;

[0031] If the time count reaches a preset threshold or real-time control logic is generated, the control is switched to the real-time control logic-based control.

[0032] As a further solution of the present invention, the communication interface is an SPI or I2C interface, and the priority of the communication interface initialization module is higher than other post-reset tasks of the MCU.

[0033] As a further solution of the present invention, the flag generating module stores the discharge state holding flag in a volatile memory of the MCU and retains the data during the MCU reset period.

[0034] As a further solution of the present invention, the preset threshold of the time counting module is greater than the maximum time value required to complete system initialization after the MCU is reset, and covers all scenarios of watchdog reset, manual reset and power-on reset of the MCU.

[0035] As a further solution of the present invention, during the time counting operation, if the control logic execution module detects a real-time control instruction to disconnect the discharge MOS tube, the disconnection operation is delayed until the time counting ends.

[0036] As a further solution of the present invention, the real-time control logic includes at least one state judgment signal generated by a battery voltage detection module, a temperature detection module or an overcurrent protection module.

[0037] As a further solution of the present invention, the state reading module is configured to: when the AFE does not respond or returns abnormal data, trigger the discharge state holding flag by default to keep the MOS tube closed.

[0038] As a further solution of the present invention, the time counting module is automatically reset and re-executes counting when the MCU is reset again.

[0039] Compared with the prior art, the present invention proposes a method and system for keeping the discharge MOS transistor closed during BMS reset, which reliably maintains the closed state of the discharge MOS transistor during BMS reset, significantly improving the safety, stability and economy of the system, and has the following beneficial effects:

[0040] 1. This invention abandons traditional hardware delay circuits, latch circuits or dedicated driver chips, and relies entirely on software logic to achieve state retention, which significantly reduces costs and system complexity, reduces PCB area occupation, reduces material costs and design complexity, and is suitable for miniaturized, low-cost BMS application scenarios (such as two-wheeled vehicles, scooters, etc.).

[0041] 2. The present invention reads the AFE status in real time (rather than relying on backup data stored in Flash) and combines it with dynamic management of flag bits in volatile memory to enhance anti-interference capabilities and improve data reliability, thereby avoiding the risk of Flash data damage or loss due to power fluctuations and electromagnetic interference, and ensuring the real-time and accuracy of the MOS tube status during reset.

[0042] 3. The present invention supports multiple triggering scenarios such as power-on reset, watchdog reset, and manual reset. The threshold of the time counting module covers the maximum delay of MCU initialization, fully covers reset scenarios, and guarantees power supply continuity. Regardless of the reset reason or system status, the discharge MOS tube can be kept closed to prevent external power supply interruption, avoid load equipment downtime or safety accidents.

[0043] 4. The communication interface initialization of this invention takes precedence over other MCU tasks, ensuring that the AFE status is immediately available after reset. This shortens status read latency, avoids control lags caused by competition in initialization tasks, and improves system response speed. Furthermore, when AFE communication is abnormal, the MOS transistor remains closed by default, and the disconnection instruction is delayed during the time count. This prioritizes power supply security in the event of communication failures or logic conflicts, avoids the risk of accidental disconnection, and adapts to complex operating conditions (such as high temperature and vibration scenarios).

[0044] 5. This invention utilizes parameterized designs such as flag bit retention time count and threshold setting to support dynamic adjustment, flexible and configurable software, and improved maintenance convenience. It can adapt to different BMS models or initialization processes without hardware modification, reducing subsequent upgrade and maintenance costs. Furthermore, after the time count ends or when real-time control logic is generated, it automatically switches to normal control mode (such as voltage / temperature / overcurrent protection strategy), ensuring safety during reset without affecting the triggering of normal BMS protection functions, thus achieving a balance between safety and functionality.

[0045] 6. The time counting module of the present invention automatically resets and re-executes when the MCU is reset again. It can cope with continuous abnormal resets (such as frequent watchdog triggering) and still maintain the MOS tube state, avoiding the system from entering a dead loop of "reset-power off-reset".

[0046] In summary, this invention solves the core issues of traditional solutions, such as high hardware costs, easy data loss, and poor anti-interference capabilities, by combining dynamic software control with real-time feedback on hardware status. It is particularly suitable for new energy equipment (such as electric vehicles and energy storage systems) with stringent requirements for power supply continuity. Its technical effects offer significant advantages in safety, economy, and applicability, providing an innovative solution for BMS design.

[0047] These and other aspects of the present application will be more clearly understood in the following description of the embodiments. It should be understood that the above general description and the following detailed description are merely exemplary and explanatory and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the following briefly introduces the drawings required for the exemplary embodiments or related technical descriptions. The drawings are used to provide a further understanding of the present invention and constitute part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the drawings:

[0049] Figure 1 Schematic diagram of a method for keeping the discharge MOS tube closed during BMS reset according to an embodiment of the present invention.

[0050] Figure 2 The flowchart of the method for keeping the discharge MOS tube closed during BMS reset according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0051] Below, the present application is further described in conjunction with the accompanying drawings and specific implementation methods. It should be noted that, under the premise of no conflict, the various embodiments or technical features described below can be arbitrarily combined to form new embodiments.

[0052] To make the purpose, technical solutions and advantages of the present invention more clearly understood, the following is a further detailed description of the embodiments of the present invention in conjunction with specific embodiments and with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0053] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are intended to distinguish two non-identical entities or non-identical parameters with the same name. Therefore, "first" and "second" are used for convenience of expression only and should not be understood as limitations on the embodiments of the present invention. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, other steps or units inherent to a process, method, system, product, or device that includes a series of steps or units.

[0054] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0055] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, combined, or partially merged, so the actual execution order may vary depending on the actual situation.

[0056] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features therein may be combined with each other.

[0057] Given the significant shortcomings of existing solutions in terms of hardware cost and system reliability, the present invention proposes a method and system for maintaining the closed state of a discharge MOS transistor during a BMS reset. This method aims to achieve reliable closed control of the discharge MOS transistor during a BMS reset through software logic, eliminating the need for additional hardware, reducing system costs, and improving anti-interference capabilities. This method eliminates the limitations of traditional solutions that rely on hardware delay circuits or software backups, and instead achieves reliable closed state control of the discharge MOS transistor during a BMS reset through pure software logic, offering greater flexibility and cost-effectiveness.

[0058] See also Figure 1 and Figure 2 As shown, an embodiment of the present invention provides a method for keeping a discharge MOS tube closed during a BMS reset, comprising the following steps:

[0059] S1. After the MCU reset is completed, the communication interface between the MCU and AFE is initialized first;

[0060] S2 reads the discharge MOS tube control state of the AFE in the current state through the communication interface;

[0061] S3. If the discharge MOS tube is detected to be in the closed state, a discharge state holding flag is generated in the MCU, and the flag holding time count is performed;

[0062] S4. During the execution of the configuration logic after the MCU is reset, when the real-time control logic of the discharge MOS tube is not generated, the AFE is continuously controlled to maintain the closed state of the discharge MOS tube according to the discharge state holding flag and the hold time count result;

[0063] S5. When the flag holding time count reaches a preset threshold or the real-time control logic of the discharge MOS tube is generated, switch to state control based on the real-time control logic.

[0064] In this embodiment, the MCU reset includes any one of the triggering scenarios of power-on reset, watchdog reset or manual reset, wherein the duration of the time count is set according to the maximum initialization delay time after the MCU reset and covers the entire initialization process after the MCU reset.

[0065] In this embodiment, the preset threshold value of the flag hold time count is set to be greater than the maximum time value required to complete system initialization after the MCU is reset. The communication interface is an SPI or I2C interface, and the initialization priority of the communication interface in S1 is higher than other post-reset configuration tasks of the MCU.

[0066] In this embodiment, during the time counting operation, if the normal logic of the MCU determines that the discharge MOS tube needs to be disconnected, the execution of the disconnection instruction is delayed until the countdown ends.

[0067] In this embodiment, the real-time control logic includes a control signal generated by at least one state judgment logic of battery voltage detection, temperature detection, or overcurrent protection control strategy.

[0068] When reading the discharge MOSFET control state under the current AFE state, if the AFE is not responding or the data is abnormal, the discharge MOSFET is kept closed by default. After the time count is started, if the MCU is reset again during the countdown, the countdown is restarted.

[0069] A method for keeping a discharge MOS tube closed during a BMS reset according to an embodiment of the present invention is specifically implemented as follows:

[0070] (1) Prioritize configuration of the communication module after reset: After the MCU is reset, the communication module between the MCU and the AFE (Analog Front End) is configured first. Since resetting the MCU does not cause the AFE to reset, after the configuration is completed, the MCU can immediately obtain the discharge MOS tube control status of the AFE in its current state through the communication interface.

[0071] (2) Recording the discharge MOS transistor status flag: After obtaining the AFE status, the MCU records the discharge MOS transistor status flag. If the discharge MOS transistor is detected to be in the closed state, the flag hold time count is simultaneously started to ensure that the discharge MOS transistor remains in the closed state during subsequent logic execution.

[0072] (3) Execute the configuration logic after MCU reset: During the execution of various configuration logics after MCU reset, if the logic judgment result of the discharge signal has not been generated, the AFE is controlled by the flag hold time to ensure that the discharge MOS tube always remains in the closed state during the reset period.

[0073] (4) Ensuring the continuity of external power supply: Through the above mechanism, the present invention can ensure that the discharge MOS tube will not be disconnected in any reset state (such as power-on reset, watchdog reset or manual reset), thereby avoiding interruption of external power supply and improving the reliability and safety of the system.

[0074] The present invention supports multiple triggering scenarios such as power-on reset, watchdog reset, and manual reset. The threshold of the time counting module covers the maximum delay of MCU initialization, and the reset scenarios are fully covered. The power supply continuity is guaranteed. Regardless of the reset reason or system status, the discharge MOS tube can be kept closed to prevent external power supply interruption, avoid load equipment downtime or safety accidents. The communication interface initialization priority of the present invention is higher than other MCU tasks, ensuring that the AFE status is obtained as soon as possible after reset, shortening the status reading delay, avoiding control lags caused by competition for initialization tasks, and improving the system response speed. Moreover, when the AFE communication is abnormal, the MOS tube is kept closed by default, and the disconnection instruction is delayed during the time counting period. In the event of communication failure or logic conflict, power supply safety is still prioritized to avoid the risk of accidental disconnection, and adapt to complex working conditions (such as high temperature and vibration scenarios).

[0075] The present invention requires no additional hardware and is implemented entirely through software logic, eliminating the need for hardware delay circuits or latching circuits, thus reducing hardware cost and design complexity. It offers high reliability by ensuring the stability of the discharge MOS transistor state during reset by acquiring the AFE state in real time and combining it with flag hold time control, thus avoiding the risk of power outages caused by Flash data loss in traditional solutions. It also offers broad applicability, suitable for various reset scenarios, ensuring the continuity of external power supply in any state. By maintaining the closed discharge MOS transistor during BMS reset, the reliability and safety of the BMS system during reset are significantly improved, while reducing hardware cost and design complexity, thus offering broad application prospects.

[0076] See also Figure 1 and Figure 2 As shown, an embodiment of the present invention further provides a system for keeping a discharge MOS tube closed during a BMS reset, comprising the following components:

[0077] Microcontroller unit (MCU), used to execute initialization logic and control strategy after reset;

[0078] An analog front-end module (AFE), connected to the MCU via a communication interface, and used to control the on / off state of the discharge MOS tube;

[0079] The communication interface initialization module is configured to prioritize initializing the communication interface between the MCU and the AFE after the MCU is reset;

[0080] A status reading module is configured to obtain the control status of the current discharge MOS tube of the AFE in real time through the communication interface;

[0081] A flag generating module is configured to generate a discharge state holding flag when detecting that the discharge MOS tube is in a closed state;

[0082] A time counting module, linked with the flag bit generating module, for starting the flag bit to hold time counting;

[0083] The control logic execution module is configured to:

[0084] If the real-time control logic is not generated, the discharge MOS tube is kept closed according to the flag bit and the time counting result;

[0085] If the time count reaches a preset threshold or real-time control logic is generated, the control is switched to the real-time control logic-based control.

[0086] In this embodiment, the communication interface is an SPI or I2C interface, and the priority of the communication interface initialization module is higher than other post-reset tasks of the MCU.

[0087] In this embodiment, the flag generating module stores the discharge state holding flag in a volatile memory of the MCU, and retains the data during the MCU reset period.

[0088] In this embodiment, the preset threshold of the time counting module is greater than the maximum time value required to complete system initialization after the MCU is reset, and covers all scenarios of watchdog reset, manual reset and power-on reset of the MCU.

[0089] In this embodiment, if the control logic execution module detects a real-time control instruction to disconnect the discharge MOS tube during the time counting operation, the disconnection operation is delayed until the time counting ends.

[0090] In this embodiment, the real-time control logic includes at least one state judgment signal generated by a battery voltage detection module, a temperature detection module, or an overcurrent protection module.

[0091] In this embodiment, the state reading module is configured to trigger the discharge state holding flag by default to keep the MOS tube closed when the AFE does not respond or returns abnormal data.

[0092] The present invention reads the AFE status in real time (rather than relying on backup data stored in Flash) and combines it with dynamic management of flag bits in volatile memory to enhance anti-interference capabilities and improve data reliability, avoiding the risk of Flash data damage or loss due to power fluctuations and electromagnetic interference, and ensuring the real-time and accuracy of the MOS tube status during reset.

[0093] In this embodiment, the time counting module is automatically reset and re-executes counting when the MCU is reset again.

[0094] The present invention abandons traditional hardware delay circuits, latch circuits or dedicated driver chips, and relies entirely on software logic to achieve state retention, which significantly reduces costs and system complexity, reduces PCB area occupation, reduces material costs and design complexity, and is suitable for miniaturized, low-cost BMS application scenarios (such as two-wheeled vehicles, scooters, etc.).

[0095] This invention utilizes parameterized designs such as flag-holding time counts and threshold settings to support dynamic adjustments, offering flexible and configurable software and improved maintenance convenience. This allows for adaptation to different BMS models or initialization processes without hardware modifications, reducing subsequent upgrade and maintenance costs. Furthermore, after the time count expires or when real-time control logic is generated, the system automatically switches to normal control mode (e.g., voltage / temperature / overcurrent protection strategies), ensuring safety during reset without affecting the triggering of the BMS's normal protection functions, thus achieving a balance between safety and functionality.

[0096] The time counting module of the present invention is automatically reset and re-executed when the MCU is reset again. It can cope with continuous abnormal resets (such as frequent watchdog triggering) and still maintain the MOS tube state, avoiding the system from entering a "reset-power off-reset" infinite loop.

[0097] In summary, this invention solves the core issues of traditional solutions, such as high hardware costs, easy data loss, and poor anti-interference capabilities, by combining dynamic software control with real-time feedback on hardware status. It is particularly suitable for new energy equipment (such as electric vehicles and energy storage systems) with stringent requirements for power supply continuity. Its technical effects offer significant advantages in safety, economy, and applicability, providing an innovative solution for BMS design.

[0098] The above are exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications may be made without departing from the scope of the embodiments disclosed in the claims. The functions, steps and / or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual form, they may also be understood as multiple unless expressly limited to the singular.

[0099] It should be understood that, as used herein, the singular form "a" or "an" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the items listed in association. The serial numbers of the embodiments disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0100] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples. Within the spirit of the embodiments of the present invention, the technical features of the above embodiments or different embodiments may be combined, and there are many other variations of different aspects of the above embodiments of the present invention, which are not provided in detail for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the scope of protection of the embodiments of the present invention.

Claims

1. A method for keeping a discharge MOS tube closed during a BMS reset, characterized in that: include: After the MCU is reset, the communication interface between the MCU and the AFE is initialized first; Reading the discharge MOS tube control state in the current state of the AFE through the communication interface; If it is detected that the discharge MOS tube is in the closed state, a discharge state holding flag is generated in the MCU, and the flag holding time count is performed; During the configuration logic execution after the MCU is reset, when the real-time control logic of the discharge MOS tube is not generated, the AFE is continuously controlled to maintain the closed state of the discharge MOS tube according to the discharge state holding flag and the holding time counting result; When the flag holding time count reaches a preset threshold or the real-time control logic of the discharge MOS tube is generated, it switches to state control based on the real-time control logic.

2. The method for keeping the discharge MOS transistor closed during BMS reset according to claim 1, characterized in that: The MCU reset includes any one of the triggering scenarios of power-on reset, watchdog reset or manual reset.

3. The method for keeping the discharge MOS transistor closed during BMS reset as claimed in claim 2, characterized in that: The duration of the time count is set according to the maximum initialization delay time after the MCU is reset, and covers the entire initialization process after the MCU is reset.

4. The method for keeping the discharge MOS transistor closed during BMS reset as claimed in claim 3, characterized in that: The communication interface is an SPI or I2C interface, and the initialization priority of the communication interface in S1 is higher than other post-reset configuration tasks of the MCU.

5. The method for keeping the discharge MOS transistor closed during BMS reset as claimed in claim 4, characterized in that: After the time count is started, if the MCU is reset again during the countdown, it will be executed again.

6. The method for keeping the discharge MOS transistor closed during BMS reset as claimed in claim 5, characterized in that: During the time counting operation, if the normal logic of the MCU determines that the discharge MOS tube needs to be disconnected, the execution of the disconnection instruction is delayed until the countdown ends.

7. The method for keeping the discharge MOS transistor closed during BMS reset according to claim 6, characterized in that: The real-time control logic includes a control signal generated by at least one state judgment logic of battery voltage detection, temperature detection or overcurrent protection control strategy.

8. The method for keeping the discharge MOS transistor closed during BMS reset as claimed in claim 7, characterized in that: The state reading module is configured to trigger the discharge state holding flag by default to keep the MOS tube closed when the AFE does not respond or returns abnormal data.

9. A system in which a discharge MOS tube remains closed during a BMS reset, characterized in that: The system is configured to perform the method for keeping the discharge MOS transistor closed during BMS reset as described in any one of claims 1 to 8, comprising: A microcontroller unit for executing initialization logic and control strategies after reset; An analog front-end module, connected to the microcontroller unit via a communication interface, and used to control the on / off state of the discharge MOS tube; The communication interface initialization module is configured to initialize the communication interface between the microcontroller unit and the analog front-end module first after the microcontroller unit is reset; A status reading module is configured to obtain the current control status of the discharge MOS tube of the analog front-end module in real time through the communication interface; A flag generating module is configured to generate a discharge state holding flag when detecting that the discharge MOS tube is in a closed state; A time counting module, linked with the flag bit generating module, for starting the flag bit to hold time counting; The control logic execution module is configured to: If the real-time control logic is not generated, the discharge MOS tube is kept closed according to the flag bit and the time counting result; If the time count reaches a preset threshold or real-time control logic is generated, the control is switched to the real-time control logic-based control.

10. The system for keeping the discharge MOS transistor closed during BMS reset as claimed in claim 9, characterized in that: The flag generating module stores the discharge state holding flag in the volatile memory of the MCU and retains the data during the MCU reset period.

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