Wi-Fi optical terminal 5G radio frequency front end power supply time sequence control method and related device

Abstract

The invention relates to the technical field of chip power supply time sequence control, in particular to a Wi-Fi optical terminal 5G radio frequency front end power supply time sequence control method and a related device. The control method comprises the following steps: outputting an initial low-level signal through a GPI O39 pin of the SOC main chip, controlling N-MOS tubes Q2 and Q5 to be in a cut-off state, ensuring that an EN pin of the BUCK chip P4U1 maintains a low level, and cutting off 5V0FEM power supply output of a 5G radio frequency front end and a USB interface so as to initialize enable signal control. After a DC12V0I N input is powered on, a 2.5 V power supply of a DDR4, an SOC core 1.2 V / 0.9 V power supply and a 1V8BUCK reference voltage are started preferentially, and after the SOC core 1.2 V / 0.9 V power supply is stable and voltage fluctuation is smaller than 5% and lasts for 2 ms, a GPIO39 pin is triggered to output a high-level enable signal so as to start a core power supply timing sequence preferentially. According to the Wi-Fi optical terminal 5G radio frequency front end power supply time sequence control method, the problems that in the prior art, the impact current is too large, and the energy utilization efficiency of an energy storage capacitor is low are effectively solved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip power timing control, and specifically to a Wi-Fi optical terminal 5G radio frequency front-end power timing control method and related devices. Background Art

[0002] In the power management design of wireless communication terminal equipment, the power timing control of the RF front-end and peripheral interfaces restricts the reliability and energy efficiency of the equipment. In existing technical solutions, for optical terminal products that support high-speed wireless communication, the power supply of its 5G RF front-end and USB interface is usually directly powered by the same buck converter circuit (BUCK), and this circuit is started synchronously with the core logic circuit power supply when powered on. Although this design meets the basic power supply requirements, it has significant defects:

[0003] On the one hand, since the RF front-end and USB interface do not need to work immediately at the initial stage of system startup, the instantaneous connection of their loads will cause a large inrush current on the power input side, posing a challenge to the stability of the power adapter and circuit.

[0004] Furthermore, during power-off, the continued operation of the step-down converter circuit consumes significant energy from the energy storage capacitor, resulting in insufficient energy reserves for critical information feedback and affecting the effective duration of the feedback signal. Balancing the timing of powering off non-core loads with energy allocation to the core circuits, particularly during input voltage drops, presents a pressing technical challenge in existing designs. Summary of the Invention

[0005] The present disclosure proposes a Wi-Fi optical terminal 5G radio frequency front-end power timing control method and related devices, aiming to overcome at least one defect existing in the prior art.

[0006] To achieve the above objectives, the technical solutions disclosed in the present invention are as follows:

[0007] According to one aspect of the present disclosure, a method for controlling a power supply timing of a 5G radio frequency front-end of a Wi-Fi optical terminal is provided. The control method includes the following steps:

[0008] The GPIO39 pin of the SOC main chip outputs an initial low-level signal to control the N-MOS transistors Q2 and Q5 to the off state, ensuring that the EN pin of the BUCK chip P4U1 maintains a low level. This cuts off the 5V0_FEM power output of the 5G RF front-end and USB interface to initialize the enable signal control.

[0009] After the DC12V0_IN input is powered on, the DDR4 2.5V power supply, the SOC core 1.2V / 0.9V power supply and the 1V8_BUCK reference voltage are started first. After the SOC core 1.2V / 0.9V power supply is stable and the voltage fluctuation is less than 5% for 2ms, the GPIO39 pin is triggered to output a high-level enable signal to start the core power timing first;

[0010] The DC12V0_IN voltage is divided by the voltage-dividing resistors PR1 and PR2 to generate an enable signal that is input to the EN pin of P4U1. When the divided voltage value reaches the power-on threshold of P4U1, 1.3V±2%, P4U1 is activated to start outputting the 5V0_FEM power supply to detect the threshold of the voltage-dividing network enable signal.

[0011] When it is detected that the DC12V0_IN voltage drops to the enable signal level below the P4U1 power-down threshold of 1.2V±2%, the N-MOS transistors Q2 and Q5 are automatically turned off, the EN pin enable signal of P4U1 is cut off, and the 5V0_FEM power supply output is stopped to protect the input voltage from dropping.

[0012] Reduce the energy consumption of the 5V0_FEM load on the energy storage capacitors P4C2 and P4C3, and use energy storage to maintain the SOC core circuit to complete data preservation during the power-off transition phase to optimize the energy distribution of the energy storage capacitors.

[0013] Furthermore, the signal amplification logic of the N-MOS transistors Q2 and Q5 is:

[0014] By default, the GPIO39 pin is grounded through a built-in pull-down resistor. When the output is low, the N-MOS transistor Q2 is cut off, and the gate voltage of the N-MOS transistor Q5 is pulled up to DC12V0_IN through P4R9, turning off Q5. When the GPIO39 outputs a high level, the N-MOS transistor Q2 is turned on and pulls down the gate voltage of the N-MOS transistor Q5, turning on the N-MOS transistor Q5 and raising the EN pin voltage of P4U1 to the output value of the voltage divider network.

[0015] Furthermore, the voltage divider network enable signal is calculated as follows:

[0016] Among them, V EN is the EN pin voltage of P4U1, V IN DC12V0_IN is the input voltage, PR1 and PR2 are the voltage divider resistor values, ensuring that the enable signal falls within the 1.3V±2% startup range at power-on;

[0017] The threshold value of the input voltage drop is calculated as follows:

[0018] Based on the power-off threshold of P4U1 (1.2V±2%) and the resistance ratio of the voltage divider resistors PR1 and PR2, the protection threshold of DC12V0_IN is calculated as:

[0019] Among them, V TH_DOWN is the power-off threshold voltage of P4U1.

[0020] Furthermore, the startup delay time of the SOC core 1.2V / 0.9V power supply is determined as follows:

[0021] After detecting that the 1V8_BUCK reference voltage is stable, the delay time T≥1ms+Δt, where Δt is the software response time, is set. After the SOC main chip completes register initialization, an enable signal is sent through the GPIO39 pin to start the 5V0_FEM power supply.

[0022] Before the 5V0_FEM power supply is started, the output signal of the voltage divider network is monitored in real time through the PFI_DYING_GASP pin. If and only if the DC12V0_IN voltage is ≥10.64V, the corresponding enable signal is ≥1.326V, and the GPIO39 pin is high for 1ms, P4U1 is triggered to start working for power-on interlock detection.

[0023] Furthermore, the configuration method of the energy storage capacitors P4C2 and P4C3 is:

[0024] The energy storage capacitors P4C2 and P4C3 are connected in parallel at the DC12V0_IN input end to reduce the transient impact of the 5V0_FEM power supply on the main capacitor by increasing the energy storage capacity, ensuring that the remaining energy is first supplied to the SOC core circuit when power is off.

[0025] According to another aspect of the present disclosure, a Wi-Fi optical terminal 5G RF front-end power supply timing control circuit is provided, which is used to implement the Wi-Fi optical terminal 5G RF front-end power supply timing control method described above, and the control circuit includes:

[0026] The SOC interface module includes a GPIO39 pin and a PFI_DYING_GASP pin. The GPIO39 pin is connected to the gate of the N-MOS tube Q2 through a resistor P4R8, and the PFI_DYING_GASP pin is connected to the node of the voltage divider resistors PR1 and PR2.

[0027] Two-stage signal amplification circuit, the sources of the N-MOS transistors Q2 and Q5 are both grounded, and the drain of the N-MOS transistor Q5 is connected to the EN pin of the BUCK chip P4U1 to achieve two-stage amplification drive of the GPIO39 signal;

[0028] A voltage divider feedback network, in which a voltage divider resistor PR1 with one end connected to DC12V0_IN is connected in series with a voltage divider resistor PR2 with one end grounded. The node voltages are input to the EN pin of the BUCK chip P4U1 and the PFI_DYING_GASP pin of the SOC respectively. The parallel capacitors P4C1 and P4C5 filter the voltage divider signal.

[0029] Buck power conversion circuit, the VIN pin of the buck chip P4U1 is connected to DC12V0_IN, the SW pin is connected to the output terminal 5V0_FEM through the inductor P4L1, the FB pin is grounded through resistors P4R2 and P4R5, and the resistor P4R4 is connected to the output terminal of 5V0_FEM to form a feedback regulation network;

[0030] Output filter unit: The output end of 5V0_FEM is connected in parallel with capacitors P4C4, P4C6, P4C7, P4C8, P4C9, and P4C10, which together with inductor P4L1 form an LC filter circuit to suppress output ripple.

[0031] Energy storage buffer circuit, capacitors P4C2 and P4C3 are connected in parallel to the DC12V0_IN input terminal to store transient energy and stabilize the input voltage.

[0032] Furthermore, the gate of the N-MOS transistor Q2 is connected to GPIO39 via a resistor P4R8, the drain is connected to the gate of the N-MOS transistor Q5, and the gate of the N-MOS transistor Q5 is pulled up via a resistor P4R9.

[0033] Furthermore, one end of the resistor P4R2 is connected to the 5V0_FEM output terminal, and the other end is connected to the FB pin of the BUCK chip P4U1 through resistors P4R4 and P4R7. A capacitor P4C11 is connected in parallel across the two ends of the resistor P4R4, and the other end of the resistor P4R2 is grounded through a resistor P4R5 to achieve feedback regulation of the output voltage.

[0034] According to another aspect of the present disclosure, a Wi-Fi optical terminal 5G radio frequency front-end power supply timing control system is provided, the control system comprising:

[0035] A power input module is connected to a DC12V±10% power supply. The output end of the power input module is connected to the DC12V0_IN interface of the control circuit and has a built-in surge protection device.

[0036] The timing control module integrates the control circuit described above and communicates with the SoC main chip through the GPIO39 and PFI_DYING_GASP pins. It is used for enabling control and voltage detection of the 5G RF front-end power supply of the Wi-Fi optical terminal.

[0037] A load driver module, whose input is connected to the 5V0_FEM output of the control circuit, is used to power the 5G FEM chip and the USB interface, and the load driver module has a built-in overcurrent protection fuse;

[0038] The energy storage filter module includes capacitors P4C2 and P4C3 at the input end and capacitors P4C4, P4C6-P4C10 at the output end, and is used to maintain the stability and transient response of the power supply signal.

[0039] According to another aspect of the present disclosure, a storage medium is provided, which stores a computer program. When the computer program is executed by a processor, the Wi-Fi optical terminal 5G RF front-end power timing control method as described above is implemented.

[0040] The beneficial effects of the present invention are:

[0041] The present invention's power timing control method for a 5G radio frequency front-end in a Wi-Fi optical terminal effectively addresses the existing issues of excessive inrush current and inefficient energy storage capacitor utilization. Specifically, by hierarchically controlling the buck converter circuit enable signal via the GPIO pins of the SOC main chip, this method achieves delayed startup of the 5G radio frequency front-end and USB interface power supplies, significantly reducing the load surge at power-up and effectively suppressing inrush current. This improves the stability of the power input side and reduces the requirements for power adapter specifications.

[0042] Furthermore, an enable signal detection mechanism based on a precise voltage divider network design can promptly cut off the power supply to non-core loads during the initial power-down period, reducing their energy consumption on the energy storage capacitors. This allows more energy to be used to maintain core circuit operation and critical signal feedback, thereby extending the effective feedback period. Through optimized hardware circuit design, this solution achieves intelligent control of power timing without complex software intervention. This not only improves device reliability in voltage fluctuation scenarios, but also reduces hardware costs by reducing the required energy storage capacitor capacity, providing an efficient and economical solution for power management in high-speed wireless communication terminals.

[0043] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 This is a flow chart of a method for controlling the power timing of a 5G radio frequency front-end of a Wi-Fi optical terminal according to an embodiment of the present invention;

[0045] Figure 2 This is a diagram of a Wi-Fi optical terminal 5G radio frequency front-end power supply timing control circuit in one embodiment of the present invention;

[0046] Figure 3 This is a schematic diagram of a Wi-Fi PON gateway power tree structure according to an embodiment of the present invention;

[0047] Figure 4 This is a SOC power-on timing diagram in one embodiment of the present invention;

[0048] Figure 5 This is a DDR4 power-on timing diagram in one embodiment of the present invention;

[0049] Figure 6 FIG. 1 is a Wi-Fi power-on timing diagram in one embodiment of the present invention. DETAILED DESCRIPTION

[0050] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0051] In the embodiments of the present invention, the words "exemplary" or "for example" or the descriptions within "()" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present invention should not be construed as being preferred or advantageous over other embodiments or designs.

[0052] refer to Figures 1 to 6 As shown, the present invention provides the following preferred embodiments:

[0053] Example 1

[0054] In order to solve the problems of excessive inrush current when wireless communication terminal equipment is powered on and low energy utilization efficiency of energy storage capacitors when powered off in the prior art, this embodiment provides a Wi-Fi optical terminal 5G RF front-end power timing control method, further optimizes the specific implementation of power timing control, and realizes precise timing management of 5G RF front-end and USB interface power supply through signal control of GPIO pins of SOC main chip and design of voltage divider network. Figure 1 As shown in the figure, the process of the power supply timing control method is as follows:

[0055] S100: Outputs an initial low-level signal through the GPIO39 pin of the SOC main chip to control the N-MOS tubes Q2 and Q5 to the off state, ensuring that the EN pin of the BUCK chip P4U1 maintains a low level. This cuts off the 5V0_FEM power output of the 5G RF front-end and USB interface to initialize the enable signal control.

[0056] S200: After the DC12V0_IN input is powered on, the DDR4 2.5V power supply, SOC core 1.2V / 0.9V power supply and 1V8_BUCK reference voltage are started first. After the SOC core 1.2V / 0.9V power supply is stable and the voltage fluctuation is less than 5% for 2ms, the GPIO39 pin is triggered to output a high-level enable signal to start the core power timing first.

[0057] S300: The DC12V0_IN voltage is divided by the voltage-dividing resistors PR1 and PR2 to generate an enable signal that is input to the EN pin of P4U1. When the divided voltage value reaches the power-on threshold of P4U1, 1.3V±2%, P4U1 is activated to start outputting the 5V0_FEM power supply to detect the threshold of the voltage-dividing network enable signal.

[0058] S400: When it is detected that the DC12V0_IN voltage drops to the enable signal level below the P4U1 power-down threshold of 1.2V±2%, it automatically turns off N-MOS tubes Q2 and Q5, cuts off the EN pin enable signal of P4U1, and stops the 5V0_FEM power output to protect the input voltage from dropping.

[0059] S500: Reduce the energy consumption of the 5V0_FEM load on the energy storage capacitors P4C2 and P4C3, and use energy storage to maintain the SOC core circuit to complete data preservation during the power-off transition phase to optimize the energy distribution of the energy storage capacitors.

[0060] Specifically, in the initial state, the GPIO39 pin of the SOC main chip outputs an initial low-level signal by default. This signal controls the gate voltage of the N-MOS tubes Q2 and Q5, putting the two tubes in the cut-off state. It should be understood that when the N-MOS tube is cut off, the conductive channel between its drain and source is disconnected, thereby ensuring that the EN pin of the BUCK chip P4U1 cannot obtain the enable voltage and maintains a low-level state. At this time, the power input by DC12V0_IN cannot be converted into 5V0_FEM power through P4U1, thereby cutting off the power supply to the 5G RF front end and USB interface. The purpose of this operation is to prevent non-core loads from being connected at the initial stage of system startup, suppress the sudden increase in load at the moment of power-on from the source, and reduce the impact on the power input side.

[0061] Furthermore, when the DC12V0_IN input is powered on, the power supply system enters the core power supply-priority startup phase. During this process, the DDR4 2.5V power supply, the SoC core 1.2V / 0.9V power supplies, and the 1V8_BUCK reference voltage are prioritized. These core power supplies provide stable operating voltages for key components such as the SoC main chip and memory, and are essential for system initialization and logic processing. Once the SoC core 1.2V / 0.9V power supplies stabilize, with voltage fluctuations of less than 5% for 2ms, the system determines that the core circuitry has entered a reliable operating state and triggers the GPIO39 pin to switch from a low-level to a high-level enable signal. This high-level signal passes through the N-MOS transistor gate control circuit, turning on N-MOS transistors Q2 and Q5. This allows the enable signal generated by the voltage divider network to be transmitted to the EN pin of P4U1, paving the way for the subsequent startup of non-core load power supplies.

[0062] Furthermore, the DC12V0_IN voltage is divided down by resistors PR1 and PR2, generating a voltage signal that serves as the input to the EN pin of P4U1. When the DC12V0_IN voltage is within the normal operating range, the divided voltage value varies with the input voltage. When this value reaches the P4U1 power-on threshold of 1.3V±2%, the EN pin is activated, and P4U1 begins normal operation and outputs the 5V0_FEM power supply. It should be noted that the resistor value ratio of the divided voltage must be designed based on the P4U1's enable voltage range and input voltage fluctuation range to ensure that the divided voltage value accurately falls within the enable threshold range when the input voltage is 12V±10%, thereby preventing false triggering and delayed startup.

[0063] Furthermore, in the event of an input voltage drop, if the DC12V0_IN voltage drops below the P4U1 power-down threshold of 1.2V±2%, the signal generated by the voltage divider network cannot maintain the valid voltage level at the EN pin. At this point, N-MOS transistors Q2 and Q5 automatically shut down, disconnecting the EN pin's enable signal. Due to the loss of valid enable, P4U1 ceases operation, the 5V0_FEM power output is disconnected, and the loads on the 5G RF front-end and USB interface are removed, preventing them from further draining the energy storage capacitor. This mechanism effectively disconnects non-core loads before the input voltage drops to a level that affects the core circuitry, preserving limited energy storage for the core circuitry.

[0064] Through the above control process, the energy consumption of the 5V0_FEM load on the energy storage capacitors P4C2 and P4C3 is significantly reduced. During the power-off transition phase, the energy stored in the energy storage capacitor can maintain the operation of the SOC core circuit for a longer period of time, providing sufficient time for completing key data preservation and DYING GASP information feedback. It is understandable that the timely disconnection of non-core loads reduces energy diversion, allowing the core circuit to maintain a stable working state when the voltage drops, thereby improving the reliability of the equipment in abnormal power outage scenarios.

[0065] The benefit of this embodiment is that, through the coordinated control of GPIO pin signals and the voltage divider network, delayed startup and early shutdown of non-core load power supplies are achieved, effectively solving the problems of excessive power-on inrush current and waste of stored energy during power-off. This solution achieves intelligent control of power timing through optimized hardware circuit design without the need for complex software intervention. This not only improves the stability of the device in voltage fluctuation scenarios, but also extends the operating time of the core circuit through reasonable energy distribution, providing an efficient solution for power management of high-speed wireless communication terminals. The entire control process is based on real-time detection of voltage signals and automatic response of hardware logic, ensuring the coordinated operation of various functional modules under different power states, meeting the reliability requirements of telecommunications specifications for FTTR equipment.

[0066] Example 2

[0067] To address the issue of matching the GPIO pin drive capability with the gate drive requirements of the power MOS tube, this embodiment further refines the signal amplification logic of the N-MOS tube, implements reliable signal transmission and logic conversion through hierarchical control of the hardware circuit, and ensures precise control of the power device by the enable signal at different levels.

[0068] In the initial logic state, the GPIO39 pin of the SOC main chip uses a built-in pull-down resistor to achieve default grounding. The presence of this pull-down resistor ensures that the pin outputs a stable low level when the system is not initialized, avoiding false triggering caused by the floating state. At this time, the gate of the N-MOS tube Q2 is in the cut-off state due to the low level, and the high impedance characteristic between its drain and source cuts off the signal path of the subsequent circuit. Furthermore, the gate of the N-MOS tube Q5 is connected to the DC12V0_IN input voltage through the pull-up resistor P4R9. When Q2 is cut off, the gate of Q5 is pulled up to the high voltage level. Since the gate-source voltage difference of the N-MOS tube needs to exceed the threshold voltage to turn on, the gate-source voltage of Q5 is close to 12V at this time, and theoretically it should be turned on. However, it should be understood that in the circuit design here, the source of Q5 is not directly grounded, but is connected to the output end of the voltage divider network. Therefore, the actual gate-source voltage needs to be comprehensively determined based on the potential of the circuit nodes. When GPIO39 outputs a low level, Q2 is cut off, causing the gate of Q5 to be pulled up by P4R9, but its source potential is affected by the voltage divider network and is at a low level when the EN pin is not activated. The gate-source voltage difference is not enough to turn on Q5, thereby ensuring that the EN pin of P4U1 remains in a low level state.

[0069] When the SOC core power supply stabilizes, GPIO39 switches to a high-level output. This causes the gate voltage of Q2 to rise, exceeding its threshold voltage and turning on. This conduction pulls the gate voltage of Q5 down to near ground, ensuring that the gate-source voltage difference between Q5 and the on-state condition meets the conduction condition, turning Q5 on. Q5's conduction transmits the enable signal generated by the voltage divider network to the EN pin of P4U1. At this point, the voltage on the EN pin is no longer controlled by the pull-up resistor, but instead is determined by the voltage divider value of DC12V0_IN applied by resistors PR1 and PR2. It should be noted that Q2, as a signal amplifier, converts the low-drive signal from the GPIO pin into a high-current signal sufficient to drive Q5, avoiding the voltage drop or response delay that would result from directly driving Q5 from the GPIO. This two-stage amplifier structure, through level shifting and impedance matching, ensures that the enable signal can quickly and accurately control the start and stop of P4U1 even in scenarios with long traces or high capacitive loads.

[0070] In the signal transmission path, the pull-up resistor P4R9's resistance value must be selected to balance power consumption and response speed. Excessively large resistance values ​​may delay charging of the Q5 gate, while too small a value may increase static power consumption. The combination of an internal pull-down resistor and an external pull-up resistor creates a reliable high- and low-level clamping mechanism, preventing signal oscillation caused by electromagnetic interference or power supply fluctuations. This design is particularly important in high-temperature or voltage-fluctuating environments, ensuring that the N-MOS transistor's switching state is controlled solely by the GPIO signal, eliminating the influence of external noise.

[0071] The benefit of this embodiment lies in the construction of a reliable level-transfer link through signal amplification and logic conversion using two-stage N-MOS transistors, thus resolving the issue of matching the microcontroller pin drive capability with the enable terminal drive requirements of the power conversion chip. This not only achieves effective low-level cutoff and reliable high-level conduction of the enable signal, but also ensures signal stability under different power supply states through the coordination of the voltage divider network and pull-up / pull-down resistors. This provides a reliable front-end control circuit for subsequent threshold detection in the voltage divider network, improving the anti-interference capability and logic response accuracy of the entire power timing control system.

[0072] Example 3

[0073] To address the issue of insufficient enable signal threshold detection accuracy, this embodiment further clarifies the parameter design method for the voltage divider network. By establishing a mathematical mapping relationship between the input voltage and the enable signal, it ensures that P4U1 achieves accurate power-on startup and power-off protection within the input voltage fluctuation range, avoiding power supply malfunction due to threshold drift.

[0074] The core function of the voltage divider network is to convert the high voltage of DC12V0_IN into a low voltage signal suitable for recognition by the EN pin of P4U1. Its working principle is based on the voltage division principle of Ohm's law. Specifically, the voltage divider resistors PR1 and PR2 are connected in series between DC12V0_IN and ground, and the EN pin is connected to the node between the two resistors. Therefore, the EN pin voltage VEN satisfies the voltage divider formula:

[0075] Among them, V EN is the EN pin voltage of P4U1, V IN The DC12V0_IN input voltage is used, and PR1 and PR2 are the voltage divider resistor values. In specific implementations, ensure that when VIN is at the rated input voltage of 12V, VEN falls within the P4U1 power-on threshold of 1.3V ± 2%, that is, 1.274V to 1.326V. By adjusting the resistance ratio of PR1 and PR2, for example, using a high-precision thin-film resistor for PR1 and a temperature-coefficient-matched chip resistor for PR2, the voltage divider error can be controlled within ±1%, meeting the chip's threshold requirements.

[0076] In the input voltage drop detection scenario, the power-off threshold calculation requires reverse deduction of the input voltage protection point. Based on the P4U1 power-off threshold of 1.2V±2% (i.e., 1.176V to 1.224V), combined with the voltage divider formula, the DC12V0_IN protection threshold can be obtained:

[0077] Among them, V TH_DOWNis the power-off threshold voltage. This calculation process takes into account the tolerance of the resistors. By selecting resistors with an accuracy of ±1%, we ensure that the actual protection threshold remains within the design range despite temperature fluctuations or long-term operation. For example, when PR1 = 100kΩ and PR2 = 10kΩ, the input voltage range corresponding to the power-on threshold is 11.74V to 12.26V, and the input voltage range corresponding to the power-off threshold is 10.92V to 11.34V, resulting in a hysteresis voltage of 0.82V, which prevents frequent starting and stopping of the EN pin when the input voltage fluctuates near the threshold.

[0078] It's important to understand that the PCB layout of the voltage divider network is equally important for detection accuracy. Short traces and low parasitic capacitance should be used to minimize the impact of high-frequency noise on voltage sampling. Furthermore, high-frequency filter capacitors connected in parallel across the voltage divider resistors suppress transient fluctuations in the input voltage and ensure the stability of the VEN signal. This hardware-level threshold detection solution eliminates the need for real-time software calculations and implements real-time mapping of the voltage signal through a fixed resistor network, reducing system resource usage and improving response speed.

[0079] The benefit of this embodiment lies in the construction of a voltage detection mechanism with hysteresis characteristics through precise voltage-divider resistor ratios and threshold calculation formulas. This ensures stable operation of the P4U1 during normal input voltage fluctuations and timely shutdown during abnormal drops. This solution achieves precise threshold control through hardware circuitry, avoiding the delay issues associated with software detection. It also leverages the physical properties of resistors to ensure long-term threshold stability, providing a reliable voltage reference for power sequencing control and improving the system's adaptability and reliability in a wide range of input voltage scenarios.

[0080] Example 4

[0081] To solve the timing synchronization problem between the core power supply and the non-core load power supply, this embodiment further clarifies the method for determining the SOC core power supply startup delay time and the power-on interlock detection mechanism. Through hardware signal monitoring and software logic coordination, it ensures that the 5G RF front-end power supply is only started after the core system is fully ready, avoiding functional abnormalities caused by incomplete initialization.

[0082] During the core power supply startup process, the 1V8_BUCK reference voltage serves as a reference signal for system initialization. Its stability is crucial for determining the proper functioning of the core circuitry. Once the 1V8_BUCK voltage is detected to be stable, the system enters a delay phase. The delay time, T, is designed to be no less than the sum of 1ms and the software response time, Δt. The 1ms delay is a hardware stability margin to compensate for startup overshoot and oscillations during the power converter's startup. Δt is the time required for the SoC to initialize registers and configure the GPIO pins. This time is determined by combining typical values ​​in the chip manual with actual measured values ​​after program optimization. The delay mechanism ensures that the SoC has completed internal logic initialization, preventing the GPIO39 pin from outputting an invalid signal before configuration is complete, potentially causing the P4U1 to start up incorrectly.

[0083] During the power-on interlock detection phase, the system monitors the VEN signal output by the voltage divider network in real time through the PFI_DYING_GASP pin. P4U1 is triggered to start operation only when the DC12V0_IN voltage is ≥10.64V (corresponding to VEN ≥1.326V, or 102% of the upper power-on threshold) and the GPIO39 pin remains high for 1ms. This conditional setting includes two layers of interlock logic: the first is voltage amplitude detection, which ensures that the input voltage not only reaches the power-on threshold but also leaves a 2% safety margin to avoid unstable startup at critical voltages; the second is signal duration detection, which uses a 1ms high-level hold time to filter out transient interference signals and prevent false triggering.

[0084] During timing control, the SoC uses an internal timer to precisely control delays, while also monitoring the VEN signal using a hardware interrupt pin to avoid resource consumption caused by software polling. This interlocking mechanism, combining hardware and software, establishes a dual-check process between core power stabilization and the startup of non-core loads. This ensures that high-power modules like the 5G RF front-end are connected only when the system is fully operational, reducing power surges during startup and improving the reliability of the coordinated operation of various functional modules.

[0085] The benefit of this embodiment lies in the establishment of a rigorous sequential startup process through the quantized design of delay time and multiple constraints on power-on interlock conditions, ensuring that the startup of non-core load power supplies is fully synchronized with the initialization of the core system. This solution not only avoids functional abnormalities caused by irregular startup timing, but also improves the system's anti-interference capabilities in complex electromagnetic environments through dual detection of voltage amplitude and duration. This provides a reliable power supply for the stable operation of high-speed wireless communication modules and meets the stringent timing control requirements of communication equipment.

[0086] Example 5

[0087] In order to solve the problem of insufficient energy supply to the core circuit during the power-off transition phase, this embodiment further optimizes the configuration method of the energy storage capacitor. By connecting energy storage capacitors P4C2 and P4C3 in parallel at the input power supply end, a local energy storage unit is constructed to effectively suppress the transient current of the 5V0_FEM load and prioritize the distribution of core circuit energy.

[0088] The energy storage capacitor configuration principle is to form a low-impedance energy storage node at the DC12V0_IN input. By increasing the capacitive energy storage capacity of this node, it absorbs transient fluctuations in the input voltage and reduces the impact on the main power supply during startup of the 5V0_FEM power supply. Specifically, P4C2 and P4C3 use a combination of electrolytic capacitors and ceramic capacitors in parallel. The electrolytic capacitors provide high-capacity energy storage to meet the continuous power supply requirements of the core circuit during power-off, while the ceramic capacitors suppress high-frequency noise and improve the transient response characteristics of the power supply. The capacitor's voltage rating should be higher than the peak input voltage, such as 16V. The capacity is calculated based on the power consumption of the core circuit during power-off, ensuring that after disconnecting non-core loads, the remaining energy can maintain the core SOC circuit operation for at least 5ms to complete data preservation operations.

[0089] In terms of circuit layout, the energy storage capacitor should be placed as close as possible to the DC12V0_IN input interface and the BUCK chip P4U1 to shorten the current path, reduce line impedance, and improve energy storage efficiency. When the 5V0_FEM power supply starts, its transient peak current is first supplied by the energy storage capacitor, reducing the instantaneous load on the input power supply, thereby reducing the voltage fluctuation of the main power supply and avoiding affecting the stability of the core circuit. During the power-off phase, when the input voltage drops below the power-off threshold, the 5G RF front-end load is disconnected. The energy stored in the energy storage capacitor is no longer released to non-core loads. Instead, it is used entirely to maintain the 1.2V / 0.9V power supply of the SOC core and the 2.5V power supply of the DDR4, ensuring that the processor has sufficient time to execute the power-off protection procedure.

[0090] It's important to understand that the equivalent series resistance (ESR) and equivalent series inductance (ESL) of the energy storage capacitor have a significant impact on energy release efficiency. Choosing low-ESR tantalum capacitors or polymer electrolytic capacitors can reduce energy loss and extend discharge time. Furthermore, by separating P4C2 and P4C3 into primary energy storage capacitors and high-frequency filter capacitors, each responding to energy demands at different time scales, a hierarchical energy storage structure is formed that not only meets the needs of high-current discharge but also suppresses interference from high-frequency noise on the core circuit.

[0091] The benefit of this embodiment lies in the construction of a local energy storage system independent of the load power supply through the rational configuration of the input energy storage capacitors. This effectively reduces the transient impact of the 5V0_FEM load on the main power supply, while also enabling targeted energy distribution during power outages. This solution significantly improves the operating stability of the core circuit during power outage transitions through hardware-level energy storage optimization, eliminating the need for complex energy management chips. Simply through capacitor selection and layout design, it provides physical layer protection for the reliable preservation of critical data and enhances the device's fault tolerance in abnormal power outage scenarios.

[0092] Example 6

[0093] To address the existing need for optimizing power sequence control circuits in terms of driving capability and signal stability, this embodiment provides a Wi-Fi optical terminal 5G RF front-end power sequence control circuit. This circuit further refines the control circuit's hardware connections and functional module coordination mechanism. Built on the Wi-Fi solution's PON gateway hardware platform, the control circuit is specifically designed for 5G RF front-end power sequence control.

[0094] Specifically, the SOC interface module serves as the interactive hub between the control circuit and the main chip. Its GPIO39 pin adopts the 1.8V level standard. The default state is grounded through a built-in pull-down resistor to ensure that the BUCK circuit is in a disabled state in the initial state to avoid power-on shock. The GPIO39 pin is connected to the gate of the N-MOS tube Q2 through the resistor P4R8. This resistor has both current limiting and signal matching functions to prevent the gate voltage from causing damage to the MOS tube. The PFI_DYING_GASP pin is connected to the series node of the voltage divider resistors PR1 and PR2, which is used to monitor the trigger signal when the input voltage drops in real time and provide a voltage reference for system feedback.

[0095] Furthermore, the two-stage signal amplification circuit consists of N-MOS transistors Q2 and Q5, both of which have their sources directly grounded, forming a common-source amplifier structure. Q2's drain is connected to Q5's gate, enabling step-by-step signal amplification. When GPIO39 outputs a high level, Q2 turns on, lowering Q5's gate-to-ground impedance, causing Q5 to turn on. Its drain outputs a high level to the EN pin of the buck chip P4U1, enabling the drive. Conversely, when GPIO39 is low, Q2 turns off, and the Q5 gate remains off by default grounding, with no drive signal to the EN pin. This two-stage amplification design effectively improves the GPIO signal drive capability, ensuring reliable buck circuit control even in scenarios with long traces or high capacitive loads.

[0096] Furthermore, the voltage divider feedback network consists of voltage divider resistors PR1 and PR2 and filter capacitors P4C1 and P4C5. PR1 is connected to the input power supply DC12V0_IN, and PR2 is grounded. The node voltage is simultaneously input to the EN pin of P4U1 and the PFI_DYING_GASP pin of the SOC. It is important to understand that this network has dual functions: for the buck circuit, the node voltage is used to determine whether the input voltage meets the enable threshold; for the system, the voltage drop status is fed back to the main chip through the PFI_DYING_GASP pin, triggering the corresponding protection mechanism. The parallel capacitor filters high-frequency noise to ensure the stability of the voltage detection signal.

[0097] Furthermore, the buck power conversion circuit is centered around the P4U1 chip. The VIN pin connects to the DC12V0_IN, and the SW pin connects to the output terminal 5V0_FEM via inductor P4L1, forming a typical step-down converter topology. The FB pin is connected to ground via resistors P4R2 and P4R5, and to the output terminal via P4R4, forming a closed-loop feedback network that adjusts the switch duty cycle in real time to stabilize the output voltage. The output filter unit consists of multiple capacitors of varying capacitance in parallel, which, together with inductor P4L1, form an LC filter circuit to effectively suppress switching ripple and meet the stringent power supply noise requirements of 5G FEM chips. The energy storage buffer circuit, with capacitors P4C2 and P4C3 connected in parallel on the input side, stores transient energy, mitigating the impact of input voltage fluctuations on downstream circuitry. This is particularly important for maintaining short-term power supply during power switching or sudden load changes, enhancing system robustness.

[0098] Furthermore, the signal flow between modules follows the timing control logic: at the initial power-on stage, GPIO39 defaults to a low level, the two-stage amplification circuit is cut off, and the BUCK circuit does not work, preventing the 5G FEM and USB interface from consuming power prematurely. When the system is initialized, the main chip outputs a high level through GPIO39, which enables the BUCK circuit after two-stage amplification, gradually loading the load and suppressing the inrush current. When the power is turned off, the voltage divider network detects the input voltage drop and shuts down the BUCK circuit in advance, reducing the consumption of the energy storage capacitor and extending the DYING GASP feedback time.

[0099] The benefits of this embodiment are that, through modular design, the electrical connections and coordination mechanisms of each functional unit are clearly defined. The two-stage amplification circuit enhances signal drive reliability. The voltage divider feedback network achieves a deep integration of voltage detection and timing control. The output and energy storage filter circuits ensure power quality and transient response capabilities. This embodiment provides a complete implementation path for power timing control at the hardware level, meeting the stringent reliability and energy efficiency requirements of telecommunications FTTR equipment.

[0100] Example 7

[0101] To address the issues of gate signal stability and drive capability optimization in a two-stage signal amplification circuit, this embodiment further refines the gate bias structure of the N-MOS transistor. By providing a pull-up resistor P4R9 at the gate of the N-MOS transistor Q5, a reliable static bias network is constructed to ensure signal transmission accuracy and anti-interference capability.

[0102] Based on the two-stage signal amplification circuit of the previous embodiment, this embodiment clarifies that the drain of the N-MOS tube Q2 is directly connected to the gate of Q5 to form a pre-stage drive path. At the same time, the gate of Q5 is connected to the stable voltage node after the DC12V0_IN voltage is divided through the resistor P4R9, forming a pull-up bias structure. It should be understood that the setting of the pull-up resistor is intended to provide a default high-level bias for the gate of Q5, ensuring that the gate potential of Q5 is stable above the effective enable threshold when no drive signal is input, avoiding the state uncertainty problem caused by the floating signal link.

[0103] The specific circuit connections are as follows: The GPIO39 pin of the SOC interface module is connected to the gate of Q2 through resistor P4R8. This resistor has both current limiting and level matching functions, preventing excessive GPIO output current from damaging the device. The source of Q2 is grounded, and the drain is connected to the gate of Q5, forming the first stage of the common-source amplifier structure. The source of Q5 is also grounded, and the drain is connected to the EN pin of the buck chip P4U1. In addition to receiving the drain signal of Q2, its gate is pulled up to the reference voltage after DC12V0_IN is divided through P4R9 to ensure that Q5 maintains a certain level in the initial state or between signal transmissions.

[0104] The operating principle of this embodiment is as follows: When GPIO39 outputs a low level (default state or system standby), the gate voltage of Q2 is lower than the N-MOS transistor's conduction threshold, and Q2 is turned off. At this time, the gate of Q5 is pulled up to a voltage above its conduction threshold (e.g., 3.3V) through P4R9, turning Q5 on. The drain voltage approaches the source potential (ground level), thereby pulling the EN pin low and shutting down the buck power conversion circuit. When GPIO39 outputs a high level (power is enabled after system initialization is completed), Q2 turns on, the drain voltage drops to near ground, and the gate of Q5 is pulled down to below the conduction threshold, turning Q5 off. The EN pin is pulled up to the enable voltage (e.g., 2.5V) through the voltage divider feedback network (composed of PR1 and PR2), triggering the buck chip to operate and output 5V0_FEM power. This negative logic control mechanism, through the pull-up resistor P4R9, ensures that Q5 is reliably turned on when Q2 is turned off, preventing false shutdown caused by a floating gate, thereby ensuring stable shutdown of the buck circuit in standby mode.

[0105] It's important to understand that the resistance values ​​of resistors P4R8 and P4R9 must meet the circuit drive requirements: P4R8 is determined based on the output capability of GPIO39 and the gate capacitance of Q2, typically selecting 10kΩ to 50kΩ to limit transient current and suppress ringing. The resistance of P4R9 must ensure that the gate voltage after pull-up is higher than the threshold voltage of Q5 while also optimizing power consumption, with a typical value of 4.7kΩ to 10kΩ. The combination of these two allows Q2 to effectively pull down the gate potential of Q5 when it's on, while maintaining Q5's gate high level through P4R9 when it's off, forming a clear switch logic boundary.

[0106] Furthermore, the introduction of a pull-up resistor improves the circuit's anti-interference performance. In high-frequency electromagnetic environments, unterminated gate pins are susceptible to noise, causing gate voltage fluctuations and triggering Q5 malfunction. By fixing the gate to a stable potential via P4R9, the effects of common-mode and differential-mode noise are effectively suppressed, ensuring signal transmission purity. Simultaneously, the two-stage amplification structure, through the current amplification effect of Q2, converts the small drive current of GPIO39 into a gate control signal for Q5, resolving the issue of insufficient drive capability for the SOC main chip pins. This is particularly suitable for scenarios where control signal routing over long distances is required in PCB layouts, avoiding drive failures due to signal attenuation.

[0107] The benefit of this embodiment lies in establishing a stable static bias mechanism by placing a pull-up resistor P4R9 on the gate of Q5. This eliminates the state uncertainty caused by a floating gate and ensures reliable operation of the two-stage amplifier circuit during timing control signal switching. This design optimizes signal transmission anti-interference capabilities and enhances the accuracy of the buck circuit enable control. This provides a more stable hardware foundation for power timing control in the 5G RF front-end of Wi-Fi optical terminals, meeting the requirements for long-term reliable operation of communication equipment in complex electromagnetic environments.

[0108] Example 8

[0109] To address the output voltage stability issue of the BUCK power conversion circuit, this embodiment further refines the resistor and capacitor configuration of the feedback regulation network. By optimizing the voltage divider ratio and frequency response of the feedback path, precise control of the 5V0_FEM output voltage is achieved.

[0110] The feedback regulation network, centered around the FB pin of the buck chip P4U1, forms a closed voltage negative feedback loop. One end of resistor P4R2 is connected to the 5V0_FEM output, while the other end is connected to the FB pin via resistors P4R4 and P4R7 in series. Capacitor P4C11 is connected in parallel across P4R4 to form an RC filter, suppressing high-frequency noise interference on the feedback signal. The other end of P4R2 is grounded via resistor P4R5, forming a voltage divider with P4R4 and P4R7. This converts the output voltage proportionally to the feedback voltage at the FB pin, which is then compared with the chip's internal reference voltage to adjust the switch duty cycle.

[0111] It's important to understand that the resistance ratio of the feedback resistors directly determines the setpoint of the output voltage. Based on the reference voltage of the P4U1 chip, in this embodiment, P4R2 and P4R5 form the pull-down resistors, while P4R4 and P4R7 form the pull-up resistors. The actual ratio must meet the 5V output requirement. Capacitor P4C11 compensates for the phase margin of the feedback loop, preventing high-frequency oscillation and improving loop stability. Its capacitance should be selected based on the inductor P4L1 and the ESR characteristics of the output capacitor. The optimal compensation point should be determined through Bode plot analysis.

[0112] The feedback regulation process is as follows: When the 5V0_FEM output voltage increases, the FB pin voltage increases accordingly. The chip's internal controller reduces the duty cycle, shortening the SW pin output pulse width, thereby lowering the output voltage. Conversely, when the output voltage decreases, the duty cycle increases, increasing the output voltage, creating a dynamic balance. The introduction of resistors P4R7 increases the adjustable parameters of the feedback loop, allowing fine-tuning of the voltage divider ratio under different load conditions, ensuring that voltage regulation meets specifications under both light and heavy loads.

[0113] Furthermore, the output filter unit's multiple capacitors (P4C4, P4C6-P4C10) utilize a combination of varying capacitance values ​​to balance low-frequency filtering and high-frequency decoupling: large-capacity electrolytic capacitors suppress low-frequency ripple, while small-capacity ceramic capacitors handle high-frequency noise. Together with inductor P4L1, this multi-stage filter network keeps output ripple below 50mV, meeting the stringent power supply noise requirements of 5G RF chips. The coordinated design of the feedback network and filter circuit effectively reduces voltage overshoot and drop during load transient response, improving the power system's dynamic performance.

[0114] The benefit of this embodiment is that by precisely designing the resistance ratio and RC compensation parameters of the feedback regulation network, high-precision and stable output voltage of the buck circuit is achieved. Combined with the multi-order filtering structure, the power quality is significantly improved, providing a clean and stable power supply environment for the 5G RF front-end. At the same time, the adaptability of the power supply system over a wide load range is enhanced, ensuring reliable operation of the equipment under different operating conditions.

[0115] Embodiment 9

[0116] To address the integration and reliability issues of power sequencing control systems, this embodiment proposes a power sequencing control system for a 5G RF front-end Wi-Fi optical terminal. This system builds a complete hardware architecture encompassing power input, sequencing control, load drive, and energy storage filtering. These modules work together to achieve full-link control of the 5G RF front-end power supply.

[0117] Specifically, the power input module accepts a DC12V±10% power supply (10.8V to 13.2V). Its DC12V0_IN output port incorporates a built-in surge protection device, such as a TVS diode or varistor, to suppress transient interference from the power grid and protect back-end circuits from high-voltage surges. The module also features a reverse polarity protection design, using Schottky diodes or MOS transistors for polarity protection to prevent device damage caused by reverse power connection.

[0118] Furthermore, the timing control module integrates the Wi-Fi optical terminal's 5G RF front-end power timing control circuit, communicating with the main SoC chip via GPIO39 and PFI_DYING_GASP pins. GPIO39 receives the main chip's enable control signal, which drives the buck chip through a two-stage amplification circuit. The PFI_DYING_GASP pin provides real-time feedback on input voltage drop status, triggering the main chip to execute the DYING GASP information reporting process. The module's internal multi-layer PCB layout isolates the high-frequency switching circuit from the low-frequency control circuit, reducing electromagnetic coupling interference and ensuring signal integrity.

[0119] Furthermore, the load driver module's input is connected to the 5V0_FEM output, powering the 5G FEM chip and USB interface. An integrated overcurrent protection fuse quickly blows when the load current exceeds the rated value (e.g., 3A), cutting off the power path and preventing overcurrent-induced device burnout or PCB trace damage. The module utilizes a distributed power supply design, with the 5G FEM and USB interface connected to their outputs via separate traces. This reduces noise coupling between them and ensures RF signal purity.

[0120] Furthermore, the energy storage filter module includes electrolytic capacitors P4C2 and P4C3 on the input side, which store transient energy and maintain short-term power supply during power input fluctuations, meeting the energy requirements during the DYING GASP feedback period. On the output side, multiple ceramic capacitors (P4C4, P4C6-P4C10) form a high-frequency decoupling network, which, together with inductor P4L1, suppresses switching ripple and ensures low-noise output voltage characteristics. The layout of the input and output capacitors follows the principle of "close to the power supply and close to the load" to shorten the high-frequency current loop and reduce the impact of parasitic inductance.

[0121] The workflow of this embodiment is as follows: when power is on, the power input module filters the surge signal, the energy storage capacitor is charged, the timing control module waits for the main chip to complete initialization, enables the BUCK circuit through GPIO39, and the load driver module gradually loads the 5GFEM and USB interface power supply; when power is off, the voltage divider feedback network detects that the input voltage is lower than 9.43V, triggers the PFI_DYING_GASP signal, the main chip starts reporting information, and at the same time the timing control module shuts down the BUCK circuit, cuts off the load power supply, reduces the consumption of the energy storage capacitor, and extends the feedback time.

[0122] Furthermore, the electrical isolation and grounding design between modules complies with EMC specifications. The power and signal grounds are connected through a single point to avoid ground loop noise and ensure stable system operation in complex electromagnetic environments. The overcurrent protection threshold and fuse specifications of the load driver module are set according to the maximum operating current of the 5G FEM chip, balancing protection sensitivity and normal operating margin.

[0123] The benefit of this embodiment is that, through modular integrated design, a complete control link from power input to load drive is constructed. The surge protection and overcurrent protection mechanisms improve the safety of the system. The energy storage filter and electromagnetic compatibility design ensure the quality and reliability of the power supply. The coordinated work of the timing control module and the main chip realizes the precise timing management of the 5G RF front-end power supply.

[0124] Example 10

[0125] This embodiment provides a storage medium storing a computer program that, when executed by a processor, implements a method for controlling the timing of a power supply of a 5G radio frequency front-end of a Wi-Fi optical terminal. The storage medium includes, but is not limited to, non-transitory storage media such as random access memory (RAM), read-only memory (ROM), flash memory, and a hard disk drive.

[0126] Specifically, the computer program includes an instruction set for controlling the output level of the GPIO39 pin on the SOC main chip, enabling power-up timing control of the buck circuit. It also includes instruction logic for monitoring the voltage signal on the PFI_DYING_GASP pin, triggering the corresponding power-down feedback process. It also includes a driver program that works in conjunction with the hardware control circuit to ensure precise matching of software logic and hardware timing. The storage medium is designed to adhere to embedded system storage specifications, and the program code has been cross-compiled and optimized to adapt to the PON SOC main chip architecture, achieving low power consumption and high real-time performance.

[0127] By solidifying the control method in the storage medium in the form of software, a deep integration of hardware timing control and software logic is achieved, allowing flexible adjustment of power timing parameters through firmware upgrades to adapt to the power supply requirements of different models of 5G FEM chips, thereby improving the scalability and compatibility of the system.

[0128] Although the present invention has been described above in detail with reference to its preferred embodiments, it is to be understood that the present invention is not limited to the embodiments described above. Instead, various modifications and changes may be made by those skilled in the art without departing from the spirit of the invention, and these modifications and changes should fall within the scope defined by the appended claims and their equivalents.

Claims

1. A Wi-Fi optical terminal 5G radio frequency front-end power supply timing control method, characterized in that: The control method comprises the following steps: The GPIO39 pin of the SOC main chip outputs an initial low-level signal to control the N-MOS transistors Q2 and Q5 to the off state, ensuring that the EN pin of the BUCK chip P4U1 maintains a low level. This cuts off the 5V0_FEM power output of the 5G RF front-end and USB interface to initialize the enable signal control. After the DC12V0_IN input is powered on, the DDR4 2.5V power supply, the SOC core 1.2V / 0.9V power supply and the 1V8_BUCK reference voltage are started first. After the SOC core 1.2V / 0.9V power supply is stable and the voltage fluctuation is less than 5% for 2ms, the GPIO39 pin is triggered to output a high-level enable signal to start the core power timing first; The DC12V0_IN voltage is divided by the voltage-dividing resistors PR1 and PR2 to generate an enable signal that is input to the EN pin of P4U1. When the divided voltage value reaches the power-on threshold of P4U1, 1.3V±2%, P4U1 is activated to start outputting the 5V0_FEM power supply to detect the threshold of the voltage-dividing network enable signal. When it is detected that the DC12V0_IN voltage drops to the enable signal level below the P4U1 power-down threshold of 1.2V±2%, the N-MOS transistors Q2 and Q5 are automatically turned off, the EN pin enable signal of P4U1 is cut off, and the 5V0_FEM power supply output is stopped to protect the input voltage from dropping. Reduce the energy consumption of the 5V0_FEM load on the energy storage capacitors P4C2 and P4C3, and use energy storage to maintain the SOC core circuit to complete data preservation during the power-off transition phase to optimize the energy distribution of the energy storage capacitors.

2. The Wi-Fi optical terminal 5G RF front-end power timing control method according to claim 1, characterized in that: The signal amplification logic of the N-MOS tubes Q2 and Q5 is: By default, the GPIO39 pin is grounded through a built-in pull-down resistor. When the output is low, the N-MOS transistor Q2 is cut off, and the gate voltage of the N-MOS transistor Q5 is pulled up to DC12V0_IN through P4R9, turning off Q5. When the GPIO39 outputs a high level, the N-MOS transistor Q2 is turned on and pulls down the gate voltage of the N-MOS transistor Q5, turning on the N-MOS transistor Q5 and raising the EN pin voltage of P4U1 to the output value of the voltage divider network.

3. The Wi-Fi optical terminal 5G RF front-end power timing control method according to claim 1, characterized in that: The voltage divider network enable signal is calculated as follows: Among them, V EN is the EN pin voltage of P4U1, V IN DC12V0_IN is the input voltage, PR1 and PR2 are the voltage divider resistor values, ensuring that the enable signal falls within the 1.3V±2% startup range at power-on; The threshold value of the input voltage drop is calculated as follows: Based on the power-off threshold of P4U1 (1.2V±2%) and the resistance ratio of the voltage divider resistors PR1 and PR2, the protection threshold of DC12V0_IN is calculated as: Among them, V TH_DOWN is the power-off threshold voltage of P4U1.

4. The Wi-Fi optical terminal 5G radio frequency front-end power timing control method according to claim 1, characterized in that: The startup delay time of the SOC core 1.2V / 0.9V power supply is determined as follows: After detecting that the 1V8_BUCK reference voltage is stable, the delay time T≥1ms+Δt, where Δt is the software response time, is set. After the SOC main chip completes register initialization, an enable signal is sent through the GPIO39 pin to start the 5V0_FEM power supply. Before the 5V0_FEM power supply is started, the output signal of the voltage divider network is monitored in real time through the PFI_DYING_GASP pin. If and only if the DC12V0_IN voltage is ≥10.64V, the corresponding enable signal is ≥1.326V, and the GPIO39 pin is high for 1ms, P4U1 is triggered to start working for power-on interlock detection.

5. The Wi-Fi optical terminal 5G radio frequency front-end power timing control method according to claim 1, characterized in that: The configuration method of the energy storage capacitors P4C2 and P4C3 is: The energy storage capacitors P4C2 and P4C3 are connected in parallel at the DC12V0_IN input end to reduce the transient impact of the 5V0_FEM power supply on the main capacitor by increasing the energy storage capacity, ensuring that the remaining energy is first supplied to the SOC core circuit when power is off.

6. A Wi-Fi optical terminal 5G radio frequency front-end power supply timing control circuit, used to implement the Wi-Fi optical terminal 5G radio frequency front-end power supply timing control method according to any one of claims 1 to 5, characterized in that: The control circuit comprises: The SOC interface module includes a GPIO39 pin and a PFI_DYING_GASP pin. The GPIO39 pin is connected to the gate of the N-MOS tube Q2 through a resistor P4R8, and the PFI_DYING_GASP pin is connected to the node of the voltage divider resistors PR1 and PR2. Two-stage signal amplification circuit, the sources of the N-MOS transistors Q2 and Q5 are both grounded, and the drain of the N-MOS transistor Q5 is connected to the EN pin of the BUCK chip P4U1 to achieve two-stage amplification drive of the GPIO39 signal; A voltage divider feedback network, in which a voltage divider resistor PR1 with one end connected to DC12V0_IN is connected in series with a voltage divider resistor PR2 with one end grounded. The node voltages are input to the EN pin of the BUCK chip P4U1 and the PFI_DYING_GASP pin of the SOC respectively. The parallel capacitors P4C1 and P4C5 filter the voltage divider signal. Buck power conversion circuit, the VIN pin of the buck chip P4U1 is connected to DC12V0_IN, the SW pin is connected to the output terminal 5V0_FEM through the inductor P4L1, the FB pin is grounded through resistors P4R2 and P4R5, and the resistor P4R4 is connected to the output terminal of 5V0_FEM to form a feedback regulation network; Output filter unit: The output end of 5V0_FEM is connected in parallel with capacitors P4C4, P4C6, P4C7, P4C8, P4C9, and P4C10, which together with inductor P4L1 form an LC filter circuit to suppress output ripple. Energy storage buffer circuit, capacitors P4C2 and P4C3 are connected in parallel to the DC12V0_IN input terminal to store transient energy and stabilize the input voltage.

7. The Wi-Fi optical terminal 5G radio frequency front-end power supply timing control circuit according to claim 6, characterized in that: The gate of the N-MOS transistor Q2 is connected to GPIO39 via a resistor P4R8 , and the drain is connected to the gate of the N-MOS transistor Q5 , and the gate of the N-MOS transistor Q5 is pulled up via a resistor P4R9 .

8. The Wi-Fi optical terminal 5G radio frequency front-end power supply timing control circuit according to claim 6, characterized in that: One end of the resistor P4R2 is connected to the 5V0_FEM output terminal, and the other end is connected to the FB pin of the BUCK chip P4U1 through resistors P4R4 and P4R7. A capacitor P4C11 is connected in parallel across the resistor P4R4, and the other end of the resistor P4R2 is grounded through a resistor P4R5 to achieve feedback regulation of the output voltage.

9. A Wi-Fi optical terminal 5G radio frequency front-end power supply timing control system, characterized in that: The control system includes: A power input module is connected to a DC12V±10% power supply. The output end of the power input module is connected to the DC12V0_IN interface of the control circuit and has a built-in surge protection device. A timing control module, which integrates the control circuit according to any one of claims 6 to 8, communicates with the SOC main chip through the GPIO39 and PFI_DYING_GASP pins, and is used for enabling control and voltage detection of the 5G RF front-end power supply of the Wi-Fi optical terminal; A load driver module, whose input is connected to the 5V0_FEM output of the control circuit, is used to power the 5G FEM chip and the USB interface, and the load driver module has a built-in overcurrent protection fuse; The energy storage filter module includes capacitors P4C2 and P4C3 at the input end and capacitors P4C4, P4C6-P4C10 at the output end, and is used to maintain the stability and transient response of the power supply signal.

10. A storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by the processor, it implements the Wi-Fi optical terminal 5G RF front-end power timing control method according to any one of claims 1 to 5.

Images