Jitter testing methods, apparatus, equipment, storage media, and computer program products

Abstract

This application provides a jitter testing method, apparatus, device, storage medium, and computer program product, relating to the field of signal measurement technology, capable of accurately testing the jitter value of a signal. The method includes: determining the device jitter value of the test equipment for the signal under test based on the noise floor value of the test equipment and the slew rate of the signal under test; correcting the random jitter value of the signal under test based on the device jitter value to obtain a corrected random jitter value; and determining the actual jitter value of the signal under test based on the corrected random jitter value and the deterministic jitter value of the signal under test.

Description

Technical Field

[0001] This application relates to the field of signal measurement technology, and in particular to a jitter testing method, apparatus, device, storage medium, and computer program product. Background Technology

[0002] Signal jitter measurement (or testing) is a key indicator for communication protocol conformance testing. While an oscilloscope can typically be used for jitter testing, the oscilloscope's operation itself can introduce interference, leading to inaccurate results. Therefore, accurately measuring signal jitter has become a pressing technical problem. Summary of the Invention

[0003] This application discloses a jitter testing method, apparatus, device, storage medium, and computer program product for accurately testing the jitter value of a signal.

[0004] Firstly, this application provides a jitter testing method. This method can be executed by a testing device, its processor, chip, or chip system, or by a logic module or software capable of implementing all or part of the testing device. The method includes: determining the device jitter value of the test device for the signal under test based on the noise floor of the test device and the slew rate of the signal under test; correcting the random jitter value of the signal under test based on the device jitter value to obtain a corrected random jitter value; and determining the actual jitter value of the signal under test based on the corrected random jitter value and the deterministic jitter value of the signal under test. Based on the technical solution provided by this application, after determining the device jitter value of the test device for the signal under test based on the noise floor of the test device and the slew rate of the signal under test, the random jitter value of the signal under test can be corrected based on the device jitter value to obtain the corrected random jitter value. Since the random jitter value of a signal is highly affected by the noise floor of the testing equipment, based on this principle, the random jitter value of the signal under test can be corrected using the equipment jitter value of the testing equipment. This reduces the impact of the testing equipment noise floor on the jitter value of the signal under test, resulting in a more accurate random jitter value. Thus, based on this corrected random jitter value and the deterministic jitter value of the signal under test, the actual jitter value of the signal under test can be accurately measured.

[0005] In one possible implementation, the random jitter value of the signal under test is corrected based on the device jitter value to obtain a corrected random jitter value. This includes: correcting the random jitter value of the signal under test based on the device jitter value and a correction coefficient corresponding to the signal under test, thus obtaining a corrected random jitter value. In this way, the correction coefficient corresponds to the signal under test. Based on this correction coefficient and the device jitter value of the test equipment, the random jitter value of the signal under test can be easily and quickly corrected, and the corrected random jitter value is more accurate.

[0006] In one possible implementation, the corrected random jitter value satisfies a first formula, which is: .in, This represents the corrected random jitter value. This represents the random jitter value of the signal under test. This represents the correction factor. This indicates the device jitter value.

[0007] Based on this implementation method, the random jitter value can be corrected based on a pre-set correction formula, which is simple and convenient.

[0008] In one possible implementation, the method further includes: determining multiple jitter points in the waveform data of the signal under test based on the waveform data of the signal under test, and determining a correction coefficient based on the waveform data of the multiple jitter points.

[0009] Based on this implementation, since the random jitter value of the signal is affected by the jitter transitions of the waveform, the correction coefficient calculated from the waveform data of the jitter points where jitter transitions occur in the waveform of the signal under test can accurately correct the random jitter value of the signal under test. In one possible implementation, the plurality of jitter points includes two jitter points near the jitter transition positions in the waveform data of the signal under test, and the correction coefficient satisfies the second formula, which is:

[0010] .

[0011] in, The correction factor, , This represents the ideal amplitude at two points near the jitter transition position. , This represents the noise value introduced at each of the two points.

[0012] Based on this implementation method, the amplitude of the jitter transition is calculated by using the amplitude of the two jitter points at the jitter transition position. Compared with simple linear interpolation, the calculation result is more accurate.

[0013] In one possible implementation, the aforementioned deterministic jitter value and random jitter value can be determined by: determining the normalized jitter histogram of the signal under test, and performing jitter separation on the normalized jitter histogram to obtain the random jitter value and deterministic jitter value of the signal under test.

[0014] Based on this implementation method, by performing jitter separation on the normalized jitter histogram of the signal under test, the random jitter value and the definite jitter value of the signal under test can be obtained directly, quickly and accurately.

[0015] In one possible implementation, determining the normalized jitter histogram of the signal under test includes: drawing the normalized jitter histogram of the signal under test based on the time deviation between the ideal edge position and the actual edge position of the signal under test.

[0016] Based on this implementation method, since the normalized jitter histogram of the signal is based on TIE as the data source, the normalized jitter histogram of the signal under test can be accurately obtained by plotting the time deviation distribution between the actual edge position and the ideal edge position of the signal under test.

[0017] In one possible implementation, the above-mentioned determination of the device jitter value of the test equipment affecting the signal under test based on the noise floor value of the test equipment and the slew rate of the signal under test includes: determining the device jitter value of the test equipment as the ratio of the noise floor value of the test equipment to the slew rate of the signal under test, which is simple and convenient.

[0018] In one possible implementation, the actual jitter value of the signal under test is less than the device jitter value. Thus, the accuracy of the actual jitter value of the signal under test can be determined by comparing it with the device jitter value.

[0019] In one possible implementation, the signal under test is a four-level pulse-amplitude modulation (PAM) signal. This allows for accurate determination of the actual jitter value of the PAM signal, expanding the application scenarios of this solution.

[0020] Secondly, this application provides a jitter testing apparatus, which can be the testing device described in the first aspect above, or any implementation of the first aspect, or an apparatus containing the aforementioned testing device, or an apparatus contained within the aforementioned testing device, such as a chip. The jitter testing apparatus includes modules, units, or means that implement the aforementioned methods. These modules, units, or means can be implemented in hardware, software, or by hardware execution to achieve software implementation. The hardware or software includes one or more modules or units corresponding to the aforementioned functions.

[0021] In some possible designs, the jitter testing device may include a determination module and a correction module. The determination module can be used to determine the device jitter value of the signal under test based on the noise floor value of the test device and the noise level of the signal under test. The correction module can be used to correct the random jitter value of the signal under test based on the device jitter value, obtaining a corrected random jitter value. The determination module can also be used to determine the actual jitter value of the signal under test based on the corrected random jitter value and the deterministic jitter value of the signal under test.

[0022] In one possible implementation, the correction module is specifically used to correct the random jitter value of the signal under test based on the device jitter value and the correction coefficient corresponding to the signal under test, so as to obtain the corrected random jitter value.

[0023] In one possible implementation, the corrected random jitter value satisfies a first formula, which is: .in, This represents the corrected random jitter value. This represents the random jitter value of the signal under test. This represents the correction factor. This indicates the device jitter value.

[0024] In one possible implementation, the correction coefficient is determined as follows: based on the waveform data of the signal under test, multiple jitter points in the waveform data are determined, and the correction coefficient is determined based on the waveform data of the multiple jitter points.

[0025] In one possible implementation, the plurality of jitter points includes two jitter values ​​near the jitter transition position in the waveform data, and the correction coefficient satisfies the second formula, which is:

[0026] .

[0027] in, This represents the correction factor. , This represents the ideal amplitude of two jitter points near the jitter transition location. , This represents the noise value introduced by each of the two jitter points.

[0028] In one possible implementation, the deterministic jitter value and the random jitter value of the signal under test are determined by: determining the normalized jitter histogram of the signal under test, and performing jitter separation on the normalized jitter histogram to obtain the random jitter value and the deterministic jitter value of the signal under test.

[0029] In one possible implementation, the determining module is specifically used to: plot a normalized jitter histogram of the signal under test based on the time deviation between the ideal edge position and the actual edge position of the signal under test.

[0030] In one possible implementation, the determining module is specifically used to: determine the device jitter value of the test device as the ratio of the noise floor value of the test device to the slew rate of the signal under test.

[0031] In one possible implementation, the actual jitter value of the signal under test is less than the device jitter value.

[0032] In one possible implementation, the signal to be measured is a four-level pulse-amplitude modulation (PAM) signal.

[0033] Thirdly, a testing device is provided, which may include any of the jitter testing devices described in the third aspect.

[0034] Fourthly, a computer-readable storage medium is provided that stores a computer program or instructions that, when run on a jitter testing apparatus, enable the jitter testing apparatus to perform the methods of any of the above aspects or any implementation thereof.

[0035] Fifthly, a computer program product containing instructions is provided, which, when run on a jitter testing apparatus, enables the jitter testing apparatus to perform the methods of any of the above aspects or any implementation thereof.

[0036] In a sixth aspect, a jitter testing apparatus (e.g., the jitter testing apparatus may be a chip or a chip system) is provided, the jitter testing apparatus including a processor for implementing the functions involved in any of the above aspects or any implementation thereof.

[0037] In some possible designs, the jitter testing device includes a memory for storing necessary program instructions and data.

[0038] In some possible designs, when the device is a chip system, it can be composed of chips or contain chips and other discrete components.

[0039] It is understood that when the jitter testing device provided by either of the above parties is a chip, the above-mentioned sending action / function can be understood as output, and the above-mentioned receiving action / function can be understood as input.

[0040] The technical effects of any of the implementation methods in aspects two through six can be found in the technical effects of the corresponding implementation method in aspect one, and will not be repeated here.

[0041] It should be noted that any of the possible implementations of any of the above aspects can be combined, provided that the solutions do not contradict each other. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 A schematic diagram illustrating a signal strength change provided in an embodiment of this application;

[0044] Figure 2 A schematic diagram of a jitter testing method provided in an embodiment of this application;

[0045] Figure 3 This is a schematic diagram of the structure of a testing device provided in an embodiment of this application;

[0046] Figure 4 A schematic diagram of a signal jitter test provided in an embodiment of this application;

[0047] Figure 5 A schematic diagram of a device noise floor configuration interface provided in an embodiment of this application;

[0048] Figure 6 A schematic diagram of another jitter testing method provided in an embodiment of this application;

[0049] Figure 7 A schematic diagram illustrating yet another jitter testing method provided in an embodiment of this application;

[0050] Figure 8 A schematic diagram of a signal jitter transition provided in an embodiment of this application;

[0051] Figure 9 A schematic diagram illustrating yet another jitter testing method provided in an embodiment of this application;

[0052] Figure 10 A schematic diagram illustrating yet another jitter testing method provided in an embodiment of this application;

[0053] Figure 11 This is a schematic diagram of the structure of a jitter testing device provided in an embodiment of this application. Detailed Implementation

[0054] Communication protocol conformance testing is a crucial step in ensuring that communication devices and systems can communicate in accordance with predetermined standards and specifications. Conformance testing not only helps verify the compatibility and interoperability of communication devices but also improves the reliability and security of the entire communication system.

[0055] Taking the IEEE 802.3bs / cd / ck protocol, OIF-CEI 56G / 112G protocol, and PCIe 6 protocol as examples, these communication protocols all adopt the four-level pulse-amplitude modulation (PAM4) signaling format. PAM4 jitter measurement is a key indicator for communication protocol conformance testing.

[0056] Typically, conformance testing uses oscilloscopes for data acquisition. However, noise generated by the oscilloscope's analog front-end introduces additional random jitter, causing the jitter test results to exceed the true value, thus preventing the test results from meeting protocol requirements. Furthermore, the PCIe 6 protocol explicitly requires the subtraction of random jitter (RJ) introduced by the background noise of the test equipment (such as the oscilloscope). Therefore, accurate calibration and subtraction of jitter introduced by the noise of the test equipment are of great importance.

[0057] Furthermore, the IEEE 802.3bs / cd / ck and OIF-CEI protocols stipulate that jitter values ​​must be calculated based on 12 specific transition edges in a pseudo-random binary sequence 13 quadrature (PRBS13Q) code pattern. However, common technical solutions rely on probability calculations / measurements based on actual sample sizes, such as calculating / measuring the nth percentile unit interval jitter (Jnu). Here, n is a positive integer, for example, 4 or 5. When n=4, calculating / measuring the 4th percentile unit interval jitter (J4u) requires more than 10,000 repetitions of the code pattern cycle, resulting in a long overall measurement time and impacting testing efficiency. When n=5, the calculation / measuring time for the 5th percentile unit interval jitter (J5u) increases tenfold. It is evident that testing time increases exponentially with decreasing probability. Therefore, the smaller the sample size, the higher the testing efficiency of jitter value measurement.

[0058] In summary, there is an urgent need to provide a device jitter calibration technology to improve the testing efficiency and measurement accuracy of PAM4 jitter measurement.

[0059] To address the aforementioned issues, in some embodiments, the degree of influence of the test device's noise floor on the signal jitter value can be determined based on the difference between the jitter value at the ideal transition position and the jitter value at the actual transition position.

[0060] The ideal transition point of a signal refers to the theoretical time point at which the signal abruptly changes from one steady state (e.g., 0) to another steady state (e.g., 1). The ideal transition point can be determined based on prior knowledge of the signal or a standard knowledge template. For example, prior knowledge of the signal may include information such as the ideal transition point, slew rate, and noise level. The slew rate is used to measure the rate of change of the signal voltage.

[0061] Generally, the slew rate of a signal can be determined based on the change in voltage and the corresponding change in time. For example, the slew rate is equal to the ratio between the change in voltage and the corresponding change in time. For instance, if the voltage of a signal increases from 5 volts (V) to 10V in 5 seconds (s), then the slew rate of the signal = (10V - 5V) / 5s = 1V / s. Of course, the calculation method for the slew rate of signals with different waveforms can be adjusted based on the above method.

[0062] In some scenarios, the signal is a digital signal (with a square waveform). The slew rate of a digital signal is typically a ratio between 10% and 90%. For example, if the voltage of a signal jumps from 0V to 5V with a rise time of 10 nanoseconds (ns), then the slew rate of the signal is = =0.4V / ns.

[0063] In other scenarios, the signal is a sinusoidal wave. The maximum slew rate of a sinusoidal signal occurs at the zero-crossing point, and is related to the signal frequency f and peak voltage V. peak Related. For example, the maximum slew rate of a sine wave signal = 2πfV peak For example, a sinusoidal signal f=1 MHz has a peak voltage V. peak If the voltage is 5V, then the slew rate of the sine wave signal is 2π × 1MHz × 5V = 31.4V / μs.

[0064] like Figure 1 The diagram illustrates a signal strength variation. It describes the relationship between the actual crossing, the actual crossing, and the threshold value.

[0065] Figure 1In the diagram, the horizontal axis (Tc) represents time or a continuous variable. The vertical axis represents signal strength or other measured values. t1[n] is the actual crossover, indicating that at a certain time point, the signal strength changes from above the threshold to below the threshold. tcross[n] is the ideal position, indicating the moment when the signal strength crosses the threshold under ideal conditions. SR×t1: represents the relationship between signal recovery time and t1. The deviation between t1[n] and tcross[n] is called the time interval error (TIE). x1[n] represents the signal.

[0066] Peffective[n] represents the effective signal value, typically used to indicate the value of a signal after filtering or other processing. Symbol rate (SR) represents the number of symbols transmitted per second (unit: Symbol / s). For example, SR=11 means 11 symbols are transmitted per second.

[0067] P1[n] and P2[n]: Represent two different states or values ​​of the signal.

[0068] In some embodiments, to determine the jitter value of the signal, the jitter value introduced by the noise of the test equipment can be obtained first. This noise-introduced jitter value can be the ratio of noise to slew rate. Then, a dual Dirac model is used to separate the deterministic jitter (DJ) and random jitter (RJ) of the signal, and the noise-introduced jitter value is subtracted from the RJ. Finally, a histogram is synthesized to calculate the n-th percentile unit interval jitter (Jnu) and root mean square jitter (Jrms) of the signal.

[0069] like Figure 2 As shown, a jitter testing method is provided, which includes:

[0070] S201. Generate K templates.

[0071] These K templates are used to match or transform the input signal for identification. These K templates are distinct. K is a positive integer.

[0072] S202, Identify the conversion between the input signal and the current template.

[0073] In one example, the testing device can compare the input signal with the k-th template to identify the transformation relationship or similarity between the signal and the template.

[0074] S203, Measuring slope rate.

[0075] Here, the slope rate (measure slew rate, SRk) refers to the slope rate of the current module k.

[0076] In one example, after identifying the transition, the test equipment can measure the slope of the transition, i.e. the rate of change of the signal, denoted as SRk.

[0077] S204, Observed values ​​of cumulative time interval error.

[0078] In one example, the test equipment can record and accumulate the error between the actual jump and the ideal jump for each time interval, known as the time interval error (TIE).

[0079] S205. Generate a histogram of TIE observations.

[0080] In one example, the testing equipment can statistically analyze the accumulated TIE observations to create a histogram, allowing for observation and analysis of the error distribution.

[0081] S206. Calculate the mean as a deterministic jitter indicator.

[0082] Here, the mean is the mean of the current module k, and this mean is used as the delay differencejitter (DDJk).

[0083] In this application, the mean of the histogram represents the deterministic jitter of the signal.

[0084] S207. Remove the mean and generate a zero-mean histogram.

[0085] In this application, the mean can be removed from the original histogram to obtain a zero-centered histogram. This histogram can be used for further analysis of the random jitter of the signal.

[0086] S208. Determine the Gaussian and non-Gaussian portions of the zero-mean histogram.

[0087] In this diagram, the Gaussian part of the zero-mean histogram is used to represent the random jitter of the signal, while the non-Gaussian part is used to represent the interference or noise in the signal.

[0088] S209. Generate rising edge jitter and falling edge jitter values ​​for the histogram.

[0089] S210. Jitter introduced by the noise of the measuring instrument.

[0090] This includes assessing the impact of noise introduced by the measuring instrument itself on jitter measurement, so that subsequent corrections can be made.

[0091] S211. Remove instrument jitter to generate compensating jitter.

[0092] S212. The bi-Dirac probability is synthesized by compensating for jitter and the mean.

[0093] based on Figure 2 The technical solution can analyze the jitter characteristics of the input signal and generate compensated jitter data to evaluate and optimize the signal quality.

[0094] but Figure 2 The technical solution directly calculates the jitter value of the signal by dividing the noise of the device by the slew rate of the signal, without considering the influence of linear interpolation. This will cause the jitter value of the signal to be too high, resulting in the calculated jitter value being higher than the actual jitter value of the signal.

[0095] In some scenarios, communication protocols such as IEEE 802.3bs / cd / ck and OIF-CEI 56G / 112G require jitter measurement of PAM4 signals, but the above-mentioned test methods and instruments have low accuracy and cannot meet the requirements.

[0096] In view of this, embodiments of this application provide a jitter testing method. This method corrects the jitter value of the signal under test by using a test device to eliminate the influence of the background noise of the test device on the jitter of the signal, thereby ensuring that the jitter value of the signal can be accurately tested.

[0097] In one example, such as Figure 3 The diagram shown is a schematic of a testing device provided in an embodiment of this application. The testing device may include a jitter calibration and subtraction module and a jitter extrapolation module.

[0098] The jitter calibration and subtraction module can be used to calibrate the impact of device noise floor on signal jitter and subtract this impact. The jitter extrapolation module can be used to calculate the jitter value of the signal with arbitrary probability.

[0099] For example, such as Figure 4 As shown, the device under test (DUT) can input the generated test signal into the test equipment. The test equipment displays the test signal carrying the noise signal through the analog front end, performs jitter calculation on the test signal through the jitter calibration and subtraction module, and calculates the Jnu of the test signal through the jitter extrapolation module.

[0100] In other examples, to configure the noise floor of the test equipment, the test equipment provided in this application embodiment can also be equipped with a noise floor configuration interface. For example... Figure 5As shown, this is a device noise floor configuration interface provided in an embodiment of this application. The device noise floor configuration interface may include a noise floor configuration window, and each noise floor configuration window is configured with noise floor adjustment controls (such as…). Figure 5 (The "+" and "-" symbols). This underlying configuration window can respond to adjustment operations and configure the noise floor of the test equipment.

[0101] The adjustment operation refers to touching / pressing the noise adjustment controls. For example, when the "+" button is touched, the noise level of the corresponding window increases, and the increase is proportional to the number of times the control is triggered. Conversely, when the "-" button is triggered, the noise level of the corresponding window decreases, and the decrease is proportional to the number of times the control is triggered. For instance, touching "+" once increases the displayed value by a first value, and touching "-" once decreases the displayed value by a first value. The first value can be 0.1, 1, etc. Taking a first value of 1 as an example, touching "+" twice increases the displayed value by 2, and touching "-" twice decreases the displayed value by 2; touching "+" N times increases the displayed value by N, and touching "-" N times decreases the displayed value by N. N is a positive integer.

[0102] Furthermore, Figure 5 The device noise floor configuration interface can also be configured with control controls. When these control controls are triggered, the test device can test the jitter value of the input signal.

[0103] In some possible implementations, the number of display boxes can be multiple ( Figure 5 Four different display boxes are shown (each illustrated in the image), each capable of displaying a different noise floor value. For example, the scope level is 0RNrms, scope level 1RNrms, scope level 2RNrms, and scope level 3RNrms. Here, RNrms represents the root mean square noise (RMS) value of the signal.

[0104] In this embodiment, different reference levels correspond to different voltage levels, and different voltage levels correspond to different noise floor values. Therefore, the user can configure different noise floor values ​​for each reference level. Of course, for ease of configuration, different voltage levels can be set to the same noise floor value. Figure 5 The device noise floor configuration interface shown allows users to set the noise floor value of the test device as needed, which is simple and convenient.

[0105] In some other examples, to facilitate user viewing of the jitter value of the input signal, the test equipment provided in this application is also equipped with a jitter display interface. This jitter display interface can display the jitter value of the input signal.

[0106] In some possible implementations, the jitter display interface can have multiple display windows, each used to display jitter values ​​corresponding to different probabilities. For example, it could include jitter values ​​corresponding to J3u, J4u, and J5u.

[0107] In one application scenario, the testing equipment can respond to a jitter test operation by displaying a jitter display interface. Combined with... Figure 5 The test equipment can respond to the control switch from the off state to the on state and display a jitter display interface.

[0108] In one possible implementation, the display interface may also include a noise removal control. In response to the noise removal control being closed, the test device displays a coarse estimate of the jitter of the input signal. In response to the noise removal interface being opened, the test device can display the actual jitter value of the input signal, which is the jitter value obtained by subtracting the jitter value introduced by the device noise from the coarse jitter estimate of the signal. This actual jitter value is consistent with or close to the actual jitter value of the signal (e.g., the difference between the two is less than a preset value).

[0109] For example, the changes in the jitter value displayed by the test device before and after the control is turned on can be shown in Table 1.

[0110] Table 1

[0111]

[0112] The data in Table 1 is merely illustrative and may include other data without limitation.

[0113] As shown in Table 1, compared to the jitter value before the noise removal control is enabled, the jitter value of the signal is significantly reduced after the noise removal control is enabled. That is, the test device provided in this application embodiment can display the jitter value after deducting the jitter value introduced by the device noise, so that the displayed jitter value of the signal is closer to the actual jitter value of the signal.

[0114] In some scenarios, to verify whether the jitter value of the signal tested by the testing equipment is consistent with or close to the actual jitter value of the signal, in this embodiment of the application, a test signal with determined jitter and noise values ​​can be input into the testing equipment to verify whether the jitter value input by the testing equipment is consistent with or close to the jitter value of the test signal. If they are consistent or close, it indicates that the testing equipment meets the requirements of the aforementioned communication protocol; if they are inconsistent or differ significantly, it indicates that the accuracy of the testing equipment is insufficient, and the parameters of the testing equipment need to be adjusted. Specifically, please refer to the description of the following embodiments, which will not be repeated here.

[0115] In some embodiments, this application provides a jitter testing method, such as... Figure 6 As shown, the method may include S601 to S603:

[0116] S601. Based on the noise floor of the test equipment and the slew rate of the signal under test, determine the equipment jitter value of the test equipment for the signal under test.

[0117] In this context, "test equipment" refers to devices capable of measuring the jitter value of a signal, such as an oscilloscope. The noise floor of the test equipment can be due to the noise generated by the equipment itself when there is no external signal input. This noise can affect measurement accuracy and signal integrity.

[0118] The noise floor value of the test equipment is related to the voltage level of the test equipment. The noise floor value corresponding to different voltage levels can be measured, and this correspondence can be saved and presented to the user through the configuration interface. This makes it convenient for the user to set the required noise floor value through the configuration interface. Specifically, the test equipment can be set with multiple voltage levels, and the test voltage generated by the test equipment is different under different voltage levels.

[0119] In combination with the above Figure 4 The device under test (DUT) generates different signals under different voltages. Therefore, to more accurately obtain the jitter value of the signal under test, given the generation voltage of the signal under test, the voltage range of the test equipment can be adjusted to match that voltage. For example, if the DUT generates the signal under test at 100mV, the test equipment can be tuned to the voltage range corresponding to 100mV. This ensures that the test voltage of the test equipment matches the generation voltage of the signal under test, guaranteeing that the signal testing environment of the test equipment is consistent with the generation environment of the signal under test, and also allows for a more accurate calculation of the jitter value of the signal under test.

[0120] The noise floor of the test equipment varies at different voltage levels. Therefore, to accurately determine the noise floor of the test equipment at the generation voltage corresponding to the signal under test, the test equipment can be turned on with its signal input port disconnected and terminated. Port termination refers to adding impedance matching (such as connecting a matching resistor) at the signal input terminal of the test equipment to prevent signal reflection. At this time, the test equipment is in an unloaded state. In this situation, in response to the noise test operation, the test equipment performs a noise test. Since the input terminal is disconnected, the noise measured by the test equipment is the noise generated by the test equipment itself when there is no signal input. Simultaneously, the voltage of the test equipment is the generation voltage corresponding to the signal under test. Therefore, the test equipment can measure the noise floor value at the generation voltage corresponding to the signal under test. After obtaining multiple noise floors of the test equipment at multiple generation voltages corresponding to the signal under test, this correspondence can be recorded and referenced, for example... Figure 5 The configuration interface is presented to the user for selection.

[0121] like Figure 5 As shown, different reference levels correspond to different noise floor values. Different reference levels can correspond to different voltages. The test equipment can select the noise floor value corresponding to the generated voltage of the signal under test according to the configuration. For example, if the generated voltage of the signal under test is equal to or close to the level of reference level 0, the test equipment can use the noise floor value set at integration level 0 as the noise floor value of the test equipment.

[0122] Furthermore, in Figure 5 When the noise floor values ​​of the four baseline levels are the same, for example, Figure 5 If the noise floor values ​​configured for the four baseline levels are user-defined, and these four baseline levels have the same noise floor value, then the test equipment can directly use the configured noise floor value as its own noise floor value. If Figure 5 If the noise floor values ​​of the four reference levels are different, the test equipment can use the noise floor value of the reference level whose voltage is the same as or close to the voltage of the signal under test as the noise floor value of the test equipment.

[0123] The signal to be measured can be a PAM signal, such as PAM4, PAM6, or PAM8. Of course, other higher-order modulation formats are also acceptable; there are no restrictions. The slew rate of the signal to be measured can be determined based on its waveform data. For details, please refer to the descriptions above; they will not be repeated here.

[0124] In this embodiment, the device jitter value of the signal under test can also be called the coarse jitter estimate or the influence jitter value. This device jitter value is the jitter value calculated by the test equipment and the signal-to-signal jitter value affected by the noise of the device itself.

[0125] In one possible implementation, the test equipment measures the device jitter value (RJ) of the signal under test. scope ) can be the noise floor value (σ) of the test equipment. noise RJ is the ratio of the slew rate of the signal being measured to the slew rate of the signal being measured. In other words, RJ... scope =σ nois / Slewrate.

[0126] S602. Based on the device jitter value, correct the random jitter value of the signal under test to obtain the corrected random jitter value.

[0127] The corrected random jitter value is the random jitter value after deducting the influence of the test equipment.

[0128] In one possible implementation, the test equipment can correct the random jitter value of the signal under test based on the equipment jitter value and the correction coefficient corresponding to the signal under test, thereby obtaining the corrected random jitter value.

[0129] The correction coefficient corresponding to the signal under test can be determined based on the waveform data of the signal under test. See below for details. Figure 8 Examples of which are not described in detail here.

[0130] In one example, the corrected random jitter value satisfies Formula 1:

[0131] (Formula 1).

[0132] in, This represents the corrected random jitter value. This represents the random jitter value of the signal under test. This represents the correction factor. This indicates the device jitter value.

[0133] S603. Based on the corrected random jitter value and the deterministic jitter value of the signal under test, determine the actual jitter value of the signal under test.

[0134] Among them, the actual jitter value of the signal under test is less than the jitter value of the device.

[0135] In one possible implementation, the test equipment can reconstruct the jitter histogram of the signal under test based on the deterministic jitter value and the corrected random jitter value, and calculate the actual jitter value of the signal under test based on the reconstructed jitter histogram.

[0136] The jitter histogram can be used to display the distribution characteristics of signal timing jitter. A jitter histogram is a statistical graph with TIE (Time Interval Estimation) on the horizontal axis and the frequency of different jitter values ​​on the vertical axis.

[0137] In this embodiment of the application, the testing device performs convolution operation on the deterministic jitter value and random jitter value of the signal under test to obtain the jitter histogram of the signal under test. For details, please refer to the prior art, which will not be elaborated here.

[0138] Furthermore, the testing equipment can also calculate the jitter value at any probability based on the jitter histogram of the signal under test.

[0139] In one example, jitter values ​​at arbitrary probabilities Satisfying Formula 2:

[0140] (Formula 2).

[0141] Where CDF(x) is the cumulative distribution function of the jitter histogram. The range of x is [-0.5, 0.5]UI. This represents the x-value corresponding to a specific cumulative distribution y. n represents the probability. For example, n=3. This represents the jitter value at 3‰.

[0142] based on Figure 6 The proposed technical solution, after determining the equipment jitter value of the test equipment based on the noise floor of the test equipment and the slew rate of the signal under test, can correct the random jitter value of the signal under test based on this equipment jitter value, thus obtaining a corrected random jitter value. Since the random jitter value of the signal is highly affected by the noise floor of the test equipment, this principle-based correction of the random jitter value of the signal under test using the equipment jitter value reduces the impact of the noise floor of the test equipment on the jitter value, resulting in a more accurate random jitter value for the signal under test. Therefore, based on this corrected random jitter value and the deterministic jitter value of the signal under test, the actual jitter value of the signal under test can be accurately measured.

[0143] Typically, abrupt changes in a signal can cause abnormal points in the waveform, resulting in abrupt transitions. To eliminate the impact of these transitions, the waveform data at the transition points can be recalculated using linear interpolation. However, the waveform data of multiple consecutive points in a signal may not conform to a linear change. For example, it may be a curve. Therefore, the waveform data at the transition points calculated using linear interpolation will contain errors.

[0144] Therefore, in order to accurately determine the correction coefficients corresponding to the signal under test, such as Figure 7 As shown, the method provided in this application embodiment may further include S701 and S702:

[0145] S701. Based on the waveform data of the signal under test, determine multiple jitter points corresponding to jitter transitions in the waveform data.

[0146] The waveform data of the signal under test can include multiple points and the amplitude of each point. The multiple jitter points of the signal under test are points near the jitter transition positions in the waveform of the signal under test. For example... Figure 8 As shown, the waveform data of the signal under test abruptly changes from point B to point C within a short period of time, causing jitter and jumps in the signal under test. Therefore, jitter and jumps occur at points B and C. That is, points B and C are points near the locations where jitter and jumps occur in the waveform of the signal under test.

[0147] In one possible implementation, to avoid misidentifying normal waveform fluctuations of the signal under test as jitter transitions, the test equipment can determine the jitter points used to calculate the correction coefficient based on waveform change data from multiple jitter points where waveform fluctuations occur.

[0148] The waveform change data can be the ratio between the amplitude difference of multiple jitter points and the corresponding time difference. If the waveform change data is greater than a preset threshold, a jitter jump occurs between the multiple jitter points; if the waveform change data is less than or equal to the preset threshold, the multiple jitter points can be considered to have normal fluctuations.

[0149] In this embodiment of the application, when describing the comparison with a threshold, "equal to" can be combined with "greater than" or "less than". For example, the above description can be replaced with: if the waveform change data is greater than or equal to a preset threshold, then a jitter jump occurs between the multiple jitter points; if the waveform change data is less than the preset threshold, then the multiple jitter points can be considered to have normal fluctuations. Other similar descriptions can be referred to here and will not be repeated.

[0150] Another possible implementation is that the testing equipment can determine the jitter transition position in the waveform data based on a preset threshold value. For example, for two consecutive points in the waveform data of the signal under test, if the waveform data of one point is higher than the preset threshold value and the waveform data of the other point is lower than the preset threshold value, then these two points are points near the jitter transition position in the signal under test.

[0151] S702. Determine the correction coefficient based on the waveform data of the multiple jitter points.

[0152] In one possible implementation, the waveform data of the jitter point may include the ideal amplitude corresponding to the jitter point and the noise value introduced by the jitter point. In one example, the correction coefficient for the noise value introduced by the jitter point can be calculated based on Formula 3.

[0153] (Formula 3).

[0154] in, This represents the correction factor. , This represents the ideal amplitude at two points near the jitter transition position. , This represents the noise value introduced at each of the two points. In actual measurements, the ideal signal amplitude... and It is not possible to obtain a signal at high speeds, where the signal slew rate is typically large. In this case, the signal amplitude is usually much larger than the noise amplitude. Therefore, we can assume... , .

[0155] Furthermore, Formula 3 above can be replaced with Formula 4:

[0156] (Formula 4).

[0157] in, , This represents the actual amplitude of two points near the jitter jump position. , .

[0158] based on Figure 7 Compared to using linear interpolation, the technical solution in this application calculates the amplitude of the jitter jump point by using the amplitude of two points at the jitter jump position, instead of simple linear interpolation, resulting in a more accurate calculation.

[0159] In some embodiments, in order to accurately determine the deterministic jitter value and random jitter value of the signal under test, such as Figure 9 As shown, the methods for determining the deterministic jitter value and the random jitter value of the signal under test may include S901 and S902.

[0160] S901. Determine the normalized jitter histogram of the signal to be tested.

[0161] The normalized jitter histogram of the signal under test uses TIE as the data source to show the time deviation distribution between the actual edge position and the ideal edge position of the signal. The horizontal axis of the normalized jitter histogram is the normalized time deviation, and the vertical axis is the probability density.

[0162] One possible implementation is that the device under test (DUT) plots a normalized jitter histogram of the signal under test based on the time deviation between the ideal edge position and the actual edge position of the signal under test.

[0163] The ideal edge position of the signal under test can be determined by clock recovery technology or by the communication protocol. Clock recovery technology can be found in existing techniques and will not be elaborated here. The actual edge position of the signal under test can be obtained by measuring the signal under test using testing equipment.

[0164] S902. Perform jitter separation on the normalized jitter histogram to obtain the deterministic jitter value and random jitter value of the signal under test.

[0165] Jitter separation is used to determine the deterministic and random jitter values ​​of a signal based on the distribution of a normalized jitter histogram. For example, jitter separation methods can include tail fitting, bimodal fitting, and spectral analysis. These three methods are briefly explained below.

[0166] 1-1 Tail Fitting Method.

[0167] Among them, the tail fitting method is suitable for scenarios where the DJ's histogram tail deviates from the Gaussian distribution.

[0168] In one example, the testing device can perform Gaussian fitting on data that deviates from a Gaussian distribution to obtain the RJ of the signal under test, and perform Gaussian fitting on other data that does not deviate from a Gaussian distribution to obtain the DJ of the signal under test.

[0169] 1-2 Bimodal Fitting Method.

[0170] The bimodal fitting method is suitable for scenarios where the normalized jitter histogram exhibits a bimodal distribution. The peak spacing between the two peaks represents the deterministic jitter value of the signal under test. The testing equipment can fit a Gaussian distribution to each peak individually and calculate the combined standard deviation. σ RJ This allows us to obtain the random jitter value of the signal under test.

[0171] For example, the signal to be measured . , This represents the bimodal standard deviation.

[0172] 1-3 Spectrum Analysis Method.

[0173] Among them, the spectrum analysis method is suitable for DJ scenarios that include periodic components.

[0174] In one example, the test equipment can perform a Fast Fourier Transform on the TIE data of the normalized histogram jitter map to identify peaks in the spectrum (i.e., periodic jitter components). After filtering out the periodic components, the test equipment can calculate the standard deviation of the remaining data to obtain the RJ of the signal under test. The peak-to-peak value in the time domain of the periodic components is the DJ of the signal under test.

[0175] based on Figure 9 The technical solution allows the testing equipment to perform jitter separation on the normalized histogram of the signal under test after determining the normalized histogram jitter pattern, thereby quickly and accurately determining the deterministic jitter value and random jitter value of the signal under test.

[0176] In another embodiment, such as Figure 10 The illustration shows a jitter testing method provided in this application embodiment, used to determine the jitter value of Jnu in a signal under test. This method is applied to a testing device and includes:

[0177] S101. Rough estimate of device jitter for measuring the signal under test.

[0178] This step can be referred to as S601 above.

[0179] S102. Calculate the correction coefficient of the signal to be measured.

[0180] This step can be referred to as S701 and S702 above.

[0181] S103, Equipment vibration deduction.

[0182] This step can be referred to as S602 above.

[0183] S104, TIE measurement.

[0184] This step can be referred to as S901 above.

[0185] S105, jitter separation.

[0186] This step can be referred to as S902 above.

[0187] S106, Jitter Histogram Reconstruction and Jitter Calculation.

[0188] This step can be referred to as S603 above.

[0189] based on Figure 10 This technical solution can determine the impact of device noise floor on signal jitter and subtract related effects, thus enabling accurate measurement of signal jitter values. Furthermore, it can calculate jitter values ​​with arbitrary probabilities for small sample signals, improving testing efficiency.

[0190] The various solutions in the above embodiments of this application can be combined without contradiction.

[0191] This application embodiment can divide the signal jitter device into functional modules or functional units according to the above method example. For example, each function can be divided into a separate functional module or functional unit, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or in software functional modules or functional units. The module or unit division in this application embodiment is illustrative and only represents one logical functional division; other division methods may be used in actual implementation.

[0192] When dividing each function into modules according to its corresponding function. Figure 11 A schematic diagram of a jitter testing device 110 is shown. The jitter testing device 110 can be the aforementioned measuring device, or it can be a device (such as a chip, chip system, etc.) applied in the measuring device. The jitter testing device 110 can be used to perform the functions of the jitter testing device involved in the above embodiments. Figure 11 The jitter testing device 110 shown may include: a determination module 111 and a correction module 112.

[0193] The determination module 111 is used to determine the device jitter value of the test equipment for the signal under test based on the noise floor value of the test equipment and the height of the signal under test.

[0194] The correction module 112 is used to correct the random jitter value of the signal under test based on the jitter value of the device, so as to obtain the corrected random jitter value.

[0195] The determination module 111 is also used to determine the actual jitter value of the signal under test based on the corrected random jitter value and the deterministic jitter value of the signal under test.

[0196] The specific implementation of the jitter testing device can refer to the behavior and function of the jitter testing device in the control method provided by the first aspect or any possible design of the first aspect, and will not be repeated here. Therefore, the provided jitter testing device can achieve the same beneficial effects as the first aspect or any possible design of the first aspect.

[0197] In some embodiments, the correction module 112 is specifically used to correct the random jitter value of the signal under test based on the device jitter value and the correction coefficient corresponding to the signal under test, so as to obtain the corrected random jitter value.

[0198] In some embodiments, the corrected random jitter value satisfies a first formula, which is: .in, This represents the corrected random jitter value. This represents the random jitter value of the signal under test. This represents the correction factor. This indicates the device jitter value.

[0199] In some embodiments, the correction coefficient is determined as follows: based on the waveform data of the signal under test, multiple jitter points in the waveform data are determined, and based on the waveform data of the multiple jitter points, the correction coefficient is determined.

[0200] In some embodiments, the correction coefficient satisfies the second formula, which is:

[0201] .

[0202] in, This represents the correction factor. , This represents the ideal amplitude at two points near the jitter transition position. , This represents the noise value introduced at each of the two points.

[0203] In some embodiments, random jitter values ​​and deterministic jitter values ​​are determined by: determining a normalized jitter histogram of the signal under test, and performing jitter separation on the normalized jitter histogram to obtain random jitter values ​​and deterministic jitter values ​​of the signal under test.

[0204] In some embodiments, the determining module 111 is specifically used to: draw a normalized jitter histogram of the signal under test based on the time deviation between the ideal edge position and the actual edge position of the signal under test.

[0205] In some embodiments, the determining module 111 is specifically used to: determine the ratio of the noise floor value of the test device to the slew rate of the signal under test as the device jitter value of the test device.

[0206] In some embodiments, the actual jitter value of the signal under test is less than the device jitter value.

[0207] In some embodiments, the signal under test is a four-level pulse-amplitude modulation (PAM) signal.

[0208] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0209] Each of the above modules or units can be implemented through software, hardware, or a combination of both. For example, the determination module and the correction module can both be implemented based on software.

[0210] In this application, "implemented through software" means that the processor reads and executes program instructions stored in memory to implement the functions corresponding to the aforementioned modules or units. Here, the processor refers to a processing circuit capable of executing program instructions, including but not limited to at least one of the following: a central processing unit (CPU), a microprocessor, a digital signal processor (DSP), a microcontroller unit (MCU), or an artificial intelligence processor, etc., and other processing circuits capable of running program instructions. In other embodiments, the processor may also include circuits with other processing functions (such as hardware circuits for hardware acceleration, bus and interface circuits, etc.). The processor can be presented as an integrated chip, for example, as an integrated chip whose processing function only includes executing software instructions, or it can also be presented as a SoC (system on a chip), that is, on a single chip, in addition to the processing circuit capable of running program instructions (usually referred to as the "core"), it also includes other hardware circuits for implementing specific functions (of course, these hardware circuits can also be implemented separately based on ASIC or FPGA). Correspondingly, the processing functions, in addition to executing software instructions, may also include various hardware acceleration functions (such as AI calculation, encoding / decoding, compression / decompression, etc.).

[0211] In this application, "implemented in hardware" means that the functions of the above-mentioned modules or units are implemented through hardware processing circuits that do not have program instruction processing capabilities. These hardware processing circuits can be composed of discrete hardware components or integrated circuits. To reduce power consumption and size, integrated circuits are typically used. Hardware processing circuits can include ASICs (application-specific integrated circuits) or PLDs (programmable logic devices); PLDs can include FPGAs (field-programmable gate arrays), CPLDs (complex programmable logic devices), and so on. These hardware processing circuits can be a single packaged semiconductor chip (e.g., packaged as an ASIC); or they can be integrated with other circuits (e.g., CPUs, DSPs) and packaged into a single semiconductor chip. For example, multiple hardware circuits and a CPU can be formed on a silicon substrate and packaged into a single chip; this type of chip is also called a SoC. Alternatively, circuits for implementing FPGA functions and a CPU can be formed on a silicon substrate and encapsulated into a single chip; this type of chip is also called a SoPC (system on a programmable chip).

[0212] It should be noted that when this application is implemented through software, hardware, or a combination of both, different software or hardware can be used, and it is not limited to using only one type of software or hardware. For example, one module or unit can be implemented using a CPU, while another module or unit can be implemented using a DSP. Similarly, when implemented using hardware, one module or unit can be implemented using an ASIC, while another module or unit can be implemented using an FPGA. Of course, it is not limited to using the same software (e.g., all through a CPU) or the same hardware (e.g., all through an ASIC) to implement some or all modules or units. Furthermore, those skilled in the art will understand that software is generally more flexible but less performant than hardware, while hardware is the opposite. Therefore, those skilled in the art can choose software, hardware, or a combination of both based on actual needs.

[0213] The foregoing preferred embodiments have further illustrated the objectives, technical solutions, and advantages of the present invention. It should be understood that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A dithering test method, characterized by, The method comprises: determining a device jitter value of the test device affecting the to-be-tested signal based on a floor noise value of the test device and a slew rate of the to-be-tested signal; the floor noise value of the test device is selected according to a configuration of the test device; the configuration of the test device comprises that a configuration interface of the test device is provided with a plurality of reference levels, different reference levels correspond to different floor noise values, and different reference levels correspond to different voltages; the floor noise value of the test device is a floor noise value of the test device under a generation voltage corresponding to the to-be-tested signal; correcting a random jitter value of the to-be-tested signal based on the device jitter value and a correction coefficient corresponding to the to-be-tested signal, to obtain a corrected random jitter value; the correction coefficient is determined based on waveform data of a jitter point corresponding to a jitter jump in the to-be-tested signal; determining an actual jitter value of the to-be-tested signal based on the corrected random jitter value and a deterministic jitter value of the to-be-tested signal.

2. The method of claim 1, wherein, The corrected random jitter value satisfies a first formula, and the first formula is: ； wherein, represents the modified random jitter value, represents the random jitter value of the signal under test, represents the modification coefficient, represents the equipment jitter value.

3. The method according to claim 1 or 2, characterized in that, The correction coefficient is determined by the following method: determining a plurality of jitter points corresponding to a jitter jump in the waveform data of the to-be-tested signal according to the waveform data of the to-be-tested signal; determining the correction coefficient according to waveform data of the plurality of jitter points.

4. The method of claim 3, wherein, The plurality of jitter points comprise two jitter points adjacent to a jitter jump position in the waveform data, and the correction coefficient satisfies a second formula, and the second formula is: ； wherein denotes the correction factor, , denotes the ideal amplitude of the two dither points in the vicinity of the dither jump position, , denotes the noise value introduced by each of the two dither points.

5. The method according to claim 1 or 2, characterized in that, The deterministic jitter value and the random jitter value are determined by the following method: determining a normalized jitter histogram of the to-be-tested signal; performing jitter separation on the normalized jitter histogram to obtain the deterministic jitter value and the random jitter value.

6. The method of claim 5, wherein, The determination of the normalized jitter histogram of the to-be-tested signal comprises: drawing the normalized jitter histogram of the to-be-tested signal according to a time deviation between an ideal edge position and an actual edge position of the to-be-tested signal.

7. The method according to claim 1 or 2, characterized in that, The determination of the device jitter value of the test device affecting the to-be-tested signal based on the floor noise value of the test device and the slew rate of the to-be-tested signal comprises: determining the device jitter value as a ratio of the floor noise value of the test device to the slew rate of the to-be-tested signal.

8. The method of claim 1 or 2, wherein, The actual jitter value is smaller than the device jitter value.

9. The method of claim 1 or 2, wherein, The to-be-tested signal is a four-level pulse amplitude modulation (PAM) signal.

10. A dithering test apparatus characterized by, Comprise: a determination module configured to determine a device jitter value of a test device to a to-be-tested signal based on a floor noise value of the test device and a slew rate of the to-be-tested signal; the floor noise value of the test device is selected according to a configuration of the test device; the configuration of the test device comprises that a configuration interface of the test device is provided with a plurality of reference levels, different reference levels correspond to different floor noise values, and different reference levels correspond to different voltages; the floor noise value of the test device is a floor noise value of the test device under a generation voltage corresponding to the to-be-tested signal; a correction module configured to correct a random jitter value of the to-be-tested signal based on the device jitter value and a correction coefficient corresponding to the to-be-tested signal, to obtain a corrected random jitter value; The correction coefficient is determined based on waveform data of a jitter point corresponding to a jitter jump in the to-be-tested signal; The determination module is further configured to determine an actual jitter value of the to-be-tested signal based on the corrected random jitter value and a deterministic jitter value of the to-be-tested signal.

11. A dithering test apparatus characterized by, The jitter test device comprises a processor; the processor is configured to run computer programs or instructions, or is configured to pass through a logic circuit, so that the jitter test device performs the method according to any one of claims 1-9.

12. A test apparatus, characterized by The test equipment comprises the jitter test device according to claim 10.

13. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions or programs, when the computer instructions or programs are run on a computer, so that the jitter test device performs the method according to any one of claims 1-9.

14. A computer program product, characterised in that, When the computer program product is run on the test equipment, the test equipment performs the method according to any one of claims 1-9.

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