Low-delay high-throughput protocol stack for hundred-Gbps satellite-borne laser communication, implementation method and satellite-borne communication equipment

Abstract

The invention discloses a low-delay high-throughput protocol stack for hundred-Gbps satellite-borne laser communication and an implementation method. A protocol stack processing function is realized by adopting FPGA (Field Programmable Gate Array) hardware. The protocol stack architecture adopts a non-independent four-channel parallel data interface, and optimizes the data stream alignment problem in the data framing and de-framing processes through a three-stage alignment algorithm; and meanwhile, a self-adaptive frame interval control mechanism is adopted to further reduce data processing time delay, so that higher data frame throughput is obtained. According to the invention, efficient protocol processing is realized on the hardware level, and low time delay and high throughput of hundred Gbps high-speed data protocol processing can be realized.

Description

Technical Field

[0001] The present invention relates to the field of optical communication data processing, and in particular to a low-latency, high-throughput protocol stack based on 100 Gbps satellite-borne laser communication, an implementation method, and satellite-borne communication equipment. Background Art

[0002] High-speed, low-latency data transmission technology has become a core requirement for future communication networks. As a crucial component of global communications, space-based backbone networks must establish uninterrupted, ultra-high-speed data transmission links between backbone nodes and provide real-time user access services. Traditional intersatellite communication technologies, limited by bandwidth and latency, are unable to meet the future demands for 100-Gbps data transmission.

[0003] Currently, satellite-borne laser communication technology is considered an ideal option for high-speed intersatellite communications due to its advantages such as high bandwidth, low latency, and strong anti-interference capabilities. However, existing protocol stack designs are mostly software-based, making it difficult to efficiently process data streams at the 100-Gbps level at the hardware level. Significant performance bottlenecks exist in data framing, deframing, and flow control. Furthermore, traditional data alignment methods and frame interval control mechanisms cannot adapt to the dynamic changes in high-speed data streams, resulting in increased data processing latency and reduced throughput. Summary of the Invention

[0004] The purpose of the present invention is to solve the problems of high latency and low throughput in the above-mentioned existing satellite-borne laser communication protocol stack in the scenario of 100 Gbps high-speed data transmission, to meet the protocol processing requirements during 100 Gbps satellite-borne high-speed data transmission, and to propose a low-latency and high-throughput protocol stack, implementation method and satellite-borne communication equipment for 100 Gbps satellite-borne laser communication to reduce the data frame processing delay and increase the data frame processing throughput.

[0005] The object of the present invention is achieved through the following technical solutions:

[0006] The present invention proposes a method for implementing a low-latency and high-throughput protocol stack for 100 Gbps satellite-borne laser communications, comprising the following steps:

[0007] S1. Build a non-independent four-channel parallel data interface architecture;

[0008] S2. Implement three-level data alignment operations in the transmit path:

[0009] -First-level alignment: complete the splicing of the UDP message header and the IP address field in the IP sending module; -Second-level alignment: complete the splicing of the key fields of the IP message in the IP sending module; -Third-level alignment: The Ethernet frame header and IP data are spliced ​​together in the MAC module;

[0010] S3 uses an adaptive frame interval control mechanism to dynamically adjust the data frame reading interval;

[0011] S4 implements bidirectional conversion of AXIS-LBUS data formats;

[0012] S5 integrates an automatic request retransmission mechanism to ensure data transmission reliability.

[0013] The three-level data alignment operation specifically includes:

[0014] The first level alignment concatenates the 8-byte UDP header and the 2-byte IP address field into a 10-byte data block;

[0015] The second level alignment stitches the 16-byte key fields of the IP header into a complete data block;

[0016] The third level alignment splices the 14-byte Ethernet frame header and the IP data into a 16-byte aligned block.

[0017] The bidirectional conversion of the AXIS-LBUS data format includes: implementing flow control when converting the sending direction, adjusting the data sending rate according to the CMAC status signal; performing data continuity processing when converting the receiving direction, converting discontinuous LBUS data frames into AXIS data frames, and reducing the interval fluctuation of discontinuous data frames.

[0018] The present invention also provides a 100 Gbps satellite-borne laser communication protocol stack system, characterized by comprising:

[0019] Four-channel parallel data processing unit, each channel is equipped with a 128-bit wide AXIS interface;

[0020] The three-level data alignment processing module uses shift registers and parallel splicing circuits to achieve cacheless data alignment;

[0021] Adaptive frame interval controller, including FIFO depth monitoring unit and dynamic adjustment unit;

[0022] AXIS-LBUS bidirectional converter, which realizes interface adaptation between the protocol stack and the 100G CMAC module;

[0023] ARQ retransmission management module supports selective retransmission mechanism.

[0024] The overall architecture performs data framing and deframing according to the transmit and receive paths, where the channels use a non-independent four-channel data interface;

[0025] In the sending path, the data stream of the user data port and the data stream of the automatic retransmission request module (ARQ) are transmitted to the UDP sending module through the arbitration module 1;

[0026] The UDP sending module and the IP sending module complete the UDP / IP protocol encapsulation, and the MAC module completes the 14-byte header encapsulation of the Ethernet frame, including the source and destination MAC addresses and protocol type;

[0027] Complete the three-level data alignment operation in the IP sending module and MAC module;

[0028] The three-level alignment operation mainly completes the data alignment of the non-independent four-channel data interface through shifting and splicing operations, without the need for data cache, and can also optimize data processing latency;

[0029] The data flow of the ARP module and the data flow of the IP sending module are transmitted to the MAC module through the arbitration 2 module;

[0030] The data sent by the MAC module is output to the AXIS_LBUS conversion module, which converts the AXIS (AXI4-Stream) data type used by the protocol stack into the LBUS (Local BUS) data type that can be received by the 100G CMAC module (100G Ethernet IP core provided by Xilinx);

[0031] The 100G CMAC IP core completes the encapsulation of the complete Ethernet frame, including adding the preamble field and CRC checksum.

[0032] In the receiving path, the 100G CMAC module deframes the data frame, performs CRC check and removes the CRC tail, and transmits the correct data frame to the AXIS_LBUS conversion module;

[0033] The AXIS_LBUS conversion module receives the discontinuous LBUS format data frames from the 100G CMAC module, converts the discontinuous data frames into continuous data frames, and converts them into AXIS data types.

[0034] Discontinuous means that there is only one frame of data in one clock cycle, and one frame of data will not be interrupted;

[0035] When performing continuous processing, when subsequently reading out data frames, an adaptive frame interval control mechanism is used to read the data frames;

[0036] The MAC module, IP receiving module, ARP module and UDP receiving module perform data frame analysis;

[0037] The three-level data alignment operation is completed in the MAC module, IP receiving module, and UDP receiving module respectively;

[0038] The data output by the UDP receiving module is directly transmitted to the user receiving module and the ARQ module.

[0039] The present invention also provides a satellite communication device, which is characterized in that it integrates the above-mentioned protocol stack system and supports: data transmission rate ≥ 100Gbps; end-to-end delay ≤ 1μs; data frame throughput ≥ 80Mpps and bit error rate ≤ 10 -12 .

[0040] The present invention adopts the above technical means and has the following technical effects:

[0041] The design of the present invention achieves lower data processing delay and higher data frame throughput, providing an efficient processing solution and implementation method for future satellite-borne 100Gbps laser communication data processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Other features, objects and advantages of the present invention will become more apparent upon reading the detailed description of non-limiting embodiments with reference to the following drawings:

[0043] Figure 1 Schematic diagram of a low-latency, high-throughput protocol stack based on 100-Gbps satellite-borne laser communications;

[0044] Figure 2 This is a schematic diagram of the three-level alignment operation of the sending channel;

[0045] Figure 3 This is a schematic diagram of converting AXIS data format to LBUS data format;

[0046] Figure 4 This is a schematic diagram of converting LBUS data format to AXIS data format;

[0047] Figure 5 It is a schematic diagram of the adaptive frame interval control mechanism; Specific implementation methods

[0048] The technical solution of the present invention is further described in detail below with reference to the accompanying drawings.

[0049] The overall structure of the present invention is layered according to the UDP / IP protocol stack, with protocol processing divided into a sending path and a receiving path. Both the sending channel and the receiving channel undergo three-level alignment operations. The user side of the protocol stack includes the user port and ARQ module. The protocols at the same layer as the IP protocol also include the ARP protocol. The MAC module only contains a 14-byte protocol encapsulation, including the destination address, source address, and protocol type. The complete Ethernet frame still needs to be completed through the 100G CMAC, including the addition of the frame check and preamble signal fields. The two exchange data through the AXIS_LBUS bidirectional conversion module.

[0050] The user side of the protocol stack also includes an automatic retransmission request module.

[0051] Its functions are described as follows:

[0052] When the protocol stack acts as the sender, the ARQ module sends control information of the data frame, including the start sequence number, end sequence number, and total number of frames.

[0053] When acting as a receiver, when a data frame is received, it is necessary to compare the received control information with the actually received valid data frame, and at the same time, it is necessary to store the sequence number of the data frame that was not received.

[0054] The protocol stack status module generates a confirmation frame valid signal, indicating that the data frame is received correctly.

[0055] A negative frame valid signal is also generated, indicating that the data frame was received with errors;

[0056] The ARQ module receives a valid frame confirmation signal or a negative frame confirmation signal according to the received protocol stack status, and generates a corresponding confirmation frame and negative frame.

[0057] The protocol stack also includes an address resolution protocol module (ARP);

[0058] Its functions are described as follows:

[0059] The ARP module can complete ARP request and ARP reply functions. When you need to find the MAC address corresponding to an IP address, you can query it through the ARP table. If the query fails, you can make an ARP request. When you receive an external ARP request, you can send an ARP reply to the outside world.

[0060] The following is combined with Figure 2 The three-level alignment operation of the present invention is further described in detail.

[0061] In the figure, AXIS0, AXIS1, AXIS2, and AXIS3 represent four non-independent data interfaces, each 128 bits wide. The transmit channel begins with first- and second-level alignment in the IP transmit module, followed by shift splicing. Third-level alignment is completed in the MAC module. During the shift splicing process, the data streams of each channel are transmitted independently.

[0062] The first level alignment process is as follows:

[0063] The IP sending module receives the UDP message header from the UDP sending module, which is 8 bytes in total.

[0064] The lower 2 bytes of the UDP packet header and the destination IP address of the IP packet header are concatenated into 10 bytes;

[0065] The spliced ​​10-byte data is spliced ​​with the upper 6-byte data of the AXIS0 channel, and then the upper 6-byte data of the AXIS1, AXIS2 and AXIS3 channels are spliced ​​with the lower 10 bytes of the AXIS0, AXIS1 and AXIS2 channels respectively, and finally the lower 10-byte data of the AXIS3 channel is stored;

[0066] The aligned data is transmitted via four AXIS channels.

[0067] The second-level alignment process is as follows:

[0068] The 16-byte data in the IP packet header (from the total length field to the high 2 bytes of the destination address) are spliced ​​into a 16-byte data block and transmitted through the AXIS0 channel;

[0069] Its AXIS1, AXIS2 and AXIS3 channels send the data in the AXIS0, AXIS1 and AXIS2 channels in sequence;

[0070] After completing the second-level alignment in the IP send module, the upper 2 bytes of the IP header (version number, header length, and service type field) are transmitted to the MAC module through an additional data channel.

[0071] The third-level alignment process is as follows:

[0072] The MAC module first concatenates the 14-byte Ethernet frame header (source MAC address, destination MAC address, and protocol field) and the 2-byte data output by the IP send module to form a 16-byte data block.

[0073] Finally, the third level alignment is performed in a similar manner to the second level alignment.

[0074] The protocol stack also includes the AXIS_LBUS conversion module;

[0075] It includes a conversion module from AXIS data format to LBUS data format and a conversion module from LBUS data format to AXIS data format.

[0076] The following is combined with Figure 3 The conversion of AXIS data format to LBUS data format is further explained in detail.

[0077] First, the input AXIS data stream first passes through the input register, is temporarily stored and then enters the FIFO;

[0078] The FIFO retains the complete frame information (start signal, end signal and data valid signal);

[0079] At the same time, the control signal of the CMAC module is stored in the input register at the first level;

[0080] The control signal includes LBUS transmit enable signal, transmit overflow signal and transmit underflow signal;

[0081] According to the control signal of CMAC, the sending flow can be controlled to avoid data frame errors;

[0082] The control signal drives the state machine to determine whether the module continues to process the data packet or pauses sending;

[0083] Subsequently, the control module generates a sending valid or sending pause signal according to the state machine output signal;

[0084] The final output register outputs a data stream that conforms to the appropriate LBUS data.

[0085] The following is combined with Figure 4 The conversion of LBUS data format to AXIS data format is further explained in detail.

[0086] The input non-continuous LBUS data stream is first converted into an AXIS data stream through the input register;

[0087] The data output of the input register is stored in the FIFO;

[0088] The frame status of the FIFO output is output to the control module;

[0089] The ready signal output by the control module is transmitted to the state machine, thereby controlling the data frame to the data continuity module, and finally the output data module outputs a continuous AXIS data stream;

[0090] The data stream after continuous processing can be more efficient when the subsequent protocol stack deframes, without the need for FIFO buffer;

[0091] The following is combined with Figure 5 The adaptive frame interval control mechanism is further explained in detail.

[0092] When the data stream transmits non-fixed-length frames, the frame interval at which the protocol stack reads data will change, adaptively changing the frame reading interval;

[0093] The module counts data frames. Since data frames can appear in the same clock cycle, the frame length may be estimated inaccurately. Therefore, it is necessary to adjust the interval according to the status of data frame storage in FIFO.

[0094] The specific operation process is:

[0095] The reading control module receives the control signal and the frame length counting signal, and outputs the frame length signal and the frame reading counter to the monitoring module;

[0096] At the same time, it outputs the ready signal to the frame interval setting module and outputs the FIFO status to the frame counting module;

[0097] The frame interval setting module receives the preparation signal, performs initial frame interval setting, and provides frame length information to the monitoring module and the reading control module.

[0098] The monitoring module records the number of cached frames in the FIFO queue in real time and tracks its dynamic changes, and determines whether the frame interval needs to be adjusted based on the threshold;

[0099] The process of judging by threshold is as follows:

[0100] When the amount of FIFO data continues to rise and reaches the set threshold, the interval adjuster is triggered to reduce the frame interval to relieve queue pressure;

[0101] The threshold value set by the module is 4. When the frame data cached in the FIFO reaches the threshold, the frame interval is adjusted by 1.

[0102] When the frame reading counter counts multiple times to meet the frame reading condition, the interval adjuster is triggered to increase the frame interval to optimize the queue utilization;

[0103] When the frame read counter reaches 2 times, the frame interval is adjusted by adding 1.

[0104] The number of frames in the FIFO changes dynamically and needs to be accurately counted. This is done by the frame counting module and output to the monitoring module and the frame interval adjustment module.

[0105] At the same time, it is determined whether to keep the frame interval unchanged according to the frame length and the adaptive frame interval;

[0106] The interval adjustment module determines the increase or decrease direction of the frame interval according to the input signal and outputs the optimized frame interval parameters.

Claims

1. A method for implementing a low-latency, high-throughput protocol stack for 100 Gbps satellite-borne laser communications, characterized in that: The following steps are involved: S1. Build a non-independent four-channel parallel data interface architecture; S2. Implement three-level data alignment operations in the transmit path: -First level alignment: The UDP packet header and IP address fields are concatenated in the IP sending module; -Second level alignment: complete the splicing of key fields of IP packets in the IP sending module; -Third-level alignment: The Ethernet frame header and IP data are spliced ​​together in the MAC module; S3 uses an adaptive frame interval control mechanism to dynamically adjust the data frame reading interval; S4 implements bidirectional conversion of AXIS-LBUS data formats; S5 integrates an automatic request retransmission mechanism to ensure data transmission reliability.

2. The method for implementing a low-latency, high-throughput protocol stack for 100 Gbps satellite-borne laser communications according to claim 1, wherein: The three-level data alignment operation specifically includes: The first level alignment concatenates the 8-byte UDP header and the 2-byte IP address field into a 10-byte data block; The second level alignment stitches the 16-byte key fields of the IP header into a complete data block; The third level alignment splices the 14-byte Ethernet frame header and the IP data into a 16-byte aligned block.

3. The method for implementing a low-latency, high-throughput protocol stack for 100 Gbps satellite-borne laser communications according to claim 1, wherein: The implementation process of the adaptive frame interval control mechanism includes: S3.1 monitors the FIFO queue depth in real time; S3.2 reducing the frame interval when the number of cached frames reaches a first threshold; S3.3 increasing the frame interval when the frame reading count reaches a second threshold; S3.4 Establish a feedback adjustment mechanism to dynamically optimize the frame interval parameters.

4. The method for implementing a low-latency, high-throughput protocol stack for 100 Gbps satellite-borne laser communications according to claim 1, wherein: The bidirectional conversion of the AXIS-LBUS data format includes: implementing flow control when converting the sending direction, adjusting the data sending rate according to the CMAC status signal; performing data continuity processing when converting the receiving direction, converting discontinuous LBUS data frames into AXIS data frames, and reducing the interval fluctuation of discontinuous data frames.

5. The method for implementing a low-latency, high-throughput protocol stack for 100 Gbps satellite-borne laser communications according to claim 1, wherein: The automatic retransmission request mechanism includes: The sending end maintains the data frame sequence number information; The receiving end generates ACK / NACK feedback through comparison; Establish a retransmission queue to manage error data frames.

6. A 100 Gbps satellite-borne laser communication protocol stack system, characterized in that: include: Four-channel parallel data processing unit, each channel is equipped with a 128-bit wide AXIS interface; The three-level data alignment processing module uses shift registers and parallel splicing circuits to achieve cacheless data alignment; Adaptive frame interval controller, including FIFO depth monitoring unit and dynamic adjustment unit; AXIS-LBUS bidirectional converter, which enables interface adaptation between the protocol stack and the 100G CMAC module; ARQ retransmission management module supports selective retransmission mechanism.

7. The 100 Gbps satellite-borne laser communication protocol stack system according to claim 6, characterized in that: The three-level data alignment processing module includes: The first-level alignment unit is configured in the IP sending module to realize the splicing of the UDP header and the IP address field; The second-level alignment unit is configured in the IP sending module to complete the reorganization of key fields of the IP message; The third-level alignment unit is configured in the MAC module and processes the splicing of the Ethernet frame header and IP data.

8. The 100 Gbps satellite-borne laser communication protocol stack system according to claim 6, characterized in that: The adaptive frame interval controller comprises: FIFO depth monitoring unit, when the number of FIFO buffered frames is ≥ 4, the frame interval is reduced by 1 clock cycle; The frame interval calculation unit increases the frame interval by 1 clock cycle when a complete frame cannot be read for 2 consecutive cycles; Dynamically adjust the execution unit and dynamically balance the frame interval within the range of 2-8 clock cycles.

9. The 100 Gbps satellite-borne laser communication protocol stack system according to claim 6, characterized in that: The AXIS-LBUS bidirectional converter includes: Transmit direction conversion module, integrated flow control state machine, responds to CMAC tx_ready and tx_overflow signals; The receiving direction conversion module includes a data continuity processing unit to eliminate discontinuous frame intervals.

10. The 100 Gbps satellite-borne laser communication protocol stack system according to claim 6, characterized in that: The ARQ retransmission management module implements: The sender maintains a sending window and records the sequence numbers of sent but unacknowledged frames; The receiving end adopts a cumulative confirmation mechanism and supports selective retransmission; The retransmission timeout timer is set to twice the link round-trip delay.

11. A satellite-borne communication device, characterized in that The protocol stack system according to any one of claims 6 to 10 is integrated, supporting: data transmission rate ≥ 100 Gbps; end-to-end delay ≤ 1 μs; Data frame throughput ≥ 80Mpps and bit error rate ≤ 10 -12 .

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