System and method for fetching and writing instructions to memory

Abstract

Read operations for a computing system are described herein. The computing system includes a non-transitory memory. In a non-transitory memory, instructions are stored in a cyclic redundancy block (CRC block). Each of the CRC blocks includes a first CRC code associated with an instruction stored in the CRC block. In the read operation, the computing system generates a second CRC code based on the instruction stored in the CRC block and compares the second CRC code with the first CRC code to determine whether the read operation is successful.

Description

Technical Field

[0001] The present application relates to computing systems and, more particularly, to execute-in-place (XiP) systems. Background Art

[0002] In execute-in-place (XiP) systems, such as those involved in the Internet of Things (IoT) and system-on-chip (SoC), instructions are stored in flash memory. One or more processors in these computing systems fetch instructions directly from flash memory. However, under certain conditions, such as high-frequency fetching, operation in high-temperature and high-voltage environments, or operation under electromagnetic interference, there is a certain probability of errors when fetching instructions from flash memory. These errors can cause logic errors and system crashes. The fetched instructions may not be consistent with the instructions actually stored in the flash memory. Therefore, it is desirable for the computing system to provide a mechanism to confirm whether the read operation was successful; that is, the fetched instructions match the instructions stored in the flash memory. Summary of the Invention

[0003] A method for fetching and writing instructions to a memory includes receiving a read request for one or more instructions located at one or more virtual read addresses from one or more processors, the one or more virtual read addresses corresponding to one or more physical read addresses of a flash memory; converting the one or more virtual read addresses into one or more physical read addresses; reading the one or more instructions located at the one or more physical read addresses of the flash memory into a first-in-first-out (FIFO) memory; reading a first cyclic redundancy check (CRC) code associated with the one or more instructions; calculating a second CRC code based on the one or more instructions; comparing the first CRC code to the second CRC code; and determining that the read operation was successful based on the first CRC code being equal to the second CRC code.

[0004] In one embodiment, a computing device includes a processor, a flash memory controller, and memory storing instructions that, when executed, configure the device to perform the steps.

[0005] In another embodiment, a non-transitory computer-readable storage medium contains instructions that, when executed by a computer, cause the computer to perform the steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] To easily identify the discussion of any particular element or operation, the most significant digit(s) in a reference number refers to the drawing number in which the element is first introduced.

[0007] Figure 1 is a block diagram illustrating components that may be present in computing system 100 according to some examples.

[0008] Figure 2is a conceptual diagram illustrating a FIFO memory of a flash memory controller and a CRC block of a flash memory of the computing system 100 according to some examples.

[0009] Figure 3 is a conceptual diagram illustrating memory organization in flash memory 106 according to some examples.

[0010] Figure 4 is a flow diagram illustrating the operation of the computing system 100 in performing a write operation to the flash memory 106 according to some examples.

[0011] Figure 5 is a flow chart illustrating further details of a process of writing to flash memory 106 according to some examples.

[0012] Figure 6 is a flow chart illustrating a read operation from flash memory 106 according to some examples.

[0013] Figure 7 is an illustration of a computing system 700 according to some examples, within which instructions 710 may be executed for causing the computing system 700 to perform any one or more of the methodologies discussed herein. DETAILED DESCRIPTION

[0014] Computing system 100 can include various internal and / or external components that contribute to computing system 100. In some examples, computing system 100 is an execute-in-place (XiP) system. XiP systems are commonly found in system-on-chip (SoC) and Internet of Things (IoT) devices. In these examples, a XiP system can fetch and execute instructions directly from non-volatile memory (e.g., flash memory 106) without first copying the instructions to random access memory (RAM). This reduces memory requirements and is beneficial in resource-constrained environments. In some examples, in a XiP system, non-volatile memory (e.g., flash memory 106) is managed by a controller (e.g., flash controller 104), which ensures reliable retrieval and writing of data to and from the non-volatile memory.

[0015] Figure 1 is a block diagram illustrating components that may be present in computing system 100 according to some examples. These components may enable computing system 100 to operate according to the techniques discussed herein. As will be understood, Figure 1 The various functional blocks shown in the may include hardware elements (including specific or general circuits), software elements (including computer code stored on a machine-readable medium), or a combination of hardware and software elements. It should also be noted that Figure 110. The present invention relates to a system 100 that is configured to store and process data in a manner that is consistent with the present invention. The system 100 includes a plurality of processors 102, a flash memory controller 104, a flash memory 106, one or more I / O ports 114, one or more input structures 116, one or more network devices 118, and a power supply 120. The flash memory controller 104 is coupled to the one or more processors 102, and the flash memory controller 104 is coupled to the flash memory 106 via a control bus (cbus) 110 and a data bus (dbus) 112. The flash memory controller 104 also includes a first-in-first-out (FIFO) memory 108. The one or more processors 102 are coupled to one or more I / O ports 114, one or more input structures 116, one or more network devices 118, and a power supply 120.

[0016] The one or more processors 102 may provide data processing capabilities for executing an operating system, programs, user and application program interfaces, and any other functions of the computing system 100. The one or more processors 102 may include one or more microprocessors, such as one or more "general purpose" microprocessors, one or more special-purpose microprocessors and / or ASICs, or some combination of these processing components. In some examples, the one or more processors 102 also include one or more microcontrollers, as well as a graphics processor, a video processor, an audio processor, and / or related chipsets.

[0017] Flash controller 104 can be a hardware device or microcontroller that manages the storage and retrieval of instructions or data for flash memory 106. In some examples, flash controller 104 includes a communication interface for receiving instructions and data. In some examples, flash controller 104 includes processing circuitry for controlling write operations and read operations to write / fetch instructions / data using the techniques described herein. In some examples, flash controller 104 causes external processing circuitry (e.g., one or more processors 102) to perform operations related to the management of flash memory 106, such as writing / fetching instructions / data using the techniques described herein. In some optional examples, flash controller 104 uses a combination of processing circuitry and external processing circuitry to perform operations related to the management of flash memory 106.

[0018] Flash memory 106 is a non-volatile storage medium that can be electrically erased and reprogrammed, and provides persistent storage of data and / or instructions. In some examples involving XiP systems, flash memory 106 stores one or more instructions executed by one or more processors 102 and / or data used to implement various functions of computing system 100, such as application or program code, data associated with the application or program, and operating system code.

[0019] In some examples, flash memory 106 stores one or more instructions to be executed by one or more processors 102. One or more processors 102 retrieve the one or more instructions by sending a read request to flash memory controller 104. Flash memory controller 104 performs a read operation to read the one or more instructions from flash memory 106, stores the one or more instructions in FIFO memory 108, and returns the one or more instructions to one or more processors 102 for execution. In some examples, the read request sent by one or more processors 102 includes a virtual read address corresponding to a physical read address in flash memory 106. In some examples, flash memory controller 104 retrieves the one or more instructions from flash memory 106 via a control bus (cbus) and retrieves data from flash memory 106 via a data bus (dbus).

[0020] Due to errors triggered by various factors, such as extraction in a high frequency, high temperature and high pressure environment, or extraction in the presence of electromagnetic interference, the extracted one or more instructions (i.e., one or more instructions stored in the FIFO memory 108 and executed by one or more processors) may be different from the one or more instructions actually stored in the flash memory 106. To address this issue, the computing system 100 can use cyclic redundancy check (CRC) technology to detect when an error occurs. In some examples, one or more instructions are associated with a first CRC code. During a read operation, after extracting one or more instructions from the flash memory 106, the flash memory controller 104 calculates a second CRC code based on the extracted one or more instructions. If the extracted one or more instructions are the same as the one or more instructions stored in the flash memory 106, the first CRC code should be the same as the second CRC code. If the extracted one or more instructions are different from the one or more instructions stored in the flash memory 106, the first CRC code will be different from the second CRC code, indicating that the read operation was unsuccessful. By comparing the first CRC code and the second CRC code in a read operation, the computing system 100 can verify whether the read operation is successful and detect errors in the read operation.

[0021] In some examples, one or more processors 102 send a write request to flash memory controller 104. Flash memory controller 104 performs a write operation to write one or more instructions to a FIFO memory and writes the one or more instructions in the FIFO memory to flash memory 106. To use CRC technology, a first CRC code corresponding to the one or more instructions can be generated in the write operation and stored in flash memory 106 together with the one or more instructions. In some examples, flash memory controller 104 calculates a first CRC code associated with the one or more instructions and stores the first CRC code in flash memory 106 together with the one or more instructions. The first CRC code generated in the write operation can be referred to as a third CRC code to distinguish it from the first CRC code used in the read operation. In some examples, the write request sent by one or more processors 102 includes a virtual write address corresponding to a physical write address in flash memory 106.

[0022] The I / O ports 114 may include ports configured to connect to various external devices, such as a power source 120 or other electronic devices (e.g., a handheld device and / or computer, a printer, a projector, an external display, a modem, a docking station, etc.). The I / O ports 114 may support any standard or proprietary interface type, such as a Universal Serial Bus (USB) port, a video port, a serial connection port, a FireWire port, an Ethernet or modem port, and / or an AC / DC power connection port.

[0023] Input structure(s) 116 may include various devices, circuits, and pathways through which input or feedback is provided to data processing circuitry, such as one or more processors 102. Such input structures 116 may be configured to control functionality of the computing system 100 when activated. For example, the input structures 116 may include buttons, sliders, switches, control pads, keys, knobs, scroll wheels, keyboards, mice, touchpads, and the like. In some examples, the input structures 116 may also include components such as global positioning system (GPS) circuitry and / or accelerometers that communicate information about the location and / or orientation of the computing system 100 to the one or more processors 102.

[0024] Network device 118, such as a network controller or network interface card (NIC). In some examples, network device 118 may be a wireless NIC that provides wireless connectivity via any 802.11 standard or any other suitable wireless networking standard. Network device 118 enables computing system 100 to communicate over a network, such as a local area network (LAN), a wide area network (WAN), a cellular network, or the Internet. In addition, computing system 100 can connect to and send or receive data from any device on the network, such as a portable electronic device, a personal computer, a printer, etc.

[0025] The power supply 120 may be one or more batteries, such as lithium-ion polymer batteries. The batteries may be removable or may be fixed within the housing of the computing system 100 and may be rechargeable. Furthermore, the power supply 120 may include an AC power source, such as provided by an electrical outlet, to which the computing system 100 may be connected via a power adapter. The power adapter may also be used to charge the one or more batteries (if present).

[0026] Figure 2 is a conceptual diagram illustrating a FIFO memory of a flash memory controller and a CRC block of a flash memory of the computing system 100 according to some examples.

[0027] As in Figure 1 As explained in the description of , flash memory 106 provides persistent storage of data and / or instructions. In some examples, flash memory 106 includes multiple memory locations. Each of the multiple memory locations holds a value and includes a corresponding physical address. The value can be an instruction or data (e.g., a first CRC code). The size of the value is 1 byte. The physical address corresponds to the virtual address. The flash memory controller 104 can use the physical address to locate where instructions / data are stored and where new instructions / data should be written. The one or more processors 102 use the virtual address to locate where instructions / data are stored and where new instructions / data should be written. In Figure 2 In the foregoing, for the purpose of discussion, all addresses are in hexadecimal notation, and all addresses in the flash memory 106 are physical addresses. The starting physical address of the flash memory 106 is 0x00000000, but in practice, the starting physical address may start from a higher address, such as 0x08000000.

[0028] In some examples, multiple memory locations are grouped into multiple CRC blocks. The size of the CRC block is determined by the length of the CPU cache line or the size of the FIFO memory 108. Figure 2In the example shown, the column pair labeled "Physical Address" and "Value" represents a CRC block. Each CRC block is 16 bytes in size, meaning it can accommodate 16 separate 1-byte instructions / data. However, it should be noted that since the CRC code occupies one memory location, which is also 1 byte, the actual byte size of each CRC block totals 17 bytes.

[0029] Flash controller 104 may receive a read request including a virtual address (e.g., virtual address 208) from one or more processors 102. Flash controller 104 may convert the virtual address into a physical address to identify a memory location. Figure 2 As shown, a memory location can be identified by its physical address 0x0001C55B, which includes instruction 0xB8, which represents a MOV instruction in an x86 system.

[0030] The flash controller 104 converts the virtual address to a physical address based on the size of the CRC block. In some examples where the size of the CRC block is 16 bytes, the flash controller 104 converts the physical read address using the following formula: physical address = virtual address + (virtual address >> 4). The operator ">>" represents a bit right shift; ">>4" represents dividing the virtual address by 2^4 (or 16), with the remainder ignored. The virtual address is divided by 16 because an additional CRC code (e.g., the first CRC code) is added to the flash memory 106 every 16 bytes. The result of virtual address >> 4 is used as an offset; the division result is then added to the original virtual address to obtain the physical address. For example, the virtual address of 0x0001AAB0 is converted to the corresponding physical address: physical address = 0x0001AAB0 + (0x0001AABO >> 4) = 0x0001AAB0 + 0x00001AAB = 0x0001C55B.

[0031] The flash controller 104 stores the CRC block associated with the physical address in the FIFO memory 108. Figure 2 As shown, in response to identifying the physical address 0x0001C55B, the flash controller 104 copies one or more instructions of the CRC block associated with the physical address 0x0001C55B (eg, 202 ) and stores the one or more instructions in the FIFO memory 108 .

[0032] Flash controller 104 calculates a second CRC code (e.g., 206) based on one or more instructions using various known methods. The second CRC code is compared with the first CRC code (e.g., 204) to verify whether the read operation was successful. In some examples, the first CRC code is found at physical address 0x0001C56B of the CRC block.

[0033] It should be emphasized that Figure 2The instructions and data values ​​shown in FIG are merely illustrative examples, which are used to illustrate the working principle of the computing system 100. Actual instructions and data values ​​may vary in practice depending on the specific configuration of the computing system 100.

[0034] Figure 3 The following is a conceptual diagram illustrating the memory organization in flash memory 106 according to some examples. Flash memory 106 can store different types of information (e.g., instructions and data). Flash memory 106 may include two or more partitions, at least one of which is designated for storing instructions and another for storing data. In some examples, the partition storing instructions is divided into CRC blocks that include CRC codes. The partition storing data is organized using a traditional method, that is, the partition storing data does not include a CRC code.

[0035] In some examples, the flash memory 106 includes two partitions, one for storing instructions (e.g., 302) and the other for storing data (e.g., 304). In these examples, the partition storing instructions (e.g., 302) is placed in a memory location at offset 0, i.e., the virtual address of the memory location is divisible by the size of the CRC block (e.g., 16). For example, the offset of the memory location 0x0001AAB0 is 0 because 0x0001AAB0 is divisible by 16, and the size of the CRC block is 16. The partition storing data is located at the other end of the flash memory 106. Figure 3 As shown, partition 302 and partition 304 do not overlap.

[0036] In some examples, flash memory 106 includes multiple images. Each of the multiple images includes instructions and data. Flash memory controller 104 combines the instructions from each of the multiple images by placing them in one or more CRC blocks. The one or more CRC blocks begin at a memory location with an offset of 0 in flash memory 106, i.e., the corresponding virtual address of the memory location is divisible by the size of the one or more CRC blocks. Computing system 100 adds a CRC code to each of the one or more CRC blocks. Computing system 100 combines the data from each of the multiple images by placing them at the other end of flash memory 106.

[0037] It needs to be emphasized that Figure 3 The instructions and data values ​​shown are merely illustrative examples, which are intended to illustrate the working principle of the flash memory 106. The actual instructions and data values ​​may vary in practice depending on the specific configuration of the computing system 100.

[0038] Figure 4is a flow chart illustrating the operations of computing system 100 in performing a write operation on flash memory 106, according to some examples. Method 400 may be embodied as computer-readable instructions for execution by one or more processors, such that the operations of method 400 may be performed in part or in whole by functional components of computing system 100; therefore, the following description will refer to method 400 by way of example. However, it should be understood that at least some of the operations of method 400 may be implemented on various other hardware configurations besides computing system 100.

[0039] In operation 402 , the computing system 100 receives a write request from one or more processors 102 via the flash controller 104 to write one or more instructions to a virtual write address in the flash memory 106 .

[0040] In operation 404, the computing system 100 converts the virtual write address to a physical write address. In some examples, in operation 404, the flash memory controller 104 converts the virtual write address to a physical write address based on the size of the CRC block. In some examples, the CRC block size is 16 bytes, and the flash memory controller 104 converts the physical write address using the following formula: physical write address = virtual write address + (virtual write address >> 4). The operator ">>" indicates a bit right shift; ">>4" indicates dividing the virtual write address by 2^4 (or 16), and the remainder is ignored. For example, the virtual write address 0x0001AAB0 is converted to the corresponding physical write address: physical write address = 0x0001AAB0 + (0x0001AAB0 >> 4) = 0x0001AAB0 + 0x00001AAB = 0x0001C55B.

[0041] In operation 406, the computing system 100 writes the one or more instructions to the FIFO memory. The flash memory controller 104 may write the one or more instructions to the FIFO memory until the current write operation of writing the one or more instructions fills the FIFO memory (i.e., reaches the maximum capacity of the FIFO memory) or all of the one or more instructions have been written to the FIFO memory. In some examples, if there are more instructions to be written to the FIFO memory than the capacity of the FIFO memory, the computing system 100 proceeds to operation 410.

[0042] In operation 408, the computing system 100 determines whether the FIFO memory is full in response to completing the writing of one or more instructions to the FIFO memory. If the flash memory controller 104 determines that the FIFO memory is full, the computing system 100 proceeds to operation 410; if the flash memory controller 104 determines that the FIFO memory is not full, the write operation is considered complete.

[0043] In operation 410, computing system 100 calculates a CRC code associated with one or more instructions written to FIFO memory. After storing the one or more instructions in FIFO memory 108, flash memory controller 104 calculates a CRC code based on the one or more instructions using various known CRC code calculation methods. In some examples, the CRC code is calculated before the one or more instructions are stored in FIFO memory 108. In some examples, the CRC code calculated during the write operation is referred to as a third CRC code.

[0044] In operation 412, the one or more instructions in the FIFO memory and the CRC code calculated in operation 410 are written to the flash memory. In some examples, the one or more instructions are written to the flash memory via cbus 110. In some examples, the write operation may include writing data instead of writing the one or more instructions to the flash memory. The data is written to the flash memory via dbus 112.

[0045] In operation 414, if the determination in operation 408 is false (i.e., the FIFO memory is not full, but all instructions in the one or more instructions have been written to the FIFO memory 108), the current write operation is considered complete. In some examples, even if the FIFO memory 108 is not completely filled, the method 400 will continue to perform operations 410 and 412 to calculate the CRC code to ensure that the one or more instructions are accurately and uninterruptedly written to the CRC block before moving to the next CRC block or performing other operations (e.g., a read operation) to prevent the one or more instructions from being corrupted by irrelevant information.

[0046] Figure 5 is a flow chart illustrating further details of a process of writing to the flash memory 106 according to some examples. The method 400 may further include operations 502, 504, and 506.

[0047] In operation 502, computing system 100 determines whether the last operation was a write operation. If the last operation was not a write operation (i.e., returns "FALSE"), computing system 100 performs operation 504. In operation 504, computing system 100 clears FIFO memory 108 to make room for the new instruction. On the other hand, if the last operation was a write operation, computing system 100 performs operation 506.

[0048] In operation 506, the computing system 100 determines whether the physical write address is within the same CRC block as the previous write operation, that is, whether the CRC block currently in the FIFO memory 108 includes the physical write address currently being written by the computing system 100. If the physical write address is within the same CRC block as the previous write operation, the computing system 100 proceeds to perform operation 406, that is, writing one or more instructions to the FIFO memory 108. If the physical write address is not within the same CRC block as the previous write operation, that is, the CRC block currently in the FIFO memory 108 does not include the physical write address currently being written by the computing system 100, the computing system 100 proceeds to perform operation 504 to clear the FIFO memory 108 before performing operation 406.

[0049] Figure 6 is a flow chart illustrating a read operation from flash memory 106 according to some examples.

[0050] In operation 602 , the computing system 100 receives a read request from one or more processors 102 for one or more instructions located at a virtual read address.

[0051] In operation 604, computing system 100 converts a virtual read address to a physical read address in response to a read request received from one or more processors 102. In some examples, the read request is for an instruction at virtual read address 0x0001AAC0. Flash controller 104 converts the virtual read address to a corresponding physical read address 0x0001C55B.

[0052] The computing system 100 converts the virtual read address to a physical read address based on the size of the CRC block. In some examples, the CRC block size is 16 bytes, and the flash memory controller 104 converts the physical read address using the following formula: physical read address = virtual read address + (virtual read address >> 4). The operator ">>" represents a bit right shift; ">>4" represents dividing the virtual address by 2^4 (or 16), with the remainder ignored. The virtual read address is divided by 16 because an additional CRC code (e.g., the first CRC code) is added to the flash memory 106 every 16 bytes. The result of the virtual read address >> 4 is used as an offset; the result of the division is then added to the original virtual read address to obtain the physical read address. For example, to convert the virtual read address 0x0001AAB0 to the corresponding physical read address: physical read address = 0x0001AAB0 + (0x0001AABO >> 4) = 0x0001AAB0 + 0x00001AAB = 0x0001C55B.

[0053] In operation 606, computing system 100 determines whether the requested one or more instructions are in the FIFO memory. If true, read operation 600 proceeds to operation 608. If false, read operation 600 proceeds to operation 610. In some examples, the requested one or more instructions have already been read from FIFO memory 108 of flash memory controller 104 via a previous read operation, so there is no need to read them again from flash memory 106. Therefore, computing system 100 proceeds to operation 608. In operation 608, flash memory controller 104 returns the requested one or more instructions in the FIFO memory to one or more processors for execution.

[0054] In operation 610, computing system 100 reads one or more instructions located at the physical read address from flash memory 106 to FIFO memory 108. In some examples, the entire CRC block including the one or more instructions (determined by the physical read address) is copied to FIFO memory 108. Figure 2 As shown, if one or more instructions are located at physical read addresses 0x0001C560 and 0x0001C561, the entire CRC block 202 is copied to the FIFO memory 108.

[0055] In operation 612 , the computing system 100 calculates a second CRC code based on the one or more instructions in the FIFO memory 108 using various known methods (eg, CRC-16-CCITT, CRC-16-IBM).

[0056] In operation 614, computing system 100 determines whether the first CRC code matches the second CRC code. If the first CRC code is equal to the second CRC code, then the one or more instructions were correctly retrieved, the read operation was successful, and computing system 100 proceeds to operation 616. In operation 616, computing system 100 returns the requested one or more instructions in FIFO memory 108 to one or more processors for execution. If the first CRC code is different from the second CRC code, then the read operation was unsuccessful, and computing system 100 performs operation 610 again. In operation 610, computing system 100 reads the one or more instructions from flash memory 106 into FIFO memory 108. It should be understood that the one or more instructions involved in the write operation can be different from or the same as the one or more instructions involved in the read operation.

[0057] Figure 7is a schematic diagram of a computing system 700 in which instructions 710 (e.g., software, programs, applications, applet, applications, or other executable code) for causing the computing system 700 to perform any one or more of the methodologies discussed herein may be executed, according to some examples. For example, the instructions 710 may cause the computing system 700 to perform any one or more of the methodologies described herein. The instructions 710 may transform a general, non-programmed computing system into a specialized machine computing system 700 that is programmed to perform the functions described and illustrated in the manner described. The computing system 700 may operate as a standalone device or may be coupled to other machines (e.g., networked). In a network deployment, the computing system 700 may operate as a server or client machine in a server-client network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The computing system 700 may include, but is not limited to, a server computer, a client computer, a personal computer (PC), a tablet computer, a laptop computer, a netbook computer, a set-top box (STB), an entertainment media system, a cellular phone, a smartphone, a mobile device, a wearable device (e.g., a smart watch), a smart home device (e.g., a smart appliance), other smart devices, a network device, a network router, a network switch, a network bridge, or any machine capable of executing instructions 710, sequentially or otherwise, that specify operations to be performed by the computing system 700. Furthermore, while a single computing system 700 is shown in the figure, the term "computing system" may include a collection of machines that individually or jointly execute instructions 710 to perform any one or more of the methodologies discussed herein.

[0058] Computing system 700 may include processor 704, memory 706, and I / O components 702, which may be configured to communicate via bus 740. In some examples, processor 704 (e.g., a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing processor (CISC), a graphics processing unit (GPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a radio frequency integrated circuit (RFIC), other processors, or any suitable combination thereof) may include processor 708 and processor 712, among others, that execute instructions 710. The term "processor" is intended to include multi-core processors, which may include two or more independent processors (sometimes referred to as "cores") that can execute instructions concurrently. Although Figure 7 Multiple processors 704 are shown, but computing system 700 may include a single processor with a single core, a single processor with multiple cores (eg, a multi-core processor), multiple processors with a single core, multiple processors with multiple cores, or any combination thereof.

[0059] The memory 706 includes a main memory 714, a static memory 716, and a storage unit 718, all of which are accessible to the processor 704 via a bus 740. The main memory 714, the static memory 716, and the storage unit 718 may store instructions 710 that embody any one or more of the methodologies or functionality described herein. During execution of the instructions 710 by the computing system 700, the instructions 710 may also reside, in whole or in part, in the main memory 714, the static memory 716, the machine-readable medium 720 in the storage unit 718, within the processor 704 (e.g., a cache memory of the processor), or any suitable combination thereof.

[0060] I / O components 702 may include various components for receiving input, providing output, generating output, sending information, exchanging information, or capturing measurements. The specific I / O components 702 included in a particular machine will depend on the type of machine. For example, a portable machine such as a mobile phone may include a touch input device or other such input mechanism, while a headless server may not include such a touch input device. I / O components 702 may include Figure 7 Many other components not shown in the figure. In various examples, the I / O components 702 may include an output component 726 and an input component 728. The output component 726 may include a visual component (e.g., a plasma display panel (PDP), a light emitting diode (LED) display, a liquid crystal display (LCD), a projector, or a cathode ray tube (CRT)), an audio component (e.g., a speaker), a tactile component (e.g., a vibration motor, a resistance mechanism), or other signal generators. The input component 728 may include an alphanumeric input component (e.g., a keyboard, a touch screen configured to receive alphanumeric input, an optical keyboard, or other alphanumeric input component), a point input component (e.g., a mouse, a touch pad, a trackball, a joystick, a motion sensor, or other pointing tool), a tactile input component (e.g., a physical button, a touch screen that provides touch location and / or force or touch gestures, or other tactile input components), an audio input component (e.g., a microphone), etc.

[0061] In further examples, the I / O component 702 may include a series of other components such as a biometric component 730, a motion component 732, an environmental component 734, or a position component 736. For example, the biometric component 730 includes a component for detecting expressions (e.g., hand representations, facial expressions, vocal expressions, body postures, or eye tracking), measuring biosignals (e.g., blood pressure, heart rate, body temperature, sweat, or brain waves), or identifying a person (e.g., voice recognition, retinal recognition, facial recognition, fingerprint recognition, or electroencephalogram-based recognition). The motion component 732 includes an acceleration sensor component (e.g., an accelerometer), a gravity sensor component, and a rotation sensor component (e.g., a gyroscope). The environment component 734 includes, for example, one or more cameras, an illumination sensor component (e.g., a photometer), a temperature sensor component (e.g., one or more thermometers for detecting ambient temperature), a humidity sensor component, a pressure sensor component (e.g., a barometer), an acoustic sensor component (e.g., one or more microphones for detecting background noise), a proximity sensor component (e.g., an infrared sensor for detecting nearby objects), a gas sensor (e.g., a gas detection sensor for detecting hazardous gas concentrations to ensure safety or measuring pollutants in the atmosphere), or other components that can provide indications, measurements, or signals corresponding to the surrounding physical environment. The position component 736 includes a position sensor component (e.g., a global positioning system (GPS) receiver component), an altitude sensor component (e.g., an altimeter or a barometer for detecting air pressure to derive altitude), an orientation sensor component (e.g., a magnetometer), etc.

[0062] Communication can be achieved through a variety of technologies. The I / O component 702 also includes a communication component 738 that can connect the computing system 700 to the network 722 or the device 724 through respective couplings or connections. For example, the communication component 738 can include a network interface component or other suitable device to connect to the network 722. In further examples, the communication component 738 can include a wired communication component, a wireless communication component, a cellular communication component, a near field communication (NFC) component, Components (e.g. Low power consumption), Components and other communication components to provide communication by other means. Device 724 can be another machine, or any of a variety of peripheral devices (e.g., a peripheral device coupled via USB).

[0063] In addition, the communication component 738 can detect an identifier or include a component that can be used to detect an identifier. For example, the communication component 738 can include a radio frequency identification (RFID) tag reader component, an NFC smart tag detection component, an optical reader component (e.g., an optical sensor for detecting one-dimensional barcodes (such as universal product code (UPC) barcodes), multi-dimensional barcodes (such as Quick Response (QR) codes, Aztec codes, Data Matrix, Data Glyphs, Maxi Codes, PDF417, Ultra Codes, UCCRSS-2D barcodes, and other optical codes)) or a sound detection component (e.g., a microphone for identifying audio signals with tags). In addition, various information can be obtained through the communication component 738, such as location information obtained through Internet Protocol (IP) geolocation, location information obtained through Location information is obtained through signal triangulation or by detecting NFC beacon signals that can indicate a specific location.

[0064] Various memories (e.g., main memory 714, static memory 716, and / or memory of processor 704) and / or storage unit 718 may store one or more instruction sets and data structures (e.g., software) that embody or are used for any one or more of the methods or functions described herein. When these instructions (e.g., instructions 710) are executed by processor 704, they cause various operations to implement the disclosed examples.

[0065] The instructions 710 may be transmitted or received over the network 722 using a transmission medium via a network interface device (e.g., a network interface component included in the communication component 738) and using any of several well-known transmission protocols (e.g., the Hypertext Transfer Protocol (HTTP)). Similarly, the instructions 710 may be transmitted or received over a coupling (e.g., a peer-to-peer coupling) with the device 724 using a transmission medium.

[0066] Example

[0067] Embodiment 1 is a method, comprising receiving, by a flash memory controller, a read request for one or more instructions located at one or more virtual read addresses from one or more processors, the one or more virtual read addresses corresponding to one or more physical read addresses of the flash memory; converting, by the flash memory controller, the one or more virtual read addresses into one or more physical read addresses; reading, by the flash memory controller, the one or more instructions located at the one or more physical read addresses of the flash memory into a FIFO memory; reading, by the flash memory controller, a first CRC code associated with the one or more instructions; calculating, by the flash memory controller, a second CRC code based on the one or more instructions; comparing, by the flash memory controller, the first CRC code and the second CRC code; and determining, by the flash memory controller, that the read operation is successful based on the first CRC code being equal to the second CRC code.

[0068] In embodiment 2 based on embodiment 1, the method further includes: determining that the read operation is unsuccessful according to that the first CRC code is different from the second CRC code; and performing all operations of reading, calculating, comparing and determining again.

[0069] In embodiment 3 based on embodiments 1-2, it also includes: the flash memory controller receives a write request from one or more processors to write one or more second instructions to one or more virtual write addresses in the flash memory; the flash memory controller converts the one or more virtual write addresses into one or more physical write addresses; the flash memory controller determines that the last operation is the last read operation; the flash memory controller clears the FIFO memory; the flash memory controller writes the one or more second instructions to the FIFO memory; the flash memory controller calculates a third CRC code related to the one or more second instructions; and the flash memory controller writes the one or more second instructions and the third CRC code in the FIFO memory to one or more physical write addresses of the flash memory.

[0070] In embodiment 4 based on embodiments 1-3, it also includes: the flash memory controller receives a write request from one or more processors to write one or more second instructions to one or more virtual write addresses in the flash memory; the flash memory controller converts the one or more virtual write addresses into one or more physical write addresses; the flash memory controller determines that the last operation is the last read operation; the flash memory controller determines that the last write operation is performed on the same CRC block based on the one or more physical write addresses; and the flash memory controller writes the one or more second instructions to the FIFO memory.

[0071] In embodiment 5 based on embodiments 1-4, it also includes: based on the current write operation filling up the FIFO memory, the flash memory controller calculates a third CRC code associated with the one or more second instructions; and the flash memory controller writes the one or more second instructions and the third CRC code in the FIFO memory to one or more physical write addresses of the flash memory.

[0072] In embodiment 6 based on embodiments 1-5, it also includes: the flash memory controller determines that the last write operation is performed on a different CRC block based on one or more physical write addresses; and the flash memory controller clears the FIFO memory.

[0073] In embodiment 7 based on embodiments 1-6, the process of writing one or more second instructions into the FIFO memory will not be interrupted by other operations and will fill up one CRC block.

[0074] In embodiment 8 based on embodiments 1-7, it further includes: determining each address of the one or more physical read addresses using the following formula: physical read address=virtual read address+(virtual read address>>4).

[0075] In embodiment 9 based on embodiments 1-8, it further includes: determining each address of the one or more physical write addresses using the following formula: physical write address=virtual write address+(virtual write address>>4).

[0076] In embodiment 10 based on embodiments 1-9, it further includes: the size of the CRC block is determined by one of the CPU cache line length and the FIFO memory capacity.

[0077] Embodiment 11 is a computing system including a method for implementing any one of embodiments 1-10.

[0078] Embodiment 12 is a non-transitory computer-readable storage medium comprising instructions that, when executed by a computer, cause the computer to implement any one of embodiments 1-10.

[0079] the term

[0080] "CPU cache line length" refers to the size of a CPU cache line, usually in bytes. It can refer to the data / instructions transferred from main memory to the cache in one cache operation.

[0081] "Commands" refer to instructions.

[0082] A "computing system" is a set of hardware and software components that processes data and executes instructions, and provides a platform for running software applications.

[0083] "Control bus (Cbus)" refers to a component of a computer system that is used to send and receive control signals / instructions within the computer system.

[0084] An "ongoing write operation" is the ongoing process of one or more processors or computing systems writing data or instructions to a specific location in memory or storage devices (such as flash memory).

[0085] "Data" is a collection of numerical values ​​specifying qualitative or quantitative variables. Data can be structured or unstructured and take many forms, including numbers, text, images, audio, and video. For example, an employee's name, ID, and salary in a database, or the pixels in an image file, all represent data. Data is different from instructions, which tell a computer system what actions to perform.

[0086] "Data bus (dbus)" refers to the components in a computing system used to send and receive data within the computing system.

[0087] A "read operation" is when the processor retrieves instructions or data from memory for execution.

[0088] A "read request" is an operation in which one or more processors request that data be retrieved (or "fetched") from a location in memory. A read request specifies the memory address (i.e., the virtual read address) from which the data is to be retrieved. This operation is used when one or more processors need to read the value of a variable or load instructions for execution.

[0089] "FIFO memory" refers to a storage device that organizes data using the "first-in, first-out" method. FIFO memory is used for buffering and managing data packets or instructions in various hardware and software systems.

[0090] An "image" is a complete copy of a system's state at a specific point in time. This might include the entire contents and structure of a storage device like a hard drive or DVD. System images are often used for backups, system recovery, or replicating settings across multiple machines. It can also refer to the contents of memory at a specific point in time.

[0091] An "instruction" is a command given to a computer to perform a specific operation. This operation might involve arithmetic, data processing, or control tasks. An instruction is the fundamental unit of programming; it tells a computer processor what to do. Each instruction typically consists of an opcode, which specifies the operation to be performed (such as addition, subtraction, moving data, or jumping to another instruction), and operands, which provide the data or data locations on which the operation is to be performed.

[0092] A "logic error" is an error or flaw in a program's source code that causes incorrect or unexpected behavior.

[0093] “Non-transitory memory” refers to media that has persistent and durable storage capabilities. Examples of non-transitory media include hard drives, solid-state drives, flash memory, CD-ROMs, DVDs, and other types of storage devices that retain stored information even when power is removed.

[0094] The "offset" is the distance between a specific memory location within a CRC block and a reference point that serves as the starting point for that CRC block. For example, Figure 2 , the memory location with physical address 0x0001C560 has an offset of 5. Another memory location with physical address 0x0001C55B has an offset of 0 because it is the start of the CRC block.

[0095] "Microcontroller(s)" refers to one or more small, independent computing devices designed to perform specific tasks within a larger system. They include an integrated processor, memory, and input / output peripherals. One or more microcontrollers are often used in embedded systems or devices to control specific operations or processes.

[0096] A partition is a section of a physical disk or memory that functions independently of other sections, providing a method for organizing data or instructions. Partitions can exist on hard drives, flash memory, and databases, effectively dividing a larger storage space into smaller, manageable units that can be operated and managed independently.

[0097] A "physical address" refers to the location where data or instructions are stored in storage hardware, such as flash memory. A physical address corresponds to an actual, accessible memory location within a computing system's storage device.

[0098] "Physical Read Address" refers to the physical address used in a read operation.

[0099] "Physical write address" refers to the physical address used in a write operation.

[0100] "Last Read Operation" means the last completed read operation by a processor or system to retrieve data or instructions from a specified location in memory or storage.

[0101] The "last operation" refers to the last operation involving a read request or a write request completed by the computing system.

[0102] "Last Write Operation" means the last completed write operation by the processor or system to write data or instructions to a specified location in memory or storage.

[0103] A "virtual address" is an address in a computing system's virtual address space that is used by one or more processors to fetch or write data or instructions. The memory accessed by one or more processors is abstracted from the actual physical memory.

[0104] A "virtual read address" refers to the virtual address used in a read operation. When one or more processors issue a read request, they use the virtual read address to represent the location within their virtual address space, but the actual data or instructions may be stored at a different location in physical memory. Different locations in physical memory can be precisely addressed using their corresponding physical addresses.

[0105] A "virtual write address" refers to the virtual address used in a write operation. When one or more processors issue a write request, they use the virtual write address to represent the location within their virtual address space, but the actual data or instructions might be written to the corresponding location in physical memory. The corresponding location in physical memory is identified by the corresponding physical address.

[0106] A "write request" is an operation in which one or more processors request that data / instructions be stored (or "written") to a location in memory. A write request specifies the memory address where the data should be stored (e.g., a virtual write address) and the data to be written to that location. For example, a processor uses this operation when it needs to save the results of a calculation or update the value of a variable.

[0107] A "XiP system" refers to a computing system designed to support execute-in-place operations. It is often found in embedded systems with limited memory resources. XiP systems allow programs to execute directly from long-term storage (e.g., flash memory) without first copying them to random access memory (RAM). One or more processors in a XiP system can fetch instructions directly from flash memory for execution.

Claims

1. A method for writing and extracting instructions, comprising: Receiving, by the flash memory controller, a read request from one or more processors for one or more instructions located at one or more virtual read addresses, the one or more virtual read addresses corresponding to one or more physical read addresses of the flash memory; The flash memory controller converts the one or more virtual read addresses into the one or more physical read addresses; The flash memory controller reads the one or more instructions located at the one or more physical read addresses of the flash memory into a FIFO memory; The flash memory controller reads a first CRC code associated with the one or more instructions; The flash memory controller calculates a second CRC code according to the one or more instructions; The flash memory controller compares the first CRC code and the second CRC code; and Based on the first CRC code being equal to the second CRC code, the flash memory controller determines that the read operation is successful.

2. The method according to claim 1, wherein Also includes: determining that the read operation is unsuccessful based on that the first CRC code is different from the second CRC code; as well as The operations of reading, calculating, comparing, and determining are performed again.

3. The method according to claim 1, wherein The one or more instructions located at the one or more virtual read addresses are one or more first instructions, the method further comprising: The flash memory controller receives a write request from one or more processors for writing one or more second instructions to the one or more virtual write addresses in the flash memory; The flash memory controller converts the one or more virtual write addresses into one or more physical write addresses; Determining, by the flash memory controller, that a previous operation is a previous read operation; The flash memory controller clears the FIFO memory; The flash memory controller writes the one or more second instructions into the FIFO memory; The flash memory controller calculates a third CRC code associated with the one or more second instructions; and The flash memory controller writes the one or more second instructions and the third CRC code in the FIFO memory into the one or more physical write addresses of the flash memory.

4. The method according to claim 1, wherein The one or more instructions located at the one or more virtual read addresses are one or more first instructions, the method further comprising: The flash memory controller receives a write request from one or more processors for writing one or more second instructions to the one or more virtual write addresses in the flash memory; The flash memory controller converts the one or more virtual write addresses into one or more physical write addresses; Determining, by the flash memory controller, that a previous operation is a previous write operation; The flash memory controller determines, based on the one or more physical write addresses, that the last write operation is performed on the same CRC block; and The flash memory controller writes the one or more second instructions into the FIFO memory.

5. The method according to claim 4, wherein Also includes: The flash memory controller calculates a third CRC code associated with the one or more second instructions based on the current write operation filling up the FIFO memory; as well as The flash memory controller writes the one or more second instructions and the third CRC code in the FIFO memory into the one or more physical write addresses of the flash memory.

6. The method according to claim 4, wherein Also includes: The flash memory controller determines, based on the one or more physical write addresses, that the last write operation is performed on a different CRC block; as well as The flash memory controller flushes the FIFO memory.

7. The method according to claim 5, wherein The process of writing the one or more second instructions into the FIFO memory will not be interrupted by other operations and will fill up a CRC block.

8. The method according to claim 1, wherein The flash memory controller converts the one or more virtual read addresses into the one or more physical read addresses, comprising: Each of the one or more physical read addresses is determined using the following formula: physical read address=virtual read address+(virtual read address>>4).

9. The method according to claim 3, wherein The flash memory controller converts the one or more virtual write addresses into the one or more physical write addresses, comprising: Each of the one or more physical write addresses is determined using the following formula: physical write address=virtual write address+(virtual write address>>4).

10. The method according to claim 4, wherein The size of the CRC block is determined by one of the length of the CPU cache line and the capacity of the FIFO memory.

11. A computing system, characterized in that: include: one or more processors; Flash memory controller; as well as A memory storing instructions that, when executed by the one or more processors, configure the computing system to perform the following operations: receiving, from the one or more processors, a read request for one or more instructions located at one or more virtual read addresses, the one or more virtual read addresses corresponding to one or more physical read addresses of the flash memory; converting the one or more virtual read addresses to the one or more physical read addresses; reading the one or more instructions located at the one or more physical read addresses of the flash memory into a FIFO memory; reading a first CRC code associated with the one or more instructions; Calculating a second CRC code according to the one or more instructions; comparing the first CRC code and the second CRC code; as well as According to the first CRC code being equal to the second CRC code, it is determined that the read operation is successful.

12. The computing system of claim 11, wherein: The instructions further configure the computing system to perform operations comprising: determining that the read operation is unsuccessful based on that the first CRC code is different from the second CRC code; and Perform all the operations of reading, calculating, comparing, and determining again.

13. The computing system of claim 11, wherein: The one or more instructions located at the one or more virtual read addresses are one or more first instructions, and the command further configures the computing system to perform operations comprising: receiving a write request from the one or more processors to write one or more second instructions to the one or more virtual write addresses in the flash memory; converting the one or more virtual write addresses into one or more physical write addresses; Determine that the last operation is the last read operation; Clearing the FIFO memory; Writing the one or more second instructions into the FIFO memory; calculating a third CRC code associated with the one or more second instructions; and The one or more second instructions and the third CRC code in the FIFO memory are written into the one or more physical write addresses of the flash memory.

14. The computing system of claim 11, wherein: The one or more instructions located at the one or more virtual read addresses are one or more first instructions, and the command further configures the computing system to perform operations comprising: receiving a write request from the one or more processors to write one or more second instructions to the one or more virtual write addresses in the flash memory; converting the one or more virtual write addresses into one or more physical write addresses; Make sure the last operation is the last write operation; Determining, based on the one or more physical write addresses, that the last write operation is performed on the same CRC block; and The one or more second instructions are written into the FIFO memory.

15. The computing system of claim 14, wherein: The commands further configure the computing system to perform the following operations, including: calculating a third CRC code associated with the one or more second instructions based on the current write operation filling up the FIFO memory; and The one or more second instructions and the third CRC code in the FIFO memory are written into the one or more physical write addresses of the flash memory.

16. The computing system of claim 14, wherein: The commands further configure the computing system to perform the following operations, including: Determining, based on the one or more physical write addresses, that the last write operation is performed on a different CRC block; and The FIFO memory is flushed.

17. The computing system of claim 11, wherein: The flash memory controller converts the one or more virtual read addresses into the one or more physical read addresses, comprising: Each of the one or more physical read addresses is determined using the following formula: physical read address=virtual read address+(virtual read address>>4).

18. The computing system of claim 14, wherein: The flash memory controller converts the one or more virtual write addresses into the one or more physical write addresses, comprising: Each of the one or more physical write addresses is determined using the following formula: physical write address=virtual write address+(virtual write address>>4).

19. A non-transitory computer-readable storage medium, characterized in that The method includes instructions that, when executed by a computing system, cause the computing system to perform operations including: receiving, from one or more processors, a read request for one or more instructions located at one or more virtual read addresses, the one or more virtual read addresses corresponding to one or more physical read addresses of the flash memory; converting the one or more virtual read addresses to the one or more physical read addresses; reading the one or more instructions located at the one or more physical read addresses of the flash memory into a FIFO memory; reading a first CRC code associated with the one or more instructions; Calculating a second CRC code according to the one or more instructions; comparing the first CRC code and the second CRC code; as well as According to the first CRC code being equal to the second CRC code, it is determined that the read operation is successful.

20. The non-transitory computer-readable storage medium of claim 19, wherein: The one or more instructions located at the one or more virtual read addresses are one or more first instructions, and wherein the command further configures the computing system to perform operations comprising: receiving a write request from the one or more processors to write one or more second instructions to the one or more virtual write addresses in the flash memory; converting the one or more virtual write addresses into one or more physical write addresses; Determine that the last operation is the last read operation; Clearing the FIFO memory; Writing the one or more second instructions into the FIFO memory; calculating a third CRC code associated with the one or more instructions; and The one or more second instructions and the third CRC code in the FIFO memory are written into the one or more physical write addresses of the flash memory.

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