Error handling method based on fault-tolerant disk array check, related memory controller and data storage device

Abstract

The invention relates to an error processing method based on fault-tolerant disk array check, a related memory controller and a data storage device. The error processing method comprises the following steps of: determining check data corresponding to read data or write data according to the read data with decoding error or the write data with programming error; selecting a plurality of data to be moved from the flash memory according to the verification data; and executing a data migration operation to migrate the plurality of data to be migrated to a target storage space in the flash memory.

Description

Technical Field

[0001] The present invention relates to a flash memory, and more particularly to an error handling method based on fault-tolerant disk array verification, and a related memory controller and data storage device. Background Art

[0002] Error correction coding (ECC) is used to correct errors when reading from flash memory devices. Before data is stored, it can be encoded using an ECC encoder to generate protection information, which can be stored as ECC codewords along with the original data. Flash memory storage devices also utilize a fault-tolerant RAID (Redundant Array of Independent Disks)-style data protection technology. This technology uses RAID parity to implement data checking and correction, and RAID-style checking and correction can be used to handle data errors that exceed the ECC's ability to correct.

[0003] Generally, when an ECC decoding error or RAID decoding error is detected, the error handling mechanism running on the flash memory device will reclaim the block containing the data with the decoding error, moving all data in that block to other blocks in the flash memory storage device to avoid potential data corruption. However, as the storage density of flash memory devices increases, the size of a single block has also increased significantly. The amount of data moved due to data errors has also increased significantly. Therefore, a more efficient error handling mechanism is needed to address the above issues. Summary of the Invention

[0004] In view of this, the present invention proposes an innovative error handling mechanism. In an embodiment of the present invention, when the error handling process moves data in response to a data error, the range of data to be moved will be considered based on the protection range of a single RAID check data. In other words, when a data error occurs (such as a decoding error when reading data or a programming error when writing data), only the stored data associated with the same RAID check data will be moved. In this way, the amount of data moved is effectively reduced and the efficiency of error handling is also improved. It is well known that the number of write and erase cycles (P / E cycles) of flash memory is limited. Therefore, when the amount of data moved during error handling is reduced, the life of the flash memory can be extended while ensuring data security.

[0005] An embodiment of the present invention provides an error handling method for a flash memory. The error handling method includes: determining check data corresponding to a read data having a decoding error or a write data having a programming error; selecting a plurality of to-be-moved data from the flash memory based on the check data; and performing a data migration operation to migrate the plurality of to-be-moved data to a target storage space in the flash memory.

[0006] An embodiment of the present invention provides a memory controller for a flash memory. The memory controller includes a storage unit and a processing unit. The storage unit is configured to store a program code. The processing unit is configured to execute the program code to perform error processing on the flash memory, including: determining, in response to a read data item experiencing a decoding error or a write data item experiencing a programming error, verification data corresponding to the read data or the write data; selecting, based on the verification data, a plurality of data items to be moved from the flash memory; and performing a data move operation to move the plurality of data items to be moved to a target storage space in the flash memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 1 is a diagram illustrating the architecture of a data storage device according to an embodiment of the present invention.

[0008] Figure 2A and Figure 2B A schematic diagram illustrating a RAID-type check mechanism according to an embodiment of the present invention is shown.

[0009] Figure 3 FIG. 4 illustrates an error handling process for a read operation according to an embodiment of the present invention.

[0010] Figure 4 FIG. 4 illustrates the intra-block write strategy according to an embodiment of the present invention.

[0011] Figure 5 The valid data determination process in an embodiment of the present invention is illustrated.

[0012] Figure 6 FIG. 4 illustrates an error handling process for a programming operation according to an embodiment of the present invention.

[0013] Figure 7 A flowchart of an error handling method according to an embodiment of the present invention is shown.

[0014]

Explanation of symbols

[0015] 10 Electronic devices

[0016] 50 host device

[0017] 52 processors

[0018] 54 RAM

[0019] 100 data storage devices

[0020] 110 Memory Controller

[0021] 112 processing units

[0022] 112C Program Code

[0023] 112M ROM

[0024] 113 Internal Memory

[0025] 114 Control Logic Circuit

[0026] 118 transmission interface circuit

[0027] 121 Page Cache

[0028] 122_1 to 122_N NV memory elements

[0029] 123 Control Circuit

[0030] 130 ECC processing circuit

[0031] 140 RAID processing circuit

[0032] Steps S101-S109, S1071-S1073, S201-S209, S310-S330 DETAILED DESCRIPTION

[0033] In the following text, many specific details are described to provide the reader with a thorough understanding of the embodiments of the present invention. However, those skilled in the art will understand how to implement the present invention without one or more specific details, or using other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the core concepts of the present invention.

[0034] References in this specification to "one embodiment" mean that the specific features, structures, or characteristics described in that embodiment may be included in at least one embodiment of the present invention. Therefore, the phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment. Furthermore, the aforementioned specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0035] Figure 1This is an architectural diagram of an electronic device and a data storage device according to an embodiment of the present invention. The electronic device 10 includes a host device 50 and a data storage device 100. The host device 50 may include at least one processor 52 for controlling the host device 50 and a random access memory (RAM) 54 for storing data and information required by the processor 52. Examples of the host device 50 include, but are not limited to, smartphones, tablets, wearable devices, personal computers (e.g., desktop computers and laptops), imaging devices (e.g., digital cameras or camcorders), game consoles, car navigation systems, printers, scanners, or server systems. Examples of the data storage device 100 include, but are not limited to, portable storage devices (e.g., memory cards compliant with SD / MMC, CF, MS, XD, or UFS specifications), solid-state drives (SSDs), and various embedded storage devices (e.g., embedded storage devices compliant with UFS or EMMC specifications).

[0036] According to various embodiments of the present invention, the data storage device 100 may include a controller (e.g., a memory controller 110) and may further include a non-volatile (NV) memory 120. The NV memory 120 is configured to store information. The NV memory 120 may include one or more NV memory elements, for example, a plurality of NV memory elements 122_1 to 122_N. The NV memory 120 may be a flash memory, and the NV memory elements 122_1 to 122_N may be a plurality of flash memory chips or a plurality of flash memory dies, respectively, but the present invention is not limited thereto. In addition, the NV memory 120 may include memory cells having a two-dimensional structure, or may include memory cells having a three-dimensional structure.

[0037] like Figure 1As shown, the memory controller 110 may include a processing unit 112, a read-only memory (ROM) 112M, an internal memory 113, a control logic circuit 114, a transmission interface circuit 118, an error correction coding (ECC) processing circuit 130, and a redundant array of independent disks (RAID) processing circuit 140. At least some of these components may be coupled to each other via a bus. The internal memory 113 may be implemented by one or more memory devices. For example, the internal memory 113 may be static RAM (SRAM) and / or dynamic RAM (DRAM). The internal memory 113 may be used to provide internal storage space for the memory controller 110, for example, to temporarily store information such as variables / parameters, data, commands, addresses, and / or address mapping tables. In some embodiments, the memory controller 110 also relies on host memory buffer (HMB) technology. By using the HMB technology, the memory controller 110 can utilize the RAM 54 (eg, DRAM) of the host device 50 as a portion or extension of the internal memory 113 , thereby improving the read and write performance of the data storage device 100 .

[0038] In addition, the ROM 112M in this embodiment is configured to store program code 112C, and the microprocessor 112 is configured to execute the program code 112C to control access to the NV memory 120. The program code 112C may include one or more program modules, such as a boot loader program code. When the data storage device 100 obtains power from the host device 50, the processing unit 112 may execute an initialization program of the data storage device 100 by executing the program code 112C. In the initialization program, the microprocessor 112 may load a set of in-system programming (ISP) program codes (not shown) from the NV memory 120. Figure 1). The microprocessor 112 can execute the set of in-system programming codes so that the data storage device 100 can have various functions. According to one embodiment of the present invention, the set of in-system programming codes may include, but are not limited to: one or more program modules related to memory access (e.g., reading, writing, and erasing), such as a read operation module, a lookup table module, a wear leveling module, a read refresh module, a read reclaim module, a garbage collection module, and a sudden power off recovery (SPOR) module, which are respectively provided to perform corresponding operations such as reading, lookup table, wear leveling, read refresh, read reclaim, garbage collection, and sudden power off recovery processing.

[0039] The memory controller 110 controls the reading, writing, and erasing of the NV memory 120 via the control logic circuit 114. Furthermore, the memory controller 110 can simultaneously execute: writing user data based on host commands from the host device 50; and writing valid data read from the NV memory 120 based on garbage collection and / or wear leveling operations. The transmission interface circuit 118 may comply with specific communication standards (for example, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the CF interface standard, the MMC interface standard, the eMMC interface standard, the UFS interface standard, the Advanced Technology Attachment (ATA) standard, the Serial ATA (SATA) standard, the Peripheral Component Interconnect Express (PCI-E) standard, the Parallel Advanced Technology Attachment (PATA) standard, etc.), and may communicate with the host device 50 according to the specific communication standard.

[0040] Generally speaking, the host device 50 may indirectly access the NV memory 120 by transmitting a host command and a corresponding logical address to the memory controller 110. The memory controller 110 receives the host command and the logical address, and translates the logical address into a physical address, and translates the host command into a memory operation command (Memory Operation Command), and further controls the NV memory 120 through the memory operation command to perform a read, program, or erase operation on the memory cell or data page (Page) with the physical address. Among them, the NV memory 120 includes one or more page buffers 121 (which can be implemented by SRAM), and one or more control circuits 123. What the memory controller 110 wants to write to the NV memory 120 will be written to the page buffer 121, and the one or more control circuits 123 read, write, or erase data according to the memory operation command sent by the memory controller 110. Address. When the memory controller 110 performs an erase operation on any NV memory element 122_k among the plurality of NV memory elements 122_1 - 122_N, at least one block in the NV memory element 122_k may be erased. Furthermore, each block of the NV memory element 122_k may include multiple pages, and access operations (e.g., read or write) may be performed on one or more pages.

[0041] In one embodiment, each of the NV memory elements 122_1-122_N may be an NV memory die or chip. Each NV memory die 122_1-122_N has control circuitry for executing memory operation commands issued by the memory controller 110. Furthermore, each NV memory die 122_1-122_N may include multiple planes. Each plane may have multiple blocks of memory cells and associated column and row control circuitry. The memory cells in each plane may be arranged in a two-dimensional or three-dimensional memory structure. Furthermore, various processing operations can be performed simultaneously on different planes using multi-plane operation commands. For example, multiple operations can be performed in parallel (simultaneously) on memory blocks in different planes to perform multi-plane (e.g., read, write, erase) operations. Furthermore, in one embodiment, the memory controller 110 may combine the memory blocks in the NV memory 120 into multiple super blocks. In one embodiment, the composition of the super blocks may span the NV memory chips 122_1-122_N. Furthermore, the super block may be used as one or more storage blocks in each of the NV memory chips 122_1 ˜ 122_N.

[0042] In one embodiment of the present invention, a logical-to-physical (L2P) address mapping table, which is composed of a plurality of L2P address mapping entries, can be divided into a plurality of mapping groups, each of which includes a portion of the mapping entries in the L2P address mapping table to perform logical-to-physical address conversion. These mapping groups are permanently stored in blocks of the NV memory 120 and loaded into the internal memory 113 when needed. Similarly, a physical-to-logical (P2L) address mapping table, which is composed of a plurality of P2L address mapping entries, can be divided into a plurality of mapping groups, each of which includes a portion of the mapping entries in the P2L address mapping table to perform physical-to-logical address conversion. These mapping groups are permanently stored in blocks of the NV memory 120 and loaded into the internal memory 113 when needed.

[0043] In the present invention, data stored in the NV memory 120 is protected by ECC checking and correction, as well as RAID-style checking and correction, performed on the data by the ECC processing circuit 130 and the RAID processing circuit 140. Specifically, the ECC processing circuit 130 can perform ECC encoding on the original data sent by the host device 50 based on the low-density parity-check code (LDPC code) architecture during data writing, and generate a codeword containing ECC check data. The codeword is then written to the NV memory 120 as the stored data. Furthermore, when reading data, the ECC processing circuit 130 performs an ECC check operation to perform ECC decoding on the data read from the NV memory 120, returning the correct data to the host device 50. Furthermore, the RAID processing circuit 140 performs RAID encoding (which may be based on an exclusive-OR operation) on a certain number of stored data (i.e., codewords generated by ECC encoding) in the NV memory 120, thereby generating RAID check data corresponding to the stored data. Generally, when the ECC processing circuit 130 cannot correct an error through the ECC check data in the codeword, the RAID processing circuit 140 can correct the error through the RAID check data. Please refer to the following for further information. Figure 2A and Figure 2B Description.

[0044] Figure 2A and Figure 2BThis is a schematic diagram of the RAID check mechanism used in an embodiment of the present invention. In the following description, the NV memory 120 is assumed to be a dual-channel memory, including channel 0 and channel 1. The NV memory elements 122_1 and 122_2 in the NV memory 120 are connected to one of the channels 0 and 1, respectively. The NV memory elements 122_1 and 122_2 on each channel have 4 planes, namely plane 0 to plane 3, and each plane has 8 pages. Figure 2A In the example, page data 0 to page data 59 are respectively stored in pages of plane 0 to plane 3 of channel 0 and channel 1, and page data 0 to page data 59 can respectively correspond to one or more code words generated by ECC encoding. In addition, RAID check data RP0 to RP3 for protecting page data 0 to page data 59 are also stored in pages of plane 0 to plane 3 of channel 0 and channel 1. RAID check data RP0 is generated by performing RAID check data encoding on page data 0 to page data 7 and page data 16 to page data 22 (for example, performing mutually exclusive operations on page data 0 to page data 7 and page data 16 to page data 22), and can be used to check and correct errors in page data 0 to page data 7 and page data 16 to page data 22; RAID check data RP1 is generated by performing RAID check data encoding on page data 8 to page data 15 and page data 23 to page data 29, and can be used to check and correct errors in page data 8 to page data 15 and page data The RAID check data RP3 is generated by encoding page data 30 to page data 37 and page data 46 to page data 52 through RAID check data, and can be used to check and correct errors in page data 30 to page data 37 and page data 46 to page data 52; the RAID check data RP3 is generated by encoding page data 38 to page data 45 and page data 53 to page data 59 through RAID check data, and can be used to check and recover errors in page data 38 to page data 45 and page data 53 to page data 59.

[0045] exist Figure 2BIn this example, data pages 0 through 34 are stored in Plane 0 through Plane 3 of Channel 0 and Channel 1, respectively. Each of these data pages 0 through 34 corresponds to one or more codewords generated by ECC encoding. Furthermore, RAID parity data RP0 through RP4, used to protect data pages 0 through 34, are also stored in Plane 0 through Plane 3 of Channel 0 and Channel 1. The RAID check data RP0 is generated by performing RAID check data encoding on page data 0 to page data 6, and can be used to check and correct errors in page data 0 to page data 6; the RAID check data RP1 is generated by performing RAID check data encoding on page data 7 to page data 13, and can be used to check and correct errors in page data 7 to page data 13; the RAID check data RP2 is generated by performing RAID check data encoding on page data 14 to page data 20, and can be used to check and correct errors in page data 14 to page data 20; the RAID check data RP3 is generated by performing RAID check data encoding on page data 21 to page data 27, and can be used to check and correct errors in page data 21 to page data 27; the RAID check data RP4 is generated by performing RAID check data encoding on page data 28 to page data 34, and can be used to check and correct errors in page data 28 to page data 34.

[0046] Note that while the name RAID might imply that the RAID parity data is stored in a redundant flash memory chip or die, this is not required. In some cases, redundant planes, redundant blocks, or redundant pages may be used to store the RAID parity data.

[0047] In the present invention, when the memory controller 110 performs a read operation based on a host command sent by the host device 50, the data is read from the NV memory 120. At this time, the memory controller 110 performs error detection on the read data. When an error is found, the memory controller 110 starts the error handling process of the present invention to improve data protection. Figure 3, which illustrates an error handling process for a read operation according to an embodiment of the present invention. First, in step S101, the memory controller 110 detects a decoding error in the read data. In one embodiment, the decoding error can be a hard decoding error or a soft decoding error occurring when the ECC processing circuit 130 performs an ECC check operation, or a decoding error occurring when the RAID processing circuit 140 performs a RAID check operation. In one embodiment, when the memory controller 110 reads data from the NV memory 120, the ECC processing circuit 130 performs an ECC check operation. If the hard decoding of the ECC check operation cannot correct the error, soft decoding is performed. If the soft decoding of the ECC check operation still cannot correct the error, the RAID processing circuit 140 performs a RAID check operation to correct the error. In various embodiments of the present invention, a hard decoding error, a soft decoding error, or a decoding error in the ECC check operation may trigger the error handling process of the present invention (regardless of whether the erroneous data is successfully corrected).

[0048] When one of the above-mentioned decoding errors is detected, the process enters step S102 to start a read error handling process, which will be performed during the period when the memory processing 110 processes the host command of the host device 50 (that is, the read error handling process is running in the background). Then, the process enters step S103 to determine whether the read data where the decoding error occurred is located in an in-use storage space. In one embodiment, the in-use storage space can be an in-use storage bank (active bank) of a super block. That is, the space currently used to write data in the NV memory 120. Please refer to Figure 4 The block write strategy of an embodiment of the present invention is shown. Figure 4As shown, in this embodiment of the present invention, each super block SB_0-SB_K is divided into multiple banks BANK_0-BANK_M. When performing a data write operation, the memory controller 110 opens a super block (e.g., super block SB_0) from super blocks SB_0-SB_K and begins writing data from bank BANK_0 within super block SB_0. When bank BANK_0 is full, bank BANK_0 is closed. The memory controller 110 then writes data to the next bank BANK_1, and so on. When bank BANK_M within super block SB_0 is full, super block SB_0 is closed, and the memory controller 110 opens a new (empty) super block for data writing. During this process, the bank currently being used to write data is referred to as the active bank. Furthermore, in one embodiment, space in a bank is allocated for writing RAID parity data and all data protected by the RAID parity data. For example, the storage bank BANK_0 of super block SB_0 can be configured to write the RAID parity data RP0 and the protected pages 0 to 7 and 16 to 22 as shown in FIG2 . The storage bank BANK_1 of super block SB_0 can be configured to write the RAID parity data RP1 and the protected pages 8 to 15 and 23 to 29, and so on.

[0049] In step S103, the memory controller 110 determines whether the read data with the decoding error is located in an in-use storage space (determined based on the physical address of the read data with the decoding error). In the aforementioned write strategy, the in-use storage space may be an in-use repository. If the read data with the decoding error is not located in the in-use repository, the process proceeds to step S104, entering the data migration phase. If not, the process proceeds to step S105. In step S105, the memory controller 110 determines whether to enter an idle state. For example, when there are no pending host read or write commands, the memory controller 110 may enter an idle state. If it is determined that the idle state is about to be entered, even if the read data with the decoding error is still located in the in-use storage space (e.g., in-use repository), the memory controller 110 writes dummy data into the remaining available space of the in-use storage space (e.g., in-use repository), thereby filling the in-use storage space with data and closing it, and proceeding to step S104. On the other hand, if the memory controller 110 determines that the memory controller 110 has not entered the idle state, the process returns to step S103 to continuously observe whether the read data with the decoding error is still in the used storage space.

[0050] In step S104, the migration phase begins, wherein the memory controller 110 determines unstable data that is at risk of corruption. That is, the data stored in the same RAID parity data as the read data that has a decoding error. Furthermore, the protection capability of a single RAID parity data is limited. When a decoding error has occurred in a piece of storage data it protects, this means that when errors occur in other storage data, the RAID parity data may not be able to correct them. Figure 2A Taking the RAID parity mechanism shown in FIG. 1 as an example, when a decoding error occurs in page data 3, the memory controller 110 determines that page data 0-7 and page data 16-22 corresponding to the RAID parity data RP0 are at risk of being uncorrectable and are therefore unstable data. Therefore, in step S104, the memory controller 110 determines the unstable data associated with the same RAID parity data based on the physical address of the read data where the decoding error occurred. In step S106, the memory controller 110 determines the logical address, such as the logical block address (LBA), corresponding to each piece of unstable data (e.g., each piece of page data 0-7 and page data 16-22). In one embodiment, the memory controller 110 can calculate the host block number (HBlock No.) and host page number (HPage No.) corresponding to each piece of unstable data in step S106 to facilitate access to the address mapping table in subsequent processes. For example, logical block address 0 may correspond to host block number 0 (HBlock 0) and host page number 0 (HPage 0), and logical block address 1 may correspond to host block number 0 (HBlock 0) and host page number 1 (HPage 1).

[0051] In step S107, the memory controller 110 determines whether each piece of data in the unstable data is valid data, for example, whether there is data at other addresses corresponding to the same logical address as the piece of data. If it is not valid data, it will be excluded from the subsequent data transfer operation. If it is valid data, it will be moved to a target storage space in the NV memory 120 in the subsequent data transfer operation. In one embodiment, step S107 further includes the following steps: Figure 4The sub-steps shown are used to check whether each piece of unstable data is valid. First, in step S1071, the memory controller 110 checks the cached flash-to-host (F2H) address mapping table in the internal memory 113 to confirm whether there is an entry corresponding to the unstable data in the F2H address mapping table. The F2H address mapping table is dynamically maintained, and entries are indexed by physical addresses and labeled with corresponding logical addresses. If the F2H address mapping table loaded into the internal memory 113 contains an entry corresponding to the unstable data and points to the unstable data, it indicates that the unstable data is the latest data and is considered valid data, and the process proceeds to step S1073. If the F2H address mapping table cached in the internal memory 113 contains an entry corresponding to the unstable data, but the entry does not point to the unstable data (for example, multiple entries point to the same logical address, and the entry is not the latest entry), it indicates that the unstable data is old data and is considered invalid. If the F2H address mapping table temporarily stored in the internal memory 113 does not have an entry corresponding to the unstable data, the process proceeds to step S1072. In step S1072, the memory controller 110 checks a host to flash memory (H2F) address mapping table stored in the NV memory 120 to confirm whether the unstable data is valid data. The H2F address mapping table provides a global mapping information query mechanism indexed by a logical address. The memory controller 110 can confirm whether the logical address of the unstable data points to the physical address of the unstable data by querying the H2F address mapping table. If so, it means that the unstable data is the latest data and is considered valid data, and the process proceeds to step S1073; if not, the unstable data is old data and is considered invalid data. In step S1073, the relevant data of the unstable data is recorded (only when the unstable data is valid data).

[0052] Please continue back Figure 3Through the above-mentioned step S107, the memory controller 110 excludes invalid data from all unstable data, and uses the valid unstable data as the data to be moved. Accordingly, step S108 performs a data movement operation according to the physical address of the data to be moved recorded in step S107. This includes: reading the data to be moved according to the recorded physical address of the data to be moved, and writing the read data to be moved to a target storage space in the NV memory 120. In one embodiment, the target storage space may be a repository of a super block. For example, if the data to be moved is located in the repository BANK_2 of the super block SB_4, the target storage space may be the repository BANK_3, BANK_4... However, in other embodiments of the present invention, the target storage space may be other blocks or other super blocks in the NV memory 120. Furthermore, when transferring the read data that has a decoding error (if the read data is valid data), it is corrected by the ECC processing circuit 130 or the RAID processing circuit 140, and the corrected read data is transferred. In one embodiment, if the ECC processing circuit 130 or the RAID processing circuit 140 cannot correct the read data that has a decoding error, the memory controller 110 may choose whether to transfer the read data. In step S109, the F2H address mapping table cached in the internal memory 113 is updated based on the physical address of the data to be transferred written in step S108 and its corresponding logical address. This includes updating the block number (HBlock) and page number (HPage) of the data to be transferred to the F2H address mapping table. Furthermore, at a specific time point, the H2F address mapping table in the NV memory 120 is updated based on the F2H address mapping table cached in the internal memory 113.

[0053] In one embodiment of the present invention, when the memory controller 110 performs a write operation based on a host command sent by the host device 50, the data is programmed into the NV memory 120. At this time, the memory controller 110 determines whether a program fail occurs based on the message returned by the NV memory 120. When an error is found, the memory controller 110 will initiate the error handling process of the present invention to enhance data protection. Figure 6, which illustrates an error handling process for programming operations in an embodiment of the present invention. First, in step S201, the memory controller 110 detects a programming error in a write data. Then, the process enters step S202 to start a programming error handling process, which will be performed while the memory controller 110 processes the host command of the host device 50 (that is, the programming error handling process is running in the background). Then, the process enters step S203 to determine whether the write data where the programming error occurred is located in a storage space in use. In one embodiment, the storage unit group in use can be a storage library in use of a super block (please refer to Figure 4 Intra-block write strategy as shown).

[0054] In step S203, the memory controller 110 determines whether the write data that has a programming error is located in an in-use storage space (determined based on the physical address of the write data that has a programming error). If the write data that has a programming error is not located in the in-use storage, the process proceeds to step S204 and enters the data migration phase. If not, the process proceeds to step S205. In step S205, the memory controller 110 determines whether it has entered an idle state. If it is determined that it is about to enter an idle state, even if the write data that has a programming error is still located in the in-use storage space (e.g., in-use storage), the memory controller 110 will fill the remaining available space of the in-use storage space (e.g., in-use storage) with dummy data, thereby causing the in-use storage space to be filled with data and closed, and then proceeding to step S204. On the other hand, if the memory controller 110 determines that it has not entered an idle state, the process returns to step S203 and continues to observe whether the write data that has a programming error is still located in the in-use storage space.

[0055] In step S204, the memory controller 110 determines unstable data at risk of corruption, i.e., stored data associated with the same RAID parity data as the write data that experienced the programming error. Therefore, in step S204, the memory controller 110 determines the unstable data associated with the same RAID parity data based on the physical address of the write data that experienced the programming error. In step S206, the memory controller 110 determines the logical address, such as the logical block address, corresponding to each piece of unstable data. In one embodiment, the memory controller 110 may calculate the host block number (HBlock No.) and host page number (HPage No.) corresponding to each piece of unstable data in step S206 to facilitate access to the address mapping table in subsequent processes.

[0056] In step S207, the memory controller 110 determines whether each piece of data in the unstable data is valid data, for example, whether there is data at other addresses corresponding to the same logical address as the data. If it is not valid data, it will be excluded from the subsequent data transfer operation. If it is valid data, it will be moved to a target storage space in the NV memory 120 in the subsequent data transfer operation. In one embodiment, step S207 further includes a similar Figure 4 The sub-steps shown are used to check whether each unstable data is valid data (repeated description is omitted here). Through the above-mentioned step S207, the memory controller 110 eliminates invalid data from all unstable data and uses the valid unstable data as the data to be moved. Accordingly, step S208 performs a data migration operation according to the physical address of the data to be moved recorded in step S207. This includes: reading the data to be moved according to the recorded physical address of the data to be moved, and writing the read data to be moved to a target storage space in the NV memory 120. In one embodiment, the target storage space can be a storage library of a super block. In other embodiments, the target storage space can be another block or other super block in the NV memory 120. When migrating the written data that has a programming error (if the written data is valid data), it will also be corrected to correct data through the ECC processing circuit 130 or the RAID processing circuit 140. In one embodiment, if the ECC processing circuit 130 or the RAID processing circuit 140 cannot correct the written data that has a programming error, the memory controller 110 may choose whether to move the written data. In step S209, the F2H address mapping table cached in the internal memory 113 is updated based on the physical address of the data to be moved written in step S208 and its corresponding logical address. This includes updating the block number (HBlock) and page number (HPage) of the data to be moved to the F2H address mapping table. Furthermore, at a specific time point, the H2F address mapping table stored in the NV memory 120 is updated based on the F2H address mapping table cached in the internal memory 113.

[0057] According to the read error handling process and the program error handling process of the aforementioned embodiments, an error handling method of the present invention can be summarized as follows: Figure 7 The simplified processing flow shown includes the following steps:

[0058] S310: In response to a read data having a decoding error or a write data having a programming error, determining a verification data corresponding to the read data or the write data;

[0059] S320: Selecting a plurality of data to be moved from the flash memory according to the verification data; and

[0060] S330: Execute a data migration operation to migrate the plurality of data to be migrated to a target storage space in the flash memory.

[0061] Since the principles and specific details of the above steps have been described in detail in the previous embodiment, they will not be repeated here. It is worth noting that the above process can be further improved by adding additional steps or making appropriate modifications and adjustments to improve the efficiency and effectiveness of error handling, thereby further improving the read and write performance, reliability and data integrity of the data storage device.

[0062] The embodiments of the present invention may be specifically implemented as an apparatus, a method or a computer program product. Accordingly, the embodiments of the present invention may take the form of an entity implemented entirely by hardware, an entity implemented entirely by software (including firmware, resident software, microcode, etc.), or an entity combining software and hardware aspects, which may be generally referred to as a "module" or "system". In addition, the embodiments of the present invention may take the form of a computer program product embodied in any tangible expression medium, and the medium has a computer-usable program code embodied in the medium. In terms of hardware, the present invention may be implemented by applying any of the following technologies or related combinations: separate operating logic of logic gates capable of executing logic functions based on data signals, and application specific integrated circuits (ASICs), programmable gate arrays (PGAs) or field programmable gate arrays (FPGAs) with appropriate combinational logic.

[0063] The flowcharts and block diagrams illustrate the architecture, functionality, and operation of the systems, methods, and computer program products of various possible implementations of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of program code, including one or more executable instructions, to implement a specific logic function. It should also be noted that each block in the block diagram and / or flowchart, as well as combinations of blocks in the block diagram and / or flowchart, can be implemented by a special-purpose hardware-based system, or a combination of special hardware and computer program instructions. These computer program instructions can be stored in a readable computer medium to instruct a computer or other programmable data processing device to operate in a specific manner so that the instructions stored in the readable computer medium generate functions / operations specified in the blocks or combinations of blocks that implement the flowchart and / or block diagram.

[0064] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A method for error handling in a flash memory, comprising: In response to a read data having a decoding error or a write data having a programming error, determining a check data corresponding to the read data or the write data; Selecting a plurality of data to be moved from the flash memory according to the verification data; and A data migration operation is performed to migrate the plurality of data to be migrated to a target storage space in the flash memory.

2. The error handling method according to claim 1, wherein: The check data is check data of a fault-tolerant redundant array of independent disks (RAID), and the RAID check data is generated by performing an exclusive OR operation on the stored data and one or more stored data in the flash memory, or the RAID check data is generated by performing an exclusive OR operation on the written data and one or more stored data in the flash memory.

3. The error handling method according to claim 1, wherein: The steps for selecting the multiple data to be moved include: The plurality of data to be moved is determined according to one or more stored data associated with the verification data in the flash memory.

4. The error handling method according to claim 3, wherein: The steps for selecting the multiple data to be moved include: For each piece of stored data in the one or more pieces of stored data associated with the verification data: Determining whether the stored data is valid data according to a logical address of the stored data; as well as If the stored data is valid data, the data is used as one of the multiple data to be moved.

5. The error handling method according to claim 4, wherein: The steps to determine whether the stored data is valid include: Checking a flash memory to host address mapping table to determine whether the stored data has a corresponding entry in the flash memory to host address mapping table; If the stored data has a corresponding entry in the flash memory to host address mapping table, determining whether the stored data is valid data according to the flash memory to host address mapping table; as well as If the stored data has no corresponding entry in the flash memory to host address mapping table, whether the stored data is valid data is determined according to a host to flash memory address mapping table.

6. The error handling method according to claim 1, wherein: Also includes: determining whether the read data having a decoding error or the write data having a programming error is located in a used storage space of the flash memory; If the read data that has a decoding error or the write data that has a programming error is located in the used storage space, the data move operation is not performed; as well as If the read data that has a decoding error or the write data that has a programming error is not located in the used storage space, the data migration operation is performed.

7. The error handling method according to claim 6, wherein: Also includes: If the read data with a decoding error or the write data with a programming error is located in the in-use storage space and the flash memory is about to enter an idle state, write dummy data into the remaining available storage space in the in-use storage space; and After writing the dummy data, the data migration operation is performed.

8. The error handling method according to claim 6, wherein: The in-use storage space is an in-use storage bank among a plurality of storage banks of a super block in the flash memory, and the target storage space is one of the plurality of storage banks of the super block that is different from the in-use storage bank.

9. The error handling method according to claim 8, wherein: Each of the plurality of storage libraries is used to store the verification data and one or more storage data associated with the verification data.

10. The error handling method according to claim 1, wherein: The decoding error is one of a hard decoding error of an error correction code (ECC) check operation, a soft decoding error of an ECC check operation, and a decoding error of a RAID check operation.

11. A memory controller for a flash memory, comprising: a storage unit for storing a program code; A processing unit, configured to execute the program code to perform error processing on the flash memory, comprising: In response to a read data having a decoding error or a write data having a programming error, determining a check data corresponding to the read data or the write data; Selecting a plurality of data to be moved from the flash memory according to the verification data; and A data migration operation is performed to migrate the plurality of data to be migrated to a target storage space in the flash memory.

12. The memory controller according to claim 11, wherein: The check data is check data of a fault-tolerant redundant array of independent disks (RAID), and the RAID check data is generated by the memory controller performing an exclusive OR operation on the storage data and one or more storage data, or the RAID check data is generated by the memory controller performing an exclusive OR operation on the write data and one or more storage data.

13. The memory controller according to claim 11, wherein: The memory controller performs the following operations: The plurality of data to be moved are selected according to one or more stored data associated with the verification data in the flash memory.

14. The memory controller according to claim 13, wherein: The memory controller performs the following operations: For each piece of stored data in the one or more pieces of stored data associated with the verification data: Determining whether the stored data is valid data according to a logical address of the stored data; as well as If the stored data is valid data, the data is used as one of the multiple data to be moved.

15. The memory controller according to claim 14, wherein: The memory controller performs the following operations: Checking a flash memory to host address mapping table to determine whether the stored data has a corresponding entry in the flash memory to host address mapping table; If the stored data has a corresponding entry in the flash memory to host address mapping table, determining whether the stored data is valid data according to the flash memory to host address mapping table; as well as If the stored data has no corresponding entry in the flash memory to host address mapping table, whether the stored data is valid data is determined according to a host to flash memory address mapping table.

16. The memory controller according to claim 11, wherein: The memory controller performs the following operations: determining whether the read data having a decoding error or the write data having a programming error is located in a used storage space of the flash memory; If the read data that has a decoding error or the write data that has a programming error is located in the used storage space, the data move operation is not performed; as well as If the read data that has a decoding error or the write data that has a programming error is not located in the used storage space, the data migration operation is performed.

17. The memory controller according to claim 16, wherein: The memory controller performs the following operations: If the read data with a decoding error or the write data with a programming error is located in the in-use storage space and the memory controller is about to enter an idle state, write dummy data into the remaining available storage space in the in-use storage space; and After writing the dummy data, the data migration operation is performed.

18. The memory controller according to claim 16, wherein: The in-use storage space is an in-use storage bank among a plurality of storage banks of a super block in the flash memory, and the target storage space is one of the plurality of storage banks of the super block that is different from the in-use storage bank.

19. The memory controller according to claim 18, wherein: Each of the plurality of storage libraries is used for storing a verification data and one or more storage data protected by the verification data.

20. The memory controller according to claim 11, wherein The decoding error is one of a hard decoding error of an error correction code (ECC) check operation, a soft decoding error of an ECC check operation, and a decoding error of a RAID check operation.

21. A data storage device comprising the memory controller according to claim 11 and a flash memory.

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