Memory system including firmware and method of operating same

Abstract

The invention relates to a memory system including firmware and a method of operating the same. The memory system includes: a memory device including firmware distributed and stored at a plurality of locations; and a controller configured to read the firmware from a different position selected from among the plurality of positions each time the firmware is loaded.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the benefit of priority from Korean Patent Application No. 10-2024-0028691, filed on February 28, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to a memory system, and more particularly, to an apparatus and operating method for improving security, maintenance, or management of firmware included in the memory system. Background Art

[0004] A data processing system including a memory system or data storage device can store greater amounts of data in the data storage device and can store data in the data storage device more quickly. Memory systems have been developed to more quickly output data stored in the data storage device. The data storage device may include non-volatile memory cells and / or volatile memory cells for storing data. Furthermore, the memory system may include firmware for controlling the operation of internal components and maintaining or managing the performance of the memory system. Firmware maintenance and management may affect the performance and durability of the memory system. Summary of the Invention

[0005] Embodiments of the present disclosure may provide a memory device, a memory system including the memory device, or a data processing apparatus including the memory system.

[0006] Embodiments of the present disclosure may provide a device and operating method that improves the reliability of a storage area or storage region allocated for storing firmware within a memory device, or improves the operational security of a memory device or memory system. The device or operating method may access the memory device to reduce variations in the operational status of multiple locations storing firmware.

[0007] In addition, embodiments of the present disclosure can improve the performance of a memory device or memory system by changing the device and operating method of the access location for reading or loading firmware to reduce the deviation of stress or interference that may occur during a read operation in an area where firmware is stored.

[0008] In an embodiment of the present disclosure, a memory system may include a memory device including firmware distributed and stored in a plurality of locations; and a controller configured to read the firmware from a different location selected from among the plurality of locations whenever the firmware is loaded.

[0009] The controller may be configured to read the firmware from a second location among the plurality of locations at a second time after reading the firmware from a first location among the plurality of locations at a first time, wherein stress or interference occurs due to the read operation performed at the first location.

[0010] In a memory system, a first page included in a first location and a second page included in a second location respectively include memory cells coupled to the same word line.

[0011] Memory cells included in the first page and the second page may be provided on the same memory layer.

[0012] The controller may be configured to, after power is supplied, select a location having at least one of a lowest read count and a lowest program / erase cycle from among the plurality of locations and load the firmware stored in the selected location.

[0013] In a memory system, each of the plurality of locations may include a plurality of pages contained in different memory blocks or different memory planes. The plurality of pages may be contiguous pages.

[0014] The controller may be configured to read firmware comprising several portions stored in a plurality of pages, each portion stored in a different memory block or a different memory plane.

[0015] The controller may be configured to read a first portion of the firmware from a first memory plane in the memory device and read a second portion different from the first portion from a second memory plane in the memory device.

[0016] The controller may be further configured to: generate or update at least one of a read count or a program / erase cycle for at least one memory block, at least one memory plane, or at least one memory page associated with a plurality of locations; and store the generated or updated read count or at least one of the program / erase cycles in the memory device.

[0017] The controller may be further configured to select access locations of the firmware such that a deviation of at least one of a read count and a program / erase cycle for each of the plurality of locations is reduced.

[0018] In another embodiment of the present disclosure, a controller may be coupled to a memory device, wherein firmware is copied and stored at multiple locations in the memory device. The controller may include at least one processor and at least one memory. The controller may be configured to: load the firmware stored at a selected location among the multiple locations; when loading the firmware from the selected location, estimate another location among the multiple locations where stress or interference occurs; and designate the estimated location as the selected location for the next firmware load.

[0019] The controller may be further configured to: compare at least one of a read count and program / erase cycles of each of the plurality of locations; and designate a location having a lowest at least one of the read count and program / erase cycles among the plurality of locations as the selected location.

[0020] Each of the plurality of locations may include a plurality of pages contained in different memory blocks or different memory planes.

[0021] The controller may be configured to read firmware comprising several portions stored in a plurality of pages, each portion stored in a different memory block or a different memory plane.

[0022] The controller may be further configured to: generate or update at least one of a read count and a program / erase cycle in each memory block, each memory plane, or each memory page associated with a plurality of locations; and store the generated or updated read count and at least one of the program / erase cycles in the memory device.

[0023] The controller may be further configured to select access locations of the firmware such that a deviation of at least one of a read count and a program / erase cycle for each of the plurality of locations is reduced.

[0024] In another embodiment of the present disclosure, a method of operating a memory system may include: selecting at least one of a plurality of locations in a memory device, the plurality of locations storing firmware; loading the firmware stored at the selected location among the plurality of locations; when loading the firmware from the selected location, estimating another location among the plurality of locations where stress or interference occurs; and designating the estimated location as the selected location for loading the firmware next time.

[0025] The method may further include comparing at least one of a read count and program / erase cycles for each of the plurality of locations; and designating a location having a lowest at least one of the read count and program / erase cycles among the plurality of locations as a selected location.

[0026] The method may further include selecting access locations of the firmware such that a deviation of at least one of a read count and a program / erase cycle for each of the plurality of locations is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The description herein refers to the drawings, wherein like reference numerals refer to like parts throughout.

[0028] Figure 1 is a block diagram describing an apparatus for controlling firmware in a memory system according to an embodiment of the present disclosure.

[0029] Figure 2is a diagram describing a data structure used in a memory system according to an embodiment of the present disclosure.

[0030] Figure 3 A memory device according to another embodiment of the present disclosure is shown.

[0031] Figure 4 A memory cell array according to another embodiment of the present disclosure is shown.

[0032] Figure 5 A cell array structure according to an embodiment of the present disclosure is shown.

[0033] Figure 6 A cell array structure according to an embodiment of the present disclosure is shown.

[0034] Figure 7 An apparatus for managing status information about a firmware storage location according to an embodiment of the present disclosure is described.

[0035] Figure 8 A firmware loading method according to an embodiment of the present disclosure is described.

[0036] Figure 9 A firmware access method according to an embodiment of the present disclosure is described.

[0037] Figure 10 A firmware loading method according to an embodiment of the present disclosure is described.

[0038] Figure 11 A firmware management method according to an embodiment of the present disclosure is described.

[0039] Figure 12 A data processing system according to another embodiment of the present disclosure is shown.

[0040] Figure 13 A memory system according to another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0041] Various embodiments of the present disclosure are described below in conjunction with the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any disclosed embodiment.

[0042] In the present disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “an embodiment,” “another embodiment,” “some embodiments,” “multiple embodiments,” “other embodiments,” “optional embodiments,” etc., are intended to indicate that any such features are included in one or more embodiments of the present disclosure, but may or may not be combined in the same embodiment.

[0043] In this disclosure, the terms "comprises," "comprising," "having," and "containing" are open-ended. As used in the appended claims, these terms specify the presence of stated elements but do not preclude the presence or addition of one or more other elements. The terms in the claims do not preclude the device from including additional components, such as interface units, circuits, etc.

[0044] Throughout this disclosure, various units, circuits, or other components may be described or claimed to be "configured to" perform one or more tasks. In such contexts, "configured to" is used to refer to a structure by indicating that the block / unit / circuit / component includes a structure (e.g., circuitry) that performs one or more tasks during operation. Thus, a given block / unit / circuit / component can be said to be configured to perform a task even when the block / unit / circuit / component is not currently operating, e.g., not turned on or activated. Examples of blocks / units / circuit / components used with the "configured to" language include hardware, circuitry, memory storing program instructions executable to perform an operation, and the like. Furthermore, "configured to" can include general-purpose structures, such as general-purpose circuitry, manipulated by software and / or firmware, such as an FPGA or general-purpose processor executing software in a manner capable of performing the associated tasks. "Configured to" can also include adapting a manufacturing process, such as a semiconductor manufacturing facility, to produce a device, such as an integrated circuit, suitable for implementing or performing one or more tasks.

[0045] As used in this disclosure, the terms "machine," "circuit," or "logic" refer to all of the following: (a) pure hardware circuit implementations, such as implementations of analog and / or digital circuitry only; and (b) combinations of circuitry with software and / or firmware, such as, as applicable: (i) a combination of processors or (ii) portions of processors / software, including a digital signal processor, software, and memory, that work together to enable a device such as a mobile phone or server to perform various functions; and (c) circuitry, such as a microprocessor or portion of a microprocessor, that requires software or firmware to function, even if the software or firmware is not physically present. The definitions of "machine," "circuit," or "logic" apply to all uses of this term in this application, including in any claims. As a further example, as used in this application, the terms "machine," "circuit," or "logic" also encompass implementations of only one processor or multiple processors or portions of processors and their accompanying software and / or firmware. The terms "machine," "circuit," or "logic" also encompass, for example, integrated circuits for memory devices, if applicable to a particular claim element.

[0046] As used herein, the terms "first," "second," "third," etc., are used as labels for the nouns preceding them and do not indicate any type of ordering, such as spatial, temporal, or logical. The terms "first" and "second" do not necessarily mean that the first value must be written before the second value. Furthermore, while these terms may be used herein to identify various components, these components are not limited by these terms. These terms are used to distinguish one component from another component that otherwise has the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0047] Furthermore, the term "based on" is used to describe one or more factors that influence a determination. This term does not exclude additional factors that may influence the determination. That is, the determination may be based solely on these factors, or at least in part on these factors. Consider the phrase "A is determined based on B." While in this case, B is a factor that influences the determination of A, such a phrase does not exclude that the determination of A is also based on C. In other cases, A may be determined solely based on B.

[0048] These and other features and advantages of the present invention will become apparent from the detailed description of the embodiments of the present disclosure and the accompanying drawings.The embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals refer to like elements.

[0049] Figure 1 1 is a block diagram illustrating a device for controlling firmware in the memory system 110 according to an embodiment of the present disclosure. Figure 1 In the embodiment of the present disclosure, the memory system 110 may include a controller 130 and a memory device 150. The memory system 110 may be coupled to another device, for example, a computing device.

[0050] The controller 130 may include at least one processor and at least one memory. The memory device 150 may be coupled to the controller 130 via at least one data path 42 and may include a plurality of unit memory cells, each unit memory cell being capable of storing at least one bit of data. For example, the memory device 150 may be a non-volatile memory including at least one die and may include a plurality of memory blocks including a plurality of memory cells.

[0051] The memory device 150 may include a system area 50_1 and a user data area 50_2. The system area 50_1 may store multiple firmware copies 40_1, 40_2, 40_3, 40_N. The user data area 50_2 may include at least one user data block 42_1, which may store data transmitted to a computing device (e.g., Figure 12 ) or from the computing device (e.g., Figure 12Representative data stored in the user data area 50_2 may include an operating system (OS), file system information, application programs, and user-requested data.

[0052] Memory device 150, comprising multiple memory blocks, can store multiple firmware copies 40_1, 40_2, 40_3, and 40_N. The firmware may include commands, programs, engines, and the like to support the basic (or fundamental) operation of memory system 110. The multiple firmware copies 40_1, 40_2, 40_3, and 40_N are identical but may be stored in different locations within memory device 150. The firmware stored in memory device 150 may be responsible for initializing the memory system. For example, the firmware may perform functions such as internal operational control, initialization, and self-diagnosis of memory system 110.

[0053] In particular, firmware can be used as low-level software to provide an interface between the hardware configuration of memory system 110 and the application-level software or operating system of a computing device connected to memory system 110. When power is supplied to memory system 110, the firmware stored in a specific location of memory device 150 can be transferred to controller 130. Controller 130 can use the firmware to perform basic operations. The firmware can be executable even when memory system 110 is initialized. For example, first firmware copy 40_1 can be stored in a fixed location in memory device 150. When power is supplied, first firmware copy 40_1 can be loaded or accessed based on a request or command issued by controller 130.

[0054] According to an embodiment, the firmware may include a boot loader. When an operating system or application program is loaded into another device (e.g., a computing device coupled to the memory system 110) and executed, the boot loader may serve as a program or command that transfers control of the memory system 110 to the other device.

[0055] The firmware described above is used to support basic operations in the memory system 110. If the firmware fails due to any of a variety of reasons, the memory system 110 may have difficulty operating normally. To avoid this, the memory device 150 may include multiple firmware copies 40_1, 40_2, 40_3, and 40_N. For example, if the first firmware copy 40_1 contains an error or fails to operate properly, the controller 130 may read or load another firmware copy from the other firmware copies 40_2, 40_3, and 40_N. In other words, the multiple firmware copies 40_1, 40_2, 40_3, and 40_N in the memory device 150 are replicated and stored in a distributed manner.

[0056] According to an embodiment, multiple firmware copies 40_1, 40_2, 40_3, and 40_N can be updated. Furthermore, the memory system 110 can store multiple firmware copies of different versions (e.g., a current version and a previous version) in the memory device 150. For example, the multiple firmware copies 40_1, 40_2, 40_3, and 40_N can include different versions of firmware. Therefore, different versions of firmware can be stored in different locations in the memory device 150.

[0057] The multiple memory blocks in the memory device 150 may be affected by various characteristics arising from the construction and operation of the non-volatile memory device. One of these characteristics is read interference. Read interference involves the phenomenon that peripheral unit memory cells are affected during the process of reading at least one unit memory cell in the block. When the unit memory cells of the block are arranged in a matrix form and multiple data are output from the unit memory cells in a specific row corresponding to the word line, the threshold voltage distribution corresponding to the data stored in the peripheral unit memory cells may change due to the voltage and current applied to the unit memory cells in the specific row. When at least one of the multiple firmware copies 40_1, 40_2, 40_3, 40_N is read or loaded, read interference may occur. Given the nature of read interference, it may be more efficient for the controller 130 to not repeatedly read or access the firmware stored in a specific location to keep the firmware copies safe and able to operate normally.

[0058] Another characteristic of the non-volatile memory cells in the multiple memory blocks of the memory device 150 is that data retention may not actually be permanent. Multiple pieces of data stored in a unit memory cell may gradually disappear or be erased over time. For example, a data entry stored in a unit memory cell of a non-volatile memory device may cause a change in the threshold voltage in the gate structure. Based on this piece of data, the controller can confine some charge to a specific layer in the gate structure. The value of this piece of data stored in the unit memory cell can be determined. However, in a natural state, the threshold voltage range may become more dispersed over time because the change may move or return to an equilibrium condition, and later, it may become difficult to specify the threshold voltage range in the unit memory cell. In this case, when the controller cannot identify the original range of the threshold voltage, the unit memory cell may lose data. The data retention of the unit memory cell related to the performance of the memory device can be characterized by retention time. As described above, considering the characteristics of read disturbance, when the controller 130 does not access any firmware copy among the multiple firmware copies 40_1, 40_2, 40_3, 40_N within the retention time, the unaccessed copies among the multiple firmware copies 40_1, 40_2, 40_3, 40_N may be lost.

[0059] In addition, a device or operating method may be provided for checking whether multiple firmware copies 40_1, 40_2, 40_3, and 40_N are normally operable. Considering the characteristics of read disturbance, accessing or reading multiple firmware copies 40_1, 40_2, 40_3, and 40_N may not be desirable. However, considering the characteristics of data retention, multiple firmware copies 40_1, 40_2, 40_3, and 40_N should be read or accessed. How the controller 130 reads or accesses the multiple firmware copies 40_1, 40_2, 40_3, and 40_N may have a complementary relationship, reflecting the characteristics of read disturbance and data retention.

[0060] Based on operational information about the multiple locations storing the multiple firmware copies 40_1, 40_2, 40_3, and 40_N, the controller 130 can estimate the service life or health status of the multiple firmware copies 40_1, 40_2, 40_3, and 40_N stored in those locations. Unit memory cells of non-volatile memory have a preset service life. Repeatedly programming and erasing data into and out of the programmed data may cause minor damage to the unit memory cells. In the memory device 150, data programming operations can be performed on a page basis, while data erasing operations can be performed on a block basis. Therefore, based on erase / write cycles (E / W cycles) and / or program / erase cycles (P / E cycles), the controller 130 can estimate the service life or health status of each memory block in the memory device 150. According to an embodiment, read counts and erase / write cycle counts (E / W cycles) can be established, updated, and stored for the multiple locations storing the multiple firmware copies 40_1, 40_2, 40_3, and 40_N in the memory device 150.

[0061] In addition, according to an embodiment, when there is a large deviation in read counts and erase / write cycles (E / W cycles) for the multiple locations storing the multiple firmware copies 40_1, 40_2, 40_3, and 40_N, the operational security or confidentiality of the multiple firmware copies 40_1, 40_2, 40_3, and 40_N may vary greatly depending on the multiple locations. Therefore, the controller 130 can access, read, erase, or store the multiple firmware copies 40_1, 40_2, 40_3, and 40_N, thereby reducing the deviation in operational information for the multiple locations storing the multiple firmware copies 40_1, 40_2, 40_3, and 40_N.

[0062] Figure 2 The internal logic configuration of the memory device 150 is shown. Figure 1 The memory device 150 shown in FIG. 1 is described as a logical memory device rather than a physical component.

[0063] Specifically, the system area 50_1 may include Figure 2 The space of the system blocks such as the firmware block 48_0, the firmware backup block 48_1, etc. is shown. For example, the firmware block 48_0 and the firmware backup block 48_1 may include Figure 1 At least a portion of multiple firmware copies 40_1, 40_2, 40_3, and 40_N are shown. System area 50_1 is a physical address area accessible only using physical addresses (e.g., physical block addresses of memory device 150), rather than logical addresses used by a computing device or host. Therefore, even if the memory system including memory device 150 is associated with a computing device, a user may not be able to access system area 50_1 through the computing device. System area 50_1 may have restricted access, meaning it may only be accessible through special instructions or programs. System area 50_1 may include basic information used to identify the hardware configuration of memory system 110 or memory device 150, firmware used to support basic operations of memory system 110, and so on. Firmware may be one of the most important data stored in memory device 150. Memory system 110 can only perform normal operations if the firmware is intact. To this end, memory system 110 may store multiple firmware copies 40_1, 40_2, 40_3, and 40_N in different locations within memory device 150. Even if the first firmware copy 40_1 among the plurality of firmware copies 40_1, 40_2, 40_3, 40_N is damaged, the memory system 110 can still perform normal operations based on the other undamaged firmware copies 40_2, 40_3, 40_N.

[0064] The user data area 50_2 including user data blocks may store user data transferred from / to a computing device associated with the memory system, etc. Representative data included in the user data area 50_2 may include an operating system (OS), file system information, application programs, and the like.

[0065] The user data area 50_2 is a logical address area that can be accessed by using a logical address such as a logical block address. For example, the logical block address (LBA) used in the logical block addressing method can be a format used by a computing device or a host to specify the location of data recorded in a storage device. In the case of a conventional hard disk, an addressing method that indicates the physical structure in the hard disk (for example, cylinder, head, and sector (Cylinder-Head-Sector, CHS)) is used. However, as the storage capacity of the hard disk increases, the addressing method corresponding to the physical structure of the hard disk has reached its limit. In such a large-capacity storage device, addresses can be specified in a manner that multiple sectors are arranged in a row in a logical order and the multiple sectors are numbered (for example, in order starting from 0), regardless of the physical structure of the hard disk. Although a computing device (for example, Figure 12The host 102 (shown in FIG. 1 ) may use logical block addresses (LBAs) to communicate or point to data entries, but the memory system 110 should match and manage the computing device's logical block addresses with physical locations (e.g., physical addresses that may indicate the actual location where the data entry is stored within the memory device 150). This information for associating logical addresses with physical addresses may be included in metadata or mapping data that can be distinguished from user data entries stored or read by the host 102.

[0066] According to an embodiment, a reserved area 50_5 in the memory device 150, including at least one reserved block, can be used to store information related to the operation of the computing device or another system associated with the memory system, or can be used for other configurations embedded in the memory system. For example, an error correction code (ECC) for an ECC circuit can be stored in the reserved area 50_5.

[0067] Similar to the system area 50_1, the reserved area 50_5 is a physical address area accessible only via physical addresses (e.g., physical block addresses). The memory system 110 stores data in the reserved area 50_5 to support various operations required or necessary for the manufacturing process, the configuration or installation process on the host 102 or a computing device, or operations associated with or interfacing with the host 102 or a computing device. While the system area 50_1 is used to support basic operations of the memory system, the reserved area 50_5 can be used to expand the operations supported by the memory system.

[0068] On the other hand, depending on the embodiment, the memory device 150 may further include at least one of a host protection area (HPA) 50_3 or a device configuration overlay (DCO) 50_4. Here, the host protection area (HPA) is proposed from the technology supported by the Advanced Technology Attachment (ATA)-4 standard. The device configuration overlay (DCO) 50_4 is supported by the ATA-6 standard. ATA may include a standard technology for interfaces used in laptops or desktop computers and may be referred to as an integrated device environment (IDE) or enhanced IDE (EIDE) method.

[0069] The Host Protected Area (HPA) 50_3 is primarily used for BIOS diagnostic utilities, system startup, and system recovery. For example, the Host Protected Area (HPA) 50_3 may not be accessible through the BIOS of the host 102. In other words, it may be an area of ​​the memory system that is invisible or unavailable to the operating system (OS) and is not typically modified by the user. The Host Protected Area (HPA) 50_3 can support system recovery without the need for separate media such as CDs or DVDs.

[0070] Device Configuration Overlay (DCO) 50_4 can be used by the memory system manufacturer to adjust disk sizes. For example, each manufacturer may have storage capacities of 300GB, 500GB, 750GB, 1TB, and so on, depending on the memory system model. Device Configuration Overlay (DCO) 50_4 can be made to appear as if the memory system has multiple sizes (e.g., 60GB, 100GB, 200GB, 500GB, or 1TB), even if the memory systems are not manufactured differently based on their storage capacity. Device Configuration Overlay (DCO) 50_4 may not be accessible through the BIOS of host 102, but may be accessible through special commands defined by the manufacturer of memory system 110.

[0071] According to an embodiment, the memory system 110 may generate, update, or store operational status information corresponding to the multiple locations storing the multiple firmware copies 40_1, 40_2, 40_3, and 40_N. For example, the memory system 110 may generate, update, or store read counts, erase / write cycles (E / W cycles), or program / erase cycles (P / E cycles) for the multiple locations storing the multiple firmware copies 40_1, 40_2, 40_3, and 40_N. Furthermore, the memory system 110 may access the multiple firmware copies 40_1, 40_2, 40_3, and 40_N to reduce variations in the operational status information for the multiple locations storing the multiple firmware copies 40_1, 40_2, 40_3, and 40_N.

[0072] Although not shown, according to an embodiment, the memory device 150 may support IDE or EIDE schemes as well as Small Computer System Interface (SCSI) schemes. Regions in the memory device 150 may be allocated or allocated differently according to configurations or operation methods supported by the memory system 110.

[0073] Figure 3 1 shows a memory device according to another embodiment of the present disclosure. Specifically, Figure 3 A memory plane included in the memory device 150 or a memory cell group (eg, a cell array) included in a memory die according to an embodiment of the present disclosure is shown.

[0074] Reference Figure 3Memory device 150 may include at least one memory group 330 (i.e., a cell array 330) having a plurality of cell strings 340. Each cell string 340 may include a plurality of nonvolatile memory cells MC0 to MCn-1 connected to corresponding bit lines among a plurality of bit lines BL0 to BLm-1. Cell strings 340 are arranged in corresponding columns of memory group 330, and each cell string 340 may include at least one drain select transistor DST and at least one source select transistor SST. The nonvolatile memory cells MC0 to MCn-1 of each cell string 340 may be connected in series between the drain select transistor DST and the source select transistor SST. Each of the nonvolatile memory cells MC0 to MCn-1 may be configured as a multi-level cell (MLC), each cell storing a data item having multiple bits. Cell strings 340 may be electrically connected to corresponding bit lines among the bit lines BL0 to BLm-1.

[0075] In an embodiment, the memory bank 330 may include Figure 3 NAND flash memory cells MC0 to MCn-1 are shown. In another embodiment, memory group 330 may be implemented as a NOR flash memory, a hybrid flash memory in which at least two different types of memory cells are mixed or combined, or a single-chip NAND flash memory in which a controller is embedded in a single memory chip. In an embodiment, memory group 330 may include a flash memory cell including a charge trapping flash (CTF) layer including a conductive floating gate or an insulating layer.

[0076] According to an embodiment, Figure 3 The illustrated memory device 150 may include at least one memory block. Memory group 330 may have a two-dimensional (2D) or three-dimensional (3D) structure. For example, each of the memory blocks in memory device 150 may be implemented as a 3D structure, such as a vertical structure. Each of the memory blocks may have a three-dimensional structure extending from a first direction to a third direction (e.g., an x-axis direction, a y-axis direction, and a z-axis direction).

[0077] A memory group 330, which includes at least one memory block, can be connected to multiple bit lines BL, multiple source select lines SSL, multiple drain select lines DSL, multiple word lines WL (e.g., WL0 to WLn-1), multiple dummy word lines DWL (not shown), and multiple common source lines CSL. In some embodiments, some of the multiple word lines WL (e.g., WL0 to WLn-1) can be used as dummy word lines DWL for data security. In one embodiment, the memory group 330 can include multiple NAND strings NS, which can each correspond to a cell string 340, for example. Each NAND string NS can include multiple memory cells MC and can be connected to a corresponding bit line BL. Furthermore, the source select transistor SST of each NAND string NS can be connected to the common source line CSL, and the drain select transistor DST of each NAND string NS can be connected to a corresponding bit line BL. In each NAND string NS, the memory cell MC can be arranged between the source select transistor SST and the drain select transistor DST.

[0078] Memory device 150 may include a voltage supply circuit 170. Voltage supply circuit 170 may provide word line voltages, for example, one or more predetermined voltages such as a program voltage, a read voltage, and a pass voltage, to corresponding word lines according to an operating mode, or may provide voltages to a bulk (e.g., a well region) of each memory block including memory cells MC0, MC1, ..., MCn-1. In this case, voltage generation by voltage supply circuit 170 may be performed under the control of control circuit 180. Furthermore, voltage supply circuit 170 may generate a plurality of variable read voltages to distinguish between a plurality of data items.

[0079] In response to control by control circuit 180, one of the memory blocks (or sectors) of the memory cell array can be selected, and one of the word lines of the selected memory block can be selected. Word line voltages can be supplied to the selected word line and unselected word lines of memory group 330, respectively. Voltage supply circuit 170 can include a voltage generating circuit for generating target voltages of various levels, which are applied to the word lines of memory group 330.

[0080] Memory device 150 may also include a read / write circuit 320 controlled by control circuit 180. Depending on the operating mode, read / write circuit 320 may operate as a sense amplifier or a write driver. For example, during verify and read operations, read / write circuit 320 may operate as a sense amplifier to read data items from the memory cell array. During programming operations, read / write circuit 320 may operate as a write driver, controlling the potential of a bit line based on the data items to be stored in the memory cell array. During programming operations, read / write circuit 320 may receive data items to be programmed into the cell array from a page buffer. Read / write circuit 320 may drive the bit lines based on the input data items. To this end, read / write circuit 320 may include multiple page buffers (PBs) 322, 324, and 326, each corresponding to each column or bit line, or each column pair or bit line pair. Depending on the embodiment, each of the multiple page buffers 322, 324, and 326 may include multiple latches. According to an embodiment, the number of latches or page buffers coupled to each bit line may be equal to or greater than the number of bits of data stored in the memory cell MC.

[0081] Page buffers 322, 324, and 326 can be connected to a data input / output device, such as a serialization circuit or serializer, via multiple buses. When each of page buffers 322, 324, and 326 is connected to the data input / output device via a different bus, delays that may occur in data transfers between page buffers 322, 324, and 326 can be reduced. For example, each page buffer 322, 324, and 326 can perform data transfers without latency.

[0082] According to an embodiment, the memory device 150 may receive a write command, write data, and information about a location where the write data is to be stored, such as a physical address. The control circuit 180 causes the voltage supply circuit 170 to generate a program pulse, a pass voltage, etc. for a program operation performed in response to the write command, and to generate one or more voltages for a verification operation performed after the program operation.

[0083] When programming multi-bit data items in the nonvolatile memory cells included in memory group 330, the error rate may be higher than the error rate when storing single-bit data items in the nonvolatile memory cells. For example, errors in the nonvolatile memory cells may be caused by inter-cell interference (CCI). To reduce errors in the nonvolatile memory cells, the width (deviation) of the threshold voltage distribution corresponding to the stored data items between the nonvolatile memory cells should be reduced.

[0084] To this end, memory device 150 may perform an incremental step pulse programming (ISPP) operation to effectively achieve a narrow threshold voltage distribution for non-volatile memory cells. In embodiments, memory device 150 may use the ISPP operation to perform a multi-step programming operation. For example, memory device 150 may separate the programming operation into a least significant bit (LSB) programming operation and a most significant bit (MSB) programming operation according to a predetermined sequence between non-volatile memory cells or pages.

[0085] The multi-bit value programmed into a memory cell in a NAND flash memory (e.g., NAND-type flash memory cells MC0 through MCn-1 in memory group 330) can be determined based on the threshold voltage window, or threshold voltage distribution, to which the threshold voltage of the memory cell belongs. As the size of each memory cell decreases and the number of data bits programmed into each memory cell increases (e.g., to 3, 4, or 5 bits), the width of the threshold voltage window used to represent each multi-bit value becomes narrower, which increases the error rate when determining the multi-bit value stored in the memory cell. This is because as the amount of charge stored in each memory cell decreases with feature size, process variations become more prevalent, resulting in larger differences in the threshold voltages of different memory cells storing the same value. As a result, it becomes increasingly difficult to determine which value the threshold voltage of a memory cell corresponds to.

[0086] According to an embodiment, the control circuit 180 may include a read retry table (RRT). The RRT may be stored in the memory device 150. During the process of applying a read voltage to a non-volatile memory cell in the memory device 150 via a word line and reading data stored in the non-volatile memory cell, a read error may occur. The control circuit 180 in the memory device 150 may manage information regarding a read retry mechanism for resolving read errors. One piece of information regarding the read retry mechanism is the read RRT. The read retry mechanism uses the RRT for the recording location where the error occurred, allowing the memory device 150 to ensure data integrity by applying an appropriate correction value (e.g., changing the read voltage level) when rereading.

[0087] Figure 4 A memory cell array according to another embodiment of the present disclosure is shown.

[0088] Reference Figure 4, the memory cell array may have a structure including parts or layers stacked along a vertical direction D1. The memory cell array may include at least one memory block. Hereinafter, a direction substantially perpendicular to the upper surface of the substrate may be defined as a first direction D1, and two directions parallel to the upper surface of the substrate and intersecting each other may be defined as a second direction D2 and a third direction D3, respectively. For example, the second direction D2 and the third direction D3 may intersect each other substantially perpendicularly. The first direction D1 may be referred to as a vertical direction, the second direction D2 may be referred to as a row direction, and the third direction D3 may be referred to as a column direction. The direction indicated by the arrow in the figure and the direction opposite thereto are described as the same direction.

[0089] For the convenience of description, Figure 4 NAND strings or cell strings SG1 to SGk connected to one bit line BL and one common source line CSL among cell strings included in a memory block are shown.

[0090] A memory block may include a plurality of cell strings SG1 to SG5 connected between the same bit line (BL) and a common source line CSL. Each of the cell strings SG1 to SGk may include at least one source select transistor SST controlled by a source select line SSL, a plurality of memory cells controlled by a word line WL, a central switch transistor CST disposed in an intermediate boundary layer IBL and controlled by a central switch word line CSWL, and a drain select transistor DST controlled by each drain select line DSL1, DSL2, DSL3, ..., DSLk.

[0091] According to an embodiment, a plurality of memory cells connected to at least one word line at both ends of the first stack ST1 and the second stack ST2 located in the first direction D1 may be dummy cells. No data may be stored in the dummy cells. In addition, according to an embodiment, the dummy cells may be used to store data with fewer bits than other memory cells. According to an embodiment, the intermediate boundary layer IBL may include at least one gate line. One gate line corresponds to a central switching word line CSWL, and the central switching word line CSWL may simultaneously control the switching operation of the central switching transistor CST connected thereto. In addition, although Figure 4 Although a structure in which the first stack ST1 and the second stack ST2 are stacked is shown, three or more stacks may be vertically stacked in the cell array 330. When a plurality of stacks are stacked, an intermediate boundary layer IBL may be provided between every two stacked stacks. The intermediate boundary layer IBL may include at least one switching transistor configured to couple a memory cell in one of the two stacks with another memory cell in the other stack.

[0092] Figure 4An embodiment is shown in which source selection transistors SST included in a plurality of cell strings SG1 to SGk are connected to a common selection line CSL However, according to an embodiment, a certain number of source selection transistors may be coupled to each of a plurality of source ground selection lines.

[0093] Reference Figures 2 to 4 , the cell array 330 may include a plurality of memory blocks arranged along a plurality of directions D1, D2, and D3. In an embodiment, the memory blocks may be composed of Figure 3 The control circuit 180 shown selects, for example, a read voltage, a program voltage, or an erase voltage may be applied to the memory block and the word line selected by the control circuit 180 .

[0094] Each of the cell strings SG1 to SGk may include a plurality of switching transistors and a plurality of memory cells capable of storing data. Here, the plurality of switching transistors may include a drain select transistor DST, a source select transistor SST, and a central switching transistor CST. Figure 4 In the embodiment shown, each of the cell strings SG1 to SGk includes one drain select transistor DST, one source select transistor SST, and one central switch transistor CST. However, depending on the embodiment, each of the cell strings SG1 to SGk may include a plurality of drain select transistors DST, a plurality of source select transistors SST, or a plurality of central switch transistors CST.

[0095] Figure 5 A cell array structure according to an embodiment of the present disclosure is shown.

[0096] Reference Figure 4 and Figure 5 , the memory device 150 may be stacked in a vertical direction (D1, Z) by a plurality of stacked layers ST1, ST2, as shown in FIG. Figure 4 As shown, nonvolatile memory cells can be placed in three-dimensional (3D) space. Specifically, Figure 5 A cell array in a 3D nonvolatile memory device according to an embodiment of the present disclosure is shown.

[0097] The memory device 150 may include a plurality of memory cells MC arranged in a cell string STR in multiple memory layers (e.g., three memory layers L1, L2, and L3). Each memory layer L1, L2, and L3 is connected to a plurality of bit lines BL1, BL2, and BL3 via a first end of a plurality of channel lines CL and to a common source line CSL via a second end of the plurality of channel lines CL. The memory device 150 may include a plurality of source select lines SSL1 to SSL4 connected to source select transistors SST1 to SST4. Furthermore, a plurality of word lines WL1 to WLn and a ground select line GSL may be connected to each of the memory layers L1, L2, and L3. The plurality of source select lines SSL1 to SSL4, the plurality of word lines WL1 to WLn, and the ground select line GSL may be arranged in a direction intersecting the plurality of channel lines CL. Each of the plurality of channel lines may be described as a cell string STR. Each cell string STR may include source selection transistors SST1 to SST4 respectively connected to a plurality of source selection lines SSL1 to SSL4 . A ground selection line GSL may be grounded to turn off the ground selection transistors GST.

[0098] Multiple word lines WL1 to WLn can each be connected to the control gates of memory cells arranged in the column direction. Each of the multiple bit lines BL1 to BL3 can be connected to one end of a source select transistor. Multiple memory cells whose control gates are connected to each word line WL1 to WLn in the row direction can be configured as a page, which is a unit for storing data or data entries. The number of pages can be changed or determined according to the storage capacity of the memory cells.

[0099] Figure 6 1 shows a cell array structure according to an embodiment of the present disclosure. Specifically, Figure 6 Described Figure 3 The internal configuration of the cell array 330 is described in .

[0100] Reference Figure 1 and Figure 6 The cell array 330 in the memory device 150 may include a plurality of memory blocks BLK(k+1), BLK(k), and BLK(k−1). Figure 6 Three memory blocks BLK(k+1), BLK(k), BLK(k-1) are shown, but the cell array 330 may include a plurality of memory blocks arranged in two or three dimensions. Figure 6In the 10-bit CMOS process, each memory block BLK(k+1), BLK(k), and BLK(k-1) includes multiple memory cells connected to 16 word lines WL0 to WL15. The 16 word lines WL0 to WL15 and a ground select line GSL, which runs perpendicular to the row or bit lines, may be arranged in parallel. However, the number of word lines included in each memory block may vary depending on the embodiment. Each memory block BLK(k+1), BLK(k), and BLK(k-1) may include a cell string corresponding to each bit line. In a memory block (e.g., BLK(k)), each cell string may be connected to a source select transistor SST(k) and a ground select transistor GST(k) connected to the corresponding bit line. The cell string may include 16 memory cells MC15 to MC0 connected in series between the source select transistor SST(k) and the ground select transistor GST(k). The number of memory cells included in the cell string may correspond to the number of word lines. The source selection transistor SST(k), the memory cells MC15 to MC0 , and the ground selection transistor GST(k) are respectively connected to a source selection line SSL(k), word lines WL15 to WL0 , and a ground selection line GSL(k).

[0101] Reference Figures 1 to 6 As memory device 150 is designed to store more data, the source select lines of adjacent memory blocks arranged in two or three dimensions can be electrically connected to each other. Furthermore, the ground select lines of adjacent memory blocks can be electrically connected to each other. For example, source select line SSL(k) of memory block BLK(k) can be electrically connected to source select line SSL(k+1) of adjacent memory block BLK(k+1). Furthermore, adjacent string / ground select transistors along a bit line can share contacts to achieve electrical connection between adjacent string / ground select lines.

[0102] When a ground select line or cell string is designed to be shared between adjacent memory blocks, the interference effect caused by a read or write operation performed on a specific memory block may affect adjacent memory blocks (e.g., a memory block that has a shared cell string but is not selected). Here, the scheme for sharing cell strings between adjacent memory blocks may include a structure in which the cell strings share the same component using electrodes or functional layers (e.g., a bulk electrode stacked in any region or any semiconductor layer on a semiconductor substrate, or disposed in a trench in the semiconductor substrate in which the cell strings are disposed). In addition, when a ground select line or cell string is designed to be shared between adjacent memory blocks, the interference effect caused by a read or write operation performed on a specific memory block among the adjacent memory blocks may be greater than when the adjacent memory blocks do not share a cell string. Because the read interference effect caused by a read operation on an open memory block differs depending on whether the adjacent memory blocks of the memory device 150 share a cell string, the memory device 150 may apply different weights when calculating the read count RD_COUNT.

[0103] Figure 7 An apparatus for managing status information about a firmware storage location according to an embodiment of the present disclosure is described.

[0104] Reference Figure 7 The firmware management device 3300 can generate, maintain, update or store status information of multiple firmware copies FW0, FW1. Multiple firmware copies FW0, FW1 can correspond to Figure 1 The multiple firmware copies 40_1, 40_2, 40_3, 40_N described in FIG. Corresponding to the design and configuration of the memory system 110 or the memory device 150, the memory device 150 may store a preset number of firmware copies.

[0105] Each of the multiple firmware copies FW0, FW1 may include multiple data entries rather than a single data chunk. For example, the first firmware copy FW0 may include a first partial firmware FW0_0, a second partial firmware FW0_1, and an (N+1)th partial firmware FW0_N. The second firmware copy FW1 may include a first partial firmware FW1_0 and a second partial firmware FW1_1. According to an embodiment, each of the multiple firmware copies FW0, FW1 may have the same size and may include the same number of partial firmware.

[0106] According to an embodiment, the memory system 110 may perform internal operations by loading one of the multiple firmware copies FW0 and FW1. Furthermore, according to an embodiment, the memory system 110 may perform internal operations by loading partial firmware of the multiple firmware copies FW0 and FW1. For example, the memory system 110 may read and load a first portion of firmware of the first firmware copy FW0, and read and load a second portion of firmware of the second firmware copy FW1.

[0107] According to an embodiment, the number of firmware copies included in the memory device (e.g., N+1 copies) and the number of partial firmware included in each firmware copy (e.g., N+1 parts) may be the same. Alternatively, according to an embodiment, the number of firmware copies included in the memory device (e.g., N copies) and the number of partial firmware included in each firmware copy (e.g., K parts) may be different.

[0108] According to an embodiment, the firmware management device 3300 may generate, maintain, update, or save status information of each partial firmware included in each of the multiple firmware copies FW0 and FW1, rather than the status information of each of the multiple firmware copies FW0 and FW1. Specifically, the firmware management device 3300 may store location information (e.g., BLK#, PL#, PG#) where each partial firmware included in each of the multiple firmware copies FW0 and FW1 is stored, as well as status information (e.g., RD_C, E / W, St_Info) for each location.

[0109] Multiple firmware copies FW0 and FW1 can be stored at different locations within the memory device 150. Furthermore, depending on the embodiment, the storage location of the partial firmware included in each of the multiple firmware copies FW0 and FW1 can also vary. Therefore, the firmware management device 3300 can check location information (e.g., BLK#, PL#, PG#) regarding the location where each partial firmware is stored. The location information may include a memory block number (BLK#), a memory plane number (PL#), or a page number (PG#). The location information for each partial firmware may vary depending on the configuration within the memory device 150.

[0110] Since the memory system 110 reads or loads partial firmware of multiple firmware copies FW0 and FW1, the firmware management device 3300 can manage the status information of each partial firmware. For example, the status information of the first partial firmware FW0_0 and the second partial firmware FW0_1 belonging to the first firmware copy FW0 may be different. Figure 7The read count RD_C of the first partial firmware FW0_0 belonging to the first firmware copy FW0 may be 20, while the read count RD_C of the second partial firmware FW0_1 belonging to the first firmware copy FW0 may be 1. The firmware management device 3300 can determine the operational safety of each partial firmware based on the status information of the corresponding partial firmware. Based on the status information, the operational safety of each partial firmware can be determined as normal (e.g., safe or secure) or warning (e.g., risky or dangerous). For example, the read count RD_C of the first partial firmware FW1_0 belonging to the second firmware copy FW1 may be 50, and the erase / program cycle (E / W) count may be 90. The read count RD_C or erase / program cycle (E / W) count of the first partial firmware FW1_0 belonging to the second firmware copy FW1 exceeds or approaches a preset safety-assured standard. Therefore, the firmware management device 3300 can determine that the operational safety of the first partial firmware FW1_0 belonging to the second firmware copy FW1 is "warning." The firmware management device 3300 can copy or move the partial firmware determined to be risky or dangerous to another location. Through this process, the firmware management device 3300 can maintain or improve the operational security of the multiple firmware copies FW0 and FW1 included in the memory device 150.

[0111] Reference Figure 2 and Figure 7 According to embodiments, the system area 50_1 and user data area 50_2 within the memory device 150 may have different standards for determining data security or operational security. The system area 50_1 has stricter standards for determining data security than the user data area 50_2. For example, if the read count RD_C exceeds 70 for a data entry stored in the user data area 50_2, operational security may be determined to be at risk (warning). On the other hand, if the read count RD_C exceeds 40 for a data entry stored in the system area 50_1, operational security may be determined to be at risk (warning). Furthermore, if the erase / program cycles (E / W) exceed 200 for a data entry stored in the user data area 50_2, operational security may be determined to be at risk (warning). On the other hand, if the erase / program cycles (E / W) exceed 100 for a data entry stored in the system area 50_1, operational security may be determined to be at risk (warning). Therefore, in the case where the firmware copy is stored in the system area 50_1 , the standard or threshold for determining operational safety may be stricter than that in the case where the data entry is stored in the user data area 50_2 .

[0112] Figure 8 A firmware loading method according to an embodiment of the present disclosure is described.

[0113] Reference Figure 8 The firmware loading method may include: determining the target firmware to be read or loaded (operation S91), determining (i.e., checking or comparing) status information of multiple locations storing the target firmware (operation S93), selecting a location with the lowest read count and / or the lowest P / E cycle (operation S95), reading the target firmware from the selected location and updating the status information about the selected location (operation S97). In addition, according to an embodiment, the firmware loading method may include setting the location where read interference occurs during a read operation of the selected location as the next location to read the target firmware (operation S99).

[0114] Reference Figure 7 Because the number of accesses to the multiple firmware copies and the multiple partial firmware belonging to the multiple firmware copies stored in the memory device 150 varies, the memory system 110 can select the partial firmware with the lowest value (e.g., lowest read count, lowest P / E cycle, or lowest access count) among the multiple partial firmware as the target firmware to be read or loaded. This operation can reduce the deviation in the status information of the multiple firmware copies or multiple partial firmware stored in the memory device 150. For example, through the firmware management device 3300, the memory system 110 can check the operating status of the multiple firmware copies or multiple partial firmware and determine which one of the multiple firmware copies or multiple partial firmware to select or access (e.g., the target firmware).

[0115] In addition, if Figures 3 to 6 As shown, the memory device 150 may include a two-dimensional or three-dimensional structure that integrates multiple memory cells. Therefore, in the process of accessing at least one of the multiple firmware copies or multiple partial firmware stored in the memory system 110, it may be difficult to avoid read interference. Read interference occurs in memory cells connected by the same word line, or in memory cells that are located adjacent to the memory cell where the read operation is performed. When other firmware copies or other partial firmware are stored in adjacent or neighboring locations, data security may be reduced even if the other firmware copies or other partial firmware are not the targets to be read or loaded (i.e., not the target firmware). Therefore, after performing an operation to read a specific firmware copy or a specific partial firmware, the memory system 110 can set another firmware copy or another partial firmware stored in an adjacent or neighboring location that caused strong read interference during the operation to read the specific firmware copy or the specific partial firmware as the next read target.

[0116] According to an embodiment, to estimate the read disturb caused by reading a specific location (e.g., a page) within the memory device 150, the memory system 110 or the firmware management device 3300 may utilize available status information. For example, read disturb may be understood as one type of stress that may occur during a read operation. The stress that may occur during a read operation may be estimated based on the number of program / erase (P / E) cycles. The memory device 150 may have a preset number of P / E cycles at which performance degradation (e.g., reduced data security) occurs. This may correspond to the service life of the memory device 150. Generally, pages with more P / E cycles may experience more read stress during a read operation due to wear, tear, and potential performance degradation of the memory device 150.

[0117] According to embodiments, the stress incurred during a read operation can be estimated based on the data retention time. Memory cells in memory device 150 can stably store data for a predetermined period of time before a bit error occurs. This may correspond to the operational performance or characteristics of memory device 150. Greater read stress may occur on pages where firmware copies or portions of firmware are programmed and remain unmodified for a long period of time, potentially leading to data loss.

[0118] According to embodiments, the stress incurred during a read operation can be estimated based on the bit error rate (BER). The bit error rate refers to the probability that an error will occur during a read operation. Pages with high bit error rates may require additional error correction mechanisms or may be subject to increased read stress due to the increased error rate.

[0119] According to embodiments, stress occurring during a read operation may be estimated in response to a voltage level applied to a memory cell. The voltage level applied during a read operation may affect the stability and stress of a page including multiple memory cells in the memory device 150. Higher voltage levels may increase the likelihood of interference or other reliability issues and may result in greater read stress on the read page and adjacent locations adjacent to the read page.

[0120] According to embodiments, stress during a read operation may occur due to a read disturb effect. Reading a particular page within memory device 150 may unintentionally affect adjacent pages due to an electrical interaction known as read disturb or read disturbance. If a particular page is frequently accessed, adjacent pages may experience increased stress compared to other pages located farther away from the particular page. Adjacent pages may be identified based on the physical distance between the adjacent pages or components that may electrically interact (e.g., the same word line or the same bit line).

[0121] Based on the operational status information, the memory system 110 or the firmware management device 3300 can estimate whether a particular page has a higher read stress or a greater read disturb effect than other pages. To this end, the memory system 110 or the firmware management device 3300 can examine program / erase cycles, data retention time, bit error rate, voltage levels applied during read operations, and components that may cause specific effects, such as read interruptions. Based on this information, the relative stress differences between multiple pages or memory blocks in the memory device 150 can be estimated.

[0122] Figure 9 A firmware access method according to an embodiment of the present disclosure is described. Here, the firmware access method shows how to determine the next read target firmware based on read disturbance.

[0123] Specifically, Figure 9 As an example, multiple firmware files are stored in adjacent locations within the memory device 150. For example, the first firmware file fw0 may be stored in the first page Page0 included in the first to fourth memory planes Plane0, Plane1, Plane2, and Plane3. The second firmware file fw1 may be stored in the second page Page1 included in the first to fourth memory planes Plane0, Plane1, Plane2, and Plane3. The third to eighth firmware files fw2 to fw7 are sequentially stored in the third to eighth pages Page2 to Page7 included in the first to fourth memory planes Plane0, Plane1, Plane2, and Plane3.

[0124] The memory system 110 can perform a read operation on the first to eighth firmware fw0 to fw7 in the memory device 150. To mitigate read disturbance or increased stress that may occur during a read operation at a specific location, the memory system 110 does not read the first to eighth firmware fw0 to fw7 stored in the same memory plane. The memory system 110 can read the first to eighth firmware fw0 to fw7 from all of the first to fourth memory planes (Plane0, Plan1, Plan2, and Plan3). For example, after reading the first firmware fw0 (①) stored in the first page Page0 of the first memory plane Plane0, the memory system 110 can read the second firmware fw1 (②) stored in the second memory plane Plane1 instead of the second page Page1 of the first memory plane Plane0. After reading the third firmware fw2 (③) stored in the third page Page2 of the third memory plane Plane2, the memory system 110 can read the fourth firmware fw3 (④) stored in the fourth page Page3 of the fourth memory plane Plane3. Memory system 110 can sequentially read the fifth to eighth firmware fw4 to fw7 (⑤, ⑥, ⑦, ⑧) from the first to fourth memory planes Plane0, Plane1, Plane2, and Plane3. This scheme or mechanism allows the read operations for the first to eighth firmware fw0 to fw7 to be performed sequentially and evenly across all of the first to fourth memory planes Plane0, Plane1, Plane2, and Plane3.

[0125] During the first read operation (①) of the first firmware fw0 stored in the first page Page0 of the first memory plane Plane0, read stress or read disturbance may occur in the first page Page0 of other memory planes (i.e., the second to fourth memory planes Plane1, Plane2, and Plane3) connected by the same word line. Figure 9When reading the first firmware fw0 stored in the first page Page0 of the first memory plane Plane0, read stress or read disturb (represented by a pattern) may occur in the first page Page0 of the second to fourth memory planes Plane1, Plane2, and Plane3. Similarly, during a second read operation (②) of the second firmware fw1 stored in the second page Page1 of the second memory plane Plane1, read stress or read disturb (represented by a pattern) may occur in the second page Page1 of the other memory planes connected by the same word line, namely, the first memory plane Plane0, the third memory plane Plane2, and the fourth memory plane Plane3. According to an embodiment, the read stress or read disturb may be proportional to the distance from the location of the accessed memory cell. Based on the estimated read stress or read disturb, the memory system 110 can select or determine the next read target (e.g., the next access location) for the first to eighth firmware fw0 to fw7.

[0126] For example, during the first read operation (①) of the first firmware fw0 stored in the first page Page0 of the first memory plane Plane0, when the difference in the operation state information is not large, the largest read disturbance may occur in the first page Page0 of the second memory plane Plane1 due to the closest distance. Therefore, the memory system 110 may select or determine the next read target of the first firmware fw0 ( ), which is stored in the first page Page0 of the second memory plane Plane1. Similarly, during the second read operation (②) of the second firmware fw1 stored in the second page Page1 of the second memory plane Plane1, the maximum read disturbance may occur in the second page Page1 of the first memory plane Plane0 or the third memory plane Plane2. Therefore, the memory system 110 can select or determine the next read target of the second firmware fw1 ( ), which is stored in the second page Page1 of the first memory plane Plane0 or the third memory plane Plane2. Figure 9 In the embodiment, the second firmware fw1 stored in the second page Page1 of the third memory plane Plane2 is selected or determined as the next read target ( ).

[0127] Reference Figure 9 In response to the read stress or read disturbance occurring during the read operations (① to ⑧) for the first to eighth firmware fw0 to fw7, the next read target ( 、 、 、 、 、 、 、 ) is set to the first firmware fw0 to the eighth firmware fw7 stored in the adjacent memory plane. Figure 9 The example shows a case where the same firmware is stored in the same page included in the first to fourth memory planes Plane0, Plane1, Plane2, and Plane3. However, according to embodiments, the same firmware may not be stored in the same page. Even in this case, the memory system 110 can prioritize the location where the maximum read disturbance is likely to occur during the process of reading the specific firmware as the next read target.

[0128] In addition, according to the embodiment, Figure 9 The read operation of the first firmware fw0 to the eighth firmware fw7 described in the above can be applied to a plurality of firmware copies FW0, FW1 or including Figure 7 The read operations corresponding to the multiple partial firmwares of the first partial firmware FW0_0, the second partial firmware FW0_1 and the (N+1)th partial firmware FW0_N described in FIG.

[0129] Figure 10 A firmware loading method according to an embodiment of the present disclosure is described.

[0130] Reference Figure 10 , the firmware loading method may include: distributively storing a plurality of firmwares based on a preset strategy (operation S81), reading at least one of the plurality of distributedly stored firmwares (operation S83), estimating a location where read stress occurs when reading the firmware (operation S85), setting the firmware associated with the main stress (i.e., stored at a location where the estimated stress is higher) as a target for the next read or load operation (operation S87), and updating status information of the read firmware (operation S89).

[0131] The memory system 110 may distribute and store a plurality of firmware in the memory device 150 (operation S81). Figure 9 As described in

[15] , multiple firmware can be distributed and stored in multiple memory cells connected to the same word line but included in different memory planes. According to embodiments, multiple firmware can be distributed and stored in the same word line, the same bit line, the same memory block, or the same memory plane according to the configuration of memory device 150. In addition, the locations where the multiple firmware are stored can vary depending on the number of firmware stored in memory device 150.

[0132] The memory system 110 may read the firmware stored in the memory device 150 when power is supplied or before performing a specific internal operation (operation S83). The memory system 110 may store or load the firmware read from the memory device 150 into a buffer or an operating memory. The memory system 110 may not keep the firmware in the buffer or the operating memory for a long time, depending on the size of the buffer or the operating memory or the characteristics of the loaded firmware. When the firmware is not kept in the buffer or the operating memory continuously, the memory system 110 may read or load the same firmware from the memory device 150 multiple times, such as Figure 9 shown.

[0133] The memory system 110 may estimate locations where read stress occurs when reading the firmware (operation S85). Furthermore, the level of stress or read disturb occurring during the read operation may be estimated based on the state information or the aforementioned method. The memory system 110 may then determine the firmware stored at the location where the estimated stress is greater or greatest as the target for the next read operation (operation S87).

[0134] Thereafter, the memory system 110 may update the state information associated with the read or loaded firmware (operation S89). Figure 7 As described above, the firmware management device 3300 can update and store the status information of the firmware based on the location information of the firmware. Here, the status information may include a read count RD_C, an erase / program cycle (E / W cycle), security information St_Info, etc.

[0135] Figure 11 A firmware management method according to an embodiment of the present disclosure is described.

[0136] Reference Figure 11 The firmware management method may include: checking compliance of a preset environment or operating condition of each firmware location (e.g., whether each firmware location satisfies a preset usage environment or operating condition) (operation S72), recovering or restoring the copied firmware or a storage block storing the firmware based on the checking result (operation S74), and storing status information associated with the restored firmware (operation S76).

[0137] Reference Figure 7 and Figure 11The memory system 110 or the firmware management device 3300 may determine security information St_Info based on determining (i.e., checking or comparing) the read count RD_C and / or the results of an erase / program cycle (E / W cycle). The security information St_Info is status information about the firmware copy or portion of the firmware, which has a preset standard or threshold (operation S72). If the security information about the firmware copy or portion of the firmware at the current location is determined to be at risk (warning), the memory system 110 or the firmware management device 3300 may copy or move the firmware copy or portion of the firmware to another location (operation S74). Thereafter, the memory system 110 or the firmware management device 3300 may update the status information of the firmware copy or portion of the firmware based on the location to which the firmware copy or portion of the firmware was copied or moved (operation S76). This firmware management method may be similar to garbage collection, wear leveling, data migration, or read retry operations performed in the memory system 110. However, since this operation is performed on firmware rather than user data, standards or thresholds regarding the operating status of the firmware or conditions for determining the location to which risky firmware is copied or moved can be set to ensure higher operational security than for user data.

[0138] Figure 12 A data processing system according to an embodiment of the present disclosure is shown.

[0139] Reference Figure 12 , the data processing system 100 may include a host 102 coupled or connected to a memory system 110. For example, the host 102 and the memory system 110 may be coupled to each other via a data bus, a host cable, etc. to perform data communication.

[0140] Memory system 110 may include memory device 150 and controller 130. Memory device 150 and controller 130 in memory system 110 may be considered to be physically separate components or elements from each other. Memory device 150 and controller 130 may be connected via at least one data path. For example, a data path may include a channel and / or a passage.

[0141] Memory device 150 may include multiple memory chips (i.e., flash memory chips) 252 connected to controller 130 via multiple channels CH0, CH1, ..., CHn and paths W0, ..., W_k. Memory chip 252 may include multiple memory planes or multiple memory dies. Depending on the embodiment, a memory plane can be considered as a logical or physical partition, including at least one memory block, a driver circuit capable of controlling an array including multiple non-volatile memory cells, and a buffer that can temporarily store data input to or output from the non-volatile memory cells. Each memory plane or each memory die may support an interleaved mode, in which multiple data input / output operations are performed in parallel or simultaneously. Depending on the embodiment, the memory blocks included in each memory plane or each memory die included in memory device 150 may be grouped as a super memory block to input / output multiple data items. Figure 12 The internal configuration of the memory device 150 shown may be changed based on the operating performance of the memory system 110. Figure 12 The internal configuration described in .

[0142] According to an embodiment, the memory device 150 and the controller 130 may be components or elements divided by function. In addition, according to an embodiment, the memory device 150 and the controller 130 may be implemented with a single chip or multiple chips.

[0143] The controller 130 can perform data input / output operations (e.g., read operations, program operations, erase operations, etc.) in response to a request or command input from an external device, such as the host 102. For example, when the controller 130 performs a read operation in response to a read request input from the external device, data stored in a plurality of non-volatile memory cells included in the memory device 150 is transferred to the controller 130. In addition, the controller 130 can independently perform operations without a request or command input from the host 102. Regarding the operating state of the memory device 150, the controller 130 can perform operations such as garbage collection (GC), wear leveling (WL), and bad block management (BBM) for checking whether a memory block is bad and handling the bad block.

[0144] Each memory chip 252 may include multiple memory blocks. A memory block may be understood as a group of nonvolatile memory cells in which data is removed together through a single erase operation. Although not shown, a memory block may include a page, which is a group of nonvolatile memory cells that store data together during a single programming operation or output data together during a single read operation. For example, a memory block may include multiple pages. The memory device 150 may include a voltage supply circuit capable of supplying at least one voltage to the memory block. The voltage supply circuit may supply a read voltage Vrd, a program voltage Vprog, a pass voltage Vpass, or an erase voltage Vers to the nonvolatile memory cells included in the memory block.

[0145] The host 102 interacting with the memory system 110, or the data processing system 100 including the memory system 110 and the host 102, may be a mobile electronic device (e.g., a vehicle), a portable electronic device (e.g., a mobile phone, an MP3 player, a laptop computer, etc.), or a non-portable electronic device (e.g., a desktop computer, a game console, a television, a projector, etc.). The host 102 may provide interaction between the host 102 and a user using the data processing system 100 or the memory system 110 through at least one operating system (OS). The host 102 sends a plurality of commands corresponding to user requests to the memory system 110, and the memory system 110 performs data input / output operations corresponding to the plurality of commands (e.g., operations corresponding to the user requests).

[0146] Reference Figure 12 , the controller 130 in the memory system operates with the host 102 and the memory device 150. As shown, the controller 130 may include a hierarchical structure including a host interface layer (HIL) 220, a flash translation layer (FTL) 240, and a flash interface layer (FIL or memory interface layer) 260.

[0147] Figure 12 The host interface layer (HIL) 220, flash translation layer (FTL) 240, and flash interface layer (FIL) 260 described in the foregoing are shown as one embodiment. The host interface layer (HIL) 220, flash translation layer (FTL) 240, and flash interface layer (FIL) 260 may be implemented in various forms depending on the operational performance of the memory system 110. According to an embodiment, the host interface layer (HIL) 220, flash translation layer (FTL) 240, and flash interface layer (FIL) 260 may be operated by a plurality of cores or processors having a pipeline structure included in the controller 130.

[0148] The host 102 and the memory system 110 may use a predetermined set of data communication rules or procedures or a preset interface to transmit and receive data therebetween. Examples of data communication standards or interfaces supported by the host 102 and the memory system 110 for transmitting and receiving data include Universal Serial Bus (USB), MultiMediaCard (MMC), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced MiniDisk Interface (ESDI), Integrated Drive Electronics (IDE), Peripheral Component Interconnect Express (PCIe or PCI-e), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Mobile Industry Processor Interface (MIPI), and the like. According to an embodiment, the host 102 and the memory system 110 may be connected to each other via a Universal Serial Bus (USB). The Universal Serial Bus (USB) is a highly scalable, hot-swappable, plug-and-play serial interface that ensures cost-effective, standardized connections to peripheral devices such as keyboards, mice, joysticks, printers, scanners, storage devices, modems, and video conferencing cameras.

[0149] Memory system 110 may support Non-Volatile Memory Express (NVMe). NVMe is an interface type based at least on Peripheral Component Interconnect Express (PCIe) and is designed to improve the performance and design flexibility of hosts 102, servers, computing devices, and the like equipped with non-volatile memory system 110. PCIe can use slots or specific cables to connect computing devices (e.g., host 102) and peripheral devices (e.g., memory system 110). For example, PCIe can use multiple pins (e.g., 18 pins, 32 pins, 49 pins, or 82 pins) and at least one wire (e.g., x1, x4, x8, or x16) to achieve high-speed data communication of hundreds of megabits per second. Depending on the embodiment, the PCIe solution can achieve bandwidths of tens to hundreds of gigabits per second.

[0150] The buffer manager 280 included in the controller 130 can coordinate with the host interface layer (HIL) 220, the flash translation layer (FTL) 240, and the flash interface layer (FIL) 260 to control the input / output of data or operational information. To this end, the buffer manager 280 can set up or establish various buffers, caches, or queues in the memory and control the input / output of data to or from the buffers, caches, or queues, or the transfer of data between the buffers, caches, or queues, in response to requests or commands generated by the host interface layer (HIL) 220, the flash translation layer (FTL) 240, and the flash interface layer (FIL) 260. For example, the controller 130 can temporarily store read data provided by the memory device 150 in response to a request from the host 102 before providing the read data to the host 102. Furthermore, the controller 130 can temporarily store write data provided by the host 102 in the memory before storing the write data in the memory device 150. When controlling operations such as read operations, program operations, and erase operations performed within the memory device 150, read data or write data transmitted or generated between the controller 130 in the memory system 110 and the memory device 150 can be stored and managed by the buffer manager 280 in a buffer, queue, or the like established in the memory. In addition to read data or write data, the buffer manager 280 can also store signals or information (e.g., mapping data, read commands, program commands, etc. used to perform operations such as programming and reading data between the host 102 and the memory device 150) in a buffer, cache, queue, or the like established in the memory. The buffer manager 280 can set up or manage command queues, program memory, data memory, write buffer / cache, read buffer / cache, data buffer / cache, mapping buffer / cache, and the like.

[0151] The host interface layer (HIL) 220 may process commands, data, and the like sent from the host 102. By way of example and not limitation, the host interface layer 220 may include a command queue manager 222 and an event queue manager 224. The command queue manager 222 may sequentially store commands, data, and the like received from the host 102 in a command queue and, for example, output them to the event queue manager 224 in the order in which they were stored in the command queue manager 222. The event queue manager 224 may sequentially transmit events used to process the commands, data, and the like received from the command queue. Depending on the embodiment, the event queue manager 224 may classify, manage, or adjust the commands, data, and the like received from the command queue. Furthermore, depending on the embodiment, the host interface layer 220 may include an encryption manager (Encyp) 226 configured to encrypt responses or output data to be sent to the host 102 or decrypt encrypted portions of commands or data sent from the host 102.

[0152] Multiple commands or data with the same characteristics can be sent from the host 102, or multiple commands and data with different characteristics can be mixed or intermixed by the host 102 and then sent to the memory system 110. For example, multiple commands for reading data, i.e., read commands, can be transmitted, or commands for reading data, i.e., read commands, and commands for programming / writing data, i.e., write commands, can be sent alternately to the memory system 110. The command queue manager 222 of the host interface layer 220 can sequentially store commands, data, etc. sent from the host 102 in a command queue. The host interface layer 220 can then estimate or predict what type of internal operation the controller 130 will perform based on the characteristics of the commands, data, etc. sent from the host 102. The host interface layer 220 can determine the processing order and priority of the commands, data, etc. based on their characteristics. Based on the characteristics of the commands, data, etc. sent from the host 102, the event queue manager 224 in the host interface layer 220 is configured to receive events from the buffer manager 280 that should be processed or handled within the memory system 110 or controller 130 based on the commands, data, etc. input from the host 102. The event queue manager 224 may then transmit the events including commands, data, etc. to the flash translation layer (FTL) 240 .

[0153] According to an embodiment, the Flash Translation Layer (FTL) 240 may include a Host Request Manager (HRM) 242, a Mapping Manager (MM) 244, a State Manager (GC / WL) 246, and a Block Manager (BM / BBM) 248. Furthermore, according to an embodiment, the Flash Translation Layer (FTL) 240 may implement a multi-threading scheme to perform data input / output (I / O) operations. The multi-threaded FTL may be implemented by a multi-core processor using multi-threading included in the controller 130. For example, the Host Request Manager (HRM) 242 may manage events transmitted from an event queue. The Mapping Manager (MM) 244 may process or control mapped data. The State Manager 246 may perform operations such as garbage collection (GC) or wear leveling (WL) after checking the operating status of the memory device 150. The Block Manager 248 may execute commands or instructions on blocks in the memory device 150.

[0154] The host request manager (HRM) 242 can use the mapping manager (MM) 244 and the block manager 248 to handle or process requests based on read and program commands and events passed from the host interface layer 220. The host request manager (HRM) 242 can send a query request to the mapping manager (MM) 244 to determine the physical address corresponding to the logical address input with the event. The host request manager (HRM) 242 can send a read request and the physical address to the flash interface layer 260 to process the read request, i.e., handle the event. In one embodiment, the host request manager (HRM) 242 can send a program request (or write request) to the block manager 248 to program data to a specific empty page in the memory device 150 that does not store data. The host request manager (HRM) 242 can then transmit a mapping update request corresponding to the program request to the mapping manager (MM) 244 to update the information mapping the logical address to the physical address, related to the program data.

[0155] The block manager 248 may convert program requests passed from the host request manager (HRM) 242, the mapping manager (MM) 244, and / or the state manager 246 into flash memory program requests for the memory device 150 to manage the flash memory blocks in the memory device 150. To maximize or enhance the programming or writing performance of the memory system 110, the block manager 248 may collect program requests and send flash memory program requests for multi-plane and single-shot programming operations to the flash memory interface layer 260. In an embodiment, the block manager 248 sends multiple flash memory program requests to the flash memory interface layer 260 to enhance or maximize parallel processing of a multi-channel and multi-directional flash memory controller.

[0156] In an embodiment, block manager 248 may manage blocks in memory device 150 based on the number of valid pages, select and erase blocks without valid pages when a free block is needed, and select blocks with the least number of valid pages when determining to perform garbage collection. State manager 246 may perform garbage collection to move valid data stored in the selected blocks to free blocks and erase data stored in the selected blocks, so that memory device 150 can have sufficient free blocks (i.e., free blocks without data).

[0157] When block manager 248 provides state manager 246 with information about a block to be erased, state manager 246 may check all flash memory pages of the block to be erased to determine whether each page of the block is valid. For example, to determine the validity of each page, state manager 246 may identify the logical address recorded in the out-of-band (OOB) area of ​​each page. To determine whether each page is valid, state manager 246 may compare the physical address of the page with the physical address mapped to the logical address obtained from the query request. State manager 246 sends a program request for each valid page to block manager 248. When the programming operation is complete, mapping manager 244 may update the mapping table.

[0158] Mapping manager 244 manages mapping data, such as a logical-physical mapping table. Mapping manager 244 processes various requests, such as queries and updates, generated by host request manager (HRM) 242 or state manager 246. Mapping manager 244 may store the entire mapping table in memory device 150 (e.g., flash memory or non-volatile memory) and cache mapping entries based on the memory's storage capacity. When a mapping cache miss occurs while processing a query or update request, mapping manager 244 may send a read request to flash interface layer 260 to load the relevant mapping table stored in memory device 150. When the number of dirty cache blocks in mapping manager 244 exceeds a certain threshold, a program request may be sent to block manager 246 to create a clean cache block and store the dirty mapping table in memory device 150.

[0159] When performing garbage collection, the state manager 246 copies valid pages to free blocks, and the host request manager (HRM) 242 can program the latest version of the data for the same logical address of the page and simultaneously issue an update request. If the state manager 246 requests a mapping update before the copy of the valid page has completed normally, the mapping manager 244 may not perform a mapping table update. This is because when the state manager 246 requests a mapping update, the mapping request is issued using old physical information, and the valid page copy is completed later. To ensure accuracy, the mapping manager 244 may perform a mapping update only when, or only when, the latest mapping table still points to the old physical address.

[0160] The flash interface layer (FIL) 260 can exchange data, commands, status information, and the like with the multiple memory chips 252 in the memory device 150 through a data communication method. According to an embodiment, the flash interface layer 260 may include a state check scheduler (SM / SC) 262 and a data path manager (DPC) 264. The state check scheduler 262 can check and determine the operating status of the multiple memory chips 252 coupled to the controller 130, the operating status of the multiple channels CH0, CH1, ..., CHn, and the multiple lanes W0, ..., W_k, and the like. The transmission and reception of data or commands can be scheduled in response to the operating status of the multiple memory chips 252 and the multiple channels CH0, CH1, ..., CHn. The data path manager 264 can control the transmission and reception of data, commands, and the like through the multiple channels CH0, CH1, ..., CHn and the lanes W0, ..., W_k based on the information transmitted by the state check scheduler 262. According to an embodiment, the data path manager 264 may include a plurality of transceivers, each transceiver corresponding to each of the plurality of channels CH0, CH1, ..., CHn. In addition, according to an embodiment, the status check scheduler 262 and the data path manager 264 included in the flash memory interface layer 260 may be implemented as a memory control sequence generator or be coupled with a memory control sequence generator.

[0161] According to an embodiment, the flash interface layer 260 may further include an ECC (Error Correction Code) circuit 266 configured to perform error checking and correction on data transmitted between the controller 130 and the memory device 150. The ECC circuit 266 may be implemented as a separate module, circuit, or firmware in the controller 130, but according to an embodiment, it may also be implemented in each memory chip 252 included in the memory device 150. The ECC circuit 266 may include a program, circuit, module, system, or device for detecting and correcting erroneous data bits processed by the memory device 150.

[0162] To detect and correct any errors in data transmitted from memory device 150, ECC circuit 266 may include an error correction code (ECC) encoder and an ECC decoder. The ECC encoder performs error correction encoding on the data to be programmed into memory device 150 to generate encoded data with parity bits added, and stores the encoded data in memory device 150. When controller 130 reads data stored in memory device 150, the ECC decoder detects and corrects error bits contained in the data read from memory device 150. For example, after performing error correction decoding on the data read from memory device 150, ECC circuit 266 may determine whether the error correction decoding was successful and output an indication signal based on the error correction decoding result, such as a correction success signal or a correction failure signal. ECC circuit 266 may use the parity bits generated during the ECC encoding of the data stored in memory device 150 to correct error bits in the read data entry. If the number of error bits is greater than or equal to the number of correctable error bits, ECC circuit 266 may not correct the error bits, but may instead output a correction failure signal indicating that correction of the error bits failed.

[0163] According to an embodiment, the error correction circuit 266 may perform error correction operations based on coded modulation such as low-density parity check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis coded modulation (TCM), block coded modulation (BCM), etc. The error correction circuit 266 may include all circuits, modules, systems, and / or devices that perform error correction operations based on at least one of the above codes.

[0164] For example, the encoder in the ECC circuit 266 can generate codewords, which serve as the unit of ECC application data. A codeword of length n bits can include k bits of user data and (nk) bits of parity. The code rate can be calculated as (k / n). The higher the code rate, the more user data can be stored in a given codeword. Longer codewords and lower code rates improve the error correction capability of the ECC circuit 266. Furthermore, the ECC circuit 266 uses information read from channels CH0, CH1, ..., CHn to perform decoding. The decoders in the ECC circuit 266 can be categorized as hard-decision decoders or soft-decision decoders, depending on how many bits represent the information to be decoded. A hard-decision decoder uses memory cell output information represented by one bit to perform decoding. This one-bit information is called hard-decision information. A soft-decision decoder uses memory cell output information consisting of two or more bits, which is more accurate. This information is called soft-decision information. The ECC circuit 266 can use either hard-decision information or soft-decision information to correct errors in the data.

[0165] According to an embodiment, to improve error correction capability, the ECC circuit 266 may use a concatenated code using two or more codes. Alternatively, the ECC circuit 266 may use a product code that divides a codeword into several rows and columns and applies a different, relatively short ECC to each row and column.

[0166] According to an embodiment, the manager included in the host interface layer 220, the flash translation layer (FTL) 240, and the flash interface layer (FIL) 260 may be implemented with a general-purpose processor, an accelerator, a dedicated processor, a co-processor, a multi-core processor, etc. According to an embodiment, the manager may be implemented with firmware that works together with the processor.

[0167] According to an embodiment, the memory device 150 is implemented as a non-volatile memory such as a flash memory, for example, a read-only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable ROM (EPROM), an electrically erasable ROM (EEPROM), a magnetic RAM (MRAM), a NAND flash memory, a NOR flash memory, etc. In another embodiment, the memory device 150 may be implemented by at least one of a phase-change random access memory (PCRAM), a resistive random access memory (ReRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), a spin transfer torque magnetic random access memory (STT-MRAM), etc.

[0168] According to an embodiment, memory system 110 can support partitioning the storage areas storing data entries in memory device 150 based on preset criteria, dedicating each partitioned area to a specific range of logical block addresses (LBAs). When supporting partitioned namespaces, memory system 110 can improve access efficiency and reduce access time by using a specific range of LBAs dedicated to each area, rather than using a specific range of LBAs across multiple areas. For example, partitioned namespaces can improve write performance, which is particularly useful for workloads that require continuous writing of large amounts of data, such as video streaming or data backup.

[0169] Figure 13 A data storage system according to an embodiment of the present disclosure is shown. Figure 13 A memory system including multiple cores or multiple processors is shown, which is an example of a data storage system. The memory system can support the high-speed non-volatile memory (NVMe) protocol.

[0170] NVMe is a transport protocol designed for solid-state storage that can operate significantly faster than traditional hard drives. NVMe supports higher input / output operations per second (IOPS) and lower latency, resulting in faster data transfers and improved overall data storage system performance. Unlike SATA, which was designed for hard drives, NVMe can exploit the parallelism of solid-state storage to more efficiently use multiple queues and processors (e.g., CPUs). NVMe is designed to allow the host to use multiple threads to achieve higher bandwidth. NVMe can fully exploit the full parallelism offered by SSDs. However, due to limited firmware scalability, limited computing power, and severe hardware contention within SSDs, storage systems may be unable to process a large number of I / O requests in parallel.

[0171] Reference Figure 13 , a host as an external device can be connected to the memory system via multiple PCIe Gen 3.0 lanes, a PCIe physical layer 412, and a PCIe core 414. Controller 400 may include three embedded processors 432A, 432B, and 432C, each of which uses multiple cores 302A and 302B. Herein, the multiple cores 302A and 302B or the multiple embedded processors 432A, 432B, and 432C may have a pipeline structure.

[0172] The plurality of embedded processors 432A, 432B, 432C may be coupled to an internal DRAM controller (DDR controller) 434 via a processor interconnect. The controller 400 further includes a low-density parity check (LDPC) sequencer 460, a direct memory access (DMA) engine 420, a scratch pad memory 450 for metadata management, and an NVMe controller 410. The components within the controller 400 may be coupled to a plurality of channels connected to the plurality of memory packages (flash memories) 152 via a flash physical layer (NAND flash PHY) 440. The plurality of memory packages 152 may correspond to Figure 12 Multiple memory chips 252 described in.

[0173] According to an embodiment, the NVMe controller 410 included in the controller 400 is a storage controller designed for use with solid-state drives (SSDs) using the NVMe interface. The NVMe controller 410 can manage data transfer between the SSD and the computer's CPU, as well as other functions such as error correction, wear leveling, and power management. The NVMe controller 410 can use a simplified, low-overhead protocol to support fast data transfer rates.

[0174] According to an embodiment, the scratch memory 450 may be a storage area provided by the NVMe controller 410 for temporarily storing data. The scratch memory 450 may be used to store data awaiting writing to the multiple memory packages 152. The scratch memory 450 may also serve as a buffer to accelerate the write process, typically using a small amount of dynamic random access memory (DRAM) or static random access memory (SRAM). When a write command is executed, the data may first be written to the scratch memory 450 and then transferred to the multiple memory packages 152 in larger blocks. The scratch memory 450 may serve as a temporary memory buffer to help optimize the write performance of the multiple memory packages 152. The scratch memory 450 may be used as an intermediate storage for data before it is written to the non-volatile memory cells.

[0175] The direct memory access (DMA) engine 420 included in the controller 400 is a component that transfers data between the NVMe controller 410 and the host memory in the host system without involving the host processor. The DMA engine 420 can support the NVMe controller 410 to directly read data from or write data to the host memory without the intervention of the host processor. According to embodiments, the DMA engine 420 can use DMA descriptors that include information about data transfers (e.g., buffer addresses, transfer lengths, and other control information) to implement or support high-speed data transfers between the host and the NVMe device.

[0176] The LDPC sequencer 460 in the controller 400 is a component that performs error correction on data stored in a plurality of memory packages 152. Here, the LDPC code is a type of error correction code commonly used in NAND flash memories to reduce bit error rates. The LDPC sequencer 460 may be designed to immediately process encoding and decoding of LDPC codes when reading data from and writing data to the NAND flash memory. According to an embodiment, the LDPC sequencer 460 may divide data into a plurality of blocks, encode each block using an LDPC code, and store the encoded data in a plurality of memory packages 152. Thereafter, when the encoded data is read from the plurality of memory packages 152, the LDPC sequencer 460 may decode the encoded data based on the LDPC code and correct errors that may occur during write or read operations. The LDPC sequencer 460 may correspond to Figure 12 The ECC circuit 266 described in .

[0177] Figure 12 and Figure 13 The controllers 130 and 400 described in

[15] can manage and control status information about memory blocks within the memory devices 150 and 152. For example, the controllers 130 and 400 can control and update mapping information for read operations or program operations, and check and update program-erase cycles (P / E cycles) that estimate or indicate the wear level of the memory blocks for wear leveling. In addition, the controllers 130 and 400 can check read counts among the operation information about the memory blocks. Furthermore, the controllers 130 and 400 can have structural information about the internal configuration (e.g., string sharing) of the memory devices 150 and 152.

[0178] The controller 130, 400 can read or load firmware from the memory device 150, 152 for internal operation. During the process of reading or loading firmware, stress or read disturbance may occur in the location where the firmware is stored and its surrounding locations. Figures 7 to 11 The devices and operating methods described herein may reduce or avoid degradation of operational security due to stress or read disturbance associated with multiple firmware copies stored in the memory devices 150 , 152 .

[0179] To ensure operational security of the firmware, the controller 130, 400 may perform data migration, read retry operations, etc. based on read counts and / or erase / write cycles (E / W cycles). In this way, the memory system can reduce errors in the process of reading or loading firmware stored in the memory devices 150, 152 and improve data input / output performance.

[0180] As described above, a memory device or memory system according to an embodiment of the present disclosure can distribute and store multiple firmware copies, manage the read count of each plane or page storing each of the multiple firmware copies, and alternately read the distributed stored firmware copies, thereby preventing or avoiding a decrease in operational security regarding the firmware copy stored in a specific location.

[0181] Furthermore, a memory device or a memory system according to an embodiment of the present disclosure may improve operational efficiency and stability by increasing the service life of a memory block storing firmware.

[0182] The methods, processes and / or operations described herein can be performed by the code or instructions run by a computer, processor, controller or other signal processing device. The computer, processor, controller or other signal processing device can be the device described herein, or an element outside the element described herein. Since the algorithm constituting the operation of the method basis or the computer, processor, controller or other signal processing device is described in detail, the code or instructions for implementing the operation of the method embodiment can convert the computer, processor, controller or other signal processing device into a special-purpose processor for performing the method herein.

[0183] Furthermore, another embodiment may include a computer-readable medium, such as a non-transitory computer-readable medium, for storing the above-mentioned code or instructions. The computer-readable medium may be a volatile or non-volatile memory or other storage device that is removably or fixedly coupled to a computer, processor, controller, or other signal processing device to execute the code or instructions for performing the operations of the method embodiments or apparatus embodiments herein.

[0184] The controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features of the embodiments disclosed herein may be implemented, for example, as non-transient logic, which may include hardware, software, or both. When implemented at least partially as hardware, the controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features may be, for example, any of a variety of integrated circuits, including but not limited to application specific integrated circuits, field programmable gate arrays, combinations of logic gates, systems on a chip, microprocessors, or other types of processing or control circuitry.

[0185] When implemented at least in part in software, the controller, processor, control circuit, device, module, unit, multiplexer, generator, logic, interface, decoder, driver and other signal generation and signal processing features may include, for example, a memory or other storage device for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller or other signal processing device. The computer, processor, microprocessor, controller or other signal processing device may be the device described herein, or an element other than the elements described herein. Since the algorithms that form the basis of the method or the operation of the computer, processor, microprocessor, controller or other signal processing device are described in detail, the code or instructions for implementing the operation of the method embodiments can convert the computer, processor, controller or other signal processing device into a dedicated processor for performing the method described herein.

[0186] Although the embodiments of the present disclosure have been described with respect to specific embodiments, it will be apparent to those skilled in the art in view of the present disclosure that various changes and modifications may be made without departing from the spirit and scope of the present disclosure as defined in the appended claims. Furthermore, the embodiments may be combined to form other embodiments.

Claims

1. A memory system comprising: a memory device including firmware distributed and stored in multiple locations; as well as The controller reads the firmware from a different location selected from among the plurality of locations each time the firmware is loaded.

2. The memory system according to claim 1, wherein: The controller reads the firmware from a second location among the plurality of locations at a second time after reading the firmware from a first location among the plurality of locations at a first time, wherein stress or interference occurs due to the read operation performed at the first location.

3. The memory system according to claim 2, wherein: A first page included in the first position and a second page included in the second position respectively include memory cells coupled to the same word line.

4. The memory system according to claim 3, wherein: Memory cells included in the first page and the second page are disposed on the same memory layer.

5. The memory system according to claim 1, wherein: The controller selects a location having at least one of a lowest read count and a lowest program / erase cycle from among the plurality of locations after power is supplied, and loads firmware stored in the selected location. The memory system according to claim 1 , wherein: Each of the plurality of locations includes a plurality of pages contained in a different memory block or a different memory plane.

7. The memory system according to claim 6, wherein: The plurality of pages are consecutive pages.

8. The memory system according to claim 6, wherein: The controller reads firmware including several parts stored in the plurality of pages, each part being stored in the different memory block or the different memory plane.

9. The memory system according to claim 8, wherein: The controller reads a first portion of the firmware from a first memory plane in the memory device and reads a second portion different from the first portion from a second memory plane in the memory device.

10. The memory system according to claim 1, wherein: The controller further: generating or updating at least one of a read count and a program / erase cycle count for at least one memory block, at least one memory plane, or at least one memory page associated with the plurality of locations; and At least one of the generated or updated read count and program / erase cycles is stored in the memory device.

11. The memory system according to claim 8, wherein: The controller further selects access locations of the firmware such that a deviation of at least one of a read count and a program / erase cycle for each of the plurality of locations is reduced.

12. A controller coupled to a memory device, firmware being copied and stored in a plurality of locations in the memory device, wherein: The controller includes at least one processor and at least one memory, and the controller: loading firmware stored in a selected location among the plurality of locations; When the firmware is loaded from the selected location, estimating another location among the plurality of locations where stress or interference occurs; and The estimated location is designated as the selected location for loading the firmware next time.

13. The controller according to claim 12, wherein: The controller further: comparing at least one of a read count and a program / erase cycle for each of the plurality of locations; and A position having the lowest at least one of the read count and the program / erase cycle count among the plurality of positions is designated as the selected position.

14. The controller according to claim 12, wherein: Each of the plurality of locations includes a plurality of pages contained in a different memory block or a different memory plane.

15. The controller according to claim 14, wherein: The controller reads firmware including several parts stored in the plurality of pages, each part being stored in the different memory block or the different memory plane.

16. The controller according to claim 12, wherein: The controller further: generating or updating at least one of a read count and a program / erase cycle count in each memory block, each memory plane, and / or each memory page associated with the plurality of locations; and At least one of the generated or updated read count and program / erase cycles is stored in the memory device.

17. The controller according to claim 12, wherein: The controller further selects access locations of the firmware such that a deviation of at least one of a read count and a program / erase cycle for each of the plurality of locations is reduced.

18. A method of operating a memory system, comprising: selecting at least one of a plurality of locations in a memory device, the plurality of locations storing firmware; loading firmware stored in a selected location among the plurality of locations; When the firmware is loaded from the selected location, estimating another location among the plurality of locations where stress or interference occurs; as well as The estimated location is designated as the selected location for loading the firmware next time.

19. The method according to claim 18, further comprising: comparing at least one of a read count and a program / erase cycle for each of the plurality of locations; as well as A position having the lowest at least one of the read count and the program / erase cycle count among the plurality of positions is designated as the selected position.

20. The method of claim 18, further comprising: Access locations of the firmware are selected such that a deviation of at least one of a read count and a program / erase cycle for each of the plurality of locations is reduced.

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