A netlist construction method, computer medium, device and program product

Abstract

The present application relates to the technical field of EDA design and advanced packaging, and particularly relates to a netlist construction method, a computer medium, equipment and a program product. The method comprises the following steps: arranging element bumps and element pins on the surface of a functional element, connecting the element bumps and the element pins by signal lines inside the functional element to construct internal connection paths of the functional element; arranging at least two interposer pins on the surface of an interposer, connecting different interposer pins by signal lines inside the interposer to construct internal connection paths of the interposer; connecting the element pins and the interposer pins by signal lines to construct external connection paths of the interposer; obtaining position information of the element bumps, projecting the element bumps to the surface of the interposer to obtain projection points; arranging projection bumps on the projection points to construct connection paths; and connecting the projection bumps and the connection paths by signal lines inside the interposer to complete construction of the netlist. The method solves the problem that the traditional netlist construction method cannot clearly express the connection relationship of the functional element.

Description

Technical Field

[0001] This invention relates to the fields of EDA design technology and advanced packaging technology, and particularly to a netlist construction method, computer media, device and program product. Background Technology

[0002] 2.5D chip design is an advanced integrated circuit packaging technology. It involves placing multiple independent, pre-fabricated functional chips, also known as functional elements, side-by-side on a shared silicon interposer. These chips, along with the interposer itself, are then connected to the underlying packaging substrate via high-density interconnects within the interposer, ultimately forming a fully functional system. Traditional 2D chip design relies on the packaging substrate, limiting interconnect density and performance. 3D chip design, on the other hand, offers the highest density and performance potential but faces significant challenges in thermal management and cost.

[0003] Existing 2.5D chip design methods typically construct a 2.5D netlist by parsing a standard Verilog file. Verilog is a language that mainly describes the functional logic connections of circuits. Directly constructing a netlist using a parsed language cannot directly and clearly describe the physical hierarchy structure unique to 2.5D packaging, nor can it clearly express the connection relationships between functional components. Summary of the Invention

[0004] To address the problem that traditional netlist construction methods cannot clearly express the connection relationships between functional elements, this invention provides a netlist construction method, computer media, device, and program product.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution: a netlist construction method for designing a chip in a program, the construction method comprising the following steps: providing a substrate, an interposer, signal lines, and at least two functional elements in the program; placing the interposer on one side of the substrate; setting component bumps and component pins on the surface of the functional elements, and connecting the component bumps and component pins inside the functional elements through signal lines to construct internal connection paths of the functional elements; setting at least two interposer pins on the surface of the interposer, and connecting different interposer pins inside the interposer through signal lines to construct internal connection paths of the interposer; placing the functional elements on the side of the interposer away from the substrate, and connecting the component pins and interposer pins through signal lines to construct external connection paths of the interposer; obtaining the position information of the component bumps, and projecting the component bumps onto the surface of the interposer based on the position information to obtain projection points; setting projection bumps on the projection points, and constructing connection paths in the order of functional element internal connection paths, interposer external connection paths, and interposer internal connection paths; connecting the projection bumps and connection paths inside the interposer through signal lines to complete the construction of the netlist.

[0006] Preferably, before providing the substrate, interposer, signal line, and at least two functional elements, the method further includes: providing a functional element template, wherein the functional element template contains the type, length, width, and substrate data of the functional element; obtaining the pre-placement position of the functional element; and instantiating the functional element template based on the pre-placement position to convert the functional element template into a functional element.

[0007] Preferably, the construction of the internal connection path of the functional element specifically includes: importing a first file, which includes the name of the functional element, the name of the element pin, the name of the first signal line, and the name of the element bump; parsing the contents of the first file; wherein, when parsing the name of the functional element, the name of the element pin, and the name of the element bump, the element bump and the element pin are set on the functional element, and when parsing the name of the first signal line, the element bump and the element pin are connected through the first signal line.

[0008] Preferably, the construction of the internal connection path of the intermediary layer specifically includes: importing a second file, which includes the driving type of the pin, the driving purpose of the pin, the name of the intermediary layer pin, and the name of the second signal line; parsing the contents of the second file; wherein, a second signal line needs to connect at least two intermediary layer pins; when parsing the driving type, driving purpose, and name of the pin, a second signal line is set on one intermediary layer pin and a second signal line is set on another intermediary layer pin; when parsing the name of the second signal line, if the names of the second signal lines connecting two different intermediary layer pins are the same, then the two different intermediary layer pins are connected through a second signal line.

[0009] Preferably, the construction of the external connection path of the intermediary layer specifically includes: importing a third file, which includes the name of a functional component, the name of a component pin, the driving type of the pin, the driving purpose of the pin, the name of the intermediary layer pin, and the name of a third signal line; parsing the contents of the third file; wherein, when parsing the driving type of the pin, the driving purpose of the pin, the name of the component pin, and the name of the intermediary layer pin, a third signal line is set on one component pin and a third signal line is set on another intermediary layer pin; when parsing the name of the third signal line, if the names of the third signal lines connecting the component pin and the intermediary layer pin are the same, then the component pin and the intermediary layer pin are connected through a third signal line.

[0010] Preferably, the step of projecting component bumps onto the surface of the intermediary layer based on position information further includes: performing layering processing on the intermediary layer and at least two functional components, so that the functional components and the intermediary layer are divided into multiple hierarchical layers; directly projecting component bumps toward the intermediary layer based on position information; wherein, if different functional components need to establish a connection relationship through the intermediary layer, after the component bumps on different functional components are projected onto the surface of the intermediary layer to form projection points, the formed projection points will be on the same hierarchical layer of the intermediary layer.

[0011] Preferably, the method is applied to 2.5D chip netlist construction. The construction of connection paths according to the order of internal connection paths of functional elements, external connection paths of the interposer layer, and internal connection paths of the interposer layer specifically includes: the constructed connection paths are connected sequentially in the order of element bumps, first signal lines, element pins, third signal lines, interposer layer pins, and second signal lines. To solve the above technical problems, the present invention provides another technical solution as follows: a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, the computer instructions being used to cause the computer to execute the netlist construction method described above.

[0012] To solve the above-mentioned technical problems, the present invention provides another technical solution as follows: a computer device applied to the above-mentioned netlist construction method, including a memory, a processor and a computer program stored in the memory, wherein the processor executes the above-mentioned computer program to implement the netlist construction method.

[0013] To solve the above-mentioned technical problems, the present invention provides another technical solution as follows: a computer program product, including a computer program or instructions, wherein the computer program or instructions implement the above-mentioned netlist construction method when executed by a processor.

[0014] Compared with the prior art, the netlist construction method, computer medium, device, and program product provided by the present invention have the following beneficial effects:

[0015] 1. An embodiment of the present invention provides a netlist construction method for designing a chip in a program. The construction method includes the following steps: providing a substrate, an interposer, signal lines, and at least two functional elements in the program; placing the interposer on one side of the substrate; setting component bumps and component pins on the surface of the functional elements, and connecting the component bumps and component pins inside the functional elements through signal lines to construct internal connection paths of the functional elements; setting at least two interposer pins on the surface of the interposer, and connecting different interposer pins inside the interposer through signal lines to construct internal connection paths of the interposer; placing the functional elements on the side of the interposer away from the substrate, and connecting the component pins and interposer pins through signal lines to construct external connection paths of the interposer; obtaining the position information of the component bumps, and projecting the component bumps onto the surface of the interposer based on the position information to obtain projection points; setting projection bumps on the projection points, and constructing connection paths in the order of functional element internal connection paths, interposer external connection paths, and interposer internal connection paths; connecting the projection bumps and connection paths inside the interposer through signal lines to complete the construction of the netlist. In this embodiment, by using a program to confirm the positional relationship between the virtual substrate, interposer, and functional components, and then projecting the component bumps, errors in the parsed file or human input errors can be eliminated. In addition, this embodiment limits the path construction order to avoid path intersection conflicts, realizes automated reconstruction of netlist construction, and clearly expresses the connection relationship between functional components while ensuring connection reliability.

[0016] 2. This invention also provides a computer-readable storage medium that has the same beneficial effects as the above-described netlist construction method, and will not be described in detail here.

[0017] 3. This invention also provides a computer device that has the same beneficial effects as the above-described netlist construction method, which will not be described in detail here.

[0018] 4. A computer program product provided in this embodiment of the invention includes a computer program or instructions, which, when executed by a processor, implement the above-described netlist construction method. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart illustrating a netlist construction method provided in the first embodiment of the present invention.

[0021] Figure 2a This is a schematic diagram illustrating the construction of internal connection paths of functional elements in a netlist construction method provided in the first embodiment of the present invention.

[0022] Figure 2b This is a simplified diagram of the construction of the internal connection path of the intermediate layer in a netlist construction method provided in the first embodiment of the present invention.

[0023] Figure 2c This is a simplified diagram of the construction of the intermediate layer and the connection path of functional elements in a netlist construction method provided in the first embodiment of the present invention.

[0024] Figure 3a This is a simplified diagram of the component bumps in the 3D chip when they are projected in the first embodiment of the present invention.

[0025] Figure 3b This is a schematic diagram of the component bumps projected onto a 2.5D chip in the first embodiment of the present invention.

[0026] Figure 4a This is a schematic diagram illustrating the construction of internal connection paths of functional elements in a netlist construction method provided in the first embodiment of the present invention.

[0027] Figure 4b This is a schematic diagram illustrating the construction of internal connection paths in the intermediate layer of a netlist construction method provided in the first embodiment of the present invention.

[0028] Figure 4c This is a schematic diagram illustrating the construction of the intermediate layer and the connection path of functional elements in a netlist construction method provided in the first embodiment of the present invention.

[0029] Figure 5 This is a schematic diagram of the projection of different functional elements onto the intermediate layer in the first embodiment of the present invention.

[0030] Figure 6 This is a schematic diagram of the structure of a computer-readable storage medium provided in the second embodiment of the present invention.

[0031] Figure 7 This is a schematic diagram of the structure of a computer device provided in the third embodiment of the present invention.

[0032] Figure 8 This is a schematic diagram of the structure of the computer program product provided in the fourth embodiment of the present invention. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0034] In the embodiments provided by this invention, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B solely based on A; B can also be determined based on A and / or other information.

[0035] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the invention. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Those skilled in the art should also recognize that the embodiments described in the specification are optional embodiments, and the actions and modules involved are not necessarily essential to the invention.

[0036] In various embodiments of the present invention, it should be understood that the sequence number of each process does not necessarily imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0037] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, or they may sometimes be executed in reverse order, depending on the functions involved. It is particularly important to note that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0038] The rapid development of semiconductor integration technology has brought semiconductor process dimensions closer to their physical limits, seemingly ushering in the "post-Moore's Law era." Consequently, the industry has proposed advanced chip packaging technologies to address the ever-increasing demand for high-performance, low-power, and low-latency chips. The 2.5D chip netlist construction method is a crucial step in chip design used to describe and verify the connections between multiple functional elements in a 2.5D heterogeneous integrated system.

[0039] 2.5D chip design is an advanced integrated circuit packaging technology. It involves placing multiple independent, pre-fabricated functional chips, also known as functional elements, side-by-side on a shared silicon interposer. These chips, along with the interposer itself, are then connected to the underlying packaging substrate via high-density interconnects within the interposer, ultimately forming a fully functional system. Traditional 2D chip design relies on the packaging substrate, limiting interconnect density and performance. 3D chip design, on the other hand, offers the highest density and performance potential but faces significant challenges in thermal management and cost.

[0040] Existing 2.5D chip design methods typically construct a 2.5D netlist by parsing a standard Verilog file. Verilog is a language that mainly describes the functional logic connections of circuits. Directly constructing a netlist using a parsed language cannot directly and clearly describe the physical hierarchy structure unique to 2.5D packaging, nor can it clearly express the connection relationships between functional components.

[0041] Silicon interposer: A high-precision silicon-based thin film located between chip functional components (such as CPU, GPU, HBM memory) and the packaging substrate. Its core function is to achieve high-density, low-latency inter-chip interconnection through its internal multi-layer wiring.

[0042] Bump: A miniature solder joint used to establish electrical and mechanical connections between chiplets and interposers, substrates, or other chips. It is an interconnect functional element in 2.5D / 3D packages.

[0043] TSV stands for Through-Silicon Via, a vertical interconnect technology used to enable electrical connections between chips or wafers, particularly in 2.5D and 3D packaging technologies. TSV achieves direct electrical connections between the top and bottom surfaces of a chip or between multiple layers of chips by etching tiny holes in a silicon substrate or chip and filling them with a conductive material (such as copper).

[0044] A functional device refers to a physical chip unit with independent circuitry, such as a computing core (CPU, GPU), memory controller, I / O interface, AI accelerator, etc. Functional devices are integrated as active or passive components onto an interposer layer in a package structure. Furthermore, the interposer layer is a special type of functional device; its function is to act as a carrier to interconnect different functional devices and to connect functional devices to the substrate.

[0045] A device template is a virtual design model of a functional element.

[0046] The difference between 2.5D and 3D chips: In 2.5D chips, functional components are arranged horizontally and placed side-by-side on an interposer. There is no direct communication between the functional components; instead, they are connected via interconnects (TSVs, through-silicon vias) in the interposer. 3D chips, on the other hand, use a vertical stacking method, directly stacking multiple functional components together and interconnecting them via vertical TSVs. It should be noted that the method provided in this invention does not involve fabricating or mounting a physical chip, but rather constructing a virtual netlist file using a program for chip design. Therefore, the substrate, interposer, signal lines, and functional components provided in this embodiment are not physical functional components, but rather virtual functional components in the program. Specifically, the method provided in this application is used for 2.5D chips.

[0047] Please see Figure 1 The first embodiment of the present invention provides a netlist construction method for designing a chip in a program. The construction method includes the following steps:

[0048] S1, within the program, a substrate, an interposer, signal lines and at least two functional elements are provided, and the interposer is placed on one side of the substrate;

[0049] S2, Set component bumps and component pins on the surface of the functional component, and connect the component bumps and component pins inside the functional component through signal lines to construct the internal connection path of the functional component;

[0050] S3, at least two interposer pins are provided on the surface of the interposer layer, and different interposer pins are connected inside the interposer layer by signal lines to construct the internal connection path of the interposer layer;

[0051] S4, Place the functional components on the side of the interposer away from the substrate, and connect the component pins and the interposer pins through signal lines to construct an external connection path for the interposer;

[0052] S5, obtain the position information of the component bump, and project the component bump onto the surface of the interposer layer based on the position information to obtain the projection point;

[0053] S6, Set projection bumps on the projection point, and construct connection paths in the order of internal connection path of functional element, external connection path of intermediary layer and internal connection path of intermediary layer;

[0054] S7 connects the projected bumps and connection paths via signal lines within the intermediate layer to complete the construction of the netlist.

[0055] Understandably, the method provided in this embodiment first deploys the structure, providing three functional components—a substrate, an interposer, and functional elements—within the program environment. The program environment can provide a virtual physics engine, a modeling kernel, and a verification system. It should be understood that directly designing using physical functional components would be extremely costly and resource-intensive, and physical functional components cannot be adjusted or modified. The program environment is the only feasible carrier for netlist construction; it transforms the geometric constraints, electrical rules, and material properties of the physical world into a computable model, automating high-density chip design tasks that are impossible to perform manually through algorithms. Therefore, after providing virtual substrates, interposers, signal lines, and functional elements in this embodiment, the positional relationship between the substrate and the interposer is first defined.

[0056] Furthermore, this embodiment first provides the construction of three types of local connection paths. For example, the first type is the construction of paths within functional elements in step S2: such as... Figure 2a As shown, HBM is the name of the functional component, and bump is the component bump, which is usually set on the surface of the functional component. Pin is the component pin, which is also set on the surface of the functional component. There is usually a certain distance between the component bump and the component pin. The position of the bump is randomly generated. When constructing the path inside the functional component, it is only necessary to connect the component bump and the component pin through the signal line net.

[0057] The second category is the internal path construction of the intermediary layer in step S2: such as... Figure 2b As shown, INTERPROSE is the name of the interposer layer, term1 and term2 are the names of the interposer pins on the interposer layer, and net1 and net2 are the names of the signal lines. When constructing the internal path of the interposer layer, it is only necessary to connect the interposer pins set on the interposer layer through the signal lines.

[0058] The third category is the path construction between cross-level functional elements in step S3: such as... Figure 2c As shown, net3 and net4 are the names of signal lines. When constructing paths between functional components across layers, it is only necessary to connect the functional components and the interposer layer using signal lines. Furthermore, after constructing these three types of local connection paths, the positional relationship between the interposer layer and the functional components is defined, so that the functional components, interposer layer, and substrate can be stacked together in sequence, corresponding to the actual physical functional components.

[0059] Furthermore, regarding the step of extracting the geometric position data of the component bumps and projecting it onto the interposer surface to generate projection points, it should be noted that, since this is a 2.5D chip design, a direct 3D projection is not required in the program. It is sufficient to project the component bumps perpendicularly towards the interposer surface based on their positions to generate a projection point. For example, Figure 3a In the diagram, bump1 is a component bump on the functional element HBM. After bump1 is projected, it is vertically projected onto the surface of the interposer layer near the functional element, forming a projection point. Bump2 is a projection bump set on the projection point. It should be understood that in the 3D view, the position of the projected projection point is related to the placement of the functional element and the interposer layer. Moreover, it can be clearly seen in the 3D view that the projection point of the component bump on the functional element onto the interposer layer is unique.

[0060] Please continue reading. Figure 3b However, when converted to a 2.5D view, because the positional relationship between the functional components and the intermediary layer was determined during the placement of the functional components and the intermediary layer, the projection point of the component bump on the functional component onto the intermediary layer is also unique. That is, each component bump will generate a corresponding projection point after projection. For example, in Figure 3b In this implementation, bump1 is a component bump on the functional element HBM. After projection, bump1 is vertically projected onto the surface of the interposer layer, forming a projection point. Bump2 is a projection bump set on the projection point. It should be understood that this embodiment provides automated connection based on geometric projection. This method extracts the position coordinates of the component bump, such as a 3D coordinate set, and projects them vertically onto the surface of the interposer layer to generate geometric projection points. This operation is completed automatically within the program without manual intervention. Projection bumps are set at the projection points as connection anchor points within the interposer layer. The position of the projection point indicates that when the functional element and the interposer layer are in contact, the component bump and the projection bump can directly contact each other, fulfilling the shortest path requirement for electrical connectivity and minimizing actual signal transmission delay. In other words, this embodiment transforms the connection between the component bump and the interposer layer circuit into a geometric mapping problem that can be automatically calculated within the program. Furthermore, when the position of the functional element is adjusted, the component bump coordinates are updated synchronously. The program automatically reprojects to generate new projection points and dynamically reconstructs the position of the projection bumps. Since the connection path is generated through program rules, the new projection bumps can quickly integrate into the existing path framework, significantly shortening the design iteration cycle.

[0061] Furthermore, after setting up the projection bumps, this embodiment sets the netlist construction order. A complete netlist first needs to integrate three types of local connection paths in sequence: internal paths within functional components (interconnection between component bumps and component pins via signal lines), external paths within the intermediary layer (interconnection between component pins and intermediary layer pins), and internal paths within the intermediary layer (interconnection between intermediary pins via signal lines). This sequence ensures the layer-by-layer closure of the connection paths, completing the connection in the order of component bumps, signal lines, component pins, signal lines, intermediary layer pins, and signal lines. Once the connection paths are closed layer by layer, the projection bumps will be integrated into the system during the internal path stage of the intermediary layer, completing the construction of the entire netlist.

[0062] It should be understood that traditional netlist construction methods, which only parse a standard file, cannot directly and clearly describe the unique physical hierarchy structure of 2.5D packaging, nor can they clearly express the connection relationships between functional components. In this embodiment, by using a program to confirm the positional relationships between the virtual substrate, interposer, and functional components, and then projecting the component bumps, errors from parsing the file or human input errors can be eliminated. Furthermore, this embodiment limits the path construction order to avoid path intersection conflicts, achieving automated reconstruction of the netlist construction, ensuring connection reliability while clearly expressing the connection relationships between functional components.

[0063] Specifically, the process includes providing the substrate, interposer, signal lines, and at least two functional elements, followed by:

[0064] A functional component template is provided, which contains the type, length, width, and substrate data of the functional component.

[0065] Obtain the pre-placement position of the functional element, and instantiate the functional element template based on the pre-placement position to convert the functional element template into a functional element.

[0066] Understandably, this embodiment allows for the pre-definition of digital functional component templates in the program. For example, the template may contain functional component type identifiers, such as CPU, HBM, or GPU; geometric parameters, such as length, width, and thickness; or substrate data, such as the matching substrate model and thermal expansion coefficient constraints. The pre-placement position of the functional component is the input parameter for instantiation. Instantiation is a crucial step in the electronic design process, transforming an abstract functional component template into a concrete design entity. By applying specific layout positions, it converts the local geometric description in the template into absolute coordinates in the global coordinate system and establishes a real-time association between the component instance and the designed substrate, thereby efficiently and consistently generating placeable and connectable functional component objects, significantly improving netlist construction and physical design efficiency. Based on this position data, the program automatically converts local coordinates in the template, such as the offset of pins relative to the center of the functional component, into absolute coordinates in the global coordinate system; it can also bind the positional relationship between the instantiated functional component and the substrate and interposer in real time. In other words, before placing functional components, designers can quickly convert the functional component template into functional components to improve netlist construction efficiency.

[0067] Further, please refer to Figure 4a In step S2 above, constructing the internal connection path of the functional element specifically includes:

[0068] The first file is included, which contains the names of functional components, component pins, first signal lines, and component bumps.

[0069] Parse the contents of the first file;

[0070] Specifically, when parsing the functional component name, component pin name, and component bump name, component bumps and component pins are set on the functional component. When parsing the first signal line name, the component bumps and component pins are connected through the first signal line.

[0071] Understandably, in this embodiment, when constructing local connection paths, the storage medium can be imported as the basis for netlist construction. The first file is a pin_list file, which, after being imported, contains a large number of functional component names, component pin names, first signal line names, and component bump names. For example, Figure 4a In the code, HBM_A is the functional component name, pinWDQSh3_t is the component pin name, and A168 is the component bump name. When parsing the first file, if HBM_A, A168, and pinWDQSh3_t are encountered, the component bump A168 and the component pin pinWDQSh3_t will be automatically set on the functional component HBM_A. When WDQSh3_t is encountered, A168 and pinWDQSh3_t will be automatically connected via the signal line WDQSh3_t to form a pattern as shown below. Figure 4a Local connection paths in the code.

[0072] It should be understood that in this implementation, virtual pins and bumps are automatically generated by parsing file fields: the program creates virtual component pins and bumps on the surface of the functional component according to the component pin names and component bump names in the file, and connects them through signal lines to establish the positional relationship of the component pins and component bumps, realizing seamless transmission of path data inside the functional component and ensuring that the path inside the functional component is closed.

[0073] Further, please refer to Figure 4b In step S3 above, constructing the internal connection path of the intermediary layer specifically includes:

[0074] The second document is introduced, which includes the driving type of the pin, the driving purpose of the pin, the name of the interposer pin, and the name of the second signal line.

[0075] Parse the contents of the second file;

[0076] One of the second signal lines needs to be connected to at least two interposer pins. When resolving the driving type, driving purpose, and interposer pin name of the pin, a second signal line is set on one interposer pin and another interposer pin. When resolving the name of the second signal line, if the names of the second signal lines connected to two different interposer pins are the same, then the two different interposer pins are connected through one second signal line.

[0077] Understandably, the second file is the term_lis file. After being included, the second file contains numerous interposer pin names, their corresponding driver types, and their intended uses. For example, Figure 4b In this context, INTERPOSER is the name of the interposer layer, and pinHBM_A_SD_WDQSh3_t and pinchip_top_A_SD_WDQSh_t[3] are the names of the interposer pins. When parsing the second file, if pinHBM_A_SD_WDQSh3_t and pinchip_top_A_SD_WDQSh_t[3] are parsed, the interposer pins pinHBM_A_SD_WDQSh3_t and pinchip_top_A_SD_WDQSh_t[3] will be automatically set on the interposer layer INTERPOSER. In addition, the driving type and driving purpose of the pin will also be parsed during the pin setting process. It should be noted that there are three types of driving types for the pins, namely input, output and inout. Input means the signal transmitted from inside the interposer layer to the pin, output means the signal transmitted from the pin to inside the interposer layer, and input means the signal transmitted between the interposer layer and the pin. The driving purpose of the pins mainly includes two types: signal purpose and power purpose. The driving of the pins can limit the function of the pins. That is, when parsing the driving type, driving purpose, and pin name of the pin in the intermediary layer, the pin location can be constructed in the intermediary layer. Furthermore, when parsing chip_top_A_SD_WDQSh_t[3], pinHBM_A_SD_WDQSh3_t and pinchip_top_A_SD_WDQSh_t[3] are automatically connected through the signal line chip_top_A_SD_WDQSh_t[3] to form a structure like Figure 4b Local connection paths in the code.

[0078] It should be understood that in this implementation, virtual pins are automatically generated by parsing file fields: the program creates virtual intermediate layer pins on the surface of the intermediate layer according to the intermediate layer pin names in the file, and connects different intermediate layer pins through signal lines, and determines the positional relationship between different intermediate layer pins, thereby realizing seamless transmission of path data within the intermediate layer and ensuring that the path within the intermediate layer is closed.

[0079] Further, please refer to Figure 4c In step S4 above, constructing the external connection path of the intermediary layer specifically includes:

[0080] Introduce a third file, which includes the name of the functional component, the name of the component pin, the drive type of the pin, the purpose of the drive of the pin, the name of the interposer pin, and the name of the third signal line.

[0081] Parse the contents of the third file;

[0082] Specifically, when resolving the driving type, driving purpose, component pin name, and intermediary pin name of a pin, a third signal line is set on one component pin and another intermediary pin. When resolving the name of the third signal line, if the names of the third signal lines connecting the component pin and the intermediary pin are the same, then the component pin and the intermediary pin are connected through a third signal line.

[0083] Understandably, the third file is a term_map file. After the third file is included, the second file contains a large number of functional component names, component pin names, interposer pin names, and pin drive types and uses. For example, Figure 4b In this context, INTERPOSER is the name of the interposer layer, HBM_A and chip_top are the names of the functional components, pinWDQSh3_t and pinWDQSh3_t[3] are the names of the component pins, and pinHBM_A_SD_WDQSh3_t and pinchip_top_A_SD_WDQSh_t[3] are the names of the interposer pins. When parsing the third file, if INTERPOSER, HBM_A, and chip_top are encountered, the component pins on the functional element and the interposer pins on the interposer will be automatically connected. When pinWDQSh3_t and pinHBM_A_SD_WDQSh3_t are encountered, the drive type and drive purpose of pin WDQSh3_t and pinHBM_A_SD_WDQSh3_t will be parsed first. When HBM_A_SD_WDQSh3_t is encountered, the pin pin WDQSh3_t and pin HBM_A_SD_WDQSh3_t will be automatically connected through the signal line HBM_A_SD_WDQSh3_t. The component pin pinWDQSh3_t[3] on the functional component chip_top and the intermediary layer pin pinchip_top_A_SD_WDQSh_t[3] on the intermediary layer are connected through the signal line chip_top_A_SD_WDQSh_t[3], which will not be elaborated further.

[0084] Understandably, in this implementation, by parsing the file fields, the component pins and the interposer pins are automatically connected via signal lines according to the driving type and driving purpose of the pins, and the positional relationship between the component pins and the interposer pins is determined, realizing seamless transmission of path data between the functional component and the interposer, and ensuring that the path between the interposer and the functional component is closed.

[0085] Specifically, this invention provides a complete method for constructing a 2.5D netlist. It innovatively uses pin_list, term_list, and term_map as storage media for netlist construction. Compared to Verilog files, the storage method proposed in this embodiment makes it easier to discover the relative relationships between each pin, functional component, and signal line, which is intuitive and clear.

[0086] Specifically, projecting component bumps onto the interposer surface based on location information also includes:

[0087] The intermediate layer and at least two functional elements are layered, so that the functional elements and the intermediate layer are divided into multiple hierarchical layers;

[0088] Based on the location information, the component bumps are projected directly toward the interposer layer;

[0089] If different functional components need to establish a connection through an intermediary layer, the component bumps on different functional components will be projected onto the surface of the intermediary layer to form projection points, and the resulting projection points will be on the same hierarchical layer of the intermediary layer.

[0090] It should be understood that both the interposer layer and functional components are composed of multiple layered structures made of different materials. Signal lines are typically placed on the same layer, and only in special cases are they placed on different layers. Therefore, if different functional components need to be connected together through the same interposer layer, and their connection relationships need to be obtained when building the netlist, it is necessary to project the projected bumps corresponding to the component bumps on different functional components onto the same layer of the interposer layer as much as possible. For example... Figure 5 As shown, functional element HBM1 is divided into n1 layers, with component bump 1 on layer a. Functional element HBM2 is divided into n2 layers, with component bump 3 on layer b. When component bump 1 is projected onto the interposer layer, and when component bump 2 is projected onto the interposer layer to form a projection point, the two projection points will be located on the same hierarchical layer of the interposer layer. Figure 5 As shown, the intermediate layer is divided into n3 layers, and projection bumps bump2 and bump4 are set on the two projection points respectively. Both bump2 and bump4 are located on the c-th layer of the intermediate layer.

[0091] Furthermore, the method provided in this embodiment is applied to 2.5D chip netlist construction. The construction of connection paths, specifically following the order of internal connection paths for functional elements, external connection paths for interposers, and internal connection paths for interposers, includes the following: the constructed connection paths are connected sequentially in the order of element bumps, first signal lines, element pins, third signal lines, interposer pins, and second signal lines. It should be understood that existing methods cannot obtain the connection relationships between these elements. This embodiment limits the path construction order, avoids path intersection conflicts, achieves automated reconstruction of the netlist construction, and clearly expresses the connection relationships between functional elements while ensuring connection reliability.

[0092] Please combine Figure 1 and Figure 6 The second embodiment of this invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions for causing the computer to execute the netlist construction method described above.

[0093] The computer-readable storage medium provided in this embodiment of the invention has the same beneficial effects as the above-described netlist construction method, and will not be described in detail here.

[0094] Please combine Figure 1 and Figure 7 The third embodiment of this invention also provides a computer device applied to the above-described netlist construction method, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the netlist construction method.

[0095] The computer device provided in this embodiment of the invention has the same beneficial effects as the above-described netlist construction method, and will not be described in detail here.

[0096] Please combine Figure 1 and Figure 8 The fourth embodiment of this invention also provides a computer program product, including a computer program or instructions, which, when executed by a processor, implement the above-described netlist construction method.

[0097] The computer program product provided in this embodiment of the invention has the same beneficial effects as the above-described netlist construction method, and will not be described in detail here.

[0098] The foregoing has provided a detailed description of a netlist construction method, computer medium, device, and program product disclosed in the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention. Any modifications, equivalent substitutions, and improvements made within the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A netlist construction method for designing chips in a program, characterized in that: The construction method includes the following steps: The program provides a substrate, an interposer, signal lines, and at least two functional components, with the interposer placed on one side of the substrate. Component bumps and component pins are set on the surface of the functional component, and the component bumps and component pins are connected by signal lines inside the functional component to construct the internal connection path of the functional component. At least two interposer pins are provided on the surface of the interposer layer, and different interposer pins are connected inside the interposer layer by signal lines to construct the internal connection path of the interposer layer. The functional components are placed on the side of the interposer away from the substrate, and the component pins and interposer pins are connected by signal lines to construct the external connection path of the interposer; Obtain the position information of the component bumps, and project the component bumps onto the surface of the interposer layer based on the position information to obtain the projection points; Set projection bumps on the projection point, and construct the connection path in the order of internal connection path of functional element, external connection path of intermediary layer, and internal connection path of intermediary layer. The netlist is constructed by connecting the projected bumps and connection paths through signal lines within the intermediate layer.

2. The netlist construction method as described in claim 1, characterized in that: Before providing the substrate, interposer, signal lines, and at least two functional elements, it also includes: A functional component template is provided, which contains the type, length, width, and substrate data of the functional component. Obtain the pre-placement position of the functional element, and instantiate the functional element template based on the pre-placement position to convert the functional element template into a functional element.

3. The netlist construction method as described in claim 2, characterized in that: The internal connection paths of the constructed functional elements specifically include: The first file is included, which contains the names of functional components, component pins, first signal lines, and component bumps. Parse the contents of the first file; Specifically, when parsing the functional component name, component pin name, and component bump name, component bumps and component pins are set on the functional component. When parsing the first signal line name, the component bumps and component pins are connected through the first signal line.

4. The netlist construction method as described in claim 2, characterized in that: The specific steps for constructing the internal connection path of the intermediary layer include: The second document is introduced, which includes the driving type of the pin, the driving purpose of the pin, the name of the interposer pin, and the name of the second signal line. Parse the contents of the second file; One of the second signal lines needs to be connected to at least two interposer pins. When resolving the driving type, driving purpose, and interposer pin name of the pin, a second signal line is set on one interposer pin and another interposer pin. When resolving the name of the second signal line, if the names of the second signal lines connected to two different interposer pins are the same, then the two different interposer pins are connected through one second signal line.

5. The netlist construction method as described in claim 2, characterized in that: The construction of the external connection path for the intermediary layer specifically includes: Introduce a third file, which includes the name of the functional component, the name of the component pin, the drive type of the pin, the purpose of the drive of the pin, the name of the interposer pin, and the name of the third signal line. Parse the contents of the third file; Specifically, when resolving the driving type, driving purpose, component pin name, and intermediary pin name of a pin, a third signal line is set on one component pin and another intermediary pin. When resolving the name of the third signal line, if the names of the third signal lines connecting the component pin and the intermediary pin are the same, then the component pin and the intermediary pin are connected through a third signal line.

6. The netlist construction method as described in claim 1, characterized in that: The method of projecting component bumps onto the interposer surface based on location information also includes: The intermediate layer and at least two functional elements are layered, so that the functional elements and the intermediate layer are divided into multiple hierarchical layers; Based on the location information, the component bumps are projected directly toward the interposer layer; If different functional components need to establish a connection through an intermediary layer, the component bumps on different functional components will be projected onto the surface of the intermediary layer to form projection points, and the resulting projection points will be on the same hierarchical layer of the intermediary layer.

7. The netlist construction method as described in claim 6, characterized in that: The method is applied to 2.5D chip netlist construction. The specific steps of constructing the connection paths in the order of functional element internal connection paths, interposer external connection paths, and interposer internal connection paths include: The constructed connection path will be connected in the following order: component bump, first signal line, component pin, third signal line, interposer pin, and second signal line.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions for causing the computer to perform the netlist construction method according to any one of claims 1 to 7.

9. A computer device, applied to the netlist construction method as described in any one of claims 1 to 7, characterized in that: The system includes a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the netlist construction method.

10. A computer program product, characterized in that: It includes a computer program or instructions that, when executed by a processor, implement the netlist construction method described in any one of 1 to 7.

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