Gate driving circuit and display device including the same

Abstract

The present disclosure relates to a micro LED display device, and relates to a display device capable of stably driving a gate driver in an active gate (GIA) circuit. According to the present disclosure, a gate driver in a GIA circuit of a display device can be stably driven without a horizontal line defect.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0029526, filed on February 29, 2024. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a gate driving circuit and a micro LED display device including the gate driving circuit. Background Art

[0004] As society progresses towards an information-based society, the field of display devices that visually represent electrical information signals is rapidly developing. Consequently, various display devices have been developed that are thin, lightweight, and have excellent performance in terms of low power consumption.

[0005] Specific examples of the display device include a liquid crystal display device (LCD), an organic light emitting display device (OLED), a quantum dot display device, a micro light emitting display device (LED) (μLED), and the like.

[0006] Such a display device uses a timing controller, a data driver, a gate driving circuit, and a display panel to perform its operation. Summary of the Invention

[0007] As display devices become thinner, technologies for embedding gate driver circuits in display panels have been developed. Gate driver circuits built into such display panels are known as gate in panel (GIP) circuits and gate in active (GIA) circuits.

[0008] A GIA circuit of a micro LED (μLED) display device is built into a display panel together with a pixel array. The present invention aims to enable at least one gate driver in the GIA circuit to be stably driven without horizontal defects.

[0009] These and other objects are solved by the subject-matter of the independent claims. Refined and advantageous embodiments are defined by the respective dependent claims.

[0010] According to an embodiment of the present disclosure, a micro-LED display device may include: a display panel having a plurality of pixel arrays disposed thereon; and a gate active (GIA) circuit that provides a scan signal to the pixel array, wherein a plurality of clock lines may be connected to the display panel, wherein the GIA circuit may include a first transistor connected to the plurality of clock lines, wherein the first transistor may be disposed along the plurality of clock lines. The clock lines may also be denoted as clock signal lines. The clock lines may extend along a straight line and / or extend in parallel and / or extend along a first direction.

[0011] The active gate circuit may include or may be a gate driver circuit disposed in an active area of ​​the display panel and / or disposed in an area where a plurality of sub-pixels or a pixel array is provided.

[0012] The first direction may refer to the direction along which the data lines are arranged. The second direction may refer to the direction along which the gate lines or scan lines connected to the sub-pixels are arranged. The second direction may be perpendicular to the first direction. Multiple pixel arrays or multiple sub-pixels may be arranged on the display panel.

[0013] The first transistors may each be disposed along and / or on and / or adjacent to a corresponding one of the plurality of clock lines connected thereto.

[0014] The GIA circuit may further include a second transistor connected to the positive start signal, wherein the second transistor may be set according to the positive start signal.

[0015] The GIA circuit may further include a third transistor connected to the reverse start signal, wherein the third transistor may be set according to the reverse start signal.

[0016] The GIA circuit may include a first gate driver that provides a first scan signal to the sub-pixel and a second gate driver that provides a second scan signal to the sub-pixel.

[0017] The first gate driver and the second gate driver may further include: a fourth transistor including a gate connected to the QB node, a source connected to the gate high voltage, and a drain connected to the Nth scan signal; and a first transistor including a gate connected to the Q node, a source connected to the Nth scan signal, and a drain connected to the Nth clock signal.

[0018] The first gate driver and the second gate driver may further include a capacitor disposed between the Nth scan signal and the Q node.

[0019] A pulse width of the second scan signal may be smaller than a pulse width of the first scan signal, and a pulse width for applying the data voltage may be larger than a pulse width of the first scan signal.

[0020] The display panel may include a first GIA area, a second GIA area, and a third GIA area. The first to third GIA areas may be arranged along a second direction. Each of the first to third GIA areas may include a plurality of first gate drivers arranged along the first direction and a plurality of second gate drivers arranged along the first direction.

[0021] According to an embodiment, a display panel may include: a plurality of pixel arrays; and an active gate (GIA) circuit, wherein the active gate (GIA) circuit provides a scan signal to the pixel array, wherein a plurality of clock lines may be connected to the display panel, wherein the GIA circuit may include a first transistor connected to the plurality of clock lines, wherein the first transistor may be arranged along the plurality of clock lines.

[0022] The GIA circuit may further include a second transistor connected to the positive start signal, wherein the second transistor may be set according to the positive start signal.

[0023] The GIA circuit may further include a third transistor connected to the reverse start signal, wherein the third transistor may be set according to the reverse start signal.

[0024] The GIA circuit may include a first gate driver that provides a first scan signal to the sub-pixel and a second gate driver that provides a second scan signal to the sub-pixel.

[0025] The first gate driver and the second gate driver may further include: a fourth transistor including a gate connected to the QB node, a source connected to the gate high voltage, and a drain connected to the Nth scan signal; and a first transistor including a gate connected to the Q node, a source connected to the Nth scan signal, and a drain connected to the Nth clock signal.

[0026] The first gate driver and the second gate driver may further include a capacitor disposed between the Nth scan signal and the Q node.

[0027] A pulse width of the second scan signal may be smaller than a pulse width of the first scan signal, and a pulse width for applying the data voltage may be larger than a pulse width of the first scan signal.

[0028] The GIA circuit may be provided on the first GIA region, the second GIA region, and the third GIA region.

[0029] A display panel is used for a micro LED display device, the display panel comprising: a plurality of pixel arrays (PXL), each of the pixel arrays comprising a plurality of sub-pixels (SP); and an active gate circuit (700), i.e., a GIA circuit (700), the GIA circuit being configured to provide at least one scan signal (SCAN1, SCAN2) to each of the pixel arrays (PXL), wherein a plurality of clock lines are used to supply clock signals (CLK1, ..., CLK8), each of the clock lines extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction, wherein the GIA circuit (700) comprises a plurality of first transistors (T7) connected to the plurality of clock lines, wherein the first transistors (T7) are arranged along the plurality of clock lines connected to the first transistors.

[0030] The display panel (100) includes a plurality of horizontal lines (HL1, ...HLN) extending along the second direction, wherein the first transistor (T7) of the first gate driver (GD1) on the first horizontal line (HL1) is connected to the clock line for supplying a first clock signal (CLK1), and the first transistor (T7) of the second gate driver (GD2) on the first horizontal line (HL1) is connected to the clock line for supplying a second clock signal (CLK2), wherein the first transistor (T7) of the first gate driver (GD1) on the second horizontal line (HL2) is connected to the clock line for supplying a third clock signal (CLK3), and the first transistor (T7) of the second gate driver (GD2) on the second horizontal line (HL2) is connected to the clock line for supplying a third clock signal (CLK4). The clock line of the fourth clock signal (CLK4), wherein the first transistor (T7) of the first gate driver (GD1) on the third horizontal line (HL3) is connected to the clock line for supplying a fifth clock signal (CLK5), and the first transistor (T7) of the second gate driver (GD2) on the third horizontal line (HL3) is connected to the clock line for supplying a sixth clock signal (CLK6), and wherein the first transistor (T7) of the first gate driver (GD1) on the fourth horizontal line (HL4) is connected to the clock line for supplying a seventh clock signal (CLK7), and the first transistor (T7) of the second gate driver (GD2) on the fourth horizontal line (HL4) is connected to the clock line for supplying an eighth clock signal (CLK8).

[0031] In the display panel, the multiple clock lines connected to the first gate driver (GD1) are arranged along the second direction in the following order: the clock line for supplying the first clock signal (CLK1), the clock line for supplying the third clock signal (CLK3), the clock line for supplying the fifth clock signal (CLK5) and the clock line for supplying the seventh clock signal (CLK7); or the clock line for supplying the first clock signal (CLK1), the clock line for supplying the fifth clock signal (CLK5), the clock line for supplying the third clock signal (CLK3) and the clock line for supplying the seventh clock signal (CLK7); or the clock line for supplying the third clock signal (CLK3), the clock line for supplying the seventh clock signal (CLK7), the clock line for supplying the first clock signal (CLK1) and the clock line for supplying the fifth clock signal (CLK5). BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0033] Figure 2 、 Figure 3 and Figure 4 is a block diagram illustrating a display panel according to an embodiment of the present disclosure.

[0034] Figure 5 is a circuit diagram illustrating a sub-pixel of a display device according to an embodiment of the present disclosure.

[0035] Figure 6 is a block diagram illustrating a gate driver according to an embodiment of the present disclosure.

[0036] Figure 7 is a circuit diagram illustrating a gate driver according to an embodiment of the present disclosure.

[0037] Figure 8 is a timing diagram of sub-pixels according to an embodiment of the present disclosure.

[0038] Figure 9 is a timing diagram of a gate driver according to an embodiment of the present disclosure.

[0039] Figure 10 is a layout diagram illustrating clock signals and a gate driver according to an embodiment of the present disclosure.

[0040] Figure 11 is a layout diagram illustrating transistors of a gate driver according to an embodiment of the present disclosure.

[0041] Figure 12FIG. 4 is a layout diagram illustrating the distance from transistor T1 to transistor T7 of a gate driver and the timing of signal transmission according to an embodiment of the present disclosure.

[0042] Figure 13 is a layout diagram showing a clock signal and a gate driver according to a first embodiment of the present disclosure.

[0043] Figure 14 is a layout diagram showing transistors of a gate driver according to the first embodiment of the present disclosure.

[0044] Figure 15 1 is a layout diagram illustrating the distance from the transistor T1 to the transistor T7 of the gate driver and the signal transmission time according to the first embodiment of the present disclosure.

[0045] Figure 16 is a layout diagram showing a clock signal and a gate driver according to a second embodiment of the present disclosure.

[0046] Figure 17 is a layout diagram showing transistors of a gate driver according to a second embodiment of the present disclosure.

[0047] Figure 18 is a layout diagram illustrating the distance from the transistor T1 to the transistor T7 of the gate driver and the time at which a signal arrives according to the second embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] The advantages and features of the present disclosure, as well as methods for achieving these advantages and features, will become apparent through the embodiments described below in conjunction with the accompanying drawings. However, the present disclosure is not limited to these embodiments and may be implemented in various variations. These embodiments are provided solely to fully disclose the present disclosure and to inform those skilled in the art of the scope of the present disclosure. The present disclosure is limited only by the appended claims.

[0049] The shapes, sizes, proportions, angles, quantities, etc. disclosed in the drawings for illustrating the embodiments of the present disclosure are exemplary, and the embodiments are not limited thereto. Throughout the specification, the same reference numerals represent substantially the same elements. In addition, in the following description of the embodiments, when it is determined that a detailed description of known related art may unnecessarily obscure the main purpose of the embodiments, it will be omitted.

[0050] Where terms such as “including,” “comprising,” “having,” and “complete” are used in this specification, other parts may be added unless “only” is used. As used herein, singular forms are intended to include plural forms as well, unless the context clearly indicates otherwise.

[0051] When interpreting constituent elements, they are deemed to include a range of error even if there is no separate explanation.

[0052] In the case of describing a positional relationship, for example, if the positional relationship between two parts is described as "on," "above," "below," or "beside," one or more other parts may be located between the two parts, unless "immediately" or "directly" is used.

[0053] Terms such as "first" and "second" may be used to distinguish between various components. However, the function or structure of a component is not limited by the name of the component and the serial number prefixed to the component name.

[0054] The following embodiments of the present disclosure may be combined with each other in part or in whole, and may be driven in a technically related manner in various ways. The embodiments may be implemented independently or in combination with each other.

[0055] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following embodiments, a display device will be described with respect to micro LEDs (μLEDs), but the present disclosure is not limited thereto.

[0056] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0057] Reference Figure 1 , a display device according to an embodiment of the present disclosure may include a display panel 100 , a timing controller 200 , a gate driver 300 , a data driver 400 , a power driver 500 , and a gamma driver 600 .

[0058] The display panel 100 includes a pixel array that displays an input image on a screen. The pixel array may include a plurality of data lines DL, a plurality of scan lines SL crossing the data lines DL, and sub-pixels SP arranged in a matrix form.

[0059] The display panel 100 may be implemented as a non-light-transmitting display panel or a light-transmitting display panel. The display panel 100 may be manufactured as a flexible display panel. The flexible display panel may be implemented as a micro LED (μLED) using a plastic substrate.

[0060] The timing controller 200 can receive digital image data (Data) of an input image and timing signals (Vsync, Hsync, and Clk) synchronized therewith from a set system. The digital image data (Data) is a differential signal and can be serial data. The timing signals may include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), and a clock (Clk). The set system may include televisions, monitors, set-top boxes, navigation systems, personal computers, home theater systems, mobile devices, wearable devices, and in-vehicle systems.

[0061] The timing controller 200 can control the operating timing of the display panel 100 according to the input frequency. The input frequency can be 60Hz in the National Television Standards Committee (NTSC) format. Recently, display devices operating at a higher frequency of 120Hz have become popular. In addition, in some cases, a display device operating at 120Hz can be temporarily controlled to operate at 60Hz. In addition, recently, a display device supporting a variable refresh rate (VRR) is also being developed. The display device of the variable refresh rate (VRR) operates by reducing the frame frequency to between 1Hz and 30Hz in a low-speed drive mode and increasing the frame frequency to 144Hz in a high-resolution video (e.g., a game mode).

[0062] The timing controller 200 can output serial image data Sdata provided to the data driver 400, command data CMD for controlling the data driver 400, a gate control signal GCS for controlling the gate driver 300, and a gamma control signal GMCS for controlling the gamma driver 600 based on the received timing signals Vsync, Hsync, and Clk.

[0063] The gate driver 300 can be implemented as a gate driving circuit directly formed on the display panel 100 along with the wiring of the TFT array and the pixel array, such as a gate-in-panel (GIP) circuit or a gate-active (GIA) circuit. The gate driver 300 can sequentially output gate signals to the scan lines SL under the control of the timing controller 200. The gate driver 300 can sequentially output signals to the plurality of scan lines SL by shifting the gate signals using a shift register.

[0064] The data driver 400 can convert the input image received as a digital signal from the timing controller 200 into a gamma compensation voltage in each frame period using gamma reference voltages GMAV1 to GMAV10 provided from a digital-to-analog converter (not shown) and the gamma driver 600, and can output the data voltage VDATA. The data driver 400 can be implemented using a plurality of source driver integrated circuits. The data driver 400 can be electrically connected to the data lines DL of the display panel 100 through a chip-on-glass (COG) process or a tape automated packaging (TAB) process.

[0065] The power driver 500 may use a DC-DC converter to output a DC power supply required to drive the pixel array of the display panel 100 and the drivers 300, 400, and 600. The power driver 500 may receive a DC input voltage Vin and generate DC voltages such as a gate high voltage VGH, a gate low voltage VGL, a high potential light emitting voltage EVDD, a low potential light emitting voltage EVSS, and a high potential reference voltage VDD.

[0066] Specifically, the gate high voltage VGH is a voltage set to be higher than a threshold voltage of a transistor formed in the sub-pixel SP. The gate high voltage VGH is output to the gate driver 300 and may be supplied to a level shifter within the gate driver 300.

[0067] The gate low voltage VGL is a voltage lower than a threshold voltage of a transistor formed in the sub-pixel SP. The gate low voltage VGL may be supplied to a level shifter within the gate driver 300.

[0068] The high potential light emitting voltage EVDD is a voltage supplied to an anode of a light emitting device and is a positive voltage for driving the light emitting device. The high potential light emitting voltage EVDD may be supplied to a high potential power supply line connected to each sub-pixel SP within the display panel 100 .

[0069] The low potential light emitting voltage EVSS is a voltage supplied to a cathode of a light emitting device and is a negative voltage for driving the light emitting device. The low potential light emitting voltage EVSS may be supplied to a low potential power line connected to each sub-pixel SP within the display panel 100 .

[0070] The high potential reference voltage VDD is a voltage output to the gamma driver 600. The high potential reference voltage VDD may be used as a reference for generating the gamma reference voltages GMAV1 to GMAV10.

[0071] The gamma driver 600 may receive the high potential reference voltage VDD output from the power driver 500. The gamma driver 600 may receive the gamma control signal GMCS from the timing controller 200, generate gamma reference voltages GMAV1 to GMAV10 having a value between the high potential reference voltage VDD and the ground voltage (0V), and the data driver 400 may output data voltages based on the gamma reference voltages GMAV1 to GMAV10.

[0072] Figure 2 、 Figure 3 and Figure 4 is a block diagram illustrating a display panel according to an embodiment of the present disclosure.

[0073] Reference Figure 2 The display panel 100 may include a first GIA area GIA1, a second GIA area GIA2, and a third GIA area GIA3. Each of the first GIA area GIA1, the second GIA area GIA2, and the third GIA area GIA3 may be provided with a plurality of pixel arrays PXL. A plurality of data drivers 400 may be provided at the bottom of the display panel 100, one data driver being provided for each of the first GIA area GIA1, the second GIA area GIA2, and the third GIA area GIA3.

[0074] For each GIA region, the data driver 400 may be provided at the bottom of the display panel 100. The data driver 400 may supply the data voltage VDATA to the plurality of pixel arrays PXL. In addition, the first gate driver GD1 and the second gate driver GD2 (eg, referring to FIG. 2 ) may be provided. Figures 3 to 5 ) can supply the first scan signal SCAN1 and the second scan signal SCAN2 to the plurality of pixel arrays PXL in each GIA area, respectively.

[0075] Reference Figure 3 and Figure 4 The first GIA area GIA1, the second GIA area GIA2, and the third GIA area GIA3 each include a first gate driver GD1 that generates a first scan signal SCAN1 and a second gate driver GD2 that generates a second scan signal SCAN2. In other words, the GIA circuit 700 may be divided into a plurality of GIA areas GIA1, GIA2, GIA3, ..., and include a plurality of first gate drivers GD1 and a plurality of second gate drivers GD2 disposed in each GIA area and connected to a plurality of sub-pixels SP.

[0076] Reference Figure 3 , the first gate driver GD1 can be set on the left side (GD1 area) of the first GIA area GIA1, the second GIA area GIA2 and the third GIA area GIA3, and the second gate driver GD2 can be set on the right side (GD2 area) of the first GIA area GIA1, the second GIA area GIA2 and the third GIA area GIA3.

[0077] In addition, the first gate driver GD1 can be set on the right side (GD2 area) of the first GIA area GIA1, the second GIA area GIA2 and the third GIA area GIA3, and the second gate driver GD2 can be set on the left side (GD1 area) of the first GIA area GIA1, the second GIA area GIA2 and the third GIA area GIA3.

[0078] exist Figure 3 In the embodiment, although the first gate driver GD1 and the second gate driver GD2 are shown as being provided for each horizontal line HL in the first area GIA1, the second area GIA2, and the third area GIA3, they may also be provided across multiple horizontal lines HL. The horizontal lines HL may extend along the second direction. One horizontal line may correspond to a row of sub-pixels.

[0079] Reference Figure 4 , the first gate driver GD1 and the second gate driver GD2 may be disposed on a center line CL of each of the first area GIA1, the second area GIA2, and the third area GIA3. Figure 4, although the first gate driver GD1 and the second gate driver GD2 are shown as being disposed only on the center line CL of each of the first area GIA1, the second area GIA2, and the third area GIA3, the first gate driver GD1 and the second gate driver GD2 may be disposed partially across a horizontal line HL of the first area GIA1, the second area GIA2, and the third area GIA3.

[0080] Figure 5 is a circuit diagram illustrating a sub-pixel of a display device according to an embodiment of the present disclosure.

[0081] Reference Figure 1 and Figure 5 , the sub-pixel SP can be connected to the data driver 400 through the data line DL. In addition, the sub-pixel SP can be connected to the GIA circuit 700 through the first scan line SL1 and the second scan line SL2. Therefore, the sub-pixel SP can receive the data voltage VDATA from the data driver 400 and the first scan signal SCAN1 and the second scan signal SCAN2 from the GIA circuit 700.

[0082] Reference Figure 2 and Figure 5 , the plurality of pixel arrays PXL include Figure 5 The sub-pixel SP shown in FIG. 1 may include a portion of transistors of the GIA circuit 700 that provides scan signals SCAN1 and SCAN2 to the scan lines SL1 and SL2 of the sub-pixel SP. Figure 10 and Figure 12 This is explained in more detail.

[0083] Reference Figure 5 , the sub-pixel SP may include a micro LED μLED, a driving transistor D-TFT, a storage capacitor Cst, a first transistor M1 and a second transistor M2.

[0084] The micro-LED μLED emits light according to the driving current. The micro-LED μLED may include an anode and a cathode, the drain of the driving transistor D-TFT may be connected to the anode, and the low potential light emitting voltage EVSS may be connected to the cathode.

[0085] The driving transistor D-TFT is coupled between the micro LED μLED and the high-voltage emission voltage EVSS. It can control the driving current to emit light based on the data voltage VDATA applied to the gate. The driving transistor D-TFT may include a source electrode, a gate electrode, and a drain electrode. The gate electrode of the driving transistor D-TFT corresponds to a first node N1, and the drain electrode corresponds to a second node N2. The high-voltage emission voltage EVDD may be connected to the source electrode of the driving transistor D-TFT.

[0086] The storage capacitor Cst may be connected between the gate and drain of the driving transistor D-TFT. The storage capacitor Cst may sample the data voltage VDATA when the first transistor M1 is turned on and may boost the gate of the driving transistor D-TFT.

[0087] The first transistor M1 may be connected between the data line DL and the gate electrode of the driving transistor D-TFT. In addition, the first transistor M1 may be connected between the data line DL and one electrode of the storage capacitor Cst.

[0088] The data voltage VDATA is applied to the data line DL, and the first transistor M1 may transmit the data voltage VDATA to the first node N1 in response to the first scan signal SCAN1 applied through the first scan line SL1 .

[0089] The second transistor M2 is connected between a power line to which a reference voltage VREF is applied and a second node N2. The second transistor M2 may precharge the second node N2 with the reference voltage VREF in response to a second scan signal SCAN2 applied through the second scan line SL2.

[0090] According to an embodiment, the driving transistor D-TFT, the first transistor M1, and the second transistor M2 may be implemented as low-temperature polycrystalline oxide (LTPS) transistors or oxide semiconductor transistors, but are not limited thereto. For example, the driving transistor D-TFT, the first transistor M1, and the second transistor M2 may be formed of P-type oxide thin film transistors or N-type oxide thin film transistors.

[0091] The sub-pixel SP according to the embodiment of the present disclosure is not limited thereto and may further include transistors and capacitors in addition to the micro LED μLED, the driving transistor D-TFT, and the storage capacitor Cst. In addition, a portion of the transistors of the GIA circuit 700 may be included between the plurality of sub-pixels SP.

[0092] Figure 6 is a block diagram illustrating a gate driver according to an embodiment of the present disclosure.

[0093] Reference Figure 5 and Figure 6 , the GIA circuit 700 may include two gate drivers GD, a first gate driver GD1 and a second gate driver GD2.

[0094] Figure 6 The gate driver shown may be a first gate driver GD1 that generates a first scan signal SCAN1 or a second gate driver GD2 that generates a second scan signal SCAN2 .

[0095] Reference Figure 5 and Figure 6 The first gate driver GD1 may generate a first scan signal SCAN1 and provide the first scan signal SCAN1 to the first transistor M1 of the sub-pixel SP. The first transistor M1 may provide a data voltage VDATA to the sub-pixel SP in response to the first scan signal SCAN1. Furthermore, the second gate driver GD2 may generate a second scan signal SCAN2 and provide the second scan signal SCAN2 to the second transistor M2 of the sub-pixel SP. The second transistor M2 may provide a reference voltage VREF to the second node N2 in response to the second scan signal SCAN2.

[0096] Reference Figure 6 The gate driver GD may include a driving circuit DRIVING CIRCUIT, a transistor T6, and a transistor T7.

[0097] The driving circuit DRIVING CIRCUIT can charge or discharge the QB node or the Q node using at least one of the gate high voltage VGH, the gate low voltage VGL, the front stage voltage FWD and the back stage voltage BWD in response to at least one of the global reset signal QRST, the forward start signal VST_F and the reverse start signal VST_B.

[0098] The gate high voltage VGH can be connected to the source of transistor T6, and the Nth scan signal SCANN can be connected to the drain. In addition, the QB node can be connected to the gate of transistor T6. Transistor T6 can pull up the Nth scan signal SCANN according to the signal of the QB node.

[0099] The Nth scan signal SCANN can be connected to the source of transistor T7, and the Nth clock signal CLKN can be connected to the drain. In addition, the Q node can be connected to the gate of transistor T7. Transistor T7 can pull down the Nth scan signal SCANN according to the signal of the Q node.

[0100] Figure 7 is a circuit diagram of a gate driver according to an embodiment of the present disclosure.

[0101] The gate driver may include a multi-stage circuit, each stage of which may be configured as follows: Figure 7 The gate driver GD may be a first gate driver GD1 or a second gate driver GD2.

[0102] Reference Figure 7, gate drivers GD1 and GD2 may include transistors T6 and T7. In transistor T6, a gate high voltage VGH is connected to the source, an Nth scan signal SCANN is connected to the drain, and the QB node is connected to the gate. Transistor T6 may pull up the Nth scan signal SCANN in response to a signal from the QB node. Here, N may be 1 or 2.

[0103] In transistor T7, the Nth scan signal SCANN is connected to the source, the Nth clock signal CLKN is connected to the drain, and the Q node is connected to the gate. Transistor T7 can respond to the signal at the Q node and pull down the Nth scan signal SCANN according to the Nth scan signal SCANN. Here, N can be 1 or 2.

[0104] Gate drivers GD1 and GD2 may further include transistors T91, T92, and Tbv3. Transistors T91 and T92 may apply a gate high voltage VGH to transistor Tbv3 in response to a global reset signal QRST. Global reset signal QRST may be applied at the end of each image frame to initialize the Q node to gate high voltage VGH. Transistor Tbv3 may apply gate high voltage VGH to the Q node in response to a gate low voltage VGL.

[0105] Reference Figure 3 and Figure 7 , gate drivers GD1 and GD2 may further include a transistor T1 and a transistor Tbv1. When gate drivers GD1 and GD2 are located at the first horizontal line HL1, transistor T1 may transmit a front-stage voltage FWD to transistor Tbv1 in response to a forward start signal VST_F. Transistor Tbv1 may apply the front-stage voltage FWD to the Q node according to the gate low voltage VGL. Here, the front-stage voltage FWD may be set to the same level as the gate low voltage VGL.

[0106] During forward operation, transistors T1 and Tbv1 can discharge the Q node to the previous voltage FWD. In this case, transistor T7 can pull down the Nth scan signal SCANN according to the Nth clock signal CLKN by discharging the Q node. Here, forward operation can be defined as sequential driving from the first horizontal line HL1 to the Nth horizontal line HLN.

[0107] When gate drivers GD1 and GD2 are located at the second horizontal line HL2 to the N-th horizontal line HLN, transistor T1 can transmit the previous stage voltage FWD to transistor Tbv1 according to the N-1 carry signal Carry N-1. Here, the N-1 carry signal Carry N-1 can be a signal output in the forward direction from the previous horizontal line HL.

[0108] In addition, the gate drivers GD1 and GD2 may further include a transistor T3N and a transistor Tbv2. When the gate drivers GD1 and GD2 are located at the first horizontal line HL1, the transistor T3N may transmit the back-stage voltage BWD to the transistor Tbv2 according to the reverse start signal VST_B. The transistor Tbv2 may transmit the back-stage voltage BWD to the Q node according to the gate low voltage VGL. Here, the back-stage voltage BWD may be set to the same level as the gate high voltage VGH.

[0109] When operating in reverse, transistors T3N and Tbv2 can charge the Q node with the back-stage voltage BWD. In this case, transistor T7 can pull up the Nth scan signal SCANN according to the Nth clock signal CLKN by charging the Q node. Here, reverse operation can be defined as sequential driving in the order from the Nth horizontal line HLN to the first horizontal line HL1.

[0110] In reverse operation, when gate drivers GD1 and GD2 are positioned in the reverse direction from the n-1th horizontal line HL N-1 to the first horizontal line HL1, transistor T3N can transmit the subsequent voltage BWD to transistor Tbv2 according to the n+1th carry signal Carry N+1. Here, the n+1th carry signal Carry N+1 can be a signal output from the previous stage circuit in the reverse direction.

[0111] In addition, the gate drivers GD1 and GD2 may further include transistors T31 and T32 and a transistor Tbv4. The transistors T31 and T32 may apply a gate high voltage VGH to the transistor Tbv4 according to a signal of the QB node. The transistor Tbv4 may apply a gate high voltage VGH to the Q node according to a gate low voltage VGL.

[0112] The transistors T31 and T32 and the transistor Tbv4 may transmit the gate high voltage VGH to the Q node during a period in which the transistor T6 is turned on due to the discharge of the QB node, thereby turning off the transistor T7.

[0113] In addition, the gate drivers GD1 and GD2 may further include transistors T4 and T41, a transistor T4Q, and a transistor Tbv6. When the Q node is charged, the transistors T4 and T41 may apply the gate low voltage VGL to the QB node to turn on the transistor T6.

[0114] During a period in which the transistor T7 is turned on due to the discharge of the Q node and applies the Nth clock signal CLKN to the Nth scan signal SCANN, the transistor T4Q and the transistor Tbv6 may turn off the transistor T6 to prevent the QB node from being discharged.

[0115] In addition, the gate drivers GD1 and GD2 may further include a transistor T5S, transistors T511 and T512, and a transistor T5H. During forward operation, the transistors T5S, transistors T511 and T512, and transistor T5H may control a signal of the QB node during forward operation.

[0116] During the forward operation, the transistor T5S may apply the previous stage voltage FWD to the transistors T511 and T512 according to the forward start signal VST_F or the (n-1)th carry signal CarryN-1.

[0117] The transistors T511 and T512 can apply the gate high voltage VGH to the QB node according to the previous stage voltage FWD, and the transistor T5H can turn off the transistors T511 and T512 according to the signal of the QB node.

[0118] In addition, the gate drivers GD1 and GD2 may further include a transistor T5N, transistors T521 and T522, and a transistor T5J. The transistor T5N, transistors T521 and T522, and transistor T5J may control a signal of the QB node during reverse operation.

[0119] During the reverse operation, the transistor T5N may apply the subsequent voltage BWD to the transistors T521 and T522 according to the reverse start signal VST_B or the (n+1)th carry signal CarryN+1.

[0120] The transistors T521 and T522 may apply the gate high voltage VGH to the QB node according to the back-stage voltage BWD, and the transistor T5J may turn off the transistors T521 and T522 according to the signal of the QB node.

[0121] In addition, gate drivers GD1 and GD2 may further include transistors T5Q1 and T5Q2 and a transistor Tbv5. Transistor Tbv5 may transmit the signal of the Q node to transistors T5Q1 and T5Q2 according to the gate low voltage VGL. Transistors T5Q1 and T5Q2 may apply the gate high voltage VGH to the QB node in response to the signal of the Q node.

[0122] When the transistor T7 applies the Nth clock signal CLKN to the Nth scan signal SCANN due to the discharge of the Q node, the transistors T5Q1 and T5Q2 and the transistor Tbv5 may turn off the transistor T6 by applying the gate high voltage VGH to the QB node.

[0123] In addition, the gate drivers GD1 and GD2 may further include a stabilization capacitor CQ. The stabilization capacitor CQ is connected between the Nth scan signal SCANN and the Q node to stabilize a voltage level when the Nth scan signal SCANN is output.

[0124] Figure 8 is a timing diagram of sub-pixels according to an embodiment of the present disclosure.

[0125] Reference Figure 5 and Figure 8 , the subpixel SP first receives the second scan signal SCAN2 from the second gate driver GD2. In this case, the second transistor M2 of the subpixel SP can apply the reference voltage VREF to the second node N2 according to the second scan signal SCAN2. Next, the subpixel SP receives the data voltage VDATA from the data driver 400.

[0126] Subsequently, the subpixel SP receives a first scan signal SCAN1 from the first gate driver GD1. In this case, the first transistor M1 of the subpixel SP may apply the data voltage VDATA to the first node N1 according to the first scan signal SCAN1.

[0127] Thus, the storage capacitor Cst of the sub-pixel SP samples the data voltage VDATA, and the driving transistor D-TFT supplies a driving current corresponding to the voltage of the first node N1 to the micro LED μLED, so that the micro LED μLED emits light.

[0128] Reference Figure 8 , a pulse width of the second scan signal SCAN2 may be set to be smaller than a pulse width of the first scan signal SCAN1 , and a pulse width for applying the data voltage VDATA may be set to be larger than a pulse width of the first scan signal SCAN1 .

[0129] Figure 9 is a timing diagram of a gate driver according to an embodiment of the present disclosure.

[0130] Reference Figure 9 During forward operation, the front-stage voltage FWD may be set to the same level as the gate high voltage VGH, and the back-stage voltage BWD may be set to the same level as the gate low voltage VGL.

[0131] The first gate driver GD1 may first initialize the QB node to the gate low voltage VGL and the Q node to the gate high voltage VGH according to the first global reset signal GD1_QRST.

[0132] Next, the first gate driver GD1 may start driving by charging the QB node with the front-stage voltage FWD and discharging the Q node to the back-stage voltage BWD according to the first positive start signal GD1_VST_F. In this case, the first gate driver GD1 may output the first scan signal SCAN1 to the first scan line SL1 of the display panel 100 according to the first clock signal CLK1.

[0133] Finally, the first gate driver GD1 may discharge the QB node to the back-stage voltage BWD and charge the Q node with the front-stage voltage FWD in response to the first reverse start signal GD1_VST_B, thereby terminating driving.

[0134] The second gate driver GD2 may first initialize the QB node to the gate low voltage VGL and the Q node to the gate high voltage VGH according to the second global reset signal GD2_QRST.

[0135] Next, the second gate driver GD2 may start driving by charging the QB node with the front-stage voltage FWD and discharging the Q node to the back-stage voltage BWD according to the second positive start signal GD2_VST_F. In this case, the second gate driver GD2 may output the second scan signal SCAN2 to the second scan line SL2 of the display panel 100 according to the second clock signal CLK2.

[0136] Finally, the second gate driver GD2 may terminate driving by discharging the QB node to the back-stage voltage BWD and charging the Q node with the front-stage voltage FWD in response to the second reverse start signal GD2_VST_B.

[0137] Figure 10 is a layout diagram illustrating clock signals and a gate driver according to an embodiment of the present disclosure.

[0138] Reference Figure 10 The first gate driver GD1 and the second gate driver GD2 may be respectively arranged on the left and right sides of the center line CL of the display panel 100 in one horizontal line HL. A plurality of first gate drivers GD1 and a plurality of second gate drivers GD2 may be provided, one first gate driver GD1 and one second gate driver GD2 being provided for each horizontal line.

[0139] The first clock signal (line or wiring) CLK1 to the eighth clock signal (line or wiring) CLK8 can be respectively arranged in the order of the first clock signal CLK1, the third clock signal CLK3, the fifth clock signal CLK5, the seventh clock signal CLK7, the second clock signal CLK2, the fourth clock signal CLK4, the sixth clock signal CLK6 and the eighth clock signal CLK8. Each clock signal wiring (or line) can be arranged and / or extended parallel to the data line.

[0140] The first clock signal CLK1, the third clock signal CLK3, the fifth clock signal CLK5, and the seventh clock signal CLK7 may be supplied to the left side of the center line CL of the display panel 100. For example, the first clock signal CLK1 may be supplied to the first gate driver GD1 of the first horizontal line HL1, the third clock signal CLK3 may be supplied to the first gate driver GD1 of the second horizontal line HL2, the fifth clock signal CLK5 may be supplied to the first gate driver GD1 of the third horizontal line HL3, and the seventh clock signal CLK7 may be supplied to the first gate driver GD1 of the fourth horizontal line HL4.

[0141] First, third, fifth, and seventh clock signals CLK1, CLK3, CLK5, and CLK7 may be periodically supplied to a first gate driver GD1 for each of the four horizontal lines HL. For example, the first clock signal CLK1 may be supplied to the first gate driver GD1 of the first and fifth horizontal lines HL1 and HL5.

[0142] In addition, the second clock signal CLK2, the fourth clock signal CLK4, the sixth clock signal CLK6, and the eighth clock signal CLK8 may be supplied to the right side of the center line CL of the display panel 100. For example, the second clock signal CLK2 may be supplied to the second gate driver GD2 of the first horizontal line HL1, the fourth clock signal CLK4 may be supplied to the second gate driver GD2 of the second horizontal line HL2, the sixth clock signal CLK6 may be supplied to the second gate driver GD2 of the third horizontal line HL3, and the eighth clock signal CLK8 may be supplied to the second gate driver GD2 of the fourth horizontal line HL4.

[0143] The second clock signal CLK2, the fourth clock signal CLK4, the sixth clock signal CLK6, and the eighth clock signal CLK8 may be periodically supplied to the second gate driver GD2 for each of the four horizontal lines HL. For example, the second clock signal CLK2 may be supplied to the second gate driver GD2 for the first horizontal line HL1 and the fifth horizontal line HL5.

[0144] Figure 11 is a layout diagram illustrating transistors of a gate driver according to an embodiment of the present disclosure.

[0145] Reference Figure 7 and Figure 11 In the first horizontal line HL1 , the first gate driver GD1 and the second gate driver GD2 may be respectively arranged in the order of transistor T1 , transistor T7 , transistor T4 , transistor T3 , transistor T9 , transistor T5Q , transistor T6 , transistor CQ and transistor T3N.

[0146] In the second horizontal line HL2 , the first gate driver GD1 and the second gate driver GD2 may be respectively disposed in the order of transistor T1 , transistor T4 , transistor T3 , transistor T7 , transistor T9 , transistor CQ, transistor T5Q, transistor T6 , and transistor T3N.

[0147] In the third horizontal line HL3 , the first gate driver GD1 and the second gate driver GD2 may be respectively disposed in the order of transistor T1 , transistor T5Q, transistor T6 , transistor CQ, transistor T9 , transistor T7 , transistor T4 , transistor T3 , and transistor T3N.

[0148] In the fourth horizontal line HL4 , the first gate driver GD1 and the second gate driver GD2 may be respectively disposed in the order of transistor T1 , transistor CQ, transistor T5Q, transistor T6 , transistor T9 , transistor T4 , transistor T3 , transistor T7 , and transistor T3N.

[0149] The arrangement order of the transistors of the first gate driver GD1 and the second gate driver GD2 may be repeated in a cycle of four horizontal lines HL.

[0150] Reference Figure 7 and Figure 11 The transistor T7 of the first gate driver GD1 may receive the first clock signal CLK1 at the first horizontal line HL1 and generate the first scan signal SCAN1. In addition, the transistor T7 of the second gate driver GD2 may receive the second clock signal CLK2 at the first horizontal line HL1 and generate the second scan signal SCAN2.

[0151] The transistor T7 of the first gate driver GD1 may receive the third clock signal CLK3 at the second horizontal line HL2 and generate the third scan signal SCAN3. In addition, the transistor T7 of the second gate driver GD2 may receive the fourth clock signal CLK4 at the second horizontal line HL2 and generate the fourth scan signal SCAN4.

[0152] The transistor T7 of the first gate driver GD1 may receive the fifth clock signal CLK5 at the third horizontal line HL3 and generate the fifth scan signal SCAN5. In addition, the transistor T7 of the second gate driver GD2 may receive the sixth clock signal CLK6 at the third horizontal line HL3 and generate the sixth scan signal SCAN6.

[0153] The transistor T7 of the first gate driver GD1 may receive the seventh clock signal CLK7 at the fourth horizontal line HL4 and generate the seventh scan signal SCAN7. In addition, the transistor T7 of the second gate driver GD2 may receive the eighth clock signal CLK8 at the fourth horizontal line HL4 and generate the eighth scan signal SCAN8.

[0154] The clock signal CLK received by the transistor T7 of the first gate driver GD1 and the second gate driver GD2 in the horizontal line HL may be repeated with a period of four horizontal lines HL.

[0155] Figure 12 is a layout diagram illustrating a distance from transistor T1 to transistor T7 of a gate driver and a signal transmission time according to an embodiment of the present disclosure.

[0156] In the horizontal line HL, the transistor T1 of the first gate driver GD1 and the second gate driver GD2 may be disposed at the leftmost side, and the transistor T3N may be disposed at the rightmost side.

[0157] Reference Figure 7 and Figure 12 When gate drivers GD1 and GD2 are located on the first horizontal line HL1, the leftmost transistor T1 can apply the front-stage voltage FWD to the Q node in response to the forward start signal VST_F. Here, the front-stage voltage FWD can be set to the same level as the gate low voltage VGL. The wiring supplying the forward start signal VST_F and the wiring supplying the reverse start signal VST_B can be arranged and / or extended parallel to the data line.

[0158] During the forward operation, the transistor T1 can discharge the Q node to the previous stage voltage FWD. In this case, the transistor T7 can pull down the Nth scan signal SCANN according to the Nth clock signal CLKN by discharging the Q node.

[0159] When the gate drivers GD1 and GD2 are located on the second to N-th horizontal lines HL2 to HLN, the leftmost transistor T1 may apply the previous stage voltage FWD to the Q node according to the scan signal SCAN supplied from the transistor T7 of the gate drivers GD1 and GD2 of the previous horizontal line HL. Here, the scan signal SCAN may be a signal output in the forward direction from the previous horizontal line HL.

[0160] Reference Figure 12, if the time when a signal is transmitted from the transistor T1 of the first gate driver GD1 of the first horizontal line HL1 to the transistor T7 is defined as T1, the time when a signal is transmitted from the transistor T1 of the first gate driver GD1 of the second horizontal line HL2 to the transistor T7 is defined as t3, the time when a signal is transmitted from the transistor T1 of the first gate driver GD1 of the third horizontal line HL3 to the transistor T7 is defined as t5, and the time when a signal is transmitted from the transistor T1 of the first gate driver GD1 of the fourth horizontal line HL4 to the transistor T7 is defined as t7, then the time from t1 to t7 can be defined as t1. <t3<t5<t7。

[0161] In this case, the signal transmission time increases from the previous horizontal line HL N-1 to the next horizontal line HL N, and thus the output deviation may increase. If the output deviation increases, a defective horizontal line of the display panel 100 may be recognized.

[0162] Reference Figure 12 , if the time when the signal is transmitted from the transistor T1 of the second gate driver GD2 of the first horizontal line HL1 to the transistor T7 is defined as t2, the time when the signal is transmitted from the transistor T1 of the second gate driver GD2 of the second horizontal line HL2 to the transistor T7 is defined as t4, the time when the signal is transmitted from the transistor T1 of the second gate driver GD2 of the third horizontal line HL3 to the transistor T7 is defined as t6, and the time when the signal is transmitted from the transistor T1 of the second gate driver GD2 of the fourth horizontal line HL4 to the transistor T7 is defined as t8, then the time from t2 to t8 can be defined as t2 <t4<t6<t8。

[0163] In this case, the signal transmission time increases from the previous horizontal line HL N-1 to the next horizontal line HL N, and thus the output deviation may increase. If the output deviation increases, a defective horizontal line of the display panel 100 may be recognized.

[0164] Figure 13 is a layout diagram illustrating clock signals and a gate driver according to an embodiment of the present disclosure.

[0165] Reference Figure 13 The first gate driver GD1 and the second gate driver GD2 may be respectively arranged on the left and right sides of the center line CL of the display panel 100 in one horizontal line HL. A plurality of first gate drivers GD1 and a plurality of second gate drivers GD2 may be provided, one first gate driver GD1 and one second gate driver GD2 being provided for each horizontal line.

[0166] The first to eighth clock signals CLK1 to CLK8 may be arranged in the order of a first clock signal CLK1, a fifth clock signal CLK5, a third clock signal CLK3, a seventh clock signal CLK7, a second clock signal CLK2, a sixth clock signal CLK6, a fourth clock signal CLK4, and an eighth clock signal CLK8, respectively. Each wiring may be arranged and / or extended parallel to the data line.

[0167] The first clock signal CLK1, the fifth clock signal CLK5, the third clock signal CLK3, and the seventh clock signal CLK7 may be supplied to the left side of the center line CL of the display panel 100. For example, the first clock signal CLK1 may be supplied to the first gate driver GD1 of the first horizontal line HL1, the fifth clock signal CLK5 may be supplied to the first gate driver GD1 of the third horizontal line HL3, the third clock signal CLK3 may be supplied to the first gate driver GD1 of the second horizontal line HL2, and the seventh clock signal CLK7 may be supplied to the first gate driver GD1 of the fourth horizontal line HL4.

[0168] The first clock signal CLK1, the fifth clock signal CLK5, the third clock signal CLK3 and the seventh clock signal CLK7 may be periodically supplied to the first gate driver GD1 for each of the four horizontal lines HL. For example, the first clock signal CLK1 may be supplied to the first gate driver GD1 of the first horizontal line HL1 and the fifth horizontal line HL5.

[0169] In addition, the second clock signal CLK2, the sixth clock signal CLK6, the fourth clock signal CLK4, and the eighth clock signal CLK8 may be supplied to the right side of the center line CL of the display panel 100. For example, the second clock signal CLK2 may be supplied to the second gate driver GD2 of the first horizontal line HL1, the sixth clock signal CLK6 may be supplied to the second gate driver GD2 of the third horizontal line HL3, the fourth clock signal CLK4 may be supplied to the second gate driver GD2 of the second horizontal line HL2, and the eighth clock signal CLK8 may be supplied to the second gate driver GD2 of the fourth horizontal line HL4.

[0170] The second clock signal CLK2, the sixth clock signal CLK6, the fourth clock signal CLK4, and the eighth clock signal CLK8 may be periodically supplied to the second gate driver GD2 for each of the four horizontal lines HL. For example, the second clock signal CLK2 may be supplied to the second gate driver GD2 of the first horizontal line HL1 and the fifth horizontal line HL5.

[0171] Figure 14 It shows that according to Figure 13 FIG. 1 is a diagram showing a layout of transistors of a gate driver according to an embodiment of the present disclosure.

[0172] Reference Figure 7 and Figure 14 In the first horizontal line HL1 , the first gate driver GD1 and the second gate driver GD2 may be respectively arranged in the order of transistor T1 , transistor T7 , transistor T4 , transistor T3 , transistor T9 , transistor T5Q , transistor T6 , transistor CQ and transistor T3N.

[0173] In the second horizontal line HL2 , the first gate driver GD1 and the second gate driver GD2 may be respectively disposed in the order of transistor T1 , transistor T5Q, transistor T6 , transistor CQ, transistor T9 , transistor T7 , transistor T4 , transistor T3 , and transistor T3N.

[0174] In the third horizontal line HL3 , the first gate driver GD1 and the second gate driver GD2 may be respectively disposed in the order of transistor T1 , transistor T4 , transistor T3 , transistor T7 , transistor T9 , transistor CQ, transistor T5Q, transistor T6 , and transistor T3N.

[0175] In the fourth horizontal line HL4 , the first gate driver GD1 and the second gate driver GD2 may be respectively disposed in the order of transistor T1 , transistor CQ, transistor T5Q, transistor T6 , transistor T9 , transistor T4 , transistor T3 , transistor T7 , and transistor T3N.

[0176] The arrangement order of the transistors of the first gate driver GD1 and the second gate driver GD2 may be repeated in a cycle of four horizontal lines HL.

[0177] Reference Figure 7 and Figure 14 The transistor T7 of the first gate driver GD1 may receive the first clock signal CLK1 at the first horizontal line HL1 and generate the first scan signal SCAN1. In addition, the transistor T7 of the second gate driver GD2 may receive the second clock signal CLK2 at the first horizontal line HL1 and generate the second scan signal SCAN2.

[0178] The transistor T7 of the first gate driver GD1 may receive the third clock signal CLK3 at the second horizontal line HL2 and generate the third scan signal SCAN3. In addition, the transistor T7 of the second gate driver GD2 may receive the fourth clock signal CLK4 at the second horizontal line HL2 and generate the fourth scan signal SCAN4.

[0179] The transistor T7 of the first gate driver GD1 may receive the fifth clock signal CLK5 at the third horizontal line HL3 and generate the fifth scan signal SCAN5. In addition, the transistor T7 of the second gate driver GD2 may receive the sixth clock signal CLK6 at the third horizontal line HL3 and generate the sixth scan signal SCAN6.

[0180] The transistor T7 of the first gate driver GD1 may receive the seventh clock signal CLK7 at the fourth horizontal line HL4 and generate the seventh scan signal SCAN7. In addition, the transistor T7 of the second gate driver GD2 may receive the eighth clock signal CLK8 at the fourth horizontal line HL4 and generate the eighth scan signal SCAN8.

[0181] The clock signal CLK received by the transistor T7 of the first gate driver GD1 and the second gate driver GD2 in the horizontal line HL may be repeated with a period of four horizontal lines HL.

[0182] Figure 15 is a layout diagram illustrating a distance from transistor T1 to transistor T7 of a gate driver and a signal transmission time according to an embodiment of the present disclosure.

[0183] In the horizontal line HL, the transistor T1 of the first gate driver GD1 and the second gate driver GD2 may be disposed on the leftmost side, and the transistor T3N may be disposed on the rightmost side.

[0184] Reference Figure 7 and Figure 15 When gate drivers GD1 and GD2 are located on the first horizontal line HL1, the leftmost transistor T1 can apply the front-stage voltage FWD to the Q node in response to the forward start signal VST_F. Here, the front-stage voltage FWD can be set to the same level as the gate low voltage VGL. The wiring supplying the forward start signal VST_F and the wiring supplying the reverse start signal VST_B can be arranged and / or extended parallel to the data line.

[0185] During the forward operation, the transistor T1 can discharge the Q node to the previous stage voltage FWD. In this case, the transistor T7 can pull down the Nth scan signal SCANN according to the Nth clock signal CLKN by discharging the Q node.

[0186] When the gate drivers GD1 and GD2 are located on the second to N-th horizontal lines HL2 to HLN, the leftmost transistor T1 may apply the previous stage voltage FWD to the Q node according to the scan signal SCAN supplied from the transistor T7 of the gate drivers GD1 and GD2 of the previous horizontal line HL. Here, the scan signal SCAN may be a signal output in the forward direction from the previous horizontal line HL.

[0187] Reference Figure 15 , if the time when a signal is transmitted from the transistor T1 of the first gate driver GD1 of the first horizontal line HL1 to the transistor T7 is defined as t1, the time when a signal is transmitted from the transistor T1 of the first gate driver GD1 of the second horizontal line HL2 to the transistor T7 is defined as t3, the time when a signal is transmitted from the transistor T1 of the first gate driver GD1 of the third horizontal line HL3 to the transistor T7 is defined as t5, and the time when a signal is transmitted from the transistor T1 of the first gate driver GD1 of the fourth horizontal line HL4 to the transistor T7 is defined as t7, then the time from t1 to t7 can be defined as t1. <t5<t3<t7。

[0188] In this case, the signal transmission time from the previous horizontal line HL N-1 to the next horizontal line HL N can be reduced, so the output deviation can be reduced. In other words, the difference between the time (t3-t1) and the time (t3-t5) can be reduced, and the difference between the time (t7-t5) and the time (t7-t1) can be reduced. As the output deviation is reduced, the defective horizontal lines of the display panel 100 can be improved.

[0189] Reference Figure 15 , if the time when the signal is transmitted from the transistor T1 of the second gate driver GD2 of the first horizontal line HL1 to the transistor T7 is defined as t2, the time when the signal is transmitted from the transistor T1 of the second gate driver GD2 of the second horizontal line HL2 to the transistor T7 is defined as t4, the time when the signal is transmitted from the transistor T1 of the second gate driver GD2 of the third horizontal line HL3 to the transistor T7 is defined as t6, and the time when the signal is transmitted from the transistor T1 of the second gate driver GD2 of the fourth horizontal line HL4 to the transistor T7 is defined as t8, then the time from t2 to t8 can be defined as t2 <t6<t4<t8。

[0190] In this case, the signal transmission time from the previous horizontal line HL N-1 to the next horizontal line HL N can be reduced, so the output deviation can be reduced. In other words, the difference between the time (t4-t2) and the time (t4-t6) can be reduced, and the difference between the time (t8-t6) and the time (t8-t2) can be reduced. As the output deviation is reduced, the defective horizontal lines of the display panel 100 can be improved.

[0191] Figure 16 is a layout diagram illustrating clock signals and a gate driver according to an embodiment of the present disclosure.

[0192] Reference Figure 16The first gate driver GD1 and the second gate driver GD2 may be respectively arranged on the left and right sides of the center line CL of the display panel 100 in one horizontal line HL. A plurality of first gate drivers GD1 and a plurality of second gate drivers GD2 may be provided, with one first gate driver GD1 and one second gate driver GD2 provided for each horizontal line.

[0193] The first to eighth clock signals CLK1 to CLK8 may be arranged in the order of the third clock signal CLK3, the seventh clock signal CLK7, the first clock signal CLK1, the fifth clock signal CLK5, the fourth clock signal CLK4, the eighth clock signal CLK8, the second clock signal CLK2, and the sixth clock signal CLK6, respectively. Each wiring may be arranged and / or extended parallel to the data line.

[0194] The third clock signal CLK3, the seventh clock signal CLK7, the first clock signal CLK1, and the fifth clock signal CLK5 may be supplied to the left side of the center line CL of the display panel 100. For example, the third clock signal CLK3 may be supplied to the first gate driver GD1 of the first horizontal line HL1, the seventh clock signal CLK7 may be supplied to the first gate driver GD1 of the fourth horizontal line HL4, the first clock signal CLK1 may be supplied to the first gate driver GD1 of the first horizontal line HL1, and the fifth clock signal CLK5 may be supplied to the first gate driver GD1 of the third horizontal line HL3.

[0195] The third clock signal CLK3, the seventh clock signal CLK7, the first clock signal CLK1 and the fifth clock signal CLK5 may be periodically supplied to the first gate driver GD1 for each of the four horizontal lines HL. For example, the first clock signal CLK1 may be supplied to the first gate driver GD1 of the first horizontal line HL1 and the fifth horizontal line HL5.

[0196] In addition, the fourth clock signal CLK4, the eighth clock signal CLK8, the second clock signal CLK2, and the sixth clock signal CLK6 may be supplied to the right side of the center line CL of the display panel 100. For example, the fourth clock signal CLK4 may be supplied to the second gate driver GD2 of the second horizontal line HL2, the eighth clock signal CLK8 may be supplied to the second gate driver GD2 of the fourth horizontal line HL4, the second clock signal CLK2 may be supplied to the second gate driver GD2 of the first horizontal line HL1, and the sixth clock signal CLK6 may be supplied to the second gate driver GD2 of the third horizontal line HL3.

[0197] The fourth clock signal CLK4, the eighth clock signal CLK8, the second clock signal CLK2, and the sixth clock signal CLK6 may be periodically supplied to the second gate driver GD2 for each of the four horizontal lines HL. For example, the second clock signal CLK2 may be supplied to the second gate driver GD2 of the first horizontal line HL1 and the fifth horizontal line HL5.

[0198] Figure 17 It shows that according to Figure 16 FIG. 1 is a diagram showing a layout of transistors of a gate driver according to an embodiment of the present disclosure.

[0199] Reference Figure 7 and Figure 17 In the first horizontal line HL1 , the first gate driver GD1 and the second gate driver GD2 may be respectively arranged in the order of transistor T1 , transistor T5Q, transistor T6 , transistor CQ, transistor T9 , transistor T7 , transistor T4 , transistor T3 , and transistor T3N.

[0200] In the second horizontal line HL2 , the first gate driver GD1 and the second gate driver GD2 may be respectively disposed in the order of transistor T1 , transistor T7 , transistor T4 , transistor T3 , transistor T9 , transistor T5Q, transistor T6 , transistor CQ, and transistor T3N.

[0201] In the third horizontal line HL3 , the first gate driver GD1 and the second gate driver GD2 may be respectively disposed in the order of transistor T1 , transistor CQ, transistor T5Q, transistor T6 , transistor T9 , transistor T4 , transistor T3 , transistor T7 , and transistor T3N.

[0202] In the fourth horizontal line HL4 , the first gate driver GD1 and the second gate driver GD2 may be respectively disposed in the order of transistor T1 , transistor T4 , transistor T3 , transistor T7 , transistor T9 , transistor CQ, transistor T5Q, transistor T6 , and transistor T3N.

[0203] The arrangement order of the transistors of the first gate driver GD1 and the second gate driver GD2 may be repeated in a cycle of four horizontal lines HL.

[0204] Reference Figure 7 and Figure 17 The transistor T7 of the first gate driver GD1 may receive the first clock signal CLK1 at the first horizontal line HL1 and generate the first scan signal SCAN1. In addition, the transistor T7 of the second gate driver GD2 may receive the second clock signal CLK2 at the first horizontal line HL1 and generate the second scan signal SCAN2.

[0205] The transistor T7 of the first gate driver GD1 may receive the third clock signal CLK3 at the second horizontal line HL2 and generate the third scan signal SCAN3. In addition, the transistor T7 of the second gate driver GD2 may receive the fourth clock signal CLK4 at the second horizontal line HL2 and generate the fourth scan signal SCAN4.

[0206] The transistor T7 of the first gate driver GD1 may receive the fifth clock signal CLK5 at the third horizontal line HL3 and generate the fifth scan signal SCAN5. In addition, the transistor T7 of the second gate driver GD2 may receive the sixth clock signal CLK6 at the third horizontal line HL3 and generate the sixth scan signal SCAN6.

[0207] The transistor T7 of the first gate driver GD1 may receive the seventh clock signal CLK7 at the fourth horizontal line HL4 and generate the seventh scan signal SCAN7. In addition, the transistor T7 of the second gate driver GD2 may receive the eighth clock signal CLK8 at the fourth horizontal line HL4 and generate the eighth scan signal SCAN8.

[0208] The clock signal CLK received by the transistor T7 of the first gate driver GD1 and the second gate driver GD2 in the horizontal line HL may be repeated with a period of four horizontal lines HL.

[0209] Figure 18 is a layout diagram illustrating a distance from transistor T1 to transistor T7 of a gate driver and a signal arrival time according to an embodiment of the present disclosure.

[0210] In the horizontal line HL, the transistor T1 of the first gate driver GD1 and the second gate driver GD2 may be disposed on the leftmost side, and the transistor T3N may be disposed on the rightmost side.

[0211] Reference Figure 7 and Figure 18 When gate drivers GD1 and GD2 are located on the first horizontal line HL1, the leftmost transistor T1 can apply the front-stage voltage FWD to the Q node in response to the forward start signal VST_F. Here, the front-stage voltage FWD can be set to the same level as the gate low voltage VGL. The wiring supplying the forward start signal VST_F and the wiring supplying the reverse start signal VST_B can be arranged and / or extended parallel to the data line.

[0212] During the forward operation, the transistor T1 can discharge the Q node to the previous stage voltage FWD. In this case, the transistor T7 can pull down the Nth scan signal SCANN according to the Nth clock signal CLKN by discharging the Q node.

[0213] When the gate drivers GD1 and GD2 are located on the second to N-th horizontal lines HL2 to HLN, the leftmost transistor T1 may apply the previous stage voltage FWD to the Q node according to the scan signal SCAN supplied from the transistor T7 of the gate drivers GD1 and GD2 of the previous horizontal line HL. Here, the scan signal SCAN may be a signal output in the forward direction from the previous horizontal line HL.

[0214] Reference Figure 18 , if the time when a signal is transmitted from the transistor T1 of the first gate driver GD1 of the first horizontal line HL1 to the transistor T7 is defined as t1, the time when a signal is transmitted from the transistor T1 of the first gate driver GD1 of the second horizontal line HL2 to the transistor T7 is defined as t3, the time when a signal is transmitted from the transistor T1 of the first gate driver GD1 of the third horizontal line HL3 to the transistor T7 is defined as t5, and the time when a signal is transmitted from the transistor T1 of the first gate driver GD1 of the fourth horizontal line HL4 to the transistor T7 is defined as t7, then the time from t1 to t7 can be defined as t3 <t7<t1<t5。

[0215] In this case, the signal transmission time from the previous horizontal line HL N-1 to the next horizontal line HL N is reduced, so the output deviation can be reduced. In other words, the difference between the time (t1-t3) and the time (t5-t3) can be reduced, and the difference between the time (t5-t7) and the time (t1-t7) can be reduced. As the output deviation is reduced, the defective horizontal lines of the display panel 100 can be improved.

[0216] Reference Figure 18 , if the time when the signal is transmitted from the transistor T1 of the second gate driver GD2 of the first horizontal line HL1 to the transistor T7 is defined as t2, the time when the signal is transmitted from the transistor T1 of the second gate driver GD2 of the second horizontal line HL2 to the transistor T7 is defined as t4, the time when the signal is transmitted from the transistor T1 of the second gate driver GD2 of the third horizontal line HL3 to the transistor T7 is defined as t6, and the time when the signal is transmitted from the transistor T1 of the second gate driver GD2 of the fourth horizontal line HL4 to the transistor T7 is defined as t8, then the time from t2 to t8 can be defined as t4 <t8<t2<t6。

[0217] In this case, the signal transmission time from the previous horizontal line HL N-1 to the next horizontal line HL N is reduced, thereby reducing output deviation. In other words, the difference between the time (t4-t2) and the time (t4-t6) can be reduced, and the difference between the time (t8-t6) and the time (t8-t2) can be reduced. As the output deviation is reduced, the defective horizontal lines of the display panel 100 can be improved.

[0218] The above description and accompanying drawings provide examples of the technical concepts of the present disclosure for illustrative purposes only. Those skilled in the art of the present invention will understand that various forms of modifications and changes, such as combinations, separations, replacements, and changes in configurations, may be made without departing from the essential features of the present invention. Therefore, the embodiments disclosed in the present disclosure are intended to illustrate the scope of the technical concepts of the present disclosure, and the scope of the present disclosure is not limited by the embodiments. The scope of the present disclosure should be interpreted based on the appended claims so that all technical concepts included in the scope equivalent to the claims belong to the present disclosure.

[0219] The micro LED display device according to the embodiment can stably drive the gate driver within the GIA circuit.

Claims

1. A display panel for a micro LED display device, comprising: a plurality of pixel arrays (PXL), each of the pixel arrays comprising a plurality of sub-pixels (SP); as well as An active gate circuit (700), namely a GIA circuit (700), configured to provide at least one scan signal (SCAN1, SCAN2) to each of the pixel array (PXL), wherein a plurality of clock lines are used to supply clock signals (CLK1, . . . , CLK8), each of the clock lines extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction, The GIA circuit (700) includes a plurality of first transistors (T7) connected to the plurality of clock lines. Wherein, the first transistor (T7) is arranged along the multiple clock lines connected to the first transistor.

2. The display panel according to claim 1 , further comprising at least one wiring for supplying a positive start signal (VST F), in, The GIA circuit (700) further includes at least one second transistor (T1) connected to the wiring for supplying the forward start signal (VST F).

3. The display panel according to any one of claims 1 to 2, further comprising at least one wiring for supplying a reverse start signal (VSTB), in, The GIA circuit (700) further includes at least one third transistor (T3N) connected to the wiring for supplying the reverse start signal (VST B).

4. The display panel according to any one of claims 1 to 3, wherein: The GIA circuit (700) comprises: at least one first gate driver (GD1) configured to provide a first scan signal (SCAN1) to a sub-pixel (SP) of the pixel array (PXL); and At least one second gate driver (GD2) is configured to provide a second scan signal (SCAN2) to the sub-pixels (SP) of the pixel array (PXL).

5. The display panel according to claim 4, wherein: Each of the first gate driver (GD1) and the second gate driver (GD2) further includes: a fourth transistor (T6) including a gate connected to the QB node, a source connected to the gate high voltage, and a drain connected to the Nth scan signal (SCANN); and A corresponding first transistor (T7) includes a gate connected to the Q node, a source connected to the Nth scan signal, and a drain connected to the Nth clock signal. The display panel according to claim 5 , wherein: Each of the first gate driver (GD1) and the second gate driver (GD2) further includes a capacitor (CQ) connected between the Nth scan signal (SCANN) and the Q node (CQ).

7. The display panel according to claim 4, 5 or 6, wherein: A pulse width of the second scan signal (SCAN2) of the second gate driver (GD2) is smaller than a pulse width of the first scan signal (SCAN1) of the first gate driver (GD1), and a pulse width for applying a data voltage (VDATA) is larger than the pulse width of the first scan signal (SCAN1).

8. The display panel according to any one of claims 1 to 7, wherein: The display panel (100) includes a first GIA area (GIA1), a second GIA area (GIA2) and a third GIA area (GIA3).

9. The display panel according to any one of claims 1 to 8, wherein: The display panel (100) comprises a plurality of horizontal lines (HL1, ...HLN) extending along the second direction, wherein the first transistor (T7) of the first gate driver (GD1) on the first horizontal line (HL1) is connected to the clock line for supplying a first clock signal (CLK1), and the first transistor (T7) of the second gate driver (GD2) on the first horizontal line (HL1) is connected to the clock line for supplying a second clock signal (CLK2), wherein the first transistor (T7) of the first gate driver (GD1) on the second horizontal line (HL2) is connected to the clock line for supplying a third clock signal (CLK3), and the first transistor (T7) of the second gate driver (GD2) on the second horizontal line (HL2) is connected to the clock line for supplying a fourth clock signal (CLK4), wherein the first transistor (T7) of the first gate driver (GD1) on the third horizontal line (HL3) is connected to the clock line for supplying a fifth clock signal (CLK5), and the first transistor (T7) of the second gate driver (GD2) on the third horizontal line (HL3) is connected to the clock line for supplying a sixth clock signal (CLK6), and wherein the first transistor (T7) of the first gate driver (GD1) on the fourth horizontal line (HL4) is connected to the clock line for supplying a seventh clock signal (CLK7), and the first transistor (T7) of the second gate driver (GD2) on the fourth horizontal line (HL4) is connected to the clock line for supplying an eighth clock signal (CLK8).

10. The display panel according to claim 9, wherein: The plurality of clock lines connected to the first gate driver (GD1) are arranged along the second direction in the following order: the clock line for supplying the first clock signal (CLK1), the clock line for supplying the third clock signal (CLK3), the clock line for supplying the fifth clock signal (CLK5), and the clock line for supplying the seventh clock signal (CLK7); or the clock line for supplying the first clock signal (CLK1), the clock line for supplying the fifth clock signal (CLK5), the clock line for supplying the third clock signal (CLK3), and the clock line for supplying the seventh clock signal (CLK7); or The clock line for supplying the third clock signal (CLK3), the clock line for supplying the seventh clock signal (CLK7), the clock line for supplying the first clock signal (CLK1), and the clock line for supplying the fifth clock signal (CLK5).

11. A micro LED display device comprising the display panel according to any one of claims 1 to 10.

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