Hammer strike prevention circuit and its memory

Abstract

This application provides a hammer impact prevention circuit and a memory having the same. The hammer impact prevention circuit includes: an enable module configured to receive a first latch control signal and a second latch control signal, and generate a latch enable signal based on the first latch control signal and the second latch control signal; when the latch enable signal is in a valid active state, the latch module latches the corresponding input address as a target address for subsequent hammer impact refresh operations; a determination module connected to the enable module generates a second latch control signal based on the target address; the second latch control signal is configured based on preset conditions, which include at least one of the following: whether the input address to be latched is the same as the target address latched in the latch module; or whether the current hammer impact refresh operation performed on the current target address has been completed. The above scheme is beneficial to improving the protection effect of the hammer impact prevention circuit on stored data.

Description

Technical Field

[0001] The disclosed embodiments of this application relate to the field of storage technology, and more specifically, to a hammer-proof circuit and a memory having therein. Background Technology

[0002] In memory circuits, a memory array consists of several rows of storage capacitor arrays. When a certain row of memory cells is frequently read, the values ​​of the storage capacitor cells in several adjacent rows may be overwritten due to signal coupling, a phenomenon known as hammering.

[0003] To reduce the impact of hammering on stored content, hammering refresh operations are needed for addresses where hammering may occur. However, current hammering prevention circuits are not ideal in protecting stored data when performing hammering refresh operations.

[0004] Therefore, improving the protection effect of hammer impact prevention circuits on stored data has become an urgent problem to be solved. Summary of the Invention

[0005] According to embodiments of this application, the present invention provides a hammer impact prevention circuit and a memory having therein, so as to at least improve the protection effect of the hammer impact prevention circuit on stored data.

[0006] According to one aspect of this application, a hammer-impact prevention circuit is disclosed, comprising an enable module, a latch module, and a determination module. The enable module is configured to receive a first latch control signal and a second latch control signal, and generate a latch enable signal based on the first and second latch control signals. The latch enable signal is in a valid active state when both the first and second latch control signals are in a valid active state. The latch module is connected to the enable module. When the latch enable signal is in a valid active state, the latch module latches the corresponding input address as a target address for subsequent hammer-impact refresh operations. The determination module is connected to the enable module and generates a second latch control signal based on the target address. The second latch control signal is configured based on preset conditions, which include at least one of the following: whether the input address to be latched is the same as the target address latched in the latch module; or whether the current hammer-impact refresh operation performed on the current target address has been completed.

[0007] The second aspect of this application discloses a memory that includes the hammer-prevention circuit described in the first aspect above.

[0008] The above scheme generates a second latch control signal through a determination module. This second latch control signal is configured based on preset conditions, including at least one of the following: whether the input address to be latched is the same as the target address latched in the latch module; or whether the current hammer refresh operation performed on the current target address has been completed. Therefore, the enable module can control the latch module to latch the corresponding input address as the target address based on whether the new address is the same as the target address, and / or whether the current hammer refresh operation on the current target address has been completed, so as to perform a hammer refresh operation on the target address. By determining whether the current hammer refresh operation on the current target address has been completed, the determination module helps prevent hammer refresh operations from being performed on the new address before the current hammer refresh operation on the current target address is completed, thereby improving the protection effect of the hammer refresh prevention circuit on the stored data. By determining whether the new address is the same as the target address, it helps prevent repeated hammer refresh operations on the same target address, thereby enabling hammer refresh operations to be performed on more different target addresses within the same time period, further improving the protection effect of the hammer refresh prevention circuit on the stored data. Attached Figure Description

[0009] The present application will be further described below with reference to the accompanying drawings and embodiments. In the drawings:

[0010] Figure 1 This is a schematic diagram of the hammer strike prevention circuit in one embodiment of this application;

[0011] Figure 2 This is a schematic diagram of the framework of a hammer-prevention circuit in the prior art;

[0012] Figure 3 This is a schematic diagram of the hammer strike prevention circuit in another embodiment of this application;

[0013] Figure 4 This is a schematic diagram of the comparator frame in one embodiment of this application;

[0014] Figure 5 This is a schematic diagram of the hammer strike prevention circuit in another embodiment of this application;

[0015] Figure 6 This is a schematic diagram of the hammer strike prevention circuit in another embodiment of this application;

[0016] Figure 7 This is a schematic diagram of the hammer strike prevention circuit in yet another embodiment of this application;

[0017] Figure 8 This is a schematic diagram of the hammer strike prevention circuit in yet another embodiment of this application;

[0018] Figure 9This is a schematic diagram of the latching unit in a hammer impact prevention circuit according to an embodiment of this application;

[0019] Figure 10 This is a schematic diagram of the memory frame according to an embodiment of this application. Detailed Implementation

[0020] To enable those skilled in the art to better understand the technical solutions of this application, the technical solutions of this application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0021] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the application. The singular forms “a,” “said,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless otherwise clearly indicated above. “Multiple” generally includes at least two, but does not exclude the inclusion of at least one.

[0022] It should be understood that the term "and / or" used herein is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship. The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0023] It should be understood that the terms "comprising," "including," or any other variations used herein are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0024] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in every place in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0025] In memory circuits, a memory array consists of several rows of storage capacitor arrays. When a certain row of memory cells is frequently read, the values ​​of the storage capacitor cells in several adjacent rows may be overwritten due to signal coupling, a phenomenon known as hammering.

[0026] To reduce the impact of hammering on stored content, hammering refresh operations are needed for addresses where hammering may occur. However, current hammering prevention circuits are not ideal in protecting stored data when performing hammering refresh operations.

[0027] To improve the protection of stored data, according to one aspect of this application, a hammer-damping prevention circuit 100 is disclosed. Please refer to... Figure 1 The hammer-strike prevention circuit 100 includes an enable module 110, a latch module 120, and a determination module 130. The enable module 110 is configured to receive a first latch control signal and a second latch control signal, and generate a latch enable signal based on the first and second latch control signals. The latch enable signal is activated when both the first and second latch control signals are in an active state. The latch module 120 is connected to the enable module 110. When the latch enable signal is in an active state, the latch module 120 latches the corresponding input address as the target address for subsequent hammer-strike refresh operations. The determination module 130 is connected to the enable module 110 and generates the second latch control signal based on the target address. The second latch control signal is configured based on preset conditions, which include at least one of the following: whether the input address to be latched is the same as the target address latched in the latch module 120; or whether the current hammer-strike refresh operation performed on the current target address has been completed.

[0028] It should be understood that the first latch control signal, the second latch control signal, and the latch enable signal can have two states: a logic high level (e.g., 3.3V) and a logic low level (e.g., 0V). The effective activation state of the first latch control signal, the second latch control signal, and the latch enable signal can be either a logic high level or a logic low level. For example, when the first latch control signal, the second latch control signal, and the latch enable signal are at a logic high level, they can be considered to be in an effective activation state. Alternatively, the effective activation states of the first latch control signal, the second latch control signal, and the latch enable signal can also be different. For example, when the first latch control signal and the second latch control signal are at a logic high level, they can be considered to be in an effective activation state, while when the latch enable signal is at a logic low level, they can be considered to be in an effective activation state, and so on. This application does not impose any restrictions on this.

[0029] The first latch control signal can be generated based on the latch state of the latch module 120. For example, the latch state of the latch module 120 includes at least two types, such as a latch occupied state and a latch idle state. The latch idle state indicates that no address is currently latched in the latch module 120, while the latch occupied state indicates that an address has been latched in the latch module 120. When the latch module 120 is in the latch occupied state, it will not latch the input address as the target address; when the latch module 120 is in the latch idle state, it can latch the input address as the target address. Therefore, based on the latch state of the latch module 120, a first latch control signal in a valid active state (e.g., high level) and a first latch control signal in a invalid active state (e.g., low level) can be generated.

[0030] For example, the aforementioned "configuration of the second latch control signal based on preset conditions" can mean that the second latch control signal is configured to be in an active state when all preset conditions are met; or, the second latch control signal is configured to be in an active state when one of the preset conditions is met; or, multiple second latch control signals corresponding to each preset condition are generated depending on whether each preset condition is met. For example, when one preset condition is met, a second latch control signal in an active state (e.g., high level) is generated, and when one preset condition is not met, a second latch control signal in an inactive state (e.g., low level) is generated. This application does not limit the configuration of the second latch control signal.

[0031] The above scheme generates a second latch control signal through the determination module 130, and the second latch control signal is configured based on preset conditions, which include at least one of the following: whether the input address to be latched is the same as the target address latched in the latch module 120; or whether the current hammer refresh operation performed on the current target address has been completed. Therefore, the enable module 110 can control the latch module 120 to latch the corresponding input address as the target address based on whether the new address is the same as the target address and / or whether the current hammer refresh operation of the current target address is completed, so as to perform a hammer refresh operation on the target address; the determination module 130, by determining whether the current hammer refresh operation of the current target address is completed, helps to prevent the hammer refresh operation on the new address from being performed before the current hammer refresh operation of the current target address is completed, thereby improving the protection effect of the hammer refresh circuit 100 on the stored data; by determining whether the new address is the same as the target address, it helps to prevent repeated hammer refresh operations on the same target address, thereby enabling the hammer refresh operation to be performed on more different target addresses in the same time, and further improving the protection effect of the hammer refresh circuit 100 on the stored data.

[0032] Please refer to Figure 2 Existing latches can latch the input address corresponding to the activation signal upon receiving an activation signal to obtain the target address. However, if only the activation signal is used as the control signal for latching, as mentioned earlier, it may lead to incomplete refreshing of the old address or repeated latching to the same target address, thereby reducing the protection effect of the hammer-proof circuit on the stored data. In this embodiment, referring to... Figure 1 By determining the second latch control signal output by the module 130, the enable module 110 generates a latch enable signal based on the first latch control signal and the second latch control signal. This enables the enable module 110 to control the latch module 120 to latch the corresponding input address as the target address based on whether the new address is the same as the target address and / or whether the current hammer refresh operation of the current target address has been completed. This helps to improve the protection effect of the hammer prevention circuit 100 on the stored data.

[0033] In some embodiments, the enable module 110 may include logic gates (not shown), such as AND gates (not shown) and NAND gates (not shown). For example, the enable module 110 may include an AND gate, which can output a high-level latch enable signal when both the first latch control signal and the second latch control signal are high, thereby controlling the latch module 120 to latch the input address (at this time, the high-level state of the latch enable signal is configured as an active state). As another example, the enable module 110 may include a NAND gate, which can output a low-level latch enable signal when both the first latch control signal and the second latch control signal are high, thereby controlling the latch module 120 to latch the input address (at this time, the low-level state of the latch enable signal is configured as an active state).

[0034] In some embodiments, please refer to Figure 3 The determination module 130 includes a first determination unit 131, which is configured to compare the input address to be latched with the target address to determine whether the input address to be latched is the same as the target address latched in the latching module 120.

[0035] It is understood that in this embodiment, the "new address" is relative to the target address (old address) stored in the latch module 120, and refers to the "input address" that has not yet been stored in the latch module 120.

[0036] An address can consist of multiple binary digits; for example, an address can include 15 bits (for example, an address can be represented as "010101010101010"). The new address is compared to the corresponding bits in the target address to determine if they are the same.

[0037] In some embodiments, the first determination unit 131 includes a comparator 400, which includes the same number of XOR gates as the number of bits of the input address and the target address. Each XOR gate compares the corresponding bits of the input address and the target address to be latched, and then outputs the second latch control signal via the NAND gate, OR gate, XOR gate in the comparator, or an integrated circuit with logic operation function.

[0038] Please refer to Figure 4The comparator 400 may include an XNOR gate, a NAND gate, a NOR gate, and an OR gate. For example, 15 XNOR gates can be used to access 15 bits of data from the input address and the destination address, respectively. <0> Target address <0> These represent the first bit of data in the input address and the target address, respectively. Input address <1> Target address <1> These represent the second data bit in the input address and the second data bit in the destination address, respectively, and so on, for the input address... <14> Target address <14> These represent the 15th bits of data in the input address and the target address, respectively. Therefore, after comparing the corresponding bits of data in the input address and the target address using an NAND gate to obtain a preliminary comparison result, the data is then passed through a NAND gate, a NOR gate / NOT gate in sequence, and finally through a NAND gate to obtain a second latch control signal used to indicate whether the input address to be latched is the same as the target address latched in the latch module 120.

[0039] exist Figure 4 In the implementation of the comparator 400 shown, the corresponding bits of the input address and the target address are XORed. The XOR operation result is then combined by AND-NOT, NOR-NOT, etc., to generate a second latch control signal. When any bit of the input address and the target address are different, the output second latch control signal is high.

[0040] The comparator 400 can be implemented in ways that are not limited to Figure 4 As shown, for example, the number of XNOR gates can be configured according to the number of bits included in the input address and the destination address; the NAND gate connected to the XNOR gate can be configured as a 5-input NAND gate, which helps to reduce the number of logic gates required.

[0041] During the normal operation phase of the memory, the row address activated during this phase is fetched, and a hammer refresh operation is performed on the adjacent addresses of that row address during the refresh phase. However, due to the limited time of the refresh phase, the hammer refresh operation on the adjacent addresses of the row address may not be completed before entering the next normal operation phase. If a new row address is fetched in the next normal operation phase, and a hammer refresh operation is performed on the adjacent addresses of that new row address in the next refresh phase, the incomplete hammer refresh operation from the previous phase will be overwritten. This results in the hammer refresh operation on the adjacent addresses of the row address fetched in the previous refresh phase not being fully executed, thus weakening the protection effect on the stored data. Furthermore, when the same row address is fetched sequentially, repeatedly performing a hammer refresh operation on the same row address not only affects the refresh efficiency but also reduces the number of addresses that the hammer refresh protection circuit can protect within the same time period, thereby weakening the protection effect on the stored data.

[0042] Therefore, in some embodiments, please refer to Figure 5 The determination module 130 further includes a second determination unit 132, which is configured to count the hammer refresh operation and determine that the current hammer refresh operation performed on the current target address is completed when the count value reaches a first value. By setting the second determination unit, the integrity of the current hammer refresh operation performed on the target address is improved, thereby improving the protection effect of the stored data.

[0043] The latch module 120 can send the target address to the refresh module 500 of the memory to perform a hammer refresh operation on the adjacent rows of the target address in the refresh module 500. For example, after each row hammer refresh operation is completed, the refresh module 500 outputs a pulse signal to the second determination unit 132. The second determination unit 132 can count the received pulse signals to count the number of hammer refresh operations performed by the refresh module 500. When the count reaches a first value, it is determined that the current hammer refresh operation performed on the current target address is complete. As an example, the second determination unit 132 can generate a second latch control signal in a valid active state (e.g., a high-level state) when the count reaches the first value. When the first latch control signal is also in a valid active state (e.g., a high-level state), the enable module 110 generates a latch enable signal in a valid active state, thereby controlling the latch module 120 to latch the corresponding input address as the target address.

[0044] The first value can be set according to actual needs. For example, if a hammer refresh operation is required to be performed on the five adjacent rows of the target address during the refresh phase, the first value can be configured as 10. The first value can also be set to any integer value such as 8, 12, 13, 16, etc. This application does not restrict this.

[0045] In some embodiments, the second determination unit 132 includes an adder (not shown), a counter (not shown), or an integrated circuit with counting function (not shown) to count the hammer refresh operation and output the second latch control signal when the count value reaches a first value.

[0046] The second determination unit 132 may include a reset function, that is, when the count value of the second determination unit 132 reaches the first value, a reset signal may be generated to reset the count value of the second determination unit 132 (for example, reset to 0).

[0047] In the above embodiment, the second determination unit 132 counts the hammer refresh operations performed on adjacent units of the target address. Only when the count reaches a first value is a second latch control signal in an effective active state generated. This causes the enable module 110 to generate a latch enable signal in an effective active state when it receives the first latch control signal in the same effective active state, and controls the latch module 120 to latch the corresponding input address as the target address. This helps to ensure that all refresh operations on the target address that may be affected are completed without interruption. In other words, it helps to ensure that the impact of the hammer phenomenon is completely eliminated before a new address is allowed to be latched, thereby improving the protection effect of the hammer prevention circuit 100 on the stored data.

[0048] In some embodiments, please refer to Figure 6 The determination unit includes a first determination unit 131 and a second determination unit 132. Referring to the foregoing embodiments, as an example, the first determination unit 131 compares the input address to be latched with the target address to determine whether the input address to be latched is the same as the target address latched in the latch module 120. If the input address to be latched is different from the target address latched in the latch module 120, a second latch control signal in a valid active state (e.g., high level) is generated. The second determination unit 132 counts the hammer refresh operation, and when the count value reaches a first value, determines that the current hammer refresh operation performed on the current target address is complete, and generates a second latch control signal in a valid active state (e.g., high level).

[0049] Therefore, in this embodiment, when the current hammer refresh operation on the current target address is completed and the input address to be latched is different from the target address latched in the latch module 120, the hammer refresh circuit 100 can temporarily control the latch module 120 to latch the corresponding input address as the target address when the first latch control signal in the effective active state arrives, so as to perform subsequent hammer refresh operations. This helps to prevent hammer refresh operations on a new address before the current hammer refresh operation on the current target address is completed, and also helps to prevent repeated hammer refresh operations on the same target address. This allows hammer refresh operations to be performed on more different target addresses in the same time, thereby further improving the protection effect of the hammer refresh circuit 100 on the stored data.

[0050] In some embodiments, please refer to Figure 7 The latch module 120 includes multiple latch units 121. When the latch enable signal is in a valid active state, the latch unit 121 sequentially latches the corresponding input address as the target address so as to perform subsequent hammer refresh operations.

[0051] In some embodiments, an address selection module 700 is further included, connected to multiple sets of latching units 121 and the determination module 130, and configured to select at least one target address from multiple target addresses output by multiple sets of latching units 121 and provide it to the determination module 130.

[0052] like Figure 7 As shown, the latch module 120 includes N sets of latch units 121 (latch unit 1 to latch unit N), and the enable module 110 has N logic gates (including but not limited to) corresponding one-to-one with the N sets of latch units 121. Figure 7 (The AND gate is shown). The input terminals of each logic gate in the enable module 110 are connected to the first latch control signal 1 to the first latch control signal N corresponding to each latch unit 121, and are also connected to the second latch control signal. Based on the first latch control signal corresponding to each latch unit 121 and the second latch control signal generated by the determination unit, latch enable signals 1 to N corresponding to each latch unit 121 are given, thereby controlling each latch unit 121 (latch unit 1 to latch unit N) to latch the input address. The address selection module 700 can select one target address from multiple latch units 121. The determination module 130 compares the new address with the target address and / or determines whether the current hammer refresh operation performed at the current target address has been completed.

[0053] When the latch module 120 includes multiple latch units 121, the address selection module 700 can be configured to select one target address from the multiple latch units 121 according to the selection signal, so that the determination module 130 compares the input address to be latched with the target address in each latch unit 121. If the input address to be latched is the same as the target address in one of the latch units 121, a second latch control signal in an inactive state (e.g., low level) is generated, thereby controlling the latch module 120 not to latch the input address.

[0054] Please refer to Figure 8 In this embodiment, the hammer strike prevention circuit 100 further includes an address selection module 700, and the determination module 130 includes a first determination unit 131 and a second determination unit. The specific working principle can be referred to the description in the foregoing embodiment, and will not be repeated here.

[0055] In some embodiments, the latch unit 121 includes at least one of a latch (not shown), a register (not shown), and a flip-flop (not shown). It receives the latch enable signal at the clock signal input terminal so that when the latch enable signal is in a valid active state, it sequentially latches the corresponding input address as the target address so as to perform subsequent hammer refresh operations.

[0056] In some embodiments, please refer to Figure 9 When the latch unit 121 is the latch, the latch unit 121 includes a transmission gate and a tri-state buffer. The transmission gate is connected to the output of the enable module 110. The transmission gate is configured to selectively receive the input address to be latched based on the latch enable signal. The tri-state buffer is connected to the output of the transmission gate and the output of the enable module 110, and is configured to control the latch module 120 to output or not output data based on the latch enable signal. The latch enable signal and the input address are inverted by a NOT gate and then given to the transmission gate. The transmission gate is turned on or off under the control of the latch enable signal. Figure 9 In the example shown, the transmission gate opens and the input address is passed in when the latch enable signal is high, and the latch unit 121 latches when the latch enable signal is low.

[0057] The second aspect of this application discloses a memory 1000, please refer to... Figure 10 It includes the hammer-prevention circuit 100 from the first aspect mentioned above.

[0058] The memory 1000 in this application can be dynamic random access memory (DRAM), or other types of memory, including but not limited to SRAM, ROM, PROM, EEPROM, SDRAM, DDR / 2 SDRAM, DDR / 3 SDRAM, DDR / 4 SDRAM, GDDRx, EDO / FPMS, FeRAM, ReRAM, RLDRAM, etc.

[0059] The above scheme generates a second latch control signal through the determination module 130, and the second latch control signal is configured based on preset conditions, which include at least one of the following: whether the input address to be latched is the same as the target address latched in the latch module 120; or whether the current hammer refresh operation performed on the current target address has been completed. Therefore, the enable module 110 can control the latch module 120 to latch the corresponding input address as the target address based on whether the new address is the same as the target address and / or whether the current hammer refresh operation of the current target address is completed, so as to perform a hammer refresh operation on the target address; the determination module 130, by determining whether the current hammer refresh operation of the current target address is completed, helps to prevent the hammer refresh operation on the new address from being performed before the current hammer refresh operation of the current target address is completed, thereby improving the protection effect of the hammer refresh circuit 100 on the stored data; by determining whether the new address is the same as the target address, it helps to prevent repeated hammer refresh operations on the same target address, thereby enabling the hammer refresh operation to be performed on more different target addresses in the same time, and further improving the protection effect of the hammer refresh circuit 100 on the stored data.

[0060] In some embodiments, the memory 1000 further includes a decoding module (not shown in the figure), which decodes the normal access command received by the memory 1000 from the host (not shown in the figure) to generate an activation signal and the input address in the foregoing embodiments of the present invention. The first latch control signal in the foregoing embodiments of the present invention is generated by other internal logic circuits (not shown in the figure) of the memory 1000 after processing the activation signal.

[0061] Furthermore, the decoding module decodes the received normal access instructions. Specifically, it can perform instruction decoding to generate activation signals and address decoding to generate input addresses. The hammer-off prevention circuit 100 is coupled to this decoding module. Due to memory size limitations, the number of latches in the memory used to latch input addresses is also limited. When the number of activation signals is greater than or even far greater than the number of latches, the latches cannot latch the input address corresponding to each activation signal and perform hammer-off refresh operations on all these input addresses. Therefore, the activation signals can be counted by a counter, and after certain conditions are met (e.g., several activation signals correspond to the same address), a first latch control signal is generated to latch the input address corresponding to the respective activation signal.

[0062] Those skilled in the art will readily recognize that numerous modifications and variations can be made to the apparatus and method while maintaining the teachings of this application. Therefore, the above disclosure should be considered limited only by the scope of the appended claims.

Claims

1. A hammer-damping prevention circuit for adjusting the hammer-damping refresh operation of a memory, characterized in that, include: The enabling module is configured to receive a first latch control signal and a second latch control signal, and generate a latch enable signal based on the first latch control signal and the second latch control signal. The latch enable signal is in a valid active state when both the first latch control signal and the second latch control signal are in a valid active state. A latch module is connected to the enable module. When the latch enable signal is in a valid active state, the latch module latches the corresponding input address as the target address for subsequent hammer refresh operations. The first latch control signal is generated based on the latch state of the latch module. The determination module is connected to the enable module and generates the second latch control signal according to the target address; The second latch control signal is configured based on preset conditions, which include at least one of the following: Whether the input address to be latched is the same as the target address latched in the latching module; or Has the current hammer refresh operation performed at the current target address completed? 2. The hammer impact prevention circuit according to claim 1, characterized in that, The determination module includes: The first determination unit is configured to compare the input address to be latched with the target address to determine whether the input address to be latched is the same as the target address latched in the latching module.

3. The hammer impact prevention circuit according to claim 2, characterized in that, The first determination unit includes a comparator, which includes the same number of XOR gates as the input address and the target address. Each XOR gate compares the corresponding bits of the input address and the target address to be latched, and then outputs the second latch control signal via NAND gates, OR gates, XOR gates in the comparator, or an integrated circuit with logic operation function.

4. The hammer-prevention circuit according to any one of claims 1 to 3, characterized in that, The determination module also includes: The second determination unit is configured to count the hammer refresh operation and determine that the current hammer refresh operation executed by the current target address is completed when the count value reaches a first value.

5. The hammer impact prevention circuit according to claim 4, characterized in that, The second determination unit includes an adder, a counter, or an integrated circuit with counting function to count the hammer refresh operation, and outputs the second latch control signal when the count value reaches a first value.

6. The hammer-damping prevention circuit according to any one of claims 1 to 3, characterized in that, The latching module includes multiple latching units. When the latching enable signal is in a valid active state, the latching unit sequentially latches the corresponding input address as the target address so as to perform subsequent hammer refresh operations.

7. The hammer-damping prevention circuit according to claim 6, characterized in that, Also includes: The address selection module, connected to multiple sets of latching units and the determination module, is configured to select at least one target address from multiple target addresses output by the multiple sets of latching units and provide it to the determination module.

8. The hammer-damping prevention circuit according to claim 6, characterized in that, The latching unit includes at least one of a latch, a register, and a flip-flop. It receives the latch enable signal at the clock signal input terminal so that when the latch enable signal is in a valid active state, it sequentially latches the corresponding input address as the target address for subsequent hammer refresh operations.

9. The hammer-damping prevention circuit according to claim 8, characterized in that, When the latch unit is the latch, the latch unit includes: A transmission gate is connected to the output of the enable module; the transmission gate is configured to selectively receive the input address to be latched based on the latch enable signal; A tri-state buffer, connected to the output of the transmission gate and the output of the enable module, is configured to control the latch module to output or not output data based on the latch enable signal.

10. A memory, characterized in that, Includes the hammer strike prevention circuit according to any one of claims 1 to 9.

11. The memory according to claim 10, characterized in that, The memory further includes a decoding module that decodes received normal access instructions to generate an activation signal and the input address, wherein a first latch control signal is generated based on the activation signal.

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