Static random access memory

Abstract

The invention discloses a static random access memory, which comprises Q storage arrays, and the storage arrays comprise M rows of storage units; the row decoding circuit is used for decoding an input address signal to obtain a chip selection signal and a row selection signal; the line-by-line voltage control circuit is used for selecting the first storage array corresponding to the chip selection signal and the target line storage unit corresponding to the line selection signal to perform read-write operation; the column data shifting circuit is used for shifting data in at least one clock period during writing operation, and performing data writing for a target row storage unit through a writing bit line under the control of an input column enable signal; the read-out selection circuit is used for pre-charging the read-out bit line of the target row storage unit during read operation and then reading out data from the target row storage unit through the multi-stage read-out bit line; a data IO port, a DC / DC circuit and a time sequence control circuit. The invention relates to a novel circuit architecture of a low-power-consumption static random access memory.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a static random access memory. Background Art

[0002] OLED microdisplay technology, with its self-luminous properties, submillimeter pixel density, ultra-wide color gamut, microsecond response speed, and low power consumption, has become the preferred display solution for power-sensitive wearable devices such as VR / AR. However, as displays evolve towards 4K / 8K resolutions and refresh rates exceeding 200Hz, timing controllers must integrate larger frame buffers to support real-time image processing algorithms such as multi-frame interpolation compensation, local dimming mapping, gamma correction, and dynamic false contour removal.

[0003] While current mainstream static random access memory (SRAM) frame buffers offer nanosecond access latency, their dynamic power consumption accounts for 50%-70% of total system power consumption. Furthermore, static power consumption caused by subthreshold leakage current increases exponentially with process scaling, severely limiting device battery life and consuming high power. Designing low-power SRAM is crucial for wearable VR / AR devices with high resolution and high refresh rates. Summary of the Invention

[0004] The present invention provides a static random access memory to reduce power consumption.

[0005] According to one aspect of the present invention, a static random access memory is provided, comprising: Q memory arrays, a row decoding circuit, a row-by-row voltage control circuit, a column data shift circuit, a timing control circuit, a readout selection circuit, a data IO port, and a DC / DC circuit, wherein the memory array comprises M rows of memory cells, and Q and M are both greater than or equal to 2;

[0006] The row decoding circuit is used to decode the input address signal to obtain a chip selection signal and a row selection signal;

[0007] The row-by-row voltage control circuit is used to provide independent power control signals for the memory array and each row of memory cells, select the first memory array corresponding to the chip select signal and the target row memory cells corresponding to the row select signal for read and write operations, provide a first power control signal to the target row memory cells, and provide a second power control signal to the target row memory cells after the row select signal is deactivated;

[0008] When the read / write operation is a write operation, the column data shift circuit is used to shift in data within at least one clock cycle, and under the control of the input column enable signal, write data to the target row storage unit through the write bit line; when the column data shift circuit writes data to the X-th row storage unit through the write bit line, the column data shift circuit is used to simultaneously preload data corresponding to the (X+1)-th row storage unit, where X is greater than or equal to 1 and less than or equal to M;

[0009] When the read / write operation is a read operation, the read selection circuit is used to precharge the read bit line of the target row memory cell and then read data from the target row memory cell through the multi-level read bit line;

[0010] The data IO ports are electrically connected to the column data shift circuit and the readout selection circuit respectively, for inputting and outputting data;

[0011] The DC / DC circuit is electrically connected to the row-by-row voltage control circuit, and is used to provide the power control signal to the row-by-row voltage control circuit;

[0012] The timing control circuit is electrically connected to the row decoding circuit, the row-by-row voltage control circuit, the column data shift circuit and the readout selection circuit respectively, and is used to perform timing control on each circuit.

[0013] Furthermore, the input power supply terminal VDD of a row of the storage cells is electrically connected to the same output terminal of the row-by-row voltage control circuit;

[0014] The row-by-row voltage control circuit provides a first power control signal of a high level to the input power supply terminal VDD of the storage cells in one row, and provides a second power control signal of a low level;

[0015] The low level of the second power control signal has a value range of 0.3V-0.9V.

[0016] Furthermore, the storage array is divided into a storage areas in terms of spatial distribution, each storage area includes b rows and c columns of storage cells, where a, b, and c are all integers greater than 0;

[0017] The row decoding circuit is used to generate a row selection signals, sequentially control the a storage areas to perform read and write operations, and control the b rows of storage units in the storage area to be opened sequentially for read and write operations.

[0018] Furthermore, the readout selection circuit is used to perform a read operation on a column of a*b memory cells using two levels of readout bit lines;

[0019] The two-stage readout bit line includes a global bit line and a sub-bit lines respectively provided corresponding to the a storage blocks, wherein the b rows of storage cells in the storage block share one sub-bit line, and the sub-bit lines are electrically connected to the global bit line via MOS switches;

[0020] The readout selection circuit is used to independently provide a precharge signal for each of the sub-bit lines. When the target row storage unit performs a read operation, a valid precharge signal is provided to the sub-bit line corresponding to the target row storage unit to precharge the sub-bit line and the global bit line, while the other sub-bit lines are disconnected from the global bit line.

[0021] Furthermore, the row-by-row voltage control circuit is used to delay the read and write operations of the target row memory cells after the second power control signal is switched to the first power control signal.

[0022] Furthermore, the row decoding circuit includes a read-write decoder shared by read and write decoding, the row-by-row voltage control circuit includes a data selector, the read-write decoder is electrically connected to the data selector, and a write word line and a read word line are provided between the data selector and the memory array;

[0023] The data selector is used to control the transmission path between the read-write decoder and the write word line to be conductive when performing a write operation;

[0024] Alternatively, the data selector is used to control the transmission path between the read / write decoder and the read word line to be conductive during a read operation;

[0025] The data selector is used to control the effective opening time of the write word line and the read word line by using a narrow pulse signal.

[0026] Furthermore, the storage unit is an 8T read-write separation storage unit suitable for low-voltage operation;

[0027] The 8T memory cell includes two PMOS transistors and six NMOS transistors;

[0028] The two PMOS transistors and the two NMOS transistors in the storage unit form two cross-coupled bistable latch structures for latching written data.

[0029] Furthermore, the column data shift circuit is a 1024-bit register, and the 1024-bit register is divided into eight 128-bit data shift blocks;

[0030] The column data shift circuit is used to shift in data under the control of a data shift-in signal, wherein each time new data is shifted in, the previously shifted in data is shifted back 128 bits so as to completely shift in the data required for a row of storage cells within 8 clock cycles;

[0031] The column data shift circuit is used to write data under the control of the column enable signal. Each time data is written, the data of a row of memory cells is written into the corresponding row of memory cells through the write bit lines.

[0032] The static random access memory (SRAM) provided by this invention utilizes a novel read / write architecture. This novel low-power SRAM circuit architecture maintains video quality even at low voltages, making it particularly suitable for microdisplay applications. Its purpose is to reduce the read / write power consumption of the SRAM during operation, as well as the leakage power consumption of large-scale storage arrays. Furthermore, it maintains excellent read / write latency and noise performance under low-voltage conditions.

[0033] Compared with the traditional structure, it has the following advantages: through the unique storage array organization and chip selection mechanism, a low-power feasible solution is achieved; at the same time, only one storage array block is in the active state for read and write operations, and the remaining (Q-1) blocks are in the idle state and only consume static power, which minimizes the overall dynamic power consumption; at the same time, the row-by-row writing method is adopted to reduce the number of row activations, further saving power consumption; the column data shift circuit eliminates the timing gap between data preparation and writing by constructing a write operation pipeline, improves data writing efficiency, and reduces writing delay; when processing high-resolution video data, the traditional architecture may take a long time to complete the writing of a frame of data, while the present invention The write operation pipeline can quickly write data into the storage array, ensuring that video data can be stored in a timely manner; in terms of read operations, the coordinated work of the readout selection circuit and the multi-level bit line readout circuit ensures that data can be read and latched quickly and accurately, effectively reducing the readout delay; through precise timing control circuits and stable voltage supply, the entire circuit can operate stably under low voltage conditions; precise timing control ensures that each module operates at the correct time point, avoiding signal conflicts and interference, thereby reducing the generation of noise; in practical applications, micro-display devices using the architecture of the present invention can present video quality at low voltage that is almost the same as that at high voltage and have the potential for low power consumption.

[0034] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 It is a schematic diagram of a random access memory provided in the comparative example;

[0037] Figure 2 Schematic diagram of a static random access memory provided by an embodiment of the present invention;

[0038] Figure 3 is a schematic diagram of another static random access memory provided by an embodiment of the present invention;

[0039] Figure 4 is a schematic diagram of a storage array provided by an embodiment of the present invention;

[0040] Figure 5 It is a partial schematic diagram of a static random access memory provided by an embodiment of the present invention;

[0041] Figure 6 is a partial schematic diagram of another static random access memory provided by an embodiment of the present invention;

[0042] Figure 7 is a partial schematic diagram of another static random access memory provided by an embodiment of the present invention;

[0043] Figure 8 is a partial schematic diagram of another static random access memory provided by an embodiment of the present invention;

[0044] Figure 9 This is a schematic diagram of a timing signal of a static random access memory provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0046] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0047] Figure 1 It is a schematic diagram of a random access memory provided in the comparative example. Figure 1 As shown, it does not include a row-by-row voltage control circuit, and its current structure is different from the static random access memory provided by the present invention. In this embodiment, the random access memory is improved on the traditional single-power 6T static random access memory architecture. Currently, there are many methods for low-power video image processing, such as using a hybrid static random access memory structure, a dual-power supply voltage structure, a write-assist circuit, and an error correction code. Among them, reducing the power supply voltage is one of the most effective power reduction technologies in VLSI systems.

[0048] However, this technology has numerous drawbacks in practical applications. First, when the power supply voltage decreases, the signal swing decreases, which directly leads to a significant decrease in the SRAM's noise margin. In this case, the SRAM becomes more sensitive to internal and external noise interference. Second, the reduced power supply voltage slows transistor switching speeds and weakens drive capability, increasing SRAM read and write latency. In the field of video display, this seriously hinders the real-time transmission of image data and causes a decrease in video frame rate. Third, low power supply voltage poses a severe challenge to memory cell stability. Transistors have difficulty maintaining steady state at low voltages. At high temperatures or with process deviations, the probability of data loss or errors increases exponentially. Sharing the read and write ports of six memory cells further exacerbates stored data corruption. Further research is needed to improve the impact of low-voltage environments on SRAM read and write latency and noise.

[0049] In microdisplay applications, SRAM is primarily used for caching image data. To deliver smooth, clear images, microdisplay devices must process and display image data in real time, requiring frequent read and write operations on the SRAM to cache and update image information. This means the SRAM is in active mode most of the time to ensure timely processing and display of image data. Only when the microdisplay device is in standby, hibernation, or certain specific low-power modes does the SRAM remain in active mode to reduce power consumption. However, these states only account for a relatively small proportion of the time during normal microdisplay use. However, the power consumption of SRAM in active mode is generally higher.

[0050] When SRAM is accessed, whether for a read or write operation, only the cells in the selected row are activated and enter the active state, generating dynamic power consumption. The memory cells in the unselected rows remain in the data retention state, generating a certain amount of leakage power. In large-scale memory arrays, leakage power consumption cannot be ignored and has become a major source of power consumption. Several solutions have been proposed to reduce leakage current power consumption, but most only work for dormant SRAM modules. These solutions often fail when the SRAM is in active operation, causing the power consumption of the active SRAM to increase dramatically. In microdisplay applications, SRAM spends most of its time in the read / write state, caching image data. The power consumption of the active SRAM already accounts for over 30% of the total microdisplay power consumption. Therefore, further reducing the power consumption of the active SRAM is necessary to promote low-power microdisplay design and meet the growing demand for energy conservation and application requirements.

[0051] Figure 2 Schematic diagram of a static random access memory provided by an embodiment of the present invention, such as Figure 2As shown, the static random access memory includes: Q memory arrays 101, a row decoding circuit 102, a row-by-row voltage control circuit 103, a column data shift circuit 104, a timing control circuit 105, a read selection circuit 106, a data IO port 107 and a DC / DC circuit 108. The memory array 101 includes M rows of memory cells 109, where 109 represents one memory cell and 110 represents a row of memory cells, and Q and M are both greater than or equal to 2; the row decoding circuit 102 is used to decode the input address signal to obtain a chip select signal and a row select signal; the row-by-row voltage control circuit 103 is used to provide independent power control signals for the memory array 101 and each row of memory cells 110, select the first memory array corresponding to the chip select signal and the target row memory cell corresponding to the row select signal for read and write operations, provide a first power control signal to the target row memory cell and provide a second power control signal to the target row memory cell after the row select signal is deactivated; when the read and write operation is a write operation, the column data shift circuit 104 is used to The data is shifted in during the clock cycle, and data is written to the target row storage unit through the write bit line under the control of the input column enable signal; the column data shift circuit 104 is used to preload the data corresponding to the (X+1)th row storage unit when writing data to the Xth row storage unit through the write bit line, where X is greater than or equal to 1 and less than or equal to M; when the read / write operation is a read operation, the read selection circuit 106 is used to precharge the read bit line of the target row storage unit, and then read the data from the target row storage unit through the multi-level read bit line. The row storage unit performs data reading; the data IO port 107 is electrically connected to the column data shift circuit 104 and the readout selection circuit 106, respectively, for inputting and outputting data; the DC / DC circuit 108 is electrically connected to the row-by-row voltage control circuit 103, for providing a power control signal to the row-by-row voltage control circuit 103; the timing control circuit 105 is electrically connected to the row decoding circuit 102, the row-by-row voltage control circuit 103, the column data shift circuit 104, and the readout selection circuit 106, respectively, for performing timing control of each circuit.

[0052] Figure 2 The static random access memory shown is a read-write shared memory, wherein the memory array 101 is electrically connected to the read selection circuit 106 via the column data shift circuit 104. Figure 2 The static random access memory shared by read and write is shown to illustrate the memory structure and working principle.

[0053] In other embodiments, Figure 3 Schematic diagram of another static random access memory provided by an embodiment of the present invention, such as Figure 3 The static random access memory shown is a read-write separation memory, wherein the memory array 101 is directly electrically connected to the read selection circuit 106, and the optional storage unit 109 adopts an 8-tube read-write separation random access memory unit suitable for low voltage operation. Figure 3 The structure and working principle of the static random access memory with read and write separation are described as follows. Figure 2 The similarities are not repeated here, and the main description is Figure 2 Differences.

[0054] In this embodiment, the static random access memory can be used for display driving. The static random access memory is suitable for, but not limited to, a streaming line-by-line voltage-controlled low-power circuit architecture. This static random access memory architecture is suitable for low-power static random access memory frame buffers, which are advantageous for use in wearable VR / AR devices with high resolution and high refresh rate. This static random access memory architecture is also suitable for silicon-based micro-display driver chip frame buffers.

[0055] The static random access memory includes Q memory arrays 101, where Q is greater than 1. In this embodiment, the storage architecture of the Q memory arrays 101 can be exactly the same. The memory array 101 includes M rows of memory cells 109, where M is greater than 1. In other embodiments, if required by the product, at least two of the Q memory arrays may be different. The different memory arrays may have different storage architectures, which include storage capacity, arrangement of memory cells, etc. Q = 8, and the memory array 101 is 32KB. The static random access memory includes 8 32KB memory arrays 101, which are marked as Bank0 to Bank7 in sequence. For a 32KB memory array 101, the multiple memory cells 109 of the 32KB memory array 101 can be spatially divided into 256 rows and 1024 columns of memory cells 109.

[0056] The static random access memory also includes a row decoding circuit 102, a row-by-row voltage control circuit 103, a column data shift circuit 104, a timing control circuit 105, a readout selection circuit 106, a data IO port 107, and a DC / DC circuit 108. The timing control circuit 105 is electrically connected to the row decoding circuit 102, the row-by-row voltage control circuit 103, the column data shift circuit 104, and the readout selection circuit 106, and is used to generate the control signals required for read and write operations under the control of the WEN signal to perform timing control of each circuit. "DC" means direct current, and the DC / DC circuit 108 can be understood as a DC-to-DC converter. Of course, if the product requires it, the static random access memory can include at least one of a DC / DC circuit, a DC / AC circuit, an AC / AC circuit, and an AC / DC circuit, where "AC" means alternating current, and the AC / AC circuit can be understood as an alternating current-to-alternating current converter.

[0057] The row decoding circuit 102 can generate Q consecutive chip select signals, and the Q consecutive chip select signals are respectively set to correspond to the Q memory arrays 101. The row decoding circuit 102 can generate M consecutive row select signals, and the M consecutive row select signals are respectively set to correspond to the M rows of memory cells in the memory array 101. Based on this, the row decoding circuit 102 is used to receive the address signal and decode it to obtain the chip select signal and the row select signal. The address signal includes the chip address, and the chip select signal obtained after the chip address is decoded can activate a memory array 101 for read and write operations. The address signal also includes the row address, and the row select signal obtained after the row address is decoded corresponds to a row of memory cells 110 in the memory array 101 that is activated for read and write operations.

[0058] Specifically, the optional row decoding circuit 102 includes 3-8 row decoders. The row decoder has an 11-bit address signal, where bits <0:7> output an 8-bit row select signal, and bits <8:10> output a 3-bit chip select signal. In other words, the 11-bit address signal output by the row decoder includes a 3-bit chip select signal and an 8-bit row select signal. The row decoding circuit 102 can use the row decoder to generate eight consecutive 3-bit chip select signals and output them through bits <8:10>. The row decoding circuit 102 can use the row decoder to generate 256 different 8-bit row select signals and output them through bits <0:7>. The eight consecutive 3-bit chip select signals correspond to eight different memory arrays (Bank 0 to Bank 7). For a memory array, the 256 consecutive 8-bit row select signals correspond to 256 rows of memory cells in the memory array.

[0059] The row-by-row voltage control circuit 103 is electrically connected to the row decoding circuit 102. The row-by-row voltage control circuit 103 determines the memory array 101 corresponding to the chip select signal as the selected memory array and activates it based on the decoded address signal provided by the row decoding circuit 102. The selected memory array can be named the first memory array. The row of memory cells 110 corresponding to the row select signal is determined as the selected row of memory cells in the first memory array and is activated. The selected row of memory cells in the first memory array is named the target row of memory cells.

[0060] The row-by-row voltage control circuit 103 is electrically connected to each memory array 101 and each row of memory cells via word lines WL. The row-by-row voltage control circuit 103 is electrically connected to a DC / DC circuit 108 and receives a power signal from the DC / DC circuit 108. The DC / DC circuit 108 optionally steps down the external voltage VDDH to a voltage VDDL and stably supplies it to the row-by-row voltage control circuit 109. The power control signals output by the row-by-row voltage control circuit 103 via the word lines WL include a first power control signal and a second power control signal. Here, the first power control signal can be a high voltage level (VDDH), and the second power control signal can be a low voltage level (VDDL).

[0061] The row-by-row voltage control circuit 103 provides independent power control signals to the memory array 101 via word lines WL. The row-by-row voltage control circuit 103 then provides independent power control signals to each row of memory cells 110 via word lines WL. The input power supply terminal VDD of an optional row of memory cells 110 can be electrically connected to the same output terminal of the row-by-row voltage control circuit 103. The row-by-row voltage control circuit 103 provides a high-level first power control signal to the input power supply terminal VDD of a row of memory cells 110, and a low-level second power control signal. The low-level value of the second power control signal ranges from 0.3V to 0.9V. In other words, when the input power supply terminal VDD of the target row of memory cells undergoing data reading or writing is at a high voltage (VDDH), the data read / write state is in operation. When the input power supply terminals VDD of the remaining rows of memory cells are at a low voltage (VDDL), the data retention state is in operation. The lower the VDDL, the lower the leakage power consumption of the memory array 101 during the data retention state.

[0062] When the SRAM is not operating, the row-by-row voltage control circuit 103 provides a second power control signal VDDL to each memory array 101 and each row of memory cells 110. When the SRAM performs a read or write operation, the row-by-row voltage control circuit 103 switches the electrical signal of the word line WL corresponding to the first memory array from the second power control signal VDDL to the first power control signal VDDH based on the chip select signal, thereby activating the first memory array. Sequentially, the row-by-row voltage control circuit 103 switches the electrical signal of the word line WL corresponding to the target row of memory cells in the first memory array from the second power control signal VDDL to the first power control signal VDDH based on the row select signal, thereby turning on the target row of memory cells in the first memory array. The read and write operations mentioned herein refer to either a read operation or a write operation. The row decoding circuit 102 receives and decodes the G2 signal. The row-by-row voltage control circuit 103 can determine whether to perform a write operation or a read operation based on the G2 signal.

[0063] During read and write operations in the static random access memory (SRAM), the row-by-row voltage control circuit 103 determines the corresponding first memory array based on the chip select signal and provides the first power control signal VDDH to the first memory array and the second power control signal VDDL to the other seven memory arrays 101. This activates the first memory array, while the other seven memory arrays 101 are idle. Therefore, during read and write operations, only one of the eight memory arrays 101 is active and generates dynamic power consumption. The remaining seven memory arrays 101, due to the chip select signal VDDL being idle, only consume static power. Sequentially, the row-by-row voltage control circuit 103 determines the corresponding target row memory cell in the first memory array based on the row select signal and provides the first power control signal VDDH to the target row memory cell and the second power control signal VDDL to the other rows of memory cells 110. This activates the target row memory cell in the first memory array, while the other rows of memory cells in the first memory array remain disabled. Sequentially, the target row storage unit can be read and written, and then after the row selection signal corresponding to the target row storage unit is canceled, the second power control signal VDDL is provided to the target row storage unit to enable the target row storage unit to store data; sequentially, the data of the next row of storage units after the target row storage unit is read, written and stored. Therefore, the static random access memory adopts a row-by-row dynamic voltage control method for read and write operations, which can further optimize power consumption management. Taking the row-by-row storage of video data as an example, during the process of buffering a frame of video data, only the input power supply terminal VDD of the row of storage units where data is being written is in a high voltage (VDDH) data reading and writing working state, while the input power supply terminals VDD of the remaining rows of storage units are in a low voltage (VDDL) data retention working state.

[0064] The column data shift circuit 104 is electrically connected between the data IO port 107 and the memory array 101. The column data shift circuit 104 is electrically connected to the memory array 101 via multiple bit lines BL, at least one of which is a write bit line. During a write operation in the static random access memory (SRAM), the write operation is performed on a target row memory cell in the first memory array, determined based on an address signal. The column data shift circuit 104 is configured to shift data in from the data IO port 107 within at least one clock cycle. For example, if the column data shift circuit 104 can shift in a 128-bit data set from the data IO port 107 within one clock cycle, the data in the target row memory cell can be fully shifted in within eight clock cycles. After the column data shift circuit 104 prepares the data for the target row memory cell, it writes the prepared data into the enabled target row memory cell via the write bit line under the control of the input column enable signal G1. In other words, the data in the target row memory cell must first be shifted from the data IO port 107 into the column data shift circuit 104, which then transfers the data to the enabled target row memory cell. When the column data shift circuit 104 writes data to the Xth row of storage cells via the write bit lines, the data corresponding to the (X+1)th row of storage cells can be simultaneously shifted into the column data shift circuit 104. The column data shift circuit 104 includes a column decoder, which decodes the signal provided by the data IO port 107 to obtain the data corresponding to the target row of storage cells and shifts them in. The data is then sequentially written to the opened target row of storage cells via the write bit lines. This achieves parallel writing and shifting, forming a write operation pipeline and eliminating the timing gap between data preparation and writing. In this case, data preparation is the data shifting process. The data IO port 107 is used to input 128-bit data.

[0065] Figure 2 This is a read-write static random access memory, so the read select circuit 106 is electrically connected to the memory array 101 through the column data shift circuit 104. The read select circuit 106 is also electrically connected to the data IO port 107. The column data shift circuit 104 is electrically connected to the memory array 101 through multiple bit lines, at least one of which is a write bit line and at least one of which is a read bit line.

[0066] When performing a read operation in a static random access memory (SRAM), the read operation is performed on the target row of memory cells in the first memory array, determined based on the address signal. Read select circuit 106 is used to precharge the read bit lines of the target row memory cells based on the PRE signal. When the RWL signal is active, data is read from the target row memory cells via multiple read bit lines. Specifically, the read row of data is latched into a read latch. The read latch is located within read select circuit 106, and the data in the read latch can be output via data IO port 107. Optional data IO port 107 is used for outputting 128-bit data.

[0067] The static random access memory (SRAM) provided by this invention utilizes a novel read / write architecture. This novel low-power SRAM circuit architecture maintains video quality even at low voltages, making it particularly suitable for microdisplay applications. Its purpose is to reduce the read / write power consumption of the SRAM during operation, as well as the leakage power consumption of large-scale storage arrays. Furthermore, it maintains excellent read / write latency and noise performance under low-voltage conditions.

[0068] Compared with the traditional structure, it has the following advantages: through the unique storage array organization and chip selection mechanism, a low-power feasible solution is achieved; at the same time, only one storage array block is in the active state for read and write operations, and the remaining (Q-1) blocks are in the idle state and only consume static power, which minimizes the overall dynamic power consumption; at the same time, the row-by-row writing method is adopted to reduce the number of row activations, further saving power consumption; the column data shift circuit eliminates the timing gap between data preparation and writing by constructing a write operation pipeline, improves data writing efficiency, and reduces writing delay; when processing high-resolution video data, the traditional architecture may take a long time to complete the writing of a frame of data, while the present invention The write operation pipeline can quickly write data into the storage array, ensuring that video data can be stored in a timely manner; in terms of read operations, the coordinated work of the readout selection circuit and the multi-level bit line readout circuit ensures that data can be read and latched quickly and accurately, effectively reducing the readout delay; through precise timing control circuits and stable voltage supply, the entire circuit can operate stably under low voltage conditions; precise timing control ensures that each module operates at the correct time point, avoiding signal conflicts and interference, thereby reducing the generation of noise; in practical applications, micro-display devices using the architecture of the present invention can present video quality at low voltage that is almost the same as that at high voltage and have the potential for low power consumption.

[0069] Figure 4 is a schematic diagram of a storage array provided by an embodiment of the present invention, such as Figure 4The optional memory array 101 shown is spatially divided into a memory areas 111, each including b rows and c columns of memory cells, where a, b, and c are all integers greater than 0. The row decoding circuit 102 is used to generate a row selection signals to sequentially control the a memory areas 111 to perform read and write operations, and to control the sequential opening of b rows of memory cells 110 in the memory area 111 for read and write operations.

[0070] In this embodiment, the storage array 101 is spatially divided into a storage area 111, which are marked as storage area 111 (1), storage area 111 (2), ..., storage area 111 (a) in sequence. The storage architecture of each storage area 111 is the same. The storage area 111 includes b rows of storage cells 110 and c columns of storage cells 109, where a, b, and c are all integers greater than 0. One storage area 111 corresponds to one row selection signal, so the row decoding circuit 102 is used to generate a row selection signal to control the a storage areas 111 to perform read and write operations in sequence. The storage area 111 corresponding to the row selection signal is the target storage area 111, and the b rows of storage cells 110 in the target storage area 111 are sequentially opened. Among them, a row of c storage cells 109 is opened at the same time, and the column data shift circuit 109 performs read and write operations on a row of c storage cells 109; sequentially, the column data shift circuit 109 performs read and write operations on the b rows of storage cells in the target storage area 111 respectively.

[0071] For a 32K static random access memory (SRAM), it can be spatially divided into 256 rows and 1024 columns, where each 16 rows of memory cells constitute a memory block 111, for a total of 16 memory blocks 111. The row decoding circuit 102 is then used to generate 16 row select signals, sequentially controlling the 16 memory blocks 111 for read and write operations. This reduces the load capacitance of the bit lines and increases the speed of data writing and reading. For the 16 rows of memory cells in memory block 111, the row-by-row voltage control circuit 103 controls the 16 rows of memory cells to be enabled row by row for read and write operations, with all 1024 memory cells in a row being enabled simultaneously for read and write operations. For a row of memory cells, when the row select signal is valid, all 1023 memory cells in a row are enabled simultaneously for read and write operations. Therefore, the load capacitance of the row select signal is relatively large, requiring a larger buffer to improve the drive capability of the row select signal and reduce write latency. In the design of the present invention, a buffer with 5 times the drive capability is used.

[0072] Figure 5 FIG. 1 is a partial schematic diagram of a static random access memory provided by an embodiment of the present invention. Figure 5As shown, the static random access memory includes two levels of wordline decoding circuits, namely a first-level decoding circuit 112 and a second-level decoding circuit 113. This structure groups decoding signals with the same or similar functions, thereby reducing the size of the row decoding circuit 102, optimizing circuit delay, and improving the stability of the decoding circuit. The first-level decoding circuit 112 can be integrated into the row decoding circuit 102, and the second-level decoding circuit 113 can be integrated into the row decoding circuit 102, or the row-by-row voltage control circuit 103, or the timing control circuit 105, without limitation, and any suitable layout is possible.

[0073] Specifically, the first-stage decoding circuit 112 can be a static decoder, primarily used to pre-decode the address signal to generate a total of 20 decoded signals, including L<0:3>, M<0:7>, and H<0:7>, which are then fed into the second-stage decoding circuit 113. In the first-stage decoding circuit 112, L<0:3> is generated by a 2:4 decoder, while M<0:7> and H<0:7> are generated by a 3:8 decoder. The 3:8 decoder is expanded by two stages of 2:4 decoders. This ensures that the delay between the decoded signals generated by the first-stage decoding circuit 112 and input to the second-stage decoding circuit 113 is consistent, thus eliminating decoding glitches.

[0074] The second-stage decoding circuit 113 can be static decoding, primarily used for detailed decoding. To reduce the circuit size of the second-stage decoding circuit 113 and reduce wiring, decoding signals with the same or similar functions can be grouped. Specifically, before the second-stage decoding circuit 113, cells with the same control signal L<0:3> can be grouped and then input into the second-stage decoding circuit 113. An AND operation is then performed on M<0:7> and H<0:7> to control L<0:3>. This converts the four three-input AND gates into four two-input AND gates. The control signal generated by the AND operation on M<0:7> and H<0:7> is connected to the four two-input AND gates, and the corresponding transistors are simultaneously turned on, which is equivalent to increasing the driving capability. Therefore, the circuit size of the corresponding transistors can be optimized to 1 / 4 of the original size, achieving a reduction in area.

[0075] According to the test, the delay of the optimized row decoding circuit 102 is 250.77 ps. Compared with the traditional three-input AND gate decoding method, the present invention reduces the decoding delay by 16.58%.

[0076] The optional readout selection circuit 106 is used to use two-level readout bit lines to read a*b memory cells in a column; the two-level readout bit lines include a global bit line and a sub-bit lines respectively set corresponding to a storage area, and b rows of memory cells in the storage area share a sub-bit line, and the sub-bit line is electrically connected to the global bit line through a MOS switch; the readout selection circuit is used to independently provide a pre-charge signal for each sub-bit line. When the target row memory cell is read, a valid pre-charge signal is provided to the sub-bit line corresponding to the target row memory cell to pre-charge the sub-bit line and the global bit line, while the other sub-bit lines are disconnected from the global bit line.

[0077] In this embodiment, a two-level bitline readout scheme is employed for a column of 256 memory cells, resulting in 16 sub-bitlines Sub_RBL. Each column of 16 memory cells shares a sub-bitline. The readout select circuit independently controls the precharge signal Sub_PRE for each sub-bitline, and the sub-bitlines are connected to the global bitline via MOS switches. When a memory block is selected for data readout, the precharge signal for the selected block becomes active, turning on the MOS switch between the sub-bitline corresponding to the selected block and the global bitline. The corresponding readout select circuit then precharges the global bitline, and thus the sub-bitlines corresponding to the selected block. The MOS switches between the sub-bitlines corresponding to unselected blocks and the global bitline are disconnected, and the sub-bitlines of the unselected blocks are not precharged. Data readout utilizes hierarchical bitline readout, with the global and local bitlines performing the readout operation. This two-level bitline readout scheme eliminates the need for sense amplifiers, reducing circuit complexity and area.

[0078] Figure 6 is a partial schematic diagram of another static random access memory provided by an embodiment of the present invention, Figure 7 is a partial schematic diagram of another static random access memory provided by an embodiment of the present invention. Figure 8 is a partial schematic diagram of another static random access memory provided by an embodiment of the present invention. Figure 9 This is a schematic diagram of a timing signal of a static random access memory provided by an embodiment of the present invention. Figures 5 to 8 The structures can be combined and connected to form the required static random access memory.

[0079] Combine Figures 5 to 8 As shown, the optional row-by-row voltage control circuit 103 is used to delay the read and write operations of the target row memory cells after the second power control signal VDDL is switched to the first power control signal VDDH.

[0080] In this embodiment, the row-by-row voltage control circuit 103 may be a row-by-row dynamic voltage control circuit. When the row select signal is high, the circuit pulls the VDD of the target row memory cell up to VDDH. When the row select signal of the target row memory cell is deactivated or low, the circuit pulls the VDD of the target row memory cell down to VDDL. When the row select signal is high, the row-by-row voltage control circuit 103 pulls the VDD of the target row memory cell up from VDDL to VDDH. Because the voltage level rise has a certain delay, data reading and writing must wait until the VDD level of the target row memory cell stabilizes. Therefore, a certain delay operation is required for the row select signal.

[0081] Specifically, row-by-row voltage control circuit 103 consists of PM1, NM1, NM2, and an inverter 114. PM1 is a PMOS transistor, and NM1 and NM2 are both NMOS transistors. The gates of PM1, NM2, and NM2 are connected to the output terminal Decn of inverter 114. The input terminal of inverter 114 is the decoded signal generated by row decoding circuit 102, which includes the row select signal. The source of PM1 is connected to the high voltage VDDH, and the drain is connected to the drain of NM1 to form another inverter. The source of NM2 is connected to the low voltage VDDL. V_Ctrl is electrically connected to the input power supply terminal VDD of the target row memory cell.

[0082] When the decode signal dec (herein, the row select signal) generated by the row decode circuit 102 is at a low level, after the decode signal dec passes through the inverter 114, Decn is at a high level, PM1 is turned off, and both NM1 and NM2 are turned on. Then, the low level VDDL received by the source of NM2 discharges V_Ctrl through NM1 and NM2, pulling V_Ctrl down to the low level VDDL, thereby reducing the power supply voltage of the input power supply terminal VDD of the corresponding row of memory cells. When the decode signal dec (herein, the row select signal) generated by the row decode circuit 102 is at a high level, after the decode signal dec passes through the inverter 114, Decn is at a low level, PM1 is turned on, and both NM1 and NM2 are turned off. Then, the high level VDDH received by the source of PM1 charges V_Ctrl through PM1, pulling V_Ctrl up to the high level VDDH, thereby increasing the power supply voltage of the input power supply terminal VDD of the corresponding row of memory cells.

[0083] When V_ctrl is stable, that is, when the power supply voltage of the input power supply terminal VDD of the target row storage unit is stable, the data read and write operations are performed, which can avoid noise and delay caused by voltage instability. At the same time, the switching of VDDH and VDDL of the input power supply terminal VDD of the storage unit will not cause the loss of dynamic power consumption of the storage unit, but only affect the static power consumption of the storage unit. Among them, when the input power supply terminal VDD of the storage unit is VDDL, it is used to maintain the data of the storage unit. The value of VDDL cannot be too low. When the VDDL voltage value is lower than a certain threshold, it may cause the storage data to be lost. Therefore, it is necessary to ensure that the value of VDDL is greater than 2VTH. In the present invention, the value of VDDH is 0.9V, and the value of VDDL is 0.4V. The leakage power consumption of the storage unit when the voltage is maintained at 0.4V and 0.9V is 0.375nW and 1.875nW respectively. With a memory architecture featuring row-by-row voltage control circuit 103, when the memory array 101 is reading or writing data, only the memory cells 109 in the row being read or written are in a high-leakage state, while the remaining memory cells are in a low-leakage state. For eight 32K memory cells, this reduces the memory array's power consumption by 79.96% when reading or writing data.

[0084] Figure 7 The static random access memory shown is suitable for a random access memory type buffer of a micro display, and a dual-frame buffer can be used for read and write operations. The same memory array does not perform read and write operations simultaneously, and no delay is required. In other words, the first memory array for write operations and the first memory array for read operations are not the same memory array. Therefore, in this embodiment, a shared read and write decoding method is adopted, that is, the read and write circuits share the row decoding and chip select decoding circuits. The optional row decoding circuit 102 includes a read-write decoder shared by read and write decoding, and the row-by-row voltage control circuit 103 includes a data selector MUX. The read-write decoder is electrically connected to the data selector MUX, and a write word line WWL and a read word line RWL are included between the data selector MUX and the storage array (including multiple cells); the data selector MUX is used to control the transmission path between the read-write decoder and the write word line WWL when performing a write operation; or, the data selector MUX is used to control the transmission path between the read-write decoder and the read word line RWL when performing a read operation; the data selector MUX is used to use a narrow pulse signal to control the effective opening time of the write word line WWL and the read word line RWL.

[0085] The optional storage unit (i.e., cell) is an 8T read-write separation storage unit suitable for low-voltage operation. The 8T storage unit includes two PMOS transistors and six NMOS transistors. The two PMOS transistors and two NMOS transistors in the storage unit form two cross-coupled bistable latch structures for latching written data. In other embodiments, the data selector MUX can also be integrated into the timing control circuit.

[0086] Specifically, for traditional 6T memory cells, since data only needs to be written once in a micro display, but needs to be read multiple times according to the image processing algorithm, frequent read and write operations and frequent changes in storage voltage are more likely to cause data corruption in the memory cell. Although the problem of data read and write operations destroying the storage value of the internal node can be improved by adjusting the transistor size, it cannot be truly solved completely. Therefore, the use of an 8T memory cell architecture with read-write separation can avoid this problem. The 8T memory cell adopts a read-write separation architecture, and read and write do not affect each other, which improves the read-write stability and read-write noise tolerance. The 8-transistor memory cell is more suitable for working under low voltage. For this embodiment, due to the use of the row-by-row voltage control circuit 103, the use of an 8T memory cell is more applicable. The read and write transistors of the 8T memory cell can be optimized separately, and non-critical transistors can adopt the minimum size.

[0087] As described above, the display frame buffer adopts a "ping-pong" operation, and reading and writing do not occur simultaneously. Therefore, a data selector MUX circuit is used to select the decoded signal dec generated by the row decoding circuit 102.

[0088] After the row select signal dec is generated, the data selector MUX selects the read and write signals. When the WEN signal is high, a write operation is performed. The decoded signal dec generated by the row decoder circuit 102 is connected to the write word line WWL, controlling the writing of data to the memory cell through the WWL path. When the WEN signal is low, a read operation is performed. The decoded signal dec generated by the row decoder circuit 102 is connected to the read word line RWL, controlling the reading of data from the memory cell through the RWL path. Furthermore, a narrow pulse signal NCLK is used to control the active turn-on time (i.e., the active high time) of the write and read word lines WWL and RWL. This reduces the leakage current and resulting power consumption along the bit line BL when the read / write transistors of the memory cell are turned on, further achieving the goal of low-power design. The narrow pulse time is 460ns.

[0089] As described above, after row select signal dec is generated by row decoder circuit 102, it still needs to pass through two circuit stages before reaching the gate of the read / write transistor of the memory cell. This provides time for the power supply signal to stabilize. In this embodiment, the power supply stabilization time is 10 ps, ​​so no additional delay operation is required.

[0090] In the 8T read-write splitting memory cell, P1, P2, N1, and N2 form two cross-coupled bistable latch structures for latching written data. The 8T read-write splitting memory cell includes two PMOS transistors, P1 and P2, and six NMOS transistors, N1, N2, N3, N4, N5, and N6.

[0091] If the data at the internal node A of the memory cell is "1," the data latched by the memory cell is "0." During a read operation, both the PRE and Sub_PRE signals are low. The PRE signal turns on the PMOS transistor electrically connected to them, and the Sub_PRE signal turns on the PMOS transistor electrically connected to them. This precharges the read sub-bit line Sub_RBL and the read global bit line GRBL to VDD through the PMOS transistors.

[0092] When the read operation starts, the precharge signal PRE and the Sub_PRE signal both become high level, and the PMOS transistor electrically connected to the PRE signal and the PMOS transistor electrically connected to the Sub_PRE signal are both turned off, which can stop charging the sub-bit line Sub_RBL and the global bit line GRBL.

[0093] When the read word line RWL is then turned on for data reading, when the RWL signal of the memory cell on the sub-bit line Sub_RBL is valid, the global bit line GRBL discharges through the sub-bit line Sub_RBL where the memory cell is located based on the data latched in the memory cell, completing the data reading. This read circuit has a simple structure, fast read speed, and omits the read amplifier. Specifically, when reading data, the first read transistor N6 is turned on. Since the data at internal node A is "1", the second read transistor N5 is also turned on. The discharge path formed by transistors N5 and N6 discharges Sub_RBL to "0". After reversing, the NMOS transistor connected thereto is turned on, discharging the global bit line GRBL to "0". When GREN is high, the output is "0", which is the value latched in the memory cell. The read analysis process when the memory cell is "1" is similar to the analysis when it is stored as "0".

[0094] refer to Figures 5 to 8 As shown, the optional column data shift circuit 104 is a 1024-bit register, which is divided into 8 128-bit data shift blocks (Group0 to Group7); the column data shift circuit 104 is used to shift in data under the control of the data shift-in signal Shift_en, wherein each time new data is shifted in, the previously shifted in data is shifted backward by 128 bits so that the data required by a row of memory cells can be completely shifted in within 8 clock cycles; the column data shift circuit 104 is used to write data under the control of the column enable signal G1, wherein each time data is written, the data of a row of memory cells is written into the corresponding row of memory cells via the write bit lines.

[0095] In this embodiment, the column data shift circuit 104 includes a 1024-bit shift register and a trigger, Shift_register, resulting in a simple structure. The 1024-bit shift register is divided into eight 128-bit data shift blocks, Groups, labeled Group0 through Group7. When the data shift-in signal Shift_en is asserted, data begins to be shifted in. Each time new data is shifted in, all previous data is shifted back 128 bits. This allows the required data signals for a row of memory cells to be fully shifted in within eight clock cycles. Once the data for a row of memory cells has been fully shifted in, the data for the row of memory cells is written to the bit lines BL under the control of the column enable signal G1, and the data is then written to the corresponding row of memory cells. When the WEN signal activates the word lines, data is written to all memory cells in a row simultaneously. While data for the previous row is being written, the column data shift circuit 104 generates the bit line data for the next row, forming a write operation pipeline. This eliminates the timing gap between data preparation and writing, improving the speed and efficiency of data writing. Row-by-row writing reduces the number of row activations. In traditional SRAM circuits, each write requires row activation. However, the streaming row-by-row writing architecture only activates the word line once a row of data is ready, thereby reducing the number of row activations and saving power.

[0096] As described above, the column data shift circuit 104 adopts a stream architecture of column data shift and a three-level collaborative optimization design, which can reduce reading and writing power consumption by 50%.

[0097] In microdisplays, the image processing module of the display driver circuit requires frequent sequential data access. Using a shift register can reduce address decoding overhead. Furthermore, the dynamic power consumption of a shift register primarily comes from flip-flop toggling. In display driver scenarios, data access patterns are highly sequential. Using a shift register reduces address decoding and random access overhead, optimizes the input capacitance of the flip-flops, and thus reduces dynamic power consumption.

[0098] The static random access memory provided by the present invention adopts a new read-write architecture, which is a new low-power static random access memory circuit architecture. The architecture can be composed of 8 32KB storage arrays, innovatively integrating row-by-row dynamic voltage control circuits, realizing row-level power switching through a PMOS / NMOS combination structure, and reducing the static power consumption of inactive rows; designing a two-level word line decoding mechanism, optimizing the three-input AND gate into a two-input structure through signal grouping reconstruction, reducing decoding delay; constructing a 128-bit column data shift pipeline, eliminating timing gaps through an 8-clock cycle preload mechanism, and coordinating with narrow pulse control to reduce leakage current, thereby improving write efficiency; developing a hierarchical readout architecture, replacing the sense amplifier with a Sub_RBL / GRBL two-level bit line, and simplifying the circuit structure. Compared with the traditional structure, the present invention reduces overall dynamic power consumption through a unique storage array organization and chip select mechanism, reduces the number of row activations and the leakage current of inactive rows through row-by-row writing, and further saves energy; precise timing control and stable voltage supply ensure low-voltage stable operation of the circuit; in practical applications, micro-display devices can present video quality similar to high voltage at low voltage and have low power consumption potential. Verified by the implementation examples, this architecture is effective in reducing power consumption, improving read and write efficiency and stability, and provides an innovative solution for the storage circuit design of high-resolution and high-refresh-rate wearable devices.

[0099] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0100] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A static random access memory, characterized in that: include: Q memory arrays, row decoding circuits, row-by-row voltage control circuits, column data shift circuits, timing control circuits, readout selection circuits, data IO ports, and DC / DC circuits, wherein the memory arrays include M rows of memory cells, and Q and M are both greater than or equal to 2; The row decoding circuit is used to decode the input address signal to obtain a chip selection signal and a row selection signal; The row-by-row voltage control circuit is used to provide independent power control signals for the memory array and each row of memory cells, select the first memory array corresponding to the chip select signal and the target row memory cells corresponding to the row select signal for read and write operations, provide a first power control signal to the target row memory cells, and provide a second power control signal to the target row memory cells after the row select signal is deactivated; When the read / write operation is a write operation, the column data shift circuit is used to shift in data within at least one clock cycle, and under the control of the input column enable signal, write data to the target row storage unit through the write bit line; when the column data shift circuit writes data to the X-th row storage unit through the write bit line, the column data shift circuit is used to simultaneously preload data corresponding to the (X+1)-th row storage unit, where X is greater than or equal to 1 and less than or equal to M; When the read / write operation is a read operation, the read selection circuit is used to precharge the read bit line of the target row memory cell and then read data from the target row memory cell through the multi-level read bit line; The data IO ports are electrically connected to the column data shift circuit and the readout selection circuit respectively, for inputting and outputting data; The DC / DC circuit is electrically connected to the row-by-row voltage control circuit, and is used to provide the power control signal to the row-by-row voltage control circuit; The timing control circuit is electrically connected to the row decoding circuit, the row-by-row voltage control circuit, the column data shift circuit and the readout selection circuit respectively, and is used to perform timing control on each circuit.

2. The static random access memory according to claim 1, wherein: An input power supply terminal VDD of a row of the memory cells is electrically connected to a same output terminal of the row-by-row voltage control circuit; The row-by-row voltage control circuit provides a first power control signal of a high level to the input power supply terminal VDD of the storage cells in one row, and provides a second power control signal of a low level; The low level of the second power control signal has a value range of 0.3V-0.9V.

3. The static random access memory according to claim 1, wherein: The storage array is divided into a storage area in terms of spatial distribution, each storage area includes b rows and c columns of storage cells, where a, b, and c are all integers greater than 0; The row decoding circuit is used to generate a row selection signals, sequentially control the a storage areas to perform read and write operations, and control the b rows of storage units in the storage area to be opened sequentially for read and write operations.

4. The static random access memory according to claim 3, wherein: The readout selection circuit is used to perform a read operation on a column of a*b memory cells using two levels of readout bit lines; The two-stage readout bit line includes a global bit line and a sub-bit lines respectively provided corresponding to the a storage blocks, wherein the b rows of storage cells in the storage block share one sub-bit line, and the sub-bit lines are electrically connected to the global bit line via MOS switches; The readout selection circuit is used to independently provide a precharge signal for each of the sub-bit lines. When the target row storage unit performs a read operation, a valid precharge signal is provided to the sub-bit line corresponding to the target row storage unit to precharge the sub-bit line and the global bit line, while the other sub-bit lines are disconnected from the global bit line.

5. The static random access memory according to claim 1, wherein: The row-by-row voltage control circuit is used to delay the read and write operations of the target row storage unit after the second power control signal is switched to the first power control signal.

6. The static random access memory according to claim 1, wherein: The row decoding circuit includes a read-write decoder shared by read and write decoding, the row-by-row voltage control circuit includes a data selector, the read-write decoder is electrically connected to the data selector, and a write word line and a read word line are provided between the data selector and the memory array; The data selector is used to control the transmission path between the read-write decoder and the write word line to be conductive when performing a write operation; Alternatively, the data selector is used to control the transmission path between the read / write decoder and the read word line to be conductive during a read operation; The data selector is used to control the effective opening time of the write word line and the read word line by using a narrow pulse signal.

7. The static random access memory according to claim 1, wherein: The storage unit is an 8T read-write separation storage unit suitable for low-voltage operation; The 8T memory cell includes two PMOS transistors and six NMOS transistors; The two PMOS transistors and the two NMOS transistors in the storage unit form two cross-coupled bistable latch structures for latching written data.

8. The static random access memory according to claim 1, wherein: The column data shift circuit is a 1024-bit register, and the 1024-bit register is divided into eight 128-bit data shift blocks; The column data shift circuit is used to shift in data under the control of a data shift-in signal, wherein each time new data is shifted in, the previously shifted in data is shifted back 128 bits so as to completely shift in the data required for a row of storage cells within 8 clock cycles; The column data shift circuit is used to write data under the control of the column enable signal. Each time data is written, the data of a row of memory cells is written into the corresponding row of memory cells through the write bit lines.

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