Memory device, programming method and memory system

Abstract

The invention discloses a memory device, a programming method and a memory system. The memory device includes a memory cell array including a plurality of memory cells and word lines coupled to the plurality of memory cells; and the peripheral circuit is configured to apply a verification voltage to the word line to perform a first verification operation on a first data state in the plurality of data states and perform a second verification operation on a second data state in the plurality of data states when incremental step pulse programming is performed on the plurality of memory cells, the first data state is adjacent to the second data state, and the distance between first expected threshold voltage distribution corresponding to the first data state and second expected threshold voltage distribution corresponding to the second data state is greater than a preset threshold value; after the first data state is verified, applying a first programming pulse to the word line so as to continuously program the memory cell expected to be programmed to the second data state; the first programming pulse is the sum of the second programming pulse and the preset offset voltage; the second program pulse is a previous program pulse of the first program pulse.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and more particularly to a memory device, a programming method, and a memory system. Background Art

[0002] Memory devices are used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) memory has become a mainstream product in the memory market due to its high storage density, manageable production costs, suitable programming and erasing speeds, and retention characteristics.

[0003] However, as people's requirements for storage devices continue to increase, there is still much room for improvement in memory devices and systems. Summary of the Invention

[0004] According to one aspect of an embodiment of the present application, a memory device is provided, comprising: a memory cell array; the memory cell array comprising a plurality of memory cells and word lines coupled to the plurality of memory cells; each memory cell being configured to be one of a plurality of data states; and a peripheral circuit coupled to the memory cell array and configured to: apply a verification voltage to the word line when incremental step pulse programming is performed on the plurality of memory cells, perform a first verification operation on a first data state among the plurality of data states, and perform a second verification operation on a second data state among the plurality of data states, wherein the first data state is adjacent to the second data state and a distance between a first expected threshold voltage distribution corresponding to the first data state and a second expected threshold voltage distribution corresponding to the second data state is greater than a preset threshold; and, after the first data state is verified, apply a first programming pulse to the word line to continue programming the memory cell expected to be programmed to the second data state; the first programming pulse is the sum of a second programming pulse and a preset offset voltage; and the second programming pulse is the programming pulse preceding the first programming pulse.

[0005] In the above scheme, the peripheral circuit is further configured to: determine the verification result of the second verification operation after the first data state is verified; divide the memory cells expected to be programmed to the second data state among the multiple memory cells into multiple groups according to the verification result; and when continuing to program the memory cells expected to be programmed to the second data state among the multiple memory cells, apply different bit line voltages to the bit lines coupled to different groups of memory cells in the multiple groups of memory cells.

[0006] In the above scheme, the peripheral circuit is further configured to: divide the memory cells expected to be programmed to the second data state among the multiple memory cells into a first group and a second group according to the verification result, wherein the memory cells included in the first group are programmed to the second data state earlier than the memory cells included in the second group; and when continuing to program the memory cells expected to be programmed to the second data state among the multiple memory cells, apply a first bit line voltage to the bit line coupled to the memory cells included in the first group; and apply a second bit line voltage to the bit line coupled to the memory cells included in the second group, wherein the first bit line voltage is greater than the second bit line voltage.

[0007] In the above scheme, the peripheral circuit is further configured to: after the first programming pulse and when the second data state has not been verified, based on the first programming pulse and with a step increment voltage as a step length, gradually continue to apply gradually larger programming pulses to the word lines coupled to the multiple storage cells until the last data state among the multiple data states is verified; wherein the step increment voltage is less than the preset offset voltage.

[0008] In the above solution, the last data state among the multiple data states is the second data state.

[0009] In the above solution, the peripheral circuit is further configured to: program each of the plurality of memory cells from one of the plurality of data states to a corresponding target data state among the plurality of target data states.

[0010] In the above scheme, the multiple data states include: data state P0, data state P1, data state P2, and data state P3, in which the voltage values ​​included in the expected threshold voltage distribution increase in sequence; wherein, the first data state is data state P2; and the second data state is data state P3.

[0011] In the above solution, the plurality of target data states include 16 target data states; wherein each of the plurality of data states is configured as corresponding 4 target data states.

[0012] In the above scheme, the peripheral circuit is further configured to: record the number of programming pulses applied to the word line coupled to the multiple memory cells; and when the number of applied programming pulses is equal to a preset number, start applying a verification voltage to the word line to simultaneously perform verification operations on the first data state and the second data state among the multiple data states.

[0013] In the above solution, the preset offset voltage is positively correlated with the distance between the first expected threshold voltage distribution and the second expected threshold voltage distribution, wherein the larger the distance is, the larger the preset offset voltage is.

[0014] According to another aspect of an embodiment of the present application, a programming method for a memory device is provided, wherein the memory device includes a plurality of memory cells and word lines coupled to the plurality of memory cells; each memory cell is configured to be one of a plurality of data states; the programming method includes: when performing incremental step pulse programming on the plurality of memory cells, applying a verification voltage to the word line, performing a first verification operation on a first data state among the plurality of data states and performing a second verification operation on a second data state among the plurality of data states, wherein the first data state is adjacent to the second data state and a distance between a first expected threshold voltage distribution corresponding to the first data state and a second expected threshold voltage distribution corresponding to the second data state is greater than a preset threshold; after the first data state is verified, applying a first programming pulse to the word line to continue programming the memory cells among the plurality of memory cells that are expected to be programmed to the second data state; the first programming pulse is the sum of a second programming pulse and a preset offset voltage; and the second programming pulse is the programming pulse preceding the first programming pulse.

[0015] In the above scheme, the programming method also includes: after the first data state is verified, determining the verification result of the second verification operation; dividing the memory cells expected to be programmed to the second data state among the multiple memory cells into multiple groups according to the verification result; when continuing to program the memory cells expected to be programmed to the second data state among the multiple memory cells, applying different bit line voltages to the bit lines coupled to different groups of memory cells in the multiple groups of memory cells.

[0016] In the above scheme, the memory cells expected to be programmed to the second data state among the multiple memory cells are divided into multiple groups according to the verification result, including: dividing the memory cells expected to be programmed to the second data state among the multiple memory cells into a first group and a second group according to the verification result, wherein the memory cells included in the first group are programmed to the second data state earlier than the memory cells included in the second group; and applying different bit line voltages to the bit lines coupled to the memory cells in different groups of the multiple groups of memory cells when continuing to program the memory cells expected to be programmed to the second data state among the multiple memory cells, including: applying a first bit line voltage to the bit lines coupled to the memory cells included in the first group when continuing to program the memory cells expected to be programmed to the second data state among the multiple memory cells; applying a second bit line voltage to the bit lines coupled to the memory cells included in the second group, wherein the first bit line voltage is greater than the second bit line voltage.

[0017] In the above scheme, the programming method also includes: after the first programming pulse and when the second data state has not been verified, based on the first programming pulse and with a step increment voltage as a step length, gradually applying gradually larger programming pulses to the word lines coupled to the multiple storage cells until the last data state among the multiple data states is verified, wherein the step increment voltage is less than the preset offset voltage.

[0018] In the above solution, the last data state is the second data state.

[0019] In the above solution, the programming method further includes: programming each of the plurality of memory cells from one of the plurality of data states to a corresponding target data state among a plurality of target data states.

[0020] In the above scheme, the multiple data states include: data state P0, data state P1, data state P2, and data state P3, in which the voltage values ​​included in the expected threshold voltage distribution increase in sequence; wherein, the first data state is data state P2; and the second data state is data state P3.

[0021] In the above solution, the plurality of target data states include 16 target data states; wherein each of the plurality of data states is configured as corresponding 4 target data states.

[0022] In the above scheme, the programming method also includes: recording the number of programming pulses applied to the word line coupled to the multiple storage cells; when the number of applied programming pulses is equal to a preset number, starting to apply a verification voltage to the word line to simultaneously perform verification operations on the first data state and the second data state among the multiple data states.

[0023] According to another aspect of the embodiments of the present application, a memory system is provided, comprising: one or more memory devices as described in any one of the above; and a memory controller coupled to and controlling the memory devices.

[0024] Embodiments of the present application provide a memory device, programming method, and memory system. The memory device includes: a memory cell array; the memory cell array includes a plurality of memory cells and word lines coupled to the plurality of memory cells; each memory cell is configured to be in one of a plurality of data states; and a peripheral circuit coupled to the memory cell array and configured to: apply a verification voltage to the word line during incremental step pulse programming of the plurality of memory cells, perform a first verification operation on a first data state among the plurality of data states, and perform a second verification operation on a second data state among the plurality of data states, wherein the first data state is adjacent to the second data state and a distance between a first expected threshold voltage distribution corresponding to the first data state and a second expected threshold voltage distribution corresponding to the second data state is greater than a preset threshold; and, after the first data state is verified, apply a first programming pulse to the word line to continue programming the memory cell intended to be programmed to the second data state; the first programming pulse is the sum of a second programming pulse and a preset offset voltage; and the second programming pulse is the programming pulse preceding the first programming pulse. An embodiment of the present application provides a memory device. When the distance between the threshold voltage distributions corresponding to two adjacent data states is greater than a preset threshold, a larger programming pulse can be used to program the latter data state, thereby saving the number of programming pulses and achieving the effect of improving the programming time. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In the accompanying drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like numerals with different letter suffixes may represent different instances of similar components. The accompanying drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0026] Figure 1 A schematic structural diagram of a memory device including a memory cell array and peripheral circuits provided in an embodiment of the present application;

[0027] Figure 2 A cross-sectional schematic diagram of an exemplary memory array including NAND memory strings provided in an embodiment of the present application;

[0028] Figure 3 A schematic structural diagram of an exemplary memory device including a peripheral circuit provided in an embodiment of the present application;

[0029] Figure 4 A schematic diagram of the structure of the step pulse of the ISPP method provided in an embodiment of the present invention;

[0030] Figure 5 A schematic diagram of a verification voltage pulse provided in an embodiment of the present application;

[0031] 6A to 6D A schematic diagram of threshold voltage distributions of different types of memory cells provided in an embodiment of the present application;

[0032] Figure 7 A schematic diagram of a threshold voltage distribution for coarse programming and a threshold voltage distribution for fine programming corresponding to an encoding method provided in an embodiment of the present application;

[0033] Figure 8 A schematic diagram showing the effect of the programming method provided in accordance with an embodiment of the present application;

[0034] Figure 9 A schematic diagram of a coarse programming process in a 4-16 two-side programming of a QLC type memory cell provided in an embodiment of the present application;

[0035] Figure 10 Provided in the embodiments of this application Figure 9 Schematic diagram of the waveform of the programming pulse and bit line voltage applied during coarse programming;

[0036] Figure 11 A flowchart of a method for programming a memory device provided in an embodiment of the present application;

[0037] Figure 12 A schematic diagram of a memory system structure is provided for an embodiment of the present application;

[0038] Figure 13A A schematic diagram of an exemplary memory card having a memory system provided in an embodiment of the present application;

[0039] Figure 13B A schematic diagram of an exemplary solid-state drive (SSD) having a memory system according to an embodiment of the present application. DETAILED DESCRIPTION

[0040] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to facilitate a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0041] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, to avoid confusion with the present application, certain technical features well known in the art are not described: that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0042] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0043] It should be understood that when an element or layer is referred to as being "on, "adjacent to, "connected to," "coupled to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be an intermediate element or layer. In contrast, when an element is referred to as being "directly on, "directly adjacent to, "directly connected to," or "directly coupled to" another element or layer, there may be no intermediate element or layer. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of this application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. When discussing a second element, component, region, layer or section, it does not necessarily mean that the first element, component, region, layer or section must be present.

[0044] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0045] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0046] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below with reference to the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0047] like Figure 1 As shown, it shows a structural diagram of a memory device 100 provided in an embodiment of the present application. Figure 1 As shown, the memory device 100 may include: a memory cell array 101; the memory cell array 101 includes a plurality of memory cells and word lines coupled to the plurality of memory cells; each memory cell is configured to one of a plurality of data states; and a peripheral circuit 102, coupled to the memory cell array 101 and configured to: apply a verification voltage to the word line when performing incremental step pulse programming on the plurality of memory cells, perform a first verification operation on a first data state among the plurality of data states, and perform a second verification operation on a second data state among the plurality of data states, wherein the first data state is adjacent to the second data state and a distance between a first expected threshold voltage distribution corresponding to the first data state and a second expected threshold voltage distribution corresponding to the second data state is greater than a preset threshold; and, after the first data state is verified, apply a first programming pulse to the word line to continue programming the memory cell expected to be programmed to the second data state; the first programming pulse is the sum of a second programming pulse and a preset offset voltage; and the second programming pulse is the programming pulse previous to the first programming pulse.

[0048] It should be noted that the memory device 100 may refer to a device for storing programs and / or data, which includes a memory cell array 101 and a peripheral circuit 102. The memory cell array 101 may be used as a storage medium for storing programs and / or data, while the peripheral circuit 102 is a general term for various circuits that control the memory cell array 101 and store programs and / or data in the memory cell array 101.

[0049] Among them, Figure 1As shown, an example of a memory cell array 101 may be a NAND flash memory array. Figure 1 As shown, the memory cells 1106 of the memory cell array 101 are provided in the form of an array of NAND memory strings 1108, each NAND memory string 1108 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 1108 includes a plurality of memory cells 1106 coupled in series and stacked vertically. Each memory cell 1106 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the storage region of the memory cell 1106. Each memory cell 1106 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0050] In some embodiments, each memory cell 1106 may be a single-level cell (SLC) having two possible data states and thus storing one bit of data. For example, the first data state "0" may correspond to a first voltage range, and the second data state "1" may correspond to a second voltage range. In some embodiments, the first voltage range and the second voltage range may be referred to as a threshold voltage distribution of the memory cell. In some embodiments, each memory cell 1106 may be a multi-level cell (MLC). For example, an MLC may store two bits per memory cell (also referred to as a double-level cell (DLC)); for another example, an MLC may store three bits per memory cell (also referred to as a tri-level cell (TLC); or for another example, a quad-level cell (QLC) may store four bits per memory cell (also referred to as a quad-level cell (QLC). Regardless of the type of memory cell, the multiple data states include an erased state and one or more programmed states. When a programming operation is performed on the memory cell, the memory cell in the erased state is programmed to a certain programmed state. Generally speaking, the voltage value in the voltage range corresponding to the programmed state of the memory cell is relatively large.

[0051] like Figure 1As shown, each NAND memory string 1108 can include a source select gate (SSG) 1110 at its source terminal and a drain select gate (DSG) 1112 at its drain terminal. The SSG 1110 and DSG 1112 can be configured to activate a selected NAND memory string 1108 (column of the array) during read and program (or write) operations. In some embodiments, the sources of the NAND memory strings 1108 in the same memory block 1104 are coupled via the same source line (SL) 1114 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 1108 in the same memory block 1104 have an array common source (ACS). According to some embodiments, the DSG 1112 of each NAND memory string 1108 is coupled to a corresponding bit line 1116, from which data can be read and written via an output bus (not shown). In some embodiments, each NAND memory string 1108 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having DSG 1112) or a deselect voltage (e.g., 0 volts (V)) to the corresponding DSG 1112 via one or more drain select lines (Drain Selective Line) or top select lines (Top Selective Line) 1113 and / or applying a select voltage (e.g., higher than the threshold voltage of the transistor having SSG 1110) or a deselect voltage (e.g., 0 V) ​​to the corresponding SSG 1110 via one or more source select lines (Source Selective Line) or bottom select lines (Bottom Selective Line) 1115.

[0052] like Figure 1 As shown, the NAND memory string 1108 can be organized into a plurality of memory blocks 1104, each of which can have a common source line 1114 (e.g., coupled to ground). In some embodiments, each memory block 1104 is a basic data unit with an erase operation, that is, all memory cells 1106 on the same memory block 1104 are erased at the same time. In order to erase the memory cells 1106 in the selected memory block 1104, the source lines 1114 coupled to the selected memory block 1104 and the unselected memory blocks 1104 in the same plane (Plane) as the selected memory block 1104 can be biased with an erase voltage (Vers) (e.g., a high positive voltage of 20V or higher). It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of blocks or any suitable fraction of blocks. As shown in FIG. Figure 4As shown, the memory cells 1106 of adjacent NAND memory strings 1108 can be coupled via word lines 1118 , that is, the same word line 1118 can be coupled to memory cells at the same position in multiple memory strings (ie, corresponding memory cells).

[0053] Figure 2 1 shows a side view of a cross section of an exemplary memory cell array 101 including NAND memory strings 1108 according to some aspects of the present application. Figure 2 As shown in FIG, a NAND memory string 1108 may include a stacked structure 210, which includes a plurality of gate layers 211 and a plurality of insulating layers 212 alternately stacked in sequence, and a memory string 1108 vertically penetrating the gate layers 211 and the insulating layers 212. The gate layers 211 and the insulating layers 212 may be alternately stacked, with two adjacent gate layers 211 separated by a layer of insulating layer 212. The number of pairs of gate layers 211 and insulating layers 212 in the stacked structure 210 may determine the number of memory cells included in the memory cell array 101.

[0054] The gate layer 211 may be formed of a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 211 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 211 includes a doped polysilicon layer. Each gate layer 211 may include a control gate surrounding a memory cell. The gate layer 211 at the top of the stacked structure 210 can extend laterally to serve as an upper select gate line 213, also known as a TSG line 1113. The upper select gate line 213 is also the lead line of the upper select gate (TSG) 1112 described above, which can be connected to a corresponding select voltage or cancel voltage. The gate layer 211 at the bottom of the stacked structure 210 can extend laterally to serve as a lower select gate line 214, also known as a source select line (source selective line) or a bottom select line (bottom selective line) 1115. The lower select gate line 214 is also the lead line of the lower select gate (BSG) 1110 described above, which can be connected to a corresponding select voltage or cancel voltage. The gate layer 211 extending laterally between the upper select gate line and the lower select gate line can serve as a word line layer 203. These word line layers 203 are also the word lines 1118 described above.

[0055] In some embodiments, the stacked structure 210 may be disposed on a substrate 201. The substrate 201 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0056] In some embodiments, NAND memory string 1108 includes a channel structure extending vertically through stacked structure 210. In some embodiments, the channel structure includes a channel hole filled with one or more semiconductor materials (e.g., serving as a semiconductor channel) and one or more dielectric materials (e.g., serving as a memory film). In some embodiments, the semiconductor channel includes silicon, such as polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). In some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0057] Return Reference Figure 1 , the peripheral circuit 102 may be coupled to the memory cell array 101 via the bit lines 1116, the word lines 1118, the source lines 1114, the SSG lines 1115, and the DSG lines 1113. The peripheral circuit 102 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 101 by applying a voltage signal and / or a current signal to each target memory cell 1106 and sensing a voltage signal and / or a current signal from each target memory cell 1106 via the bit lines 1116, the word lines 1118, the source lines 1114, the SSG lines 1115, and the DSG lines 1113. The peripheral circuit 102 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 3 Some exemplary peripheral circuits are shown, and the peripheral circuit 102 includes a page buffer / sense amplifier 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, a control logic 312, a register 314, an interface 316, and a data bus 318. It should be understood that in some examples, the peripheral circuit 102 may also include Figure 3 Additional circuitry not shown.

[0058] Specifically, the page buffer / sense amplifier 304 can be configured to read data from the memory cell array 101 and program (write) data to the memory cell array 101 based on control signals from the control logic 312. In one example, the page buffer / sense amplifier 304 can store program data (or write data) to be programmed into the memory cells coupled to a word line in the memory cell array 101. In another example, the page buffer / sense amplifier 304 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 1106 coupled to the selected word line 1118. In yet another example, the page buffer / sense amplifier 304 can also sense a low-power signal from the bit line 1116 representing the data bit stored in the memory cell 1106 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 306 can be configured to be controlled by the control logic 312 and select one or more NAND memory strings 408 by applying a bit line voltage generated by the voltage generator 310.

[0059] The row decoder / word line driver 308 can be configured to be controlled by control logic 312 and to select / deselect memory blocks 404 of the memory cell array 101 and to select / deselect word lines 1118 of the memory blocks 404. The row decoder / word line driver 308 can also be configured to drive the word lines 1118 using word line voltages generated from the voltage generator 310. In some embodiments, the row decoder / word line driver 308 can also select / deselect and drive the SSG lines 1115 and the DSG lines 1113. As described in detail below, the row decoder / word line driver 308 is configured to perform an erase operation on the memory cells 1106 coupled to the selected word line(s) 1118. The voltage generator 310 can be configured to be controlled by control logic 312 and to generate word line voltages (e.g., read voltages, programming pulses, pass voltages, local voltages, verification voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 101.

[0060] Among them, the control logic 312 can be coupled to each circuit described above and is configured to control the operation of each peripheral circuit. The register 314 can be coupled to the control logic 312 and includes a status register, a command register, and an address register for storing status information, command operation code (OP code), and command address for controlling the operation of each peripheral circuit. The interface 316 can be coupled to the control logic 312 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 312, as well as buffer status information received from the control logic 312 and relay it to the host. The interface 316 can also be coupled to the column decoder / bit line driver 306 via the data bus 318 and act as a data I / O interface and data buffer to buffer data and relay it to the memory cell array 101 or relay or buffer data from the memory cell array 101.

[0061] Return Reference Figure 1 , the peripheral circuit 102 is coupled to the memory cell array 101 via a word line, and the corresponding operation is achieved by applying a corresponding operating voltage to the word line. The word line here is any one of the word lines 1118 described above. The multiple memory cells mentioned can be all or part of the memory cells coupled to the word line. The multiple memory cells can also be referred to as a memory page (or page), which is a unit of programming or reading. Based on this, the operation provided by the embodiment of the present application can be: when the multiple memory cells are subjected to incremental step pulse programming (ISPP), after a certain programming pulse, a verification voltage is applied to the word line, and verification is simultaneously started for the first data state and the second data state whose threshold voltage distribution is adjacent and the distance between them is greater than a preset threshold. After the first data state is verified, the first programming pulse is continued to be applied to the word line to continue programming the memory cell expected to be programmed to the second data state. The first programming pulse can be the sum of the previous programming pulse (i.e., the second programming pulse) and a preset offset voltage. The preset offset voltage is greater than the step increment voltage of the ISPP. That is, when the threshold voltages (Vt) corresponding to multiple data states are unevenly distributed, when programming to two data states with a large interval, after the previous data state is programmed, a higher programming pulse can be used when programming the next data state, which can save the number of applied programming pulses (pulse count) and thus achieve the effect of improving the programming time.

[0062] Here, the so-called ISPP can be based on the step voltage to gradually increase the word line bias voltage while programming multiple memory cells several times, so that the multiple memory cells are programmed to the corresponding data states in the multiple data states. pgmFor reference Figure 4 That is, the programming pulse applied to the word line coupled to the programmed memory cell is gradually increased in a certain increment until the programmed memory cell is programmed to the target data state. It should be noted that applying a programming pulse once can be called a programming loop (PGM Loop).

[0063] It should be understood that during the programming of the memory cell, in order to understand whether the programmed memory cell is programmed to the target data state, a verification operation (verify) is added between the application of two programming pulses to determine whether the programmed memory cell is programmed to the target data state. The two programming pulses applied may be adjacent programming pulses or not. In other words, the programming operation and the verification operation may be performed alternately, or the verification operation may be performed after applying multiple programming pulses according to actual conditions. The verification operation may be one or a group of verification voltage pulses, such as Figure 5 As shown, Figure 5 501 and 503 are step programming pulses V pgm ; 502 is a verification voltage pulse.

[0064] Based on this, the first verification operation and the second verification operation here are verification of the first data state and verification of the second data state respectively, that is, the first verification operation is to verify whether the corresponding memory cell is programmed to the first data state; the second verification operation is to verify whether the corresponding memory cell is programmed to the second data state. The verification voltage is such as Figure 5 A certain verification voltage pulse is shown.

[0065] In practice, for a memory page, the memory cells it contains are configured to store one, two, three, four bits of data, etc. as described above. Then, depending on the number of bits of data that the memory cell is configured to store, when a memory page is successfully programmed, the number of data states it contains is different. Specifically, a memory cell that stores one bit of data (also referred to as SLC as mentioned above) corresponds to two data states: an erased state and a programmed state, and its threshold voltage distribution is as follows: Figure 6A As shown. A memory cell storing two bits of data (also referred to as DLC as mentioned above) has four corresponding data states: one erased state and three programmed states, and its threshold voltage distribution is as follows Figure 6B As shown. A memory cell storing three bits of data (also referred to as TLC as mentioned above) has eight corresponding data states: one erased state and seven programmed states, and its threshold voltage distribution is as follows Figure 6C As shown. A memory cell storing four bits of data (also referred to as QLC as mentioned above) has 16 corresponding data states: one erased state and fifteen programmed states, and its threshold voltage distribution is as follows Figure 6Dshown.

[0066] That is, if Figure 6A As shown, in an SLC, there are two corresponding threshold voltage distributions: E and P1. Threshold voltage distribution E corresponds to the erased data state, while threshold voltage distribution P1 corresponds to the data state. The threshold voltage of threshold voltage distribution E corresponding to the erased data state is lower than the threshold voltage of threshold voltage distribution P1 in the data state. Therefore, memory cells with threshold voltages in threshold voltage distribution E are in the erased data state, while memory cells with threshold voltages in threshold voltage distribution P1 are in the data state. In some embodiments, memory cells in the erased data state store data 1, while memory cells in the data state store data 0.

[0067] like Figure 6B As shown, in DLC, there are four corresponding threshold voltage distributions: E, P1, P2, and P3, with threshold voltages increasing in sequence. Similarly, threshold voltage distribution E corresponds to the erased data state; threshold voltage distributions P1, P2, and P3 correspond to the data states. In some embodiments, erased memory cells store data 11, memory cells programmed to the P1 data state store data 10, memory cells programmed to the P2 data state store data 10, and memory cells programmed to the P3 data state store data 00.

[0068] like Figure 6C As shown, in TLC, it corresponds to eight threshold voltage distributions: E, P1, P2, P3, P4, P5, P6, and P7, with the threshold voltage increasing in sequence. Similarly, threshold voltage distribution E corresponds to the erased data state; threshold voltage distributions P1, P2, P3, P4, P5, P6, and P7 correspond to the data state. In some embodiments, the erased memory cell can store data 111, the memory cell programmed to the P1 data state stores data 110, the memory cell programmed to the P2 data state stores data 101, the memory cell programmed to the P3 data state stores data 100, the memory cell programmed to the P4 data state stores data 011, the memory cell programmed to the P5 data state stores data 010, the memory cell programmed to the P6 data state stores data 001, and the memory cell programmed to the P7 data state stores data 000.

[0069] like Figure 6DAs shown, in QLC, it corresponds to 16 threshold voltage distributions: E, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, and P15, with the threshold voltage increasing in sequence. Similarly, threshold voltage distribution E corresponds to the erased data state; threshold voltage distributions P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, and P15 correspond to the data states. For data state PN, the data state PN has a higher threshold voltage than data state PN-1 and a lower threshold voltage than data state PN+1, where N is greater than or equal to 2. The voltage value in the threshold voltage distribution corresponding to data state P1 is higher than the voltage value in the threshold voltage distribution corresponding to data state E. In some embodiments, an erased memory cell may store data 1111, and memory cells programmed to data states L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, and L15 may sequentially store data 1110, 1101, 1100, 1011, 1010, 1001, 1000, 0111, 0110, 0101, 0100, 0011, 0010, 0001, and 0000. It should be noted that, regardless of the aforementioned type of memory cell, each threshold voltage distribution (data state) corresponds to a predetermined value of a set of data bits stored in the memory cell, and the specific relationship between the data programmed into the memory cell and the threshold voltage level of the memory cell depends on the data encoding scheme adopted by the memory cell, for example, an encoding scheme using a Gray code.

[0070] According to the above description, the multiple data states mentioned here can refer to the data states corresponding to the storage cells in a storage page when they are arranged as types such as DLC, TLC, and QLC, and the multiple data states can refer to multiple intermediate data states or multiple target data states in the programming process. In practical applications, for flash memory devices with multiple data states, such as NAND flash memory devices, in order to reduce coupling and interference between word lines when programming storage cells, in some embodiments, multiple programming can be used when programming storage pages or blocks to achieve a tighter threshold voltage distribution, such as the two-step programming method of QLC, and it can include 16-16, 10-16, 8-16, 6-16 and 4-16, etc. Among them, in this application, the intermediate data states can refer to the successful programming results of non-last programming in multi-pass programming, such as the 4-16 two-side programming described above, the 4 data states configured to be included are intermediate data states, wherein non-last programming can also be referred to as coarse programming. The target data state may refer to the successful result of the last programming pass in multiple programming passes. For example, in the two-side programming of 4-16 described above, the 16 data states configured to be included are the target data states. The last programming pass is called fine programming.

[0071] Here, the so-called adjacent first data state and second data state may refer to two data states with adjacent threshold voltage distributions when programming a memory page in sequence from a data state with a low threshold voltage distribution to a data state with a high threshold voltage distribution. For example, Figure 6B The data states P1 and P2 shown are two adjacent data states; for example, Figure 6B The data state P2 and the data state P3 shown are also two adjacent data states.

[0072] It should be understood that the "first" in the first data state and the "second" in the second data state are only used to distinguish two different data states and are not used for limitation. In other words, the first data state and the second data state can refer to Figure 6B 、 6C , any two adjacent data states in 6D. The so-called first expected threshold voltage distribution may refer to the threshold voltage distribution corresponding to the first data state, such as Figure 6B As shown, the threshold voltage distribution corresponding to the data state P1. The so-called second expected threshold voltage distribution may refer to the threshold voltage distribution corresponding to the second data state, that is, the range of threshold voltages to which the corresponding memory cells are expected to be programmed, such as Figure 6B As shown, the threshold voltage distribution corresponding to the data state P2.

[0073] Figures 6B to 6D The threshold voltage distribution in the figure is the threshold voltage distribution corresponding to each data state under a relatively ideal state. In practice, for each programming method, for different Gray codes, the threshold voltage Vt of the memory cell during coarse programming and the threshold voltage Vt of the memory cell during fine programming have different corresponding relationships. Among them, in the multi-pass programming process customized according to the set Gray code, the distance between the threshold voltage distributions corresponding to some adjacent intermediate data states in the coarse programming is relatively large, such as Figure 7 As shown, in the programming on both sides of the QLC type memory cell, the distance between the threshold voltages corresponding to the data state P2 and the data state P3 of the memory cell in the coarse programming is relatively large. At this time, if the corresponding memory cell is programmed according to the normal ISPP step increment voltage, the number of pulses to be applied is relatively large, and the programming time is relatively long. Therefore, in the embodiment of the present application, during the programming process, after the data state P2 is verified, a larger offset voltage is added on the basis of the previous programming pulse, and a higher programming pulse is used for the next programming to save the pulse count, thereby achieving the effect of improving the programming time. The specific programming effect is as follows. Figure 8 As shown. Among them, dotted line 1 indicates that the first data state (such as data state P2) is successfully verified, and the threshold voltage distribution corresponding to the second data state (such as data state P3); dotted line 2 indicates the threshold voltage distribution of data state P3 after a higher programming pulse is used for the next programming. PV1, PV2, and PV3 are the verification voltages of data state P1, data state P2, and data state P3 respectively. The arrow indicates the next normal ISPP programming after a higher programming pulse is used for the next programming. Vth represents the threshold voltage. From Figure 8 As can be seen, after a higher programming pulse, the maximum value of the threshold voltage distribution corresponding to data state P3 is close to the verify voltage of data state P3. Then, by applying a normal ISPP programming pulse (with an increased increment voltage), the memory cell is programmed to data state P3, thus speeding up programming. The increment voltage here can be the same as or different from the increment voltage before the higher programming pulse.

[0074] Here, the distance between the first expected threshold voltage distribution corresponding to the first data state and the second expected threshold voltage distribution corresponding to the second data state may refer to the voltage difference between the maximum voltage value of the first expected threshold voltage distribution and the minimum voltage value of the second expected threshold voltage distribution, for example Figure 7The voltage difference between the maximum voltage value of the threshold voltage distribution corresponding to data state P2 and the minimum voltage value of the threshold voltage distribution corresponding to data state P3 in the coarse programming of the memory cell shown is the distance between the threshold voltage distribution corresponding to data state P2 and the threshold voltage distribution corresponding to data state P3. That is, when the voltage difference is greater than the preset threshold, the first programming pulse is the sum of the second programming pulse and the preset offset voltage. Here, the preset threshold can be determined based on actual conditions. In an optional solution, the preset threshold can be 1 volt (V). That is, when the voltage difference described above is greater than 1V, a preset offset voltage is required to obtain a larger programming pulse.

[0075] In some embodiments, the preset offset voltage is positively correlated with a distance between the first expected threshold voltage distribution and the second expected threshold voltage distribution, wherein the larger the distance, the larger the preset offset voltage.

[0076] In some embodiments, the peripheral circuit can also be configured to: determine the verification result of the second verification operation after the first data state is verified; divide the memory cells expected to be programmed to the second data state among the multiple memory cells into multiple groups according to the verification result; and when continuing to program the memory cells expected to be programmed to the second data state among the multiple memory cells, apply different bit line voltages to the bit lines coupled to different groups of memory cells in the multiple groups of memory cells.

[0077] It should be noted that, during the programming process, the greater the bit line voltage applied to the bit line connected to the memory string to which the memory cell is coupled, the programming speed of the memory cell is suppressed. Due to manufacturing or other reasons, the programming speeds of the memory cells are different. Therefore, the memory cells expected to be programmed to the second data state are no exception, which includes memory cells with a faster programming speed, which can be programmed to the second data state faster; it also includes memory cells with a slower programming speed, which can be programmed to the second data state slower. Therefore, corresponding to memory cells with different programming speeds, when programming, a larger bit line voltage is applied to the memory cells with a faster programming speed to suppress their programming speed and prevent over-programming. A smaller bit line voltage is applied to the memory cells with a slower programming speed to ensure their programming speed. That is, after the first data state is successfully verified, the memory cells expected to be programmed to the second data state will also be programmed, and their threshold voltage distributions such as Figure 8 As shown by the dotted line 1. Figure 8It can be seen that after the first data state is successfully verified, the difference between the threshold voltage corresponding to each memory cell expected to be programmed to the second data state and the second expected threshold voltage distribution corresponding to the second data state is different. Therefore, for memory cells with different threshold voltages, or for memory cells with different programming speeds, different bit line voltages need to be applied to their bit lines during the subsequent programming process. Specifically, based on the verification results of the second verification operation, the memory cells expected to be programmed to the second data state are divided into multiple groups, and different bit line voltages are applied to the memory cells in different groups in the subsequent programming loop.

[0078] In some embodiments, the peripheral circuit is further configured to: divide the memory cells expected to be programmed to the second data state among the multiple memory cells into a first group and a second group according to the verification result, wherein the memory cells included in the first group are programmed to the second data state earlier than the memory cells included in the second group; and when continuing to program the memory cells expected to be programmed to the second data state among the multiple memory cells, apply a first bit line voltage to the bit line coupled to the memory cells included in the first group; and apply a second bit line voltage to the bit line coupled to the memory cells included in the second group, wherein the first bit line voltage is greater than the second bit line voltage.

[0079] It should be noted that after the first data state is verified, since the second data state is verified simultaneously with the first data state, a second verification operation performed on the second data state generates a verification result. Based on the verification result of the second verification operation, the memory cells expected to be programmed to the second data state are divided into a first group and a second group, with the memory cells in the first group being programmed to the second data state before the memory cells in the second group. At this point, when programming continues, the bit lines coupled to the memory cells in the first group are applied with a first bit line voltage, while the bit lines coupled to the memory cells in the second group are applied with a second bit line voltage, where the first bit line voltage is greater than the second bit line voltage.

[0080] Here, the memory cells expected to be programmed to the second data state are divided based on the verification results of the second verification operation after the first data state has been verified. An optional division method can be as follows: a threshold can be set. The difference between the threshold voltage of dotted line 1 and the minimum value of the second expected threshold voltage is determined, and the difference is compared with the threshold; the memory cells corresponding to the difference less than the threshold are divided into the first group; the memory cells corresponding to the difference greater than the threshold are divided into the second group. Other division methods are also possible. In short, the programming speeds of memory cells in different groups are different, and different bit line voltages are applied during programming.

[0081] In some embodiments, the peripheral circuit is further configured to: after the first programming pulse and when the second data state has not been verified, based on the first programming pulse and with a step increment voltage as a step length, gradually continue to apply gradually larger programming pulses to the word lines coupled to the multiple storage cells until the last data state among the multiple data states is verified; wherein the step increment voltage is less than the preset offset voltage.

[0082] It should be noted that, after the first programming pulse, if the second data state has not been verified, programming needs to be continued. In subsequent programming, the programming pulse can be gradually increased based on the first programming pulse with a step-by-step increment voltage as the step size until the last data state of the multiple data states is verified. In other words, after the first programming pulse, if programming needs to be continued, the programming pulse is gradually increased in accordance with the ISPP method to achieve continued programming until the last data state is verified.

[0083] In some embodiments, the last data state among the plurality of data states is the second data state. That is, the second data state may be the last data state among the plurality of data states, that is, programming is sufficient so that the second data state passes verification.

[0084] If the plurality of data states are a plurality of intermediate data states in coarse programming, in some embodiments, the peripheral circuit is further configured to: program each of the plurality of memory cells from one of the plurality of data states to a corresponding target data state in a plurality of target data states.

[0085] That is, the aforementioned multiple data states may be intermediate data states. In this case, one of the intermediate data states needs to be programmed into a corresponding target data state among the multiple target data states.

[0086] For example, Figure 7 As shown, in some embodiments, the multiple data states include: data state P0, data state P1, data state P2, and data state P3, in which the voltage values ​​included in the expected threshold voltage distribution increase in sequence; wherein, the first data state is data state P2; and the second data state is data state P3.

[0087] In some embodiments, the plurality of target data states includes 16 target data states; wherein each of the plurality of data states is configured as corresponding 4 target data states.

[0088] That is, the plurality of data states include: data state P0, data state P1, data state P2, and data state P3, whose voltage values ​​are sequentially increased in the expected threshold voltage distribution, and when the target data states include 16, when programming is finally completed, each of the plurality of data states needs to be configured as the corresponding 4 target data states. For example, Figure 7 As shown, the coarsely programmed P0 corresponds to the finely programmed E, P1, P7, and P8, a total of four target data states; the coarsely programmed P1 corresponds to the finely programmed P2, P3, P6, and P9, a total of four target data states; the coarsely programmed P2 corresponds to the finely programmed P4, P5, P10, and P11, a total of four target data states; the coarsely programmed P3 corresponds to the finely programmed P12, P13, P14, and P15, a total of four target data states.

[0089] In some embodiments, the peripheral circuit can also be configured to: record the number of programming pulses applied to the word line coupled to the multiple memory cells; and when the number of applied programming pulses is equal to a preset number, start applying a verification voltage to the word line to simultaneously perform verification operations on the first data state and the second data state among the multiple data states.

[0090] It should be noted that the preset number of times may be related to the step increment voltage. Different step increment voltages result in different preset numbers. The larger the step increment voltage, the fewer the preset numbers. In other words, depending on the actual situation, the number of programming pulses applied before the verification operation is performed simultaneously on the first data state and the second data state may be different.

[0091] An embodiment of the present application provides a memory device. During its programming process, when there is an uneven distribution of threshold voltage Vt in coarse programming or fine programming according to an encoding method, for example, the distance between the threshold voltage distributions of data state P2 and data state P3 is greater than a preset threshold. At this time, after a specific programming pulse, programming verification is started for data state P2 and data state P3 at the same time. After the data state P2 is verified, a larger programming pulse is used to continue programming the storage cell expected to be programmed to the second data state, thereby reducing programming loops.

[0092] In order to understand this application, Figure 7 The uneven distribution of threshold voltage in coarse programming in the two-side programming of the 4-16 QLC is used as an example to illustrate. Figure 9 and Figure 10 ,in, Figure 9 Describes the schematic flow chart of rough programming; Figure 10 Shown Figure 7 The programming pulse and bit line voltage application waveforms of coarse programming are shown.

[0093] See also Figure 9The coarse programming process may include: applying a programming pulse to the corresponding word line to perform a programming operation; verifying data state P1; after data state P1 is successfully verified, continuing to apply programming pulses to the word line by increasing the voltage by a set step size to continue programming; when the number of applied programming pulses reaches k (preset number), simultaneously verifying data state P2 and data state P3; when data state P2 is not successfully verified, continuing to apply programming pulses to the word line by increasing the voltage by a set step size to continue programming; when data state P2 is successfully verified, adding a larger preset offset voltage to the previous programming pulse to obtain a larger programming pulse (first programming pulse), applying the larger programming pulse to the word line, and simultaneously applying different bit line voltages to the bit lines coupled to the memory cells in the first group of programming speed blocks and the second group of slow programming speed blocks into which the memory cells intended to be programmed to data state P3 are divided according to the verification result of data state P3 when data state P2 is successfully verified, so as to perform a precise programming operation. Wherein, V is applied to the bit lines of the memory cells in the first group high ; Apply V to the bit line of the second group of memory cells low , V high Greater than V low Afterwards, if the data state P3 is still not successfully verified, the first programming pulse is continued as the basis and the step increment voltage is used as the step length, and gradually larger programming pulses are applied to the word lines coupled to the multiple memory cells until the last data state is verified, thereby ending the coarse programming.

[0094] in, Figure 9The coarse programming process shown can be summarized as follows: The P1 / P2 data states (hereinafter referred to as P1 state and P2 state) are initially programmed using ISPP, and verification is simultaneously initiated for the P2 / P3 data states (hereinafter referred to as P3 state) in a specific programming loop (pgm loop). The P3 state uses the same verification voltage as the P2 state. Based on the verification results, the memory cells intended to be programmed to the P3 state are divided into a programming block of memory cells (fast cells), i.e., the first group, and a programming block of memory cells (slow cells), i.e., the second group. After the P2 state is verified (verify pass), based on the verification information obtained from verifying the P3 state, when continuing programming, a high voltage (Vhigh) is applied to the corresponding bit line (BL) of the fast cell; a slightly lower voltage (Vslow) is applied to the corresponding BL of the slow cell. Vslow can be 0V or a negative value, with Vhigh being greater than Vslow. This suppresses rapid programming of the fast cells and prevents over-programming. Furthermore, for the word line, an additional offset voltage (Vpgm offset) (dVpgm, also known as the preset offset voltage) is added based on the programming voltage of the previous pulse, and the next programming pulse is applied. At this point, the P3 state + 3sigma is close to the verification voltage of the P3 state. If further programming is required, ISPP programming is resumed: Based on the previous programming voltage, ISPP programming is continued. The ISPP step increment voltage (Pulse width) can remain unchanged or be appropriately increased or decreased. Programming continues until the last state is verified.

[0095] in, Figure 9 The waveforms of the programming pulses and bit line voltage applied during the coarse programming are shown in FIG. Figure 10 See Figure 10 At the beginning of programming, Vpgm_init is applied to the word line, and then it is increased in sequence according to the ISPP method, for example, Vpgm_init+ISPP*n; and when the data state P2 is successfully verified, a preset offset voltage (dVpgm) is added to the programming pulse, for example, Vpgm_init+ISPP*n+dVpgm. After that, programming is performed in sequence according to the ISPP method, for example, Vpgm_init+ISPP*n+dVpgm+ISPP*1. And when programming is performed using Vpgm_init+ISPP*n+dVpgm, the bit line voltages on the bit lines of the memory cells in different groups expected to be programmed to P3 are different, for example, the one with fast programming speed uses V high; Use V for slow programming speed low .

[0096] The same inventive concept as above, such as Figure 11 As shown, the present embodiment also provides a method for programming a memory device. The memory device includes a plurality of memory cells and word lines coupled to the plurality of memory cells; each memory cell is configured to one of a plurality of data states; the programming method may include:

[0097] 1101: applying a verification voltage to the word line when performing incremental step pulse programming on the plurality of memory cells, performing a first verification operation on a first data state among the plurality of data states and performing a second verification operation on a second data state among the plurality of data states, wherein the first data state is adjacent to the second data state and a distance between a first expected threshold voltage distribution corresponding to the first data state and a second expected threshold voltage distribution corresponding to the second data state is greater than a preset threshold;

[0098] 1102: After the first data state is verified, a first programming pulse is applied to the word line to continue programming the memory cells among the multiple memory cells that are expected to be programmed to the second data state; the first programming pulse is the sum of the second programming pulse and a preset offset voltage; the second programming pulse is the previous programming pulse of the first programming pulse.

[0099] In some embodiments, the programming method may further include: determining a verification result of the second verification operation after the first data state is verified; dividing the memory cells expected to be programmed to the second data state among the multiple memory cells into multiple groups based on the verification result; and applying different bit line voltages to the bit lines coupled to different groups of memory cells among the multiple groups of memory cells when continuing to program the memory cells expected to be programmed to the second data state among the multiple memory cells.

[0100] In some embodiments, dividing the memory cells expected to be programmed to the second data state among the multiple memory cells into multiple groups based on the verification result includes: dividing the memory cells expected to be programmed to the second data state among the multiple memory cells into a first group and a second group based on the verification result, wherein the memory cells included in the first group are programmed to the second data state earlier than the memory cells included in the second group; and applying different bit line voltages to bit lines coupled to memory cells in different groups of the multiple groups of memory cells when continuing to program the memory cells expected to be programmed to the second data state among the multiple memory cells, including: applying a first bit line voltage to the bit lines coupled to the memory cells included in the first group when continuing to program the memory cells expected to be programmed to the second data state among the multiple memory cells; applying a second bit line voltage to the bit lines coupled to the memory cells included in the second group, wherein the first bit line voltage is greater than the second bit line voltage.

[0101] In some embodiments, the programming method further includes: after the first programming pulse and when the second data state has not been verified, based on the first programming pulse and with a step increment voltage as a step length, gradually applying gradually larger programming pulses to the word lines coupled to the multiple memory cells until the last data state among the multiple data states is verified, wherein the step increment voltage is less than the preset offset voltage.

[0102] In some embodiments, the last data state is the second data state.

[0103] In some embodiments, the programming method further includes programming each of the plurality of memory cells from one of the plurality of data states to a corresponding target data state of a plurality of target data states.

[0104] In some embodiments, the multiple data states include: data state P0, data state P1, data state P2, and data state P3, in which the voltage values ​​included in the expected threshold voltage distribution increase in sequence; wherein the first data state is data state P2; and the second data state is data state P3.

[0105] In some embodiments, the plurality of target data states includes 16 target data states; wherein each of the plurality of data states is configured as corresponding 4 target data states.

[0106] In some embodiments, the programming method further includes: recording the number of programming pulses applied to the word line coupled to the multiple memory cells; when the number of applied programming pulses is equal to a preset number, starting to apply a verification voltage to the word line to simultaneously perform verification operations on the first data state and the second data state among the multiple data states.

[0107] It should be noted that this method and the aforementioned memory device belong to the same inventive concept. The terms appearing in this method have been explained in detail in the aforementioned memory device and are also applicable here and will not be repeated one by one.

[0108] Based on the same inventive concept as above, Figure 12 As shown, an embodiment of the present application further provides a memory system 120. The memory system 120 includes: one or more memory devices 1201 as described above; and a memory controller 1202 coupled to and controlling the memory devices.

[0109] It should be noted that the memory system 120 can communicate with the host. The host and / or the memory system 120 can be included in various products, such as Internet of Things (IoT) devices, such as refrigerators or other devices, sensors, motors, mobile communication devices, cars, unmanned driving, etc., to support product processing, communication or control. In one embodiment, the memory system 120 can be a discrete memory or memory component of the host device. In other embodiments, the memory system 120 can also be part of an integrated circuit, such as part of a system on chip (SOC). At this time, the memory system 120 is stacked or otherwise assembled with one or more components of the host. In other embodiments, the aforementioned memory system can be implemented and packaged in products such as memory cards, drives, etc., such as Figure 13A and Figure 13B As shown, Figure 13A A schematic diagram illustrating an exemplary memory card having a memory system according to aspects provided herein; Figure 13B Schematic diagram of an exemplary solid-state drive (SSD) having a memory system according to some aspects of the present invention is shown. Figure 13A In one example shown in FIG, a memory controller 1202 and a single memory device 1201 of a memory system may be integrated into a memory card 130. The memory card 130 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMC micro), an SD card (SD, mini SD, micro SD, SDHC), a UFS, etc. The memory card 130 may also include a memory card connector 1301 for coupling the memory card 130 to a host. In FIG. Figure 13BIn another example shown in , the memory controller 1202 and the plurality of memory devices 1201 can be integrated into the SSD 131. The SSD 131 can also include an SSD connector 1311 for coupling the SSD 131 to the host. In some embodiments, the storage capacity and / or operating speed of the SSD 131 is greater than the storage capacity and / or operating speed of the memory card 130.

[0110] In some embodiments, the host described above may include a processor and a host RAM, wherein the host RAM may include DRAM, SDRAM, or any other suitable volatile or non-volatile memory device. The memory system 120 may be provided with one or more communication interfaces to communicate with one or more components in the host. The one or more components in the host may be a Serial Advanced Technology Attachment (SATA) interface, a high-speed peripheral component interconnect (PCIe) interface, a Universal Serial Bus (USB) interface, a Universal Flash Storage (UFS) interface, an eMMC interface, or a SATA-based microprocessor. TM interface, etc. The host may also include electronic components, a memory card reader, or one or more other electronic components external to the memory system 120.

[0111] In some embodiments, the memory controller 1202 can receive instructions from the host and communicate with the memory device 1201. For example, the memory controller 1202 can execute write or erase instructions to transfer data to one or more memory cells, planes, sub-blocks, blocks, or pages in the memory device 1201, or the memory controller 1202 can execute read instructions to transfer data to the host. In hardware, the memory controller 1202 may include one or more controller units, circuits, or components configured to control access across the memory device 1201 and provide a translation layer between the host and the memory system 120. The memory controller 1202 may also include one or more input / output (I / O) circuits, lines, or interfaces to transfer data to or from the memory device 1201. The memory controller 1202 may also include a memory management unit and an array control unit. The memory management unit may include circuit hardware or firmware, such as multiple components or integrated circuits associated with various memory management functions. Taking NAND memory as an example, memory system operation or management functions are described. Those skilled in the art will appreciate that other forms of non-volatile memory may have similar memory operation or management functions. NAND memory management functions may include wear leveling, such as garbage collection or reclamation, error detection or correction, block retirement, or one or more other memory management functions. The memory management unit may process host instructions into commands recognizable by the memory system 120, such as parsing or formatting instructions received from the host into commands related to the operation of the memory device 1201. Alternatively, the memory management unit may generate device commands for the array control unit or one or more other components of the memory system 120, such as commands that implement various memory management functions. The memory management unit may be configured to include a set of management tables for maintaining various information associated with one or more components of the memory system 120, such as various information related to a memory cell array or one or more memory cells coupled to the memory controller 1202. For example, the management tables may include information such as block age, block erase count, error history, or one or more error counts for one or more blocks of memory cells coupled to the memory controller 1202. Error counts may include operation error counts, read bit error counts, and the like. In some embodiments, if the detected error count exceeds a certain threshold, the bit error is considered uncorrectable. In some embodiments, the management table may maintain counts of correctable and uncorrectable bit errors, among other things. The management table may also include one or more L2P tables, each containing one or more L2P pointers that associate a logical address with a physical address at the memory device 1201. In some embodiments, the management table may include an unencrypted L2P table and / or an encrypted L2P table.The unencrypted L2P table may include L2P pointers indicating unencrypted logical addresses and unencrypted physical addresses; the encrypted L2P table may include encrypted physical addresses and encrypted L2P pointers indicating unencrypted logical addresses. In actual implementation, the management table may be stored in the memory management unit, meaning that the management table may be stored in the RAM of the memory controller 1202. In other embodiments, the management table may also be stored in the memory device 1201. During use, the memory management unit may read part or all of the cached management table from the RAM of the memory controller 1202; alternatively, the management table may be read from the memory device 1201.

[0112] The array control unit may include circuit systems or components configured to control and complete the following memory device operations, such as controlling the writing of data to one or more memory cells in the memory system 120 coupled to the memory controller 1202, reading data from the one or more memory cells, or erasing the one or more memory cells. The array control unit may receive commands sent by the host or host commands generated internally by the memory management unit. The host commands may be commands associated with wear leveling, error detection or correction, etc.

[0113] The array control unit may also include an error correction code (ECC) component, which may include an ECC engine or other circuitry for detecting or correcting errors associated with writing data to or reading data from one or more memory cells in the memory system 120 coupled to the memory controller 1202. The memory controller 1202 is configured to efficiently detect and recover from error events associated with various operations or data storage, such as bit errors, operational errors, etc., while maintaining the integrity of data transmitted between the host and the memory system 120 or maintaining the integrity of stored data, such as by using redundant RAID storage, etc., and removing, such as retiring, failed memory resources, such as memory cells, memory arrays, pages, blocks, etc., to prevent future errors.

[0114] In the aforementioned memory system, in some embodiments, the memory device includes: a memory cell array; the memory cell array includes a plurality of memory cells and word lines coupled to the plurality of memory cells; each memory cell is configured to be one of a plurality of data states; and a peripheral circuit coupled to the memory cell array and configured to: apply a verification voltage to the word line when performing incremental step pulse programming on the plurality of memory cells, perform a first verification operation on a first data state among the plurality of data states, and perform a second verification operation on a second data state among the plurality of data states, wherein the first data state is adjacent to the second data state and a distance between a first expected threshold voltage distribution corresponding to the first data state and a second expected threshold voltage distribution corresponding to the second data state is greater than a preset threshold; and, after the first data state is verified, apply a first programming pulse to the word line to continue programming the memory cell expected to be programmed to the second data state; the first programming pulse is the sum of a second programming pulse and a preset offset voltage; and the second programming pulse is the programming pulse preceding the first programming pulse.

[0115] In some embodiments, the peripheral circuit is further configured to: determine a verification result of the second verification operation after the first data state is verified; divide the memory cells among the multiple memory cells that are expected to be programmed to the second data state into multiple groups based on the verification result; and apply different bit line voltages to the bit lines coupled to different groups of memory cells among the multiple groups of memory cells when continuing to program the memory cells among the multiple memory cells that are expected to be programmed to the second data state.

[0116] In some embodiments, the peripheral circuit is further configured to: divide the memory cells expected to be programmed to the second data state among the multiple memory cells into a first group and a second group according to the verification result, wherein the memory cells included in the first group are programmed to the second data state earlier than the memory cells included in the second group; when continuing to program the memory cells expected to be programmed to the second data state among the multiple memory cells, apply a first bit line voltage to the bit line coupled to the memory cells included in the first group; apply a second bit line voltage to the bit line coupled to the memory cells included in the second group, wherein the first bit line voltage is greater than the second bit line voltage.

[0117] In some embodiments, the peripheral circuit is further configured to: after the first programming pulse and when the second data state has not been verified, based on the first programming pulse and with a step increment voltage as a step length, gradually continue to apply gradually larger programming pulses to the word lines coupled to the multiple storage cells until the last data state among the multiple data states is verified; wherein the step increment voltage is less than the preset offset voltage.

[0118] In some embodiments, the last data state of the plurality of data states is the second data state.

[0119] In some embodiments, the peripheral circuit is further configured to program each of the plurality of memory cells from one of the plurality of data states to a corresponding target data state of a plurality of target data states.

[0120] In some embodiments, the multiple data states include: data state P0, data state P1, data state P2, and data state P3, in which the voltage values ​​included in the expected threshold voltage distribution increase in sequence; wherein the first data state is data state P2; and the second data state is data state P3.

[0121] In some embodiments, the plurality of target data states includes 16 target data states; wherein each of the plurality of data states is configured as corresponding 4 target data states.

[0122] In some embodiments, the peripheral circuit is further configured to: record the number of programming pulses applied to the word line coupled to the multiple memory cells; and when the number of applied programming pulses is equal to a preset number, start applying a verification voltage to the word line to simultaneously perform verification operations on the first data state and the second data state among the multiple data states.

[0123] In the above solution, the preset offset voltage is positively correlated with the distance between the first expected threshold voltage distribution and the second expected threshold voltage distribution, wherein the larger the distance is, the larger the preset offset voltage is.

[0124] It should be noted that the memory system includes the aforementioned memory device, and therefore, the two have the same technical features. The terms appearing in the memory system have been explained in detail in the aforementioned memory device and are also applicable here and will not be repeated one by one.

[0125] The above description is intended to be illustrative, not restrictive. For example, the above examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments may be used, such as those available to a person of ordinary skill in the art upon reading the above description. It should be understood that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features may be combined together to simplify the present invention. This should not be interpreted as meaning that unclaimed disclosed features are essential to any claim. On the contrary, the disclosed subject matter may be less than all the features of a particular disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, with each claim independently serving as a separate embodiment, and it is expected that these embodiments may be combined with each other in various combinations or permutations. The scope of the present invention should be determined with reference to the appended claims and the full scope of equivalents to which these claims are entitled.

Claims

1. A memory device, characterized in that: include: memory cell array; The memory cell array includes a plurality of memory cells and a word line coupled to the plurality of memory cells; Each memory cell is configured in one of a plurality of data states; and a peripheral circuit coupled to the memory cell array and configured to: When performing incremental step pulse programming on the plurality of memory cells, applying a verification voltage to the word line, performing a first verification operation on a first data state among the plurality of data states and performing a second verification operation on a second data state among the plurality of data states, wherein the first data state is adjacent to the second data state and a distance between a first expected threshold voltage distribution corresponding to the first data state and a second expected threshold voltage distribution corresponding to the second data state is greater than a preset threshold; and After the first data state is verified, a first programming pulse is applied to the word line to continue programming the memory cell expected to be programmed to the second data state; the first programming pulse is the sum of the second programming pulse and a preset offset voltage; the second programming pulse is the previous programming pulse of the first programming pulse.

2. The memory device according to claim 1, wherein The peripheral circuit is further configured as follows: After the first data state is verified, determining a verification result of the second verification operation; dividing memory cells expected to be programmed to the second data state among the plurality of memory cells into a plurality of groups according to the verification result; And when continuing to program memory cells expected to be programmed to the second data state among the plurality of memory cells, different bit line voltages are applied to bit lines coupled to different groups of memory cells among the plurality of groups of memory cells.

3. The memory device according to claim 2, wherein: The peripheral circuit is further configured to: divide the memory cells expected to be programmed to the second data state among the plurality of memory cells into a first group and a second group according to the verification result, wherein the memory cells included in the first group are programmed to the second data state earlier than the memory cells included in the second group; And when continuing to program the memory cells among the multiple memory cells that are expected to be programmed to the second data state, a first bit line voltage is applied to the bit line coupled to the memory cells included in the first group; and a second bit line voltage is applied to the bit line coupled to the memory cells included in the second group, wherein the first bit line voltage is greater than the second bit line voltage.

4. The memory device according to claim 1, wherein: The peripheral circuit is further configured to: after the first programming pulse and when the second data state has not been verified, continue to apply programming pulses of gradually increasing magnitude to word lines coupled to the plurality of memory cells based on the first programming pulse and with a step-increment voltage as a step length, until a last data state among the plurality of data states is verified; Wherein, the step increment voltage is smaller than the preset offset voltage.

5. The memory device according to claim 4, wherein: The last data state among the multiple data states is the second data state. The memory device according to claim 1 , wherein: The peripheral circuit is further configured to program each of the plurality of memory cells from one of the plurality of data states to a corresponding target data state of a plurality of target data states.

7. The memory device according to claim 6, wherein: The multiple data states include: data state P0, data state P1, data state P2, and data state P3, whose voltage values ​​included in the expected threshold voltage distribution increase in sequence; wherein, the first data state is data state P2; and the second data state is data state P3.

8. The memory device according to claim 7, wherein: The plurality of target data states include 16 target data states; wherein each of the plurality of data states is configured as corresponding 4 target data states.

9. The memory device according to claim 1, wherein: The peripheral circuit is further configured to: record the number of programming pulses applied to the word lines coupled to the plurality of memory cells; When the number of applied programming pulses is equal to a preset number, a verification voltage is applied to the word line to simultaneously perform a verification operation on the first data state and the second data state of the plurality of data states.

10. The memory device according to claim 1, wherein The preset offset voltage is positively correlated with a distance between the first expected threshold voltage distribution and the second expected threshold voltage distribution, wherein the larger the distance is, the larger the preset offset voltage is.

11. A method for programming a memory device, characterized in that: The memory device includes a plurality of memory cells and a word line coupled to the plurality of memory cells; Each memory cell is configured to be in one of a plurality of data states; the programming method includes: When performing incremental step pulse programming on the plurality of memory cells, applying a verification voltage to the word line, performing a first verification operation on a first data state among the plurality of data states and performing a second verification operation on a second data state among the plurality of data states, wherein the first data state is adjacent to the second data state and a distance between a first expected threshold voltage distribution corresponding to the first data state and a second expected threshold voltage distribution corresponding to the second data state is greater than a preset threshold; After the first data state is verified, a first programming pulse is applied to the word line to continue programming the memory cells among the multiple memory cells that are expected to be programmed to the second data state; the first programming pulse is the sum of the second programming pulse and a preset offset voltage; and the second programming pulse is the previous programming pulse of the first programming pulse.

12. The programming method according to claim 11, characterized in that: The programming method further comprises: After the first data state is verified, determining a verification result of the second verification operation; dividing memory cells expected to be programmed to the second data state among the plurality of memory cells into a plurality of groups according to the verification result; While continuing to program memory cells intended to be programmed to the second data state among the plurality of memory cells, different bit line voltages are applied to bit lines coupled to different groups of memory cells among the plurality of groups of memory cells.

13. The programming method according to claim 12, characterized in that: The dividing the memory cells expected to be programmed to the second data state among the plurality of memory cells into a plurality of groups according to the verification result includes: dividing the memory cells expected to be programmed to the second data state among the plurality of memory cells into a first group and a second group according to the verification result, wherein the memory cells included in the first group are programmed to the second data state earlier than the memory cells included in the second group; And when continuing to program the memory cells expected to be programmed to the second data state among the multiple memory cells, different bit line voltages are applied to the bit lines coupled to the memory cells in different groups among the multiple groups of memory cells, including: when continuing to program the memory cells expected to be programmed to the second data state among the multiple memory cells, a first bit line voltage is applied to the bit lines coupled to the memory cells included in the first group; and a second bit line voltage is applied to the bit lines coupled to the memory cells included in the second group, wherein the first bit line voltage is greater than the second bit line voltage.

14. The programming method according to claim 11, characterized in that: The programming method further comprises: After the first programming pulse and when the second data state has not been verified, gradually increasing programming pulses are applied to the word lines coupled to the multiple memory cells based on the first programming pulse and with a step increment voltage as a step length until the last data state of the multiple data states is verified, wherein the step increment voltage is less than the preset offset voltage.

15. The programming method according to claim 14, characterized in that: The last data state is the second data state.

16. The programming method according to claim 11, characterized in that: The programming method further includes programming each of the plurality of memory cells from one of the plurality of data states to a corresponding target data state of a plurality of target data states.

17. The programming method according to claim 16, characterized in that: The multiple data states include: data state P0, data state P1, data state P2, and data state P3, whose voltage values ​​included in the expected threshold voltage distribution increase in sequence; wherein, the first data state is data state P2; and the second data state is data state P3.

18. The programming method according to claim 17, characterized in that: The plurality of target data states include 16 target data states; wherein each of the plurality of data states is configured as corresponding 4 target data states.

19. The programming method according to claim 11, wherein: The programming method further comprises: recording the number of programming pulses applied to the word lines coupled to the plurality of memory cells; When the number of applied programming pulses is equal to a preset number, a verification voltage starts to be applied to the word line to simultaneously perform a verification operation on the first data state and the second data state of the plurality of data states.

20. A memory system, characterized in that: include: One or more memory devices according to any one of claims 1 to 11; and a memory controller coupled to the memory device and controlling the memory device.

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