DDR4 sdram fixed bit error test method and apparatus based on high energy particles

Abstract

The application relates to a DDR4 SDRAM fixed bit error test method and device based on high-energy particles, and the method comprises the following steps: S1, obtaining a DDR4 SDRAM sample device, selecting a target radiation source and irradiation energy; S2, irradiating the sample device according to the target radiation source and the irradiation energy from an initial particle fluence; S3, judging whether the sample device after irradiation appears a fixed bit error, if not, irradiating the sample device according to the initial particle fluence and increasing the particle fluence, repeating S3, if the fixed bit error appears, recording the particle fluence reaching a damage threshold and determining the number of fixed bit errors; S4, measuring an annealing curve of the sample device, obtaining the annealing curve according to the particle fluence reaching the damage threshold, and determining an optimal device according to the damage threshold and the annealing curve. The application can effectively evaluate the DDR4 SDRAM fixed bit error.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of integrated circuit testing, in particular to a DDR4 SDRAM fixed bit error test method and device based on high-energy particles. BACKGROUND

[0002] It has become a widespread consensus in the industry to build high-performance large-capacity storage and computing systems on satellites to achieve on-orbit data storage and real-time data processing. At the same time, these tasks tend to or can only use low-cost, low-hardened Commercial Off-the-Shelf (COTS) devices. High-performance DDR4 SDRAM (Double Data Rate 4 Synchronous Dynamic Random-Access Memory) will be widely used in these computing and storage devices and become a key link affecting the reliability of system functions.

[0003] Dynamic random access memory (SDRAM) has developed rapidly in the past decade. The transistor morphology and process size have undergone major changes, which may make it sensitive to space radiation environments, including solar proton events (SPE) faced by high-orbit satellites, and protons in the inner radiation belt captured by the Earth's magnetic field, especially in the South Atlantic Anomaly (SAA) strong proton radiation environment. Compared with single-event upsets leading to failures, hard damage that cannot be recovered by power cycling is more harmful and has a longer impact duration. DDR4 SDRAM fixed bit errors occur in certain locations in the memory cell for a long time and multiple times. In on-orbit applications, single-event upsets and fixed bit errors may exhibit similar phenomena and cause misjudgments, but their mechanisms and properties are different. In the current design scheme of high-performance space electronic equipment, only commercial-grade DDR4 SDRAM can be selected, so it is necessary to propose a ground test and screening method in response to devices from different manufacturers and production batches to determine the optimal device to maximize the avoidance of hard damage caused by fixed bit errors in on-orbit space applications to ensure the safe operation of space electronic systems. The current main evaluation method in China still focuses on temperature cycling, cycle aging test, and single-event upset. There is no mature test evaluation method for DDR4 SDRAM fixed bit error hard damage. SUMMARY

[0004] The application aims to provide a DDR4 SDRAM fixed bit error test method and device based on high-energy particles, which can effectively evaluate DDR4 SDRAM fixed bit errors.

[0005] To achieve the above object, the present application provides the following scheme:

[0006] The DDR4 SDRAM fixed bit error test method based on high-energy particles comprises the following steps:

[0007] S1, obtaining a DDR4 SDRAM sample device, selecting a target radiation source and irradiation energy;

[0008] S2, irradiating the sample device according to the initial particle fluence based on the target radiation source and irradiation energy;

[0009] S3, judging whether the sample device after irradiation has a fixed bit error, if not, irradiating the sample device according to the initial particle fluence and increasing the particle fluence, repeating S3, if yes, recording the particle fluence reaching the damage threshold and determining the number of fixed bit errors;

[0010] S4, measuring the annealing curve of the sample device, obtaining the annealing curve according to the particle fluence reaching the damage threshold, and determining the optimal device according to the damage threshold and the annealing curve.

[0011] Optionally, the selecting of the target radiation source and irradiation energy comprises the following steps:

[0012] Disassembling the sample device to obtain a silicon crystal die;

[0013] Measuring the silicon crystal die by using focused ion beam technology and an electron microscope to obtain the distance from the substrate edge to the active area;

[0014] Calculating the maximum atomic displacement distribution of incident particles in the silicon substrate, and selecting the target radiation source and irradiation energy according to whether the distance from the substrate edge to the active area and the maximum atomic displacement distribution are within a preset range.

[0015] Optionally, the judging whether the sample device after irradiation has a fixed bit error comprises judging whether the sample device after irradiation has a fixed bit error by full address chessboard cycle read-write verification.

[0016] Optionally, the recording of the particle fluence reaching the damage threshold comprises the following steps:

[0017] If errors occur at the same fixed physical address in multiple full address chessboard cycle read-writes, and the errors do not disappear after re-powering on, it is determined that a damage event of fixed bit error occurs, and the particle fluence reaching the damage threshold is recorded.

[0018] Optionally, the measuring of the annealing curve of the sample device comprises the following steps:

[0019] S41, preset initial self-refresh interval time of the sample device, carry out the chessboard cycle read-write test under the initial self-refresh interval time, and acquire the fixed bit error quantity under the initial self-refresh interval time;

[0020] S42, gradually reduce the self-refresh interval, run the chessboard cycle read-write test, and acquire the fixed bit error quantity under the gradually reduced self-refresh interval;

[0021] S43, judge whether the fixed bit error disappears, if yes, acquire the annealing curve, if no, continue to judge whether the predetermined total annealing time is reached, if yes, acquire the annealing curve, and if no, return to S41.

[0022] Optionally, the annealing curve comprises:

[0023] According to the error bit quantity, the total bit quantity of the chip and the particle fluence reaching the damage threshold, the error cross section is calculated, and the annealing curve is drawn according to the error cross section.

[0024] The calculation method of the error cross section comprises:

[0025]

[0026] Wherein, σ 固定位 is the error cross section, N 错误比特数量 is the error bit quantity, C 芯片总比特数 is the total bit quantity of the chip, and F 高能粒子注量 is the particle fluence reaching the damage threshold.

[0027] The application further provides a device for realizing the DDR4 SDRAM fixed bit error test method based on high-energy particles, comprising: an upper computer and a lower computer.

[0028] The upper computer is used for issuing instructions to the lower computer.

[0029] The lower computer is used for executing corresponding programs after receiving corresponding instructions, and reporting sample device error states, error counts, working voltage and working current parameters, and visualizing error information distribution and electrical parameter change characteristics.

[0030] The beneficial effects of this invention are as follows: This invention provides a test method and apparatus for evaluating the susceptibility of fixed bit errors in DDR4 SDRAM from different manufacturers and batches. This method is applicable to DDR4 SDRAM with the same package and electrical interface specifications, and can effectively identify the physical address distribution and error mode characteristics of fixed bit errors in the chip. By selecting appropriate particle types, energies, and flux during the test, this method can effectively identify fixed bit errors. By comparing the annealing characteristics of fixed bit errors under different damage flux thresholds and self-refresh intervals, a reliable basis can be provided for the screening of commercial-grade DDR4 SDRAM chips, thereby determining the optimal device. This method provides a standardized ground-based test method for the selection and evaluation of DDR SDRAM devices in high-performance aerospace electronic systems. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a flowchart of a high-energy particle-based DDR4 SDRAM fixed bit error test method according to an embodiment of the present invention;

[0033] Figure 2 The range parameters of 5MeV protons in silicon material calculated using the Monte Carlo method in this embodiment of the invention;

[0034] Figure 3 This is a flowchart illustrating the measurement of annealing curves under different self-refresh levels, temperatures, and times according to an embodiment of the present invention.

[0035] Figure 4 This is a flowchart illustrating the extraction and analysis of error data through a checkerboard loop read / write test, as described in an embodiment of the present invention.

[0036] Figure 5 This is a schematic diagram of a high-energy particle-based DDR4 SDRAM fixed bit error testing device according to an embodiment of the present invention;

[0037] Figure 6 This is a diagram showing the distribution of fixed bit errors in each bank of DDR4 SRAM according to an embodiment of the present invention.

[0038] Figure 7 This is an annealing curve of sample M5 irradiated with 5MeV protons according to an embodiment of the present invention. Detailed Implementation

[0039] With reference to the accompanying drawings, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of the present application.

[0040] In order to make the above objectives, characteristics and advantages of the present application more apparent, further specific embodiments of the present application will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0041] Embodiment one:

[0042] The embodiment provides a DDR4 SDRAM fixed bit error test method based on high-energy particles, including:

[0043] S1, obtaining a DDR4 SDRAM sample device, selecting a target radiation source and irradiation energy;

[0044] S2, irradiating the sample device according to the target radiation source and irradiation energy from an initial particle fluence;

[0045] S3, judging whether the sample device after irradiation appears a fixed bit error, if not, irradiating the sample device according to an increased particle fluence from the initial particle fluence, repeating S3, if yes, recording a particle fluence reaching a damage threshold and determining a number of fixed bit errors;

[0046] S4, measuring an annealing curve of the sample device, and obtaining the annealing curve according to the particle fluence reaching the damage threshold, and determining an optimal device according to the damage threshold and the annealing curve.

[0047] Specifically, the irradiation test is carried out by using the particle source. Since the damage mechanism of the fixed bit error is the change of electrical characteristics caused by the lattice defects caused by atomic displacement, the test can be carried out under the condition of no bias after the device is removed from the package and the silicon substrate is exposed and works normally. In order to avoid the blocking effect of air on particles, the test is carried out in a vacuum environment as much as possible. Before the test is carried out, a plurality of particle fluence levels need to be determined. The particle fluence can be 1x10 7 p / cm 2 After the particle fluence, the test work of the fixed bit error is started.

[0048] Further, the selection of the target radiation source and irradiation energy includes:

[0049] The sample device is disassembled to obtain a silicon crystal die;

[0050] According to the measurement of the silicon wafer by the focused ion beam technology and the electron microscope, the distance from the substrate edge to the active area is obtained;

[0051] The maximum atomic displacement distribution of the incident particles in the silicon substrate is calculated, and the target radiation source and the irradiation energy are selected according to whether the distance from the substrate edge to the active area and the maximum atomic displacement distribution are within a preset range.

[0052] Specifically, a sample of the device to be tested is first destructively disassembled to observe the internal structure, and the silicon wafer is taken out by the chip unpackaging method, and then the device array area is observed by the focused ion beam (Focused Ion Beam) technology and the electron microscope in the storage array area S1. The distance from the chip to the active area (Active Aera) of the substrate is determined, which is due to the reverse packaging characteristics of the device, so that the incident particles can only be tested from the back of the device without affecting the electrical testability. After obtaining the accurate distance from the substrate edge to the active area, the maximum atomic displacement distribution of the incident particles in the silicon substrate is calculated, and the appropriate irradiation source and irradiation energy are selected.

[0053] Further, judging whether the sample device after irradiation has a fixed bit error includes: judging whether the sample device after irradiation has a fixed bit error by full address chessboard cycle read-write verification.

[0054] Further, recording the particle fluence reaching the damage threshold includes:

[0055] If errors occur at the same fixed physical address in multiple full address chessboard cycle read-write operations, and the errors do not disappear after re-powering, it is determined that a fixed bit error damage event occurs, and the particle fluence reaching the damage threshold is recorded.

[0056] Further, annealing curve measurement of the sample device includes:

[0057] S41, preset the initial self-refresh interval time of the sample device, perform chessboard cycle read-write test under the initial self-refresh interval time, and obtain the number of fixed bit errors under the initial self-refresh interval time;

[0058] S42, gradually reduce the self-refresh interval, run the chessboard cycle read-write test, and obtain the number of fixed bit errors under the gradually reduced self-refresh interval;

[0059] S43, judge whether the fixed bit error disappears, if it disappears, obtain the annealing curve, if it does not disappear, continue to judge whether the predetermined total annealing time is reached, if it is reached, obtain the annealing curve, if it is not reached, return to S41.

[0060] Further, obtaining the annealing curve includes:

[0061] The error cross section is calculated based on the number of error bits, the total number of bits in the chip, and the particle injection rate that reaches the damage threshold. The annealing curve is then plotted based on the error cross section.

[0062] The calculation method for the faulty section is as follows:

[0063]

[0064] Where, σ 固定位 For the incorrect section, N 错误比特数量 C represents the number of error bits. 芯片总比特数 F represents the total number of bits in the chip. 高能粒子注量 The particle flux required to reach the damage threshold.

[0065] The following description, in conjunction with the accompanying drawings, further illustrates this embodiment:

[0066] Figure 1 This is a schematic diagram of a DDR4 SDRAM fixed bit error test process according to an embodiment of the present invention. S1: A sample of the device under test is first subjected to a destructive disassembly test to observe its internal structure. After removing the silicon die using a chip unpacking method, the device array area is observed using focused ion beam (FIB) technology and an electron microscope. S2: The distance from the chip edge to the active area is determined. This is because the flip-chip packaging characteristic of the device means that, without affecting electrical testability, the test can only be conducted by incident particles from the back of the device. After obtaining the precise distance from the substrate edge to the active area, the maximum atomic displacement distribution of the incident particles in the silicon substrate is calculated, and a suitable irradiation source and irradiation energy are selected. Figure 2 For example, using the Monte Carlo method to calculate the range parameters of 5MeV protons in silicon, including maximum range, atomic displacement, and linear energy transfer data, if the distribution position of the maximum atomic displacement of the particles is close to the measured distance from the edge of the DDR4 SDRAM device substrate to the active region, the optimal experimental particle type and energy conditions can be determined. Further irradiation experiments can be conducted using this particle source. Since the damage mechanism of fixed-position errors is the change in electrical properties caused by lattice defects due to atomic displacement, the experiment can be carried out under unbiased conditions after the device is unpackaged and the exposed silicon substrate has been tested and found to be functioning normally. Simultaneously, to avoid the potential obstruction of particles by air, the experiment should be conducted in a vacuum environment if possible. S3: Before conducting the experiment, several particle flux levels need to be determined, starting from 1×10⁻⁶. 7 p / cm 2S4: After that, the high-energy particle fluence is increased by one or two orders of magnitude successively. After reaching the test point of one fluence level, the sample is taken out for testing (a plurality of samples of the same batch can also be prepared to observe at different fluence levels), and the test method is to observe whether a fixed bit error occurs by reading and checking after full-address chessboard cycle writing, S5: If no fixed bit error occurs, the irradiation fluence is continued to increase until the next observation point is reached. S6: If an error is found at a fixed physical address in multiple read-write cycles, and the error does not disappear after re-powering, it is considered that a fixed bit error damage event has occurred, the particle fluence reaching the damage threshold is recorded, and the post-irradiation test phase is entered. S7: The number of error bits is determined by multiple full-address cycle reading and writing, and the average and standard deviation are calculated, and room temperature annealing or high temperature annealing tests are performed according to actual needs, S8: Annealing curve measurement under different self-refresh levels, temperatures, and time conditions. S9: Compare the damage threshold and annealing curve of different (for example, different manufacturers, production batches, and different degrees of cycle aging experiment) DDR4 SDRAM devices under the same test conditions, and select the device with high damage threshold and fast annealing speed as the optimal device.

[0067] Since such errors are affected by device operating conditions, different operating parameter levels need to be further adjusted to comprehensively measure radiation damage characteristics. This step includes several sub-processes such as Figure 3 shown. SS1: At the first time after irradiation testing, the irradiated device is set to the standard X1 working condition of the DDR4 SDRAM device self-refresh interval T refi 7.9 microseconds. SS2: Run multiple rounds of chessboard cycle reading and writing tests to record the number of errors, SS3: Then gradually reduce the self-refresh interval T refi to X2: 3.95 microseconds and X4: 1.925 microseconds or set more levels as needed, SS4: Run chessboard cycle reading and writing tests to determine the number of errors under this T refi condition, SS5: Determine whether the fixed bit error disappears, SS6: If it does not disappear, continue to determine whether the predetermined total annealing time is reached, SS7: If it is not reached, continue the fixed interval annealing test and repeat steps SS1-SS5. When the maximum time interval is reached or the fixed bit error disappears, the post-irradiation test is ended, and the annealing curve under different refresh levels is drawn as a parameter for device evaluation.

[0068] Example Two:

[0069] This embodiment provides a DDR4 SDRAM fixed bit error test device based on high-energy particles, comprising: an upper computer and a lower computer;

[0070] The upper computer is used to issue instructions to the lower computer;

[0071] The lower computer is used for executing corresponding programs after receiving corresponding instructions and reporting sample device error states, error counts, working voltage and working current parameters, and visualizing error information distribution and electrical parameter change characteristics.

[0072] Specifically, the DDR4 SDRAM test software and hardware system is a key support in the test process, and the basic structure of the software and hardware is as shown in the figure Figure 5 The test system is composed of an upper computer and a lower computer,

[0073] The lower computer comprises:

[0074] (1) a SoC, wherein a programmable logic part (PL) and a processing system (PS) are contained;

[0075] (2) a FGBA-96 test fixture;

[0076] (3) a cache DDR4;

[0077] (4) a gigabit Ethernet port physical layer chip (PHY);

[0078] (5) a CAN interface communication module;

[0079] (6) a serial communication module;

[0080] The upper computer comprises:

[0081] (1) a SoC state monitoring program module;

[0082] (2) a DDR4 basic working parameter and command issuing program module;

[0083] (3) a PL DDR4 data high-speed transmission and storage program module;

[0084] (4) an error data and electrical data storage and visualization program module;

[0085] (5) the PL communicates with the DDR4 SDRAM device to be tested through an XPIO interface in a NOC bus;

[0086] (6) the PS is used for processing test data and uploading data through a gigabit Ethernet port.

[0087] The DDR4 basic working parameter and command issuing module comprises:

[0088] (a) an instruction control system based on CAN bus communication;

[0089] (b) instruction design includes data pattern, test method, cycle number and test switch signal.

[0090] The error data, electrical data storage and visualization module comprises:

[0091] (a) a MySQL database interaction program;

[0092] (b) a graphical interaction interface subprogram;

[0093] (c) an error information distribution and electrical parameter change characteristic visualization drawing subprogram.

[0094] The lower computer part utilizes the programmable logic part (Programmable Logic, PL) in the SoC 7 to realize the communication of the XPIO interface in the NOC bus and the DDR4 SDRAM test device 6, which is placed in the FGBA-96 test fixture 7, and the test device can be flexibly disassembled and assembled without welding. The processing system (Processing System, PS) in the SoC is used to realize the processing and uploading of test data, and the basic components include a plurality of cache DDR4 5 for temporarily storing data in the test DDR4. Since the capacity of the DDR4 SDRAM usually reaches several Gbit, the performance of the traditional serial communication is difficult to meet the test requirements, so the PS end and the gigabit Ethernet port physical layer chip (PHY) are used to realize the Ethernet function; the CAN interface is used to upload the voltage and current of the test device and receive the test command information from the upper computer; the serial port is used to upload the running state of the test system, including the starting process, device connection state, etc.

[0095] The personal computer can run the upper computer control program, wherein the SoC state monitoring module 1 is used to receive and process various state information reported by the SoC of the lower computer, and is used to confirm whether the test system has been normally started and whether the test device has been fixed in the test fixture and connected normally. The DDR4 basic working parameter and command issuing module 2 includes an instruction control system realized by the CAN bus communication, and the instructions in the instruction design include data patterns (all 0, all 1 and chessboard test), test methods (single read-write or cyclic read-write), cycle times, test switch signals, etc. After the lower computer receives the corresponding instructions, the corresponding programs are executed and the error state of the test device, error count, working voltage and working current, etc. are reported. The PL DDR4 data high-speed transmission and storage module 3 includes a high-speed transmission function of the internal data of the test device realized based on the TCP / IP protocol. The error data, electrical data storage and visualization module 4 includes a MySQL database program for storing detailed error data. The graphical interaction interface subprogram can export the data of a specific test round according to the user's needs; the error information distribution and electrical parameter change characteristic visualization drawing subprogram is used to observe the error distribution.

[0096] The high-energy particle irradiation part of the experimental results obtained by the device of the embodiment are as follows:

[0097] The distance from the silicon substrate edge to the active area of a to-be-tested DDR4 SDRAM sample is measured by using a focused ion beam test measurement, and simulation calculation shows that the atomic displacement peak of 5 MeV protons is located near 215 um, which is close to the measurement result of the device. Therefore, the test is carried out by using protons with this energy. As a comparison, 3 MeV and 80 MeV protons are used as reference groups. The atomic displacement peak of 3 MeV protons cannot reach the active area of the device in theory, so it cannot cause errors. The 80 MeV protons can completely penetrate the active area due to the long range, so they cannot deposit much energy or cause much atomic displacement in the active area. The test results of multiple samples are shown in Table 1. It can be seen that no fixed position error is found under the irradiation of 3 MeV and 80 MeV protons. Three fluence levels are set in the 5 MeV irradiation test, and it is found that fixed position error occurs only under the condition of 1x10 11 p / cm 2 fluence, and the corresponding fixed position error damage threshold is recorded. The test system described in the embodiment is used to extract and analyze the error data, and it is found that the error distribution in the Bank Group (BG) number distribution of the address space of the DDR4 SDRAM is still slightly different, and the distribution in each bank is relatively uniform, as shown in Figure 6 .

[0098] As shown in Figure 4 , the extraction and analysis of error data by the chessboard cycle read-write test specifically include: SSA: dividing the entire address space of the DDR4 SDRAM from the low address to the high address into a plurality of data blocks of the same size; SSB: writing 4-bit 16 hexadecimal number 5555 into the addresses of odd blocks and writing 4-bit 16 hexadecimal number AAAA into the addresses of even blocks; SSC: reading the data in these addresses after writing all the addresses and comparing and verifying the data with the written data, and the verification range is the entire address space of the chip; SSD: reporting the total number of errors, addresses, and error types (errors of 0 changing to 1 or errors of 1 changing to 0) on the Ethernet of the test system; SSE: re-writing AAAA into odd blocks and 5555 into even blocks from the low address; SSF: verifying the entire memory space after writing all the addresses, and reporting the total number of errors, addresses, and error types (errors of 0 changing to 1 or errors of 1 changing to 0) on the Ethernet of the test system; SSH: judging whether the predetermined test cycle is reached; SSI: calculating the average number of errors and the standard error when the predetermined test cycle is reached, and returning to SSA when the predetermined test cycle is not reached.

[0099] Table 1

[0100]

[0101] Table 2

[0102]

[0103] Table 2 is a typical fixed bit error failure mode tested after irradiation, which is divided into fixed 0 and fixed 1 failure types:

[0104] Fixed 0: that is, write 1 read 0 error.

[0105] Fixed 1: write 0 read 1 error.

[0106] Both of these error modes are single bit errors, and the two error modes are in a 1:1 corresponding relationship in total.

[0107] Figure 7 The annealing curve of the device 5 MeV proton irradiation sample M5 is shown. After about 96 hours of room temperature annealing, the number of fixed bit errors is determined by using the test system for irradiation test every 24 hours. Then high temperature annealing test is carried out in the oven at 85 degrees Celsius to obtain the fixed bit error annealing curve. The annealing test shows that high temperature can accelerate the annealing of fixed bit damage of DDR4 SDRAM device, and under the X4 refresh interval, the fixed bit error decreases by about two orders of magnitude, while the X2 refresh interval has less effect on the fixed bit error. The fixed bit error characteristic curve of the device is drawn. The calculation method of the error cross section is:

[0108]

[0109] The purpose of the formula is to draw the annealing curve, which is the calculation method of the vertical coordinate of the annealing curve. 固定位 Error cross section, N 错误比特数量 Number of error bits, C 芯片总比特数 Total number of bits of the chip, F 高能粒子注量 Particle fluence to reach damage threshold.

[0110] The above-described embodiments are only descriptions of the preferred modes of the present application, and do not limit the scope of the present application. Without departing from the design spirit of the present application, various modifications and improvements to the technical solutions of the present application made by those skilled in the art shall fall within the protection scope determined by the claims of the present application.

Claims

1. A method for testing fixed bit errors in DDR4 SDRAM based on high-energy particles, characterized in that, include: S1. Obtain DDR4 SDRAM sample devices and select target radiation source and irradiation energy; S2. Irradiate the sample device with an initial particle fluence based on the target radiation source and irradiation energy. S3. Determine whether a fixed bit error occurs in the sample device after irradiation. If no fixed bit error occurs, increase the particle fluence according to the initial particle fluence and irradiate the sample device. Repeat S3. If a fixed bit error occurs, record the particle fluence that reaches the damage threshold and determine the number of error bits. S4. Perform annealing curve measurement on the sample device, and obtain the annealing curve based on the particle flux that reaches the damage threshold. Determine the optimal device based on the damage threshold and the annealing curve. The annealing curve measurement of the sample device includes: S41. Preset the initial self-refresh interval time of the sample device, and perform a checkerboard cyclic read / write test under the initial self-refresh interval time to obtain the number of fixed bit errors under the initial self-refresh interval time. S42. Gradually reduce the self-refresh interval and run a checkerboard loop read / write test to obtain the number of fixed bit errors under the gradually reduced self-refresh interval. S43. Determine whether the fixed position error has disappeared. If it has disappeared, obtain the annealing curve. If it has not disappeared, continue to determine whether the predetermined total annealing time has been reached. If it has been reached, obtain the annealing curve. If it has not been reached, return to S41. Obtaining the annealing curve includes: calculating the error cross section based on the number of error bits, the total number of bits in the chip, and the particle injection rate that reaches the damage threshold; and plotting the annealing curve based on the error cross section. The method for calculating the erroneous section is as follows: ； in, This is an incorrect section. The number of error bits. This represents the total number of bits in the chip. The particle flux required to reach the damage threshold.

2. The method for testing fixed bit errors in DDR4 SDRAM based on high-energy particles according to claim 1, characterized in that, The selection of target radiation sources and irradiation energy includes: The sample device was disassembled to obtain a bare silicon wafer; The distance from the substrate edge to the active region is obtained by measuring the silicon crystal wafer using focused ion beam technology and electron microscopy. Calculate the maximum atomic displacement distribution of the incident particles in the silicon substrate, and select the target radiation source and irradiation energy based on whether the distance from the edge of the substrate to the active region and the maximum atomic displacement distribution are within a preset range.

3. The method for testing fixed bit errors in DDR4 SDRAM based on high-energy particles according to claim 1, characterized in that, Determining whether a fixed bit error occurs in a sample device after irradiation includes: using a full address checkerboard loop read / write check to determine whether a fixed bit error occurs in a sample device after irradiation.

4. The method for testing fixed bit errors in DDR4 SDRAM based on high-energy particles according to claim 3, characterized in that, The recorded particle fluence that reached the damage threshold includes: If an error occurs at the same fixed physical address during multiple full-address checkerboard loop read / write operations, and the error does not disappear after power-on, a damage event with a fixed bit error is determined, and the particle flux that reaches the damage threshold is recorded.

5. An apparatus for implementing the high-energy particle-based DDR4 SDRAM fixed bit error testing method according to any one of claims 1-4, characterized in that, include: Host computer and slave computer; The host computer is used to send instructions to the slave computer; The lower-level machine is used to execute the corresponding program after receiving the corresponding instruction and report the error status, error count, working voltage and current parameters of the sample device, and visualize the distribution of error information and the changing characteristics of electrical parameters.

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