Base chip, memory system and semiconductor structure

Abstract

The embodiment of the invention provides a basic chip, a storage system and a semiconductor structure, and the basic chip is configured to receive first data and first coded data in a writing stage and carry out first error detection and correction processing, the first coded data is obtained by carrying out first error correction code coding processing on the first data, second data is transmitted to a storage chip in the writing stage, and the second data comprises the first data after the first error detection and correction processing; the basic chip is further configured to receive the second data from the storage chip in a reading stage, perform second error correction code encoding processing on the second data to generate second encoded data, and transmit third data in the reading stage, the third data comprises the second coded data and the first data after the first error detection and correction processing.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a basic chip, a storage system, and a semiconductor structure. Background Art

[0002] Semiconductor storage can be divided into non-volatile storage and volatile storage. Dynamic Random Access Memory (DRAM), as a volatile storage, has advantages such as high storage density and fast read and write speeds, and is widely used in various electronic systems.

[0003] As DRAM manufacturing processes become more advanced and storage density increases, errors may occur in stored data, seriously affecting DRAM performance. Therefore, DRAM typically uses error checking and correction (ECC) technology to detect or correct errors in stored data. Summary of the Invention

[0004] The embodiments of the present application provide a basic chip, a storage system, and a semiconductor structure, which are at least helpful in solving the problem of limited area of ​​the controller or storage chip.

[0005] According to some embodiments of the present application, on the one hand, embodiments of the present application provide a basic chip, which is applied to a storage system, including: the basic chip is configured to receive first data and first coded data in a write phase and perform a first error detection and correction process, the first coded data is obtained by performing a first error correction code encoding process on the first data, and second data is transmitted to the storage chip in the write phase, and the second data includes the first data after the first error detection and correction process; the basic chip is also configured to receive the second data from the storage chip in a read phase and perform a second error correction code encoding process on the second data to generate second coded data, and transmit third data in the read phase, and the third data includes the second coded data and the first data after the first error detection and correction process.

[0006] In addition, the basic chip includes: a first error detection and correction module, which is configured to receive the first data and the first encoded data in the writing phase and perform the first error detection and correction processing; a second encoding module, which is configured to receive the first data after the first error detection and correction processing in the reading phase and perform the second error correction code encoding processing to generate the second encoded data.

[0007] In addition, the basic chip is also configured to, in the write stage, perform a third error correction code encoding process on the first data after the first error detection and correction process to generate third encoded data, and the second data also includes the third encoded data; in the read stage, before performing the second error correction code encoding process, it also includes performing a second error detection and correction process on the second data, and the third data includes the first data after the first error detection and correction process as the first data after the second error detection and correction process.

[0008] In addition, the basic chip also includes: a third encoding module, which is configured to receive the first data after the first error detection and correction processing in the writing phase and perform the third error correction code encoding processing to generate the third encoded data; a second error detection and correction module, which is configured to receive the second data in the reading phase and perform the second error detection and correction processing.

[0009] In addition, the basic chip also includes: a first serial-to-parallel conversion module, which is configured to receive the first data and the first encoded data in the write phase, and perform a first serial-to-parallel conversion on the first data and the first encoded data, and transmit the first data and the first encoded data after the first serial-to-parallel conversion to the first error detection and correction module; a first parallel-to-serial conversion module, which is configured to receive the third data from the second encoding module in the read phase, and perform a first parallel-to-serial conversion on the third data, and transmit the third data after the first parallel-to-serial conversion to the controller.

[0010] In addition, the basic chip also includes: a second parallel-to-serial conversion module, which is configured to receive the second data and perform a second parallel-to-serial conversion process in the write phase, and transmit the second data after the second parallel-to-serial conversion process to the storage chip; a second serial-to-parallel conversion module, which is configured to receive the second data from the storage chip and perform a second serial-to-parallel conversion process in the read phase, and transmit the second data after the second serial-to-parallel conversion process to the second encoding module.

[0011] In addition, the basic chip is also configured to generate a first error detection flag signal during the first error detection and correction process, and based on the first error detection flag signal, record errors in the first data and the first encoded data during transmission.

[0012] In addition, the basic chip also includes: a first storage cache module, which is configured to store the error conditions of the first data and the first encoded data during the transmission process; a first command module, which receives a first polling instruction and generates a first command signal and a first clock signal; the first storage cache module is also configured to output a first characterization signal based on the first command signal and the first clock signal, and the first characterization signal characterizes the error conditions of the first data and the first encoded data during the transmission process.

[0013] In addition, the basic chip is also configured to generate a second error detection flag signal during the second error detection and correction processing, and based on the second error detection flag signal, record the error conditions of the third encoded data and the first data after the first error detection and correction processing during transmission.

[0014] In addition, the basic chip also includes: a second storage cache module, the second storage cache module is configured to store the third encoded data and the error conditions of the first data after the first error detection and correction processing during the transmission process; a second command module, the second command module receives a second polling instruction and generates a second command signal and a second clock signal; the second storage cache module is also configured to output a second characterization signal based on the second command signal and the second clock signal, the second characterization signal characterizing the error conditions of the third encoded data and the first data after the first error detection and correction processing during the transmission process.

[0015] According to some embodiments of the present application, on the other hand, an embodiment of the present application provides a storage system, including a controller, a basic chip and a storage chip, and further including: the controller is configured to perform a first error correction code encoding process on the first data in the write phase to generate first coded data, and transmit the first data and the first coded data to the basic chip; the basic chip is configured to receive the first data and the first coded data in the write phase and perform a first error detection and correction process, and transmit second data to the storage chip in the write phase, the second data including the first data after the first error detection and correction process; the basic chip is also configured to receive the first data from the storage chip in the read phase. The second data is encoded and processed by a second error correction code to generate second encoded data, and third data is transmitted to the controller in the reading phase, wherein the third data includes the second encoded data and the first data after the first error detection and correction processing; the storage chip is configured to receive the second data from the basic chip and store the second data in the writing phase, and transmit the second data to the basic chip in the reading phase; the controller is also configured to receive the third data from the basic chip in the reading phase, perform a third error detection and correction processing on the third data, and obtain the first data after the third error detection and correction processing.

[0016] In addition, the controller includes: a first encoding module, which is configured to perform the first error correction code encoding processing on the first data in the writing phase to generate the first encoded data; a third error detection and correction module, which is configured to receive the third data in the reading phase and perform the third error detection and correction processing.

[0017] In addition, the basic chip includes: a first error detection and correction module, which is configured to receive the first data and the first encoded data in the writing phase and perform the first error detection and correction processing; a second encoding module, which is configured to receive the first data after the first error detection and correction processing in the reading phase and perform the second error correction code encoding processing to generate the second encoded data.

[0018] In addition, the basic chip is also configured to, in the write stage, perform a third error correction code encoding process on the first data after the first error detection and correction process to generate third encoded data, and the second data also includes the third encoded data; in the read stage, before performing the second error correction code encoding process, it also includes performing a second error detection and correction process on the second data, and the third data includes the first data after the first error detection and correction process as the first data after the second error detection and correction process; the storage chip includes: a first storage module, the first storage module is used to store the first data after the first error detection and correction process; a second storage module, the second storage module is used to store the third encoded data.

[0019] In addition, the basic chip also includes: a third encoding module, which is configured to receive the first data after the first error detection and correction processing in the writing phase and perform the third error correction code encoding processing to generate the third encoded data; a second error detection and correction module, which is configured to receive the second data in the reading phase and perform the second error detection and correction processing.

[0020] In addition, the first error correction code encoding process, the second error correction code encoding process, the first error detection and correction process, and the third error detection and correction process are performed using a first coding algorithm, the third error correction code encoding process and the second error detection and correction process are performed using a second coding algorithm, and the first coding algorithm is different from the second coding algorithm.

[0021] In addition, the basic chip also includes: a first serial-to-parallel conversion module, which is configured to receive the first data and the first encoded data in the write phase, perform a first serial-to-parallel conversion on the first data and the first encoded data, and transmit the first data and the first encoded data after the first serial-to-parallel conversion to the first error detection and correction module; a first parallel-to-serial conversion module, which is configured to receive the third data from the second encoding module in the read phase, perform a first parallel-to-serial conversion on the third data, and transmit the third data after the first parallel-to-serial conversion to the controller.

[0022] In addition, the basic chip also includes: a second parallel-to-serial conversion module, which is configured to receive the second data and perform a second parallel-to-serial conversion process in the write phase, and transmit the second data after the second parallel-to-serial conversion process to the storage chip; a second serial-to-parallel conversion module, which is configured to receive the second data from the storage chip and perform a second serial-to-parallel conversion process in the read phase, and transmit the second data after the second serial-to-parallel conversion process to the second encoding module.

[0023] In addition, the basic chip is also configured to generate a first error detection flag signal during the first error detection and correction processing, and based on the first error detection flag signal, record the error conditions of the first data and the first encoded data during the transmission process; the storage system also includes: a first register, the first register is configured to store the error conditions of the first data and the first encoded data during the transmission process.

[0024] In addition, the basic chip is also configured to generate a second error detection flag signal during the second error detection and correction processing, and based on the second error detection flag signal, record the error conditions of the first data during the transmission process after the first error detection and correction processing; the storage system also includes: a second register, the second register is configured to store the error conditions of the first data during the transmission process after the first error detection and correction processing.

[0025] In addition, the controller is also configured to generate a third error detection flag signal during the third error detection and correction processing, and based on the third error detection flag signal, record the error conditions of the first data during the transmission process after the second error detection and correction processing; the storage system also includes: a third register, and the third register is configured to store the error conditions of the first data during the transmission process after the second error detection and correction processing.

[0026] According to some embodiments of the present application, another aspect of the present application further provides a semiconductor structure comprising: a carrier substrate; the aforementioned storage system, wherein the controller and the basic chip are both located on a surface of the carrier substrate, and the storage chip is located on a surface of the basic chip away from the carrier substrate. The technical solution provided by the embodiments of the present application has the following advantages:

[0027] In the technical solution of the basic chip provided in the embodiment of the present application, the basic chip performs error detection and correction processing on the first data and the first coded data during the write phase, and transmits the first data after the error detection and correction processing to the storage chip as the second data; and the basic chip receives the second data from the storage chip during the read phase and performs error correction code encoding processing to generate second coded data, and transmits third data, which includes the second coded data and the first data after the error detection and correction processing. Therefore, the basic chip has encoding processing functions and error detection and correction functions, so that the storage chip in the storage system does not need to have encoding processing functions and error detection and correction functions, and the basic chip can share the encoding processing functions and error detection and correction functions required by the controller, thereby helping to improve the performance of the controller and the storage chip, and rationally utilize the chip area of ​​the basic chip, thereby helping to improve the storage performance of the storage system. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0029] Figure 1 is a structural schematic diagram of a semiconductor structure;

[0030] Figure 2 for Figure 1 A schematic diagram of data transmission in a semiconductor structure is provided;

[0031] Figures 3 to 10 A schematic diagram of the structure of the basic chip provided in the embodiment of the present application;

[0032] Figures 11 to 15 A schematic diagram of the structure of the storage system provided in an embodiment of the present application;

[0033] Figure 16 A schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] Figure 1 A schematic diagram of a semiconductor structure. Figure 2 for Figure 1 Schematic diagram of data transmission in semiconductor structures provided.

[0035] refer to Figure 1The semiconductor structure may include: a substrate 11; a base chip 12 and a controller 13 respectively located on the surface of the substrate 11; a plurality of core chips 14 are stacked on the base chip 12, and the core chip 14 may be a DRAM chip. Figure 2 The data transmission process in the semiconductor structure includes: in the write phase, the controller 13 transmits data to the basic chip 12, and the basic chip 12 transmits the data to the core chip 14. The controller 13 can first perform error correction code encoding processing on the data before transmitting the data; in the read phase, the core chip 14 transmits the data to the basic chip 12, and then the basic chip 12 transmits the data to the controller 13. The controller 13 receives the data and performs error correction code decoding processing to detect and correct errors in the data.

[0036] It is not difficult to find that in the above-mentioned semiconductor structure, the basic chip 12 does not participate in the error detection and correction processing, that is, the basic chip 12 has no error correction code encoding function and corresponding error detection and correction function, and the controller 13 or the core chip 14 is required to complete the error detection. This causes the chip area of ​​the controller 13 and the core chip 14, which are already tight, to become even tighter, thereby affecting the performance of the controller 13 and the core chip 14, and further causing the storage performance of the entire semiconductor structure to be improved.

[0037] The present application provides a basic chip, a storage system and a semiconductor structure, wherein the basic chip has error detection and correction functions. Figure 3 This is a schematic diagram of the first structure of the basic chip provided in some embodiments of the present application. Figure 4 A second structural diagram of a basic chip provided in some embodiments of the present application is shown. Figure 5 This is a schematic diagram of the third structure of the basic chip provided in the embodiment of the present application. Figure 6 This is a fourth structural diagram of the basic chip provided in the embodiment of the present application. Figure 7 A fifth structural diagram of the basic chip provided in an embodiment of the present application; Figure 8 A sixth structural diagram of the basic chip provided in an embodiment of the present application; Figure 9 This is a seventh structural diagram of the basic chip provided in an embodiment of the present application.

[0038] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, each embodiment of the present application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in each embodiment of the present application to help readers better understand the present application. However, even without these technical details and various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0039] refer to Figure 3 The basic chip 100 is applied to a storage system, wherein the basic chip 100 is configured to receive first data data1 and first coded data ecc1 and perform a first error detection and correction process in a write phase, where the first coded data ecc1 is obtained by performing a first error correction code (ECC) encoding process on the first data data1, and transmit second data data2 to the storage chip in the write phase, where the second data data2 includes the first data data1 after the first error detection and correction process; the basic chip 100 is also configured to receive second data data2 from the storage chip in a read phase and perform a second error correction code encoding process on the second data data2 to generate second coded data ecc2, and transmit third data data3 in the read phase, where the third data data3 includes the second coded data ecc2 and the first data data1 after the first error detection and correction process.

[0040] In the embodiment of the present application, the basic chip 100 participates in error correction code encoding processing and error detection and correction processing during data transmission.

[0041] In some embodiments, the basic chip 100 can be connected between a first port A and a second port B, wherein the first port A is connected to a data transmission port of a controller of a storage system, and the second port B is connected to a data transmission port of a memory chip of the storage system. It is understood that the first port A and the second port B are collectively referred to, and the first port A includes multiple data transmission ports, and the second port B includes multiple data transmission ports. The number of data transmission ports is related to the amount of data to be transmitted by the basic chip 100. For example, the number of data transmission ports can be the same as the amount of data to be transmitted by the basic chip 100, and one data item can be transmitted via one data transmission port.

[0042] Both the error correction code encoding process and the error detection and correction process are used to implement ECC error detection and correction to detect and locate errors that occur during the first data transmission process and correct the errors. In some embodiments, the ECC error detection and correction may adopt a Reed Solomon Code (RS) error correction mechanism. Accordingly, the error correction code encoding process may adopt an RS encoding algorithm to generate encoded data, and the decoding process in the error detection and correction process may adopt an RS decoding algorithm. In other embodiments, the ECC error detection and correction may adopt a Hamming Code error correction mechanism. Accordingly, the error correction code encoding process may adopt a Hamming Code encoding algorithm to generate encoded data, and the decoding process in the error detection and correction process may adopt a Hamming Code decoding algorithm.

[0043] In some embodiments, the first data data1 may be 256-bit data, and accordingly, the first encoded data ecc1 may be 16-bit data. It is understood that in other embodiments, the number of bits of the first encoded data may also vary depending on the specific algorithm used in the error correction code encoding process. Furthermore, the number of bits of the first data data1 may also be other numbers, such as 128, 512, etc.

[0044] Furthermore, in some embodiments, the basic chip 100 may be further configured to generate a first error detection flag signal during error detection and correction processing, and based on the first error detection flag signal, record errors in the first data data1 and the first coded data ecc1 during transmission. Specifically, if an error occurs in the first data data1 or the first coded data ecc1 during transmission, the first error detection flag signal is generated; if no error occurs in the first data data1 or the first coded data ecc1 during transmission, the first error detection flag signal is not generated. Furthermore, in some embodiments, the first error detection flag signal may be defined as follows: if an error occurs in the first data data1 or the first coded data ecc1 during transmission, the first error detection flag signal is 1; if no error occurs in the first data data1 or the first coded data ecc1 during transmission, the first error detection flag signal is 0. In other embodiments, the first error detection flag signal can also be positioned as: if an error occurs in the first data data1 or the first coded data ecc1 during transmission, the first error detection flag signal is 0; if no error occurs in the first data data1 and the first coded data ecc1 during transmission, the first error detection flag signal is 1.

[0045] like Figure 4 As shown, in some embodiments, the basic chip 100 may further include: a first storage cache module 101, the first storage cache module 101 is configured to store the error conditions of the first data data1 and the first encoded data ecc1 during the transmission process; a first command module 102, the first command module 102 receives the first polling instruction PS1, and generates a first command signal CMD1 and a first clock signal CLK1; the first storage cache module is also configured to output a first characterization signal flag1 based on the first command signal CMD1 and the first clock signal CLK1, the first characterization signal flag1 characterizing the error conditions of the first data data1 and the first encoded data ecc1 during the transmission process.

[0046] It can be understood that the above-mentioned error conditions of the first data data1 and the first coded data ecc1 during the transmission process refer to the error conditions of the first data data1 and the first coded data ecc1 during the transmission process from the controller to the basic chip 100 .

[0047] Furthermore, if the first polling instruction PS1 is not received, the first storage cache module 101 only stores the error status of the first data data1 and the first coded data ecc1 during transmission. Upon receiving the first polling instruction PS1, the first command module 102 controls the first storage cache module 101 to output a first indication signal flag1 indicating the error status of the first data data1 or the first coded data ecc1 during transmission. Based on this first indication signal flag1, the error status of the first data data1 and the first coded data ecc1 can be determined.

[0048] In some embodiments, the first characterization signal flag1 may be a binary number string. For example, if an error is detected in the first data data1 or the first coded data ecc1 during transmission, 1 is recorded; if no error is detected in the first data data1 or the first coded data ecc1 during transmission, 0 is recorded. Thus, after a period of time, the first characterization signal flag1 is a binary number string consisting of 0 and 1. In other embodiments, the first characterization signal flag1 may also be a decimal value. For example, the first storage cache module 101 may be a counter. If an error is detected in the first data data1 during transmission, 1 is added. Thus, after a period of time, the first characterization signal flag1 is a decimal value related to the number of errors.

[0049] In some embodiments, the first storage cache module 101 may be a first-in, first-out (FIFO) register. Using a FIFO register as the first storage cache module 101 allows for caching of continuous data streams, preventing data loss during storage operations. Furthermore, errors in the transmission of the first data data1 are collected and stacked for storage, avoiding frequent bus operations and improving data transmission speed.

[0050] In addition, in some embodiments, the first clock signal CLK1 may be independently generated by the first command module 102; in other embodiments, the first clock signal CLK1 may also be provided externally, such as by a controller that generates the first polling instruction PS1.

[0051] Figure 5 This is a schematic diagram of the third structure of the basic chip provided in the embodiment of this application. Figure 5In some embodiments, the basic chip 100 may include: a first error detection and correction module 110, the first error detection and correction module 110 is configured to receive the first data data1 and the first encoded data ecc1 in the write phase and perform a first error detection and correction process; a second encoding module 120, the second encoding module 120 is configured to receive the first data data1 after the first error detection and correction process in the read phase and perform a second error correction code encoding process to generate the second encoded data ecc2.

[0052] Since the first error detection and correction module 110 and the second encoding module 120 are separate modules, the independence between the encoding and decoding operations is further improved, thereby avoiding data crosstalk. It should be noted that the terms "first," "second," and "third" in the embodiments of the present application are only used for descriptive purposes and do not specifically limit the order in which the corresponding features appear.

[0053] The first error correction code encoding process may employ a Hamming code encoding operation or a Reed-Solomon code encoding operation. Accordingly, the first error detection and correction module 110 may employ a Hamming code decoding operation or a Reed-Solomon code decoding operation. The second encoding module 120 may employ a Hamming code encoding operation or a Reed-Solomon code encoding operation. In some embodiments, the first error detection and correction module 110 may receive first data data1 and first encoded data ecc1 from the controller, perform a first error detection and correction process on the first data data1, and then transmit second data data2 to the memory chip. The second data data2 is the first data data1 after the first error detection and correction process. The second encoding module 120 may receive second data data2 from the memory chip, perform a second error correction code encoding process on the second data data2 to obtain second encoded data ecc2, and transmit the second encoded data ecc2 and the first data data1 after the first error detection and correction process to the controller, so that the controller can continue to perform error detection and correction on the first data data1 after the first error detection and correction process using the second encoded data ecc2.

[0054] Figure 6 This is a schematic diagram of the fourth structure of the basic chip provided in the embodiment of this application. Figure 6In some embodiments, in addition to the first error detection and correction module 110 and the second encoding module 120, the basic chip 100 may also include: a first serial-to-parallel conversion (DES, DESerializer) module 130, the first serial-to-parallel conversion module 130 is configured to receive the first data data1 and the first encoded data ecc1 in the write phase, perform a first serial-to-parallel conversion process on the first data data1 and the first encoded data ecc1, and transmit the first data data1 and the first encoded data ecc1 after the first serial-to-parallel conversion process to the first error detection and correction module 110; a first parallel-to-serial conversion (SER, SERlializer) module 140, the first parallel-to-serial conversion module 140 is configured to receive the third data data3 from the second encoding module 120 in the read phase, perform a first parallel-to-serial conversion process on the third data data3, and transmit the third data data3 after the first parallel-to-serial conversion process to the controller.

[0055] The provision of first serial-to-parallel conversion module 130 and first parallel-to-serial conversion module 140 can reduce the number of transmission channels between basic chip 100 and the controller, increasing the number of bits transmitted by each transmission channel. Furthermore, the reduced number of transmission channels can reduce the number of data transmission ports required on basic chip 100 and the controller, thereby saving the chip area of ​​basic chip 100 and the chip area of ​​the controller. First data data1 is transmitted serially to first serial-to-parallel conversion module 130. First serial-to-parallel conversion module 130, also known as a deserializer, deserializes the serial first data data1 and the first encoded data ecc1. First parallel-to-serial conversion module 140 serially processes third data data3 and transmits the serially processed third data data3. First parallel-to-serial conversion module 140, also known as a serializer, serializes the serially processed third data data3.

[0056] For example, if the first data data1 is 256 bits, the first data data1 is transmitted to the first serial-to-parallel conversion module 130 using 32 transmission channels; if the first encoded data ecc1 is 16 bits, the first encoded data ecc1 is transmitted to the first serial-to-parallel conversion module 130 using 2 transmission channels; after the first data data1 and the first encoded data ecc1 are deserialized by the first serial-to-parallel conversion module 130, the first data data1 is transmitted in parallel to the first error detection and correction module 110 using 256 transmission channels, and the first encoded data ecc1 is transmitted to the first error detection and correction module 110 via 16 transmission channels. The third data is 256bit+16bit, where 256bit is the first data after the first error detection and correction processing, and 16bit is the second encoded data ecc2. The third data datat3 can be converted into 32+2 strings of data after serial processing by the first parallel-to-serial conversion module 140, and the 32+2 strings of data can be transmitted through 32+2 transmission channels accordingly, where 32 strings of data are the first data data1 after the first error detection and correction processing, and 2 strings of data are the second encoded data ecc2.

[0057] Figure 7 This is a fifth structural diagram of the basic chip provided in the embodiment of this application. Figure 7 In some embodiments, in addition to the first error detection and correction module 110, the second encoding module 120, the first serial-to-parallel conversion module 130 and the first parallel-to-serial conversion module 140, the basic chip 100 may also include: a second parallel-to-serial conversion module 150, the second parallel-to-serial conversion module is configured to receive the second data data2 and perform a second parallel-to-serial conversion process in the write phase, and transmit the second data data2 after the second parallel-to-serial conversion process to the memory chip; a second serial-to-parallel conversion module 160, the second serial-to-parallel conversion module 160 is configured to receive the second data data2 from the memory chip and perform a second serial-to-parallel conversion process in the read phase, and transmit the second data data2 after the second serial-to-parallel conversion process to the second encoding module 120.

[0058] The second parallel-to-serial conversion module 150 performs serial processing on the second data data2, which helps reduce the number of transmission channels between the basic chip 100 and the memory chip, thereby reducing the number of data transmission ports required on the basic chip 100 and the memory chip, and further reducing the chip area of ​​the basic chip 100 and the memory chip. For example, the second data data2 may include the 256-bit first data data1 after the first error detection and correction processing. After the parallel-to-serial conversion by the second parallel-to-serial conversion module 150, the second data data2 can be transmitted to the memory chip using 128 transmission channels.

[0059] The second serial-to-parallel conversion module 160 performs parallel processing on the second data data2 transmitted from the memory chip, i.e., performs serial-to-parallel processing on the second data data2, and transmits the processed second data data2 to the second encoding module 120. For example, the second serial-to-parallel conversion module 160 can convert the 128-bit second data data2 into 256-bit parallel data.

[0060] Figure 8 This is a sixth structural diagram of the basic chip provided in the embodiment of the present application. Figure 8 The basic chip 100 can also be configured to, in the write phase, perform a third error correction code encoding process on the first data data1 after the first error detection and correction process to generate third encoded data ecc3, and the second data data2 also includes the third encoded data ecc3; in the read phase, before performing the second error correction code encoding process, it also includes performing a second error detection and correction process on the second data data2, and the third data data3 includes the first data data1 after the first error detection and correction process as the first data data1 after the second error detection and correction process.

[0061] In this way, the second data data2 includes both the first data data1 after the first error detection and correction processing and the third encoded data ecc3. The first error detection and correction processing allows error detection during the transmission of the first data data1 and the first encoded data ecc1 from the controller to the basic chip 100, and can correct any data errors. Furthermore, the second error detection and correction processing allows error detection during the transmission of the second data data2 between the basic chip 100 and the memory chip, and can correct any data errors. It is understood that the transmission of the second data data2 between the basic chip 100 and the memory chip includes the transmission of the second data data2 from the basic chip 100 to the memory chip during a write phase and the transmission of the second data data2 from the memory chip to the basic chip 100 during a read phase. In this way, error detection and correction can be performed on data transmission along at least two transmission paths, facilitating the identification of the specific path where the data transmission error occurred. Furthermore, the at least two error detection and correction processes improve the accuracy of data error correction.

[0062] Furthermore, it is understood that the first error correction code encoding process and the third error correction code encoding process can be performed using different encoding algorithms. For example, the first encoded data ecc1 can be 16-bit data, and the third encoded data ecc3 can be 32-bit data. Accordingly, the first error detection and correction process and the second error detection and correction process can be performed using different decoding algorithms. That is, the first error correction code encoding process and the first error detection and correction process are performed using a first compilation algorithm, and the third error correction code encoding process and the second error detection and correction process are performed using a second compilation algorithm. The first compilation algorithm and the second compilation algorithm can be different. Using different compilation algorithms for ECC error detection can further improve the accuracy of data error correction and reduce the difficulty of the basic chip 100 in identifying different encoded data. In other embodiments, the first compilation algorithm and the second compilation algorithm can also be the same.

[0063] refer to Figure 8 In addition to the first error detection and correction module 110 and the second encoding module 120, the basic chip 100 may also include: a third encoding module 111, which is configured to receive the first data data1 after the first error detection and correction processing and perform third error correction code encoding processing in the writing phase to generate third encoded data ecc3. Correspondingly, the second data data2 includes the first data data1 after the first error detection and correction processing and the third encoded data ecc3; a second error detection and correction module 121, which is configured to receive the second data data2 and perform second error detection and correction processing in the reading phase.

[0064] The third encoding module 111 is connected between the first error detection and correction module 110 and the memory chip, and the second error detection and correction module 121 is connected between the memory chip and the second encoding module 120. The second error detection and correction module 121 receives the third coded data ecc3 and the first data data1 after the first error detection and correction processing, and performs a second error detection and correction processing on the third coded data ecc3 and the first data data1 after the first error detection and correction processing.

[0065] The provision of the second error detection and correction module 121 is conducive to detecting whether data is erroneous during the process of transmitting from the storage chip to the basic chip 100 during the reading phase, and correcting the erroneous data, which is conducive to further improving the data error detection and correction capabilities.

[0066] Figure 9 The seventh structural diagram of the basic chip provided in the embodiment of the present application is shown in FIG. Figure 9 In some embodiments, the first error detection and correction module 110 may also generate a first error detection flag signal during the first error detection and correction process, and further reference is made to Figures 4 to 7 and Figure 9In some embodiments, the basic chip 100 may further include: a first storage cache module 101, the first storage cache module 101 is configured to store the error condition of the first data data1 during the transmission process; a first command module 102, the first command module 102 receives the first polling instruction PS1, and generates a first command signal CMD1 and a clock signal CLK1; the first storage cache module 101 is also configured to output a first characterization signal flag1 based on the first command signal CMD1 and the first clock signal CLK1, the first characterization signal flag1 characterizing the error condition of the first data data1 or the first encoded data ecc1 during the transmission process.

[0067] For detailed descriptions of the first storage cache module 101 and the first command module 102 , please refer to the corresponding descriptions of the aforementioned embodiments, which will not be repeated here. Specifically, the first storage cache module 101 is connected to the first error detection and correction module 110 .

[0068] Figure 10 The eighth structural diagram of the basic chip provided in the embodiment of the present application is shown in FIG. Figure 10 In some embodiments, the basic chip 100 may further include: a first serial-to-parallel conversion module 130 and a first parallel-to-serial conversion module 140. For detailed descriptions of the first serial-to-parallel conversion module 130 and the first parallel-to-serial conversion module 140, please refer to the above description and will not be repeated here. Figure 9 In some embodiments, the basic chip 100 may further include: a second parallel-to-serial conversion module 150 and a second serial-to-parallel conversion module 160; wherein the second parallel-to-serial conversion module 150 is connected between the third encoding module 111 and the memory chip, and in addition to performing parallel-to-serial processing on the first data data1 after the first error detection basic processing, the second parallel-to-serial conversion module 150 also performs parallel-to-serial processing on the third encoded data ecc3; the second serial-to-parallel conversion module 160 is connected between the memory chip and the second error detection and correction module 121, and the second serial-to-parallel conversion module 160 performs serial-to-parallel processing on the third encoded data ecc3 transmitted from the memory chip and the first data data1 after the first error detection and correction processing.

[0069] For descriptions of the first serial-to-parallel conversion module 130, the first parallel-to-serial conversion module 140, the second serial-to-parallel conversion module 160, and the second parallel-to-serial conversion module 150, please refer to the aforementioned detailed description and will not be repeated here. It will be appreciated that in some embodiments, the basic chip 100 includes the first serial-to-parallel conversion module 130 and the first parallel-to-serial conversion module 140; in other embodiments, the basic chip 100 includes the first serial-to-parallel conversion module 130, the first parallel-to-serial conversion module 140, the second parallel-to-serial conversion module 150, and the second serial-to-parallel conversion module 160.

[0070] In some embodiments, the basic chip 100 may be further configured to generate a second error detection flag signal during the second error detection and correction process, and based on the second error detection flag signal, record errors during the transmission of the third encoded data ecc1 and the first data data1 after the first error detection and correction process, i.e., record errors during the transmission of the second data data2. Specifically, the transmission path involved in the transmission of the second data data2 includes transmission from the third encoding module 111 to the storage chip during the write phase and transmission from the storage chip to the second error detection and correction module 121 during the read phase.

[0071] Based on the second error detection flag signal, it is convenient to check the error conditions of the third coded data ecc1 and the first data data1 after the first error detection and correction processing during the transmission process.

[0072] refer to Figure 9 and Figure 10 In some embodiments, the basic chip 100 may further include: a second storage cache module 131, the second storage cache module 131 is configured to store the third encoded data ecc3 and the error conditions of the first data data1 after the first error detection and correction processing during the transmission process; a second command module 132, the second command module 132 receives the second polling instruction PS2, and generates a second command signal CMD2 and a second clock signal CLK2; the second storage cache module 131 is also configured to output a second characterization signal flag2 based on the second command signal CMD2 and the second clock signal CLK2, the second characterization signal flag2 characterizing the error conditions of the third encoded data ecc3 and the first data data1 after the first error detection and correction processing during the transmission process.

[0073] Specifically, the second storage cache module 131 is connected to the second error detection and correction module 121 .

[0074] For detailed description of the second storage cache module, please refer to the aforementioned description of the first storage buffer module. For detailed description of the second command module, please refer to the aforementioned description of the first command module, which will not be repeated here.

[0075] The basic chip 100 provided in the above embodiment not only has the function of data transmission, but also has the functions of error correction code encoding processing and error detection and correction processing. In this way, the chip area of ​​the basic chip 100 can be effectively utilized, reducing the chip area pressure of the controller and memory chip, and saving the chip area of ​​the controller and memory chip.

[0076] In addition, the basic chip 100 can also have the functions of data serial processing and deserialization processing, which is beneficial to reducing the transmission channels between the controller and the basic chip 100, and reducing the transmission channels between the memory chip and the basic chip 100, thereby saving the number of data transmission ports required on the controller, the basic chip 100 and the memory chip, and further saving the chip area of ​​the controller, the basic chip 100 and the memory chip.

[0077] In addition, both the first error detection and correction module 110 and the second error detection and correction module 121 can perform error detection and correction on data, which is beneficial to improving the data error detection and correction capability and can locate the transmission path of the data error.

[0078] Another embodiment of the present application further provides a storage system, which includes a controller, a storage chip, and the basic chip provided in the aforementioned embodiment. The storage system provided in another embodiment of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that for parts that are identical or corresponding to the aforementioned embodiment, reference can be made to the detailed description of the aforementioned embodiment and will not be repeated below.

[0079] Figure 11 A first structural diagram of the storage system provided in an embodiment of the present application.

[0080] refer to Figure 11The storage system includes: a basic chip 200, a controller 300 and a storage chip 400; the controller 300 is configured to perform a first error correction code encoding process on the first data data1 in the write phase to generate the first encoded data ecc1, and transmit the first data data1 and the first encoded data ecc1 to the basic chip 200; the basic chip 200 is configured to receive the first data data1 and the first encoded data ecc1 in the write phase and perform a first error detection and correction process, and transmit the second data data2 to the storage chip 400 in the write phase, the second data data2 including the first data data1 after the first error detection and correction process; the basic chip 200 is also configured to receive the second data data1 from the storage chip 400 in the read phase. data2 and performs a second error correction code encoding process to generate second encoded data ecc2, and transmits third data data3 to the controller 300 in the reading phase, the third data data3 including the second encoded data ecc2 and the first data data1 after the first error detection and correction process; the memory chip 400 is configured to receive the second data data2 from the basic chip 200 and store the second data data2 in the writing phase, and transmit the second data data2 to the basic chip 200 in the reading phase; the controller 300 is also configured to receive the third data data3 from the memory chip 200 in the reading phase, perform a third error detection and correction process on the third data data3, and obtain the first data data1 after the third error detection and correction process.

[0081] In the above-mentioned storage system, the error correction code encoding processing and error detection and correction processing of the data are all implemented by the basic chip 200. Therefore, the storage chip 400 does not need to perform encoding processing and error detection and correction processing, and the basic chip 200 can share the encoding processing and error detection and correction processing required by the controller 300, thereby reducing the functions required by the controller 300 and the storage chip 400. Therefore, the pressure of the chip area of ​​the controller 300 and the storage chip 400 can be alleviated, so as to better improve the performance of the controller 300 and the storage chip 400, for example, the reliability of the storage chip 400 can be improved, thereby improving the storage performance of the storage system.

[0082] In some embodiments, the storage system may be a DRAM storage system, such as a DDR (double data rate) 4 DRAM storage system or a DDR5 DRAM storage system. In other embodiments, the storage system may be an SRAM (Static Random-Access Memory) storage system, a NAND storage system, a NOR storage system, a FeRAM storage system, or a PCRAM storage system.

[0083] The controller 300 may include: a first encoding module 301, the first encoding module 301 is configured to perform a first error correction code encoding process on the first data data1 in the write phase to generate the first encoded data ecc1; a third error detection and correction module 302, the third error detection and correction module 302 is configured to receive the third data data3 in the read phase and perform a third error detection and correction process.

[0084] The foundation chip 200 provides a high-speed interface for data transmission in the storage system. Furthermore, the foundation chip 200 is used to manage and control the storage chip 400. In some embodiments, the foundation chip 200 can be used to monitor and manage the temperature of the storage chip 400, as well as perform memory built-in self-test (MBIST) and self-repair on the storage chip 400. Furthermore, the foundation chip 200 is used to perform error detection and correction on transmitted data.

[0085] Figure 12 This is a second structural diagram of the storage system provided in the embodiment of the present application. Figure 12 In some embodiments, the basic chip 200 may include: a first error detection and correction module 210, the first error detection and correction module 210 is configured to receive the first data data1 and the first encoded data ecc1 in the write phase and perform a first error detection and correction process; a second encoding module 220, the second encoding module 220 is configured to receive the first data data1 after the first error detection and correction process in the read phase and perform a second error correction code encoding process to generate the second encoded data ecc2.

[0086] Specifically, the first error detection and correction module 210 is connected between the data transmission port of the controller 300 and the data transmission port of the memory chip 400, and the second encoding module 220 is connected between the data transmission port of the controller 300 and the data transmission port of the memory chip 400. Because the second data data2 does not include encoded data, the memory chip 400 can include a storage module for storing the first data after the first error detection and correction processing. This eliminates the need for an encoding module for storing encoded data, thereby saving area of ​​the memory chip 400 and reducing the design difficulty of the memory chip 400.

[0087] The following takes the first data data1 as 256 bits and the first coded data ecc1 as 16 bits as an example. Figure 12 The working principle of the storage system shown is explained as follows:

[0088] During the write phase, the controller 300 transmits 256 bits of first data data1 and 16 bits of first encoded data ecc1 to the first error detection and correction module 210. The first error detection and correction module 210 receives the 256 bits of first data data1 and the 16 bits of first encoded data ecc1, performs a first error detection and correction process, and outputs the 256 bits of first data data1 after the first error detection and correction process. The 256 bits of first data data1 after the first error detection and correction process constitute the second data data2. Specifically, if the 256 bits of first data data1 do not contain errors, the 256 bits of first data data1 are transmitted to the memory chip 400. If the 256 bits of first data data1 contain errors, error correction is performed on the bits where the errors occur, and the 256 bits of first data data1 after the error correction process are transmitted to the memory chip 400.

[0089] During the reading phase, the memory chip 400 transmits the second data data2 to the second encoding module 220 . The second encoding module 220 performs a second error correction code encoding process to generate 16-bit second encoded data ecc2 , and transmits the 256-bit first data data1 and the 16-bit second encoded data ecc2 to the controller 300 .

[0090] In the above solution, the memory chip 400 does not need to be designed with a memory module for storing encoded data, which helps save the chip area of ​​the memory chip 400. In addition, both the basic chip 200 and the controller 300 have error detection and correction processing functions, and the dual error detection and correction processing helps improve data error detection and correction capabilities.

[0091] Figure 13 This is a schematic diagram of the third structure of the storage system provided in the embodiment of the present application. Figure 13 In some embodiments, in addition to including the first error detection and correction module 210 and the second encoding module 220, the basic chip 200 is also configured to, in the writing phase, perform a third error correction code encoding process on the first data data1 after the first error detection and correction process to generate third encoded data ecc3, and the second data data2 also includes the third encoded data ecc3; in the reading phase, before performing the second error correction code encoding process, it also includes performing a second error detection and correction process on the second data data2, and the third data data3 includes the first data data1 after the first error detection and correction process as the first data data1 after the second error detection and correction process.

[0092] Thus, the second data data2 includes not only the first data after the first error detection and correction processing but also the third coded data ecc3. Figure 13 The memory chip 400 includes: a first memory module 410, the first memory module 410 is used to store the first data data1 after the first error detection and correction processing; a second memory module 420, the second memory module 420 is used to store the third coded data ecc3.

[0093] Accordingly, reference Figure 13 The basic chip 200 may further include: a third encoding module 211, which is configured to receive the first data data1 after the first error detection and correction processing in the writing phase and perform a third error correction code encoding process to generate third encoded data ecc3; a second error detection and correction module 221, which is configured to receive the second data data2 in the reading phase and perform a second error detection and correction process.

[0094] In some embodiments, the first error correction code encoding process, the second error correction code encoding process, the first error detection and correction process, and the third error detection and correction process are performed using a first compilation algorithm, while the third error correction code encoding process and the second error detection and correction process are performed using a second compilation algorithm, and the first compilation algorithm and the second compilation algorithm are different. Using different compilation algorithms to perform error detection and correction on data is beneficial to further improve the accuracy of data error detection and correction. Specifically, the encoding algorithm used by the third encoding module 211 and the first encoding module 301 can be different, the encoding algorithm used by the third encoding module 211 and the second encoding module 220 can be different, and the decoding algorithm used by the first error detection and correction module 210 and the second error detection and correction module 221 can be different.

[0095] Figure 14 and Figure 15 This is a fourth structural diagram of the storage system provided in the embodiment of the present application. Figure 14 and Figure 15 In some embodiments, the basic chip 200 may further include: a first serial-to-parallel conversion module 230, the first serial-to-parallel conversion module 230 being configured to receive the first data data1 and the first encoded data ecc1 in a write phase and perform a first serial-to-parallel conversion process on the first data data1 and the first encoded data ecc1, and transmit the first data data1 and the first encoded data ecc1 after the first serial-to-parallel conversion process to the first error detection and correction module 210; a first parallel-to-serial conversion module 240, the first parallel-to-serial conversion module 240 being configured to receive the third data data3 from the second encoding module 220 in a read phase and perform a first parallel-to-serial conversion process on the third data data3, and transmit the third data data3 after the first parallel-to-serial conversion process to the controller 300.

[0096] Specifically, the first serial-to-parallel conversion module 230 is connected between the data transmission port of the controller 300 and the data transmission port of the first error detection and correction module 210, and the first parallel-to-serial conversion module 240 is connected between the data transmission port of the controller 300 and the data transmission port of the first error detection and correction module 210. In this way, the number of transmission channels between the controller 300 and the basic chip 200 can be less than the number of bits of the first data data1, thereby saving the number of transmission channels between the controller 300 and the basic chip 200, and saving the number of data transmission ports required to be set on the basic chip 200 and the controller 300, which is beneficial to reducing the complexity of the electrical connection structure between the controller 300 and the basic chip 200, and saving the chip area of ​​the controller 300 and the basic chip 200. The following will take the first data data1 as 256 bits and the first coded data as 16 bits as an example. Figure 14 The working principle of the storage system shown in FIG. 2 is described below. It should be noted that the first error detection and correction module 210 and the second encoding module 220 will not be described in detail below.

[0097] During the write phase, there may be 32+2 transmission channels between the controller 300 and the first error detection and correction module 210. The 256-bit first data data1 is transmitted to the first serial-to-parallel conversion module 230 via 32 transmission channels for serial-to-parallel processing, and the 16-bit first encoded data ecc1 is transmitted to the first serial-to-parallel conversion module 230 via 2 transmission channels for serial-to-parallel processing. The first serial-to-parallel conversion module 230 outputs the 256-bit first data data1 and the 16-bit first encoded data ecc1 transmitted in parallel. The first data data1 and the first encoded data ecc1 are transmitted to the first error detection and correction module 210 for the first error detection and correction processing and then continue to be transmitted to the memory chip 400. During the reading stage, the 256-bit first data and the 16-bit second encoded data ecc2 output by the second encoding module 220 are transmitted to the first parallel-to-serial conversion module 240 for parallel-to-serial processing. The 256-bit first data data1 after parallel-to-serial processing can be transmitted to the controller 300 via 32 transmission channels, and the 16-bit second encoded data ecc2 after parallel-to-serial processing can be transmitted to the controller 300 via 2 transmission channels.

[0098] It is understandable that, in other embodiments, the number of transmission channels between the controller 300 and the first error detection and correction module 210 may also be other appropriate numbers, such as 128, 64, or 16.

[0099] refer to Figure 14 and Figure 15The basic chip 200 may further include: a second parallel-to-serial conversion module 250, which is configured to receive the second data data2 and perform a second parallel-to-serial conversion process in the write phase, and transmit the second data data2 after the second parallel-to-serial conversion process to the memory chip 400; a second serial-to-parallel conversion module 260, which is configured to receive the second data data2 from the memory chip 400 and perform a second serial-to-parallel conversion process in the read phase, and transmit the second data after the second serial-to-parallel conversion process to the second encoding module 220.

[0100] refer to Figure 14 In some examples, the second parallel-to-serial conversion module 250 is connected between the data transmission port of the first error detection and correction module 210 and the data transmission port of the memory chip 400, and the second serial-to-parallel conversion module 260 is connected between the data transmission port of the memory chip 400 and the data transmission port of the second encoding module 220. Figure 15 In other examples, the second parallel-to-serial conversion module 250 is connected between the data transmission port of the memory chip 400 and the data transmission port of the third encoding module 211, and the second serial-to-parallel conversion module 260 is connected between the data transmission port of the memory chip 400 and the data transmission port of the second error detection and correction module 221.

[0101] In this way, the number of transmission channels between the memory chip 400 and the basic chip 200 can be less than the number of bits of the first data data1, thereby saving the number of transmission channels between the memory chip 400 and the basic chip 200, which is beneficial to reducing the number of data transmission ports required to be set on the basic chip 200 and the memory chip 400, and is beneficial to reducing the complexity of the electrical connection structure between the memory chip 400 and the basic chip 200, saving the chip area of ​​the memory chip 400 and the basic chip 200.

[0102] It is understood that the number of data transmission channels between the controller 300 and the basic chip 200 is M, and the number of data transmission channels between the basic chip 200 and the memory chip 400 is N; wherein M and N are both positive integers greater than 1. In some embodiments, the second data includes the first data after the first error detection and correction processing. Taking the first data as 256 bits and the first coded data as 16 bits as an example, M can be 32+2, where 32 data transmission channels are used to transmit the first data and 2 data transmission channels are used to transmit the first coded data; the first data after the first error detection and correction processing is 256 bits, N can be 32, 64, or 128, and the N data transmission channels are used to transmit the first data after the first error detection and correction processing.

[0103] In other embodiments, the second data includes not only the first data after the first error detection and correction processing but also third coded data. Taking the first data as 256 bits, the first coded data as 16 bits, and the third coded data as 32 bits as an example, M can be 32+2, N can be 128+16, 32 data transmission channels in M ​​are used to transmit the first data, 2 data transmission channels in M ​​are used to transmit the first coded data, 128 data transmission channels in N are used to transmit the first data after the first error detection and correction, and 6 data transmission channels in N are used to transmit the third data.

[0104] refer to Figures 12 to 15 In some embodiments, the basic chip 200 may also be configured to generate a first error detection flag signal during the first error detection and correction process, and based on the first error detection flag signal, record the error conditions of the first data data1 and the first encoded data ecc1 during the transmission process; the storage system may also include: a first register 501, the first register 501 is configured to store the error conditions of the first data data1 and the first encoded data ecc1 during the transmission process.

[0105] Specifically, refer to Figures 12 to 15 The basic chip 200 may include: a first storage cache module 201, the first storage cache module 201 is configured to store the error conditions of the first data data1 and the first encoded data ecc1 during the transmission process; a first command module 202, the first command module 202 receives the first polling instruction PS1, and generates a first command signal CMD1 and a first clock signal CLK1; the first storage cache module 201 is also configured to output a first characterization signal flag1 to the first register 500 based on the first command signal CMD1 and the first clock signal CLK1, the first characterization signal flag1 characterizing the error conditions of the first data data1 and the first encoded data ecc1 during the transmission process.

[0106] In some embodiments, the controller 300 may be further configured to issue a first polling instruction PS1 to the first command module 202, that is, the controller 300 periodically issues inquiries to control the first storage cache module 201 to output the first characterization signal flag1 to the first register 501. It will be appreciated that in other embodiments, the first polling instruction may also be provided by an external circuit.

[0107] refer to Figure 13 and Figure 15In some embodiments, the basic chip 200 may also be configured to generate a second error detection flag signal during the second error detection and correction process, and based on the second error detection flag signal flag2, record the error condition of the first data data1 during the transmission process after the first error detection and correction process; the storage system may also include: a second register 502, the second register 502 is configured to store the error condition of the first data data1 during the transmission process after the first error detection and correction process.

[0108] refer to Figure 13 and Figure 15 In some embodiments, the basic chip 200 may further include: a second storage cache module 251, the second storage cache module 251 is configured to store the error condition of the first data data1 after the first error detection and correction processing during the transmission process; a second command module 261, the second command module 261 receives the second polling instruction PS2, and generates a second command signal CMD2 and a second clock signal CLK2; the second storage cache module 251 is also configured to output a second characterization signal flag2 to the second register 502 based on the second command signal CMD2 and the second clock signal CLK2, the second characterization signal flag2 characterizing the error condition of the first data data1 after the first error detection and correction processing during the transmission process.

[0109] refer to Figure 13 and Figure 15 In some embodiments, the controller 300 may further be configured to generate a third error detection flag signal during the third error detection and correction process, and based on the third error detection flag signal, record the error condition of the first data data1 during the transmission process after the second error detection and correction process; the storage system may further include: a third register 503, and the third register 503 is configured to store the error condition of the first data data1 during the transmission process after the second error detection and correction process.

[0110] refer to Figure 13 and Figure 15 In some embodiments, the controller 300 may further include: a third storage cache module 271, the third storage cache module 271 is configured to store the error situation of the first data after the second error detection and correction processing during the transmission process; a third command module 281, the third command module 281 receives the third polling instruction PS3, and generates a third command signal CMD3 and a third clock signal CLK3; the third storage cache module 271 is also configured to output a third characterization signal flag3 to the third register 503 based on the third command signal CMD3 and the third clock signal CLK3, the third characterization signal flag3 represents the error situation of the first data data1 after the second error detection and correction processing during the transmission process.

[0111] It can be understood that the first register 501 , the second register 502 and the third register 503 can be the same register.

[0112] In the storage system provided by the above embodiment, the basic chip 200 can realize the error detection and correction functions. Accordingly, the storage chip 400 does not need to have the error detection and correction functions, and the basic chip 200 can share the error detection and correction functions originally undertaken by the controller 300. Therefore, it is beneficial to save the space area of ​​the controller 300 and the storage chip 400, so that the storage performance of the storage chip 400 is improved, thereby improving the storage performance of the storage system.

[0113] In addition, the configuration of the first error detection and correction module 210, the second error detection and correction module 221 and the third error detection and correction module 302 enables error detection and correction on different data transmission paths, thereby improving the error detection and correction capability of the storage system and facilitating the location of the specific data transmission path where the error occurs.

[0114] Accordingly, embodiments of the present application further provide a semiconductor structure that may include the storage system provided in the aforementioned embodiments. The semiconductor structure provided in the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that for portions that are identical or corresponding to the aforementioned embodiments, reference can be made to the detailed description of the aforementioned embodiments and will not be repeated below.

[0115] Figure 16 A schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention.

[0116] refer to Figure 16 The semiconductor structure includes: a carrier substrate 600; the storage system provided by the aforementioned embodiment, and the controller 300 and the basic chip 200 are both located on the surface of the carrier substrate 600, and the storage chip 400 is located on the surface of the basic chip 200 away from the carrier substrate 600.

[0117] The semiconductor structure may include a plurality of memory chips 400 stacked in sequence. The semiconductor structure may be a memory device such as a DRAM device or an SRAM device.

[0118] In some embodiments, the carrier substrate 600 may be a PCB (Printed Circuit Board). Detailed descriptions of the storage system can be found in the aforementioned embodiments and will not be repeated here.

[0119] The semiconductor structure can be a 2.5D (dimensions) device, that is, the semiconductor structure is a stacked structure, which is beneficial to saving horizontal size, and utilizing the basic chip 200 in the semiconductor structure to realize ECC error detection and correction function, which is beneficial to improving the performance of the semiconductor structure.

[0120] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present application, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present application. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined in the claims.

Claims

1. A storage system, characterized in that: Including basic chips and memory chips, as well as: The basic chip is configured to receive first data and first coded data and perform first error detection and correction processing during a write phase, wherein the first coded data is obtained by performing a first error correction code encoding process on the first data, and transmit second data to the storage chip during the write phase, wherein the second data includes the first data after the first error detection and correction processing; The basic chip is further configured to, during a read phase, receive the second data from the memory chip and perform a second error correction code encoding process on the second data to generate second encoded data, and transmit third data during the read phase, the third data including the second encoded data and the first data after the first error detection and correction process; The memory chip is configured to receive the second data from the basic chip and store the second data during the write phase, and transmit the second data to the basic chip during the read phase; The basic chip includes: a first error detection and correction module, wherein the first error detection and correction module is configured to receive the first data and the first coded data and perform the first error detection and correction process during the writing phase; The second encoding module is configured to receive the first data after the first error detection and correction processing in the reading phase and perform the second error correction code encoding processing to generate the second encoded data.

2. The storage system according to claim 1, wherein: The basic chip is further configured to, in the write phase, perform a third error correction code encoding process on the first data after the first error detection and correction process to generate third encoded data, and the second data also includes the third encoded data; in the read phase, before performing the second error correction code encoding process, further include performing a second error detection and correction process on the second data, and the third data includes the first data after the first error detection and correction process as the first data after the second error detection and correction process; the memory chip includes: a first storage module, the first storage module being configured to store the first data after the first error detection and correction processing; A second storage module, wherein the second storage module is used to store the third encoded data.

3. The storage system according to claim 2, wherein: The basic chip also includes: a third encoding module, wherein the third encoding module is configured to receive the first data after the first error detection and correction processing in the write phase and perform the third error correction code encoding processing to generate the third encoded data; a second error detection and correction module, wherein the second error detection and correction module is configured to receive the second data in the read phase and perform the second error detection and correction processing.

4. The storage system according to claim 2, wherein: The first error correction code encoding process, the second error correction code encoding process, and the first error detection and correction process are performed using a first coding algorithm, the third error correction code encoding process and the second error detection and correction process are performed using a second coding algorithm, and the first coding algorithm is different from the second coding algorithm.

5. The storage system according to claim 1, wherein: The basic chip also includes: a first serial-to-parallel conversion module, the first serial-to-parallel conversion module being configured to receive the first data and the first coded data in a writing phase, perform a first serial-to-parallel conversion on the first data and the first coded data, and transmit the first data and the first coded data after the first serial-to-parallel conversion to the first error detection and correction module; The first parallel-to-serial conversion module is configured to receive the third data from the second encoding module in a reading phase, perform a first parallel-to-serial conversion on the third data, and output the third data after the first parallel-to-serial conversion.

6. The storage system according to claim 5, wherein: The basic chip also includes: a second parallel-to-serial conversion module, the second parallel-to-serial conversion module being configured to receive the second data and perform a second parallel-to-serial conversion process during a write phase, and transmit the second data after the second parallel-to-serial conversion process to the memory chip; The second serial-to-parallel conversion module is configured to receive the second data from the storage chip and perform a second serial-to-parallel conversion process during the reading phase, and transmit the second data after the second serial-to-parallel conversion process to the second encoding module.

7. The storage system according to claim 1, wherein: The basic chip is further configured to generate a first error detection flag signal during the first error detection and correction process, and based on the first error detection flag signal, record errors in the first data and the first coded data during transmission; The storage system further includes: The first register is configured to store error conditions of the first data and the first coded data during transmission.

8. The storage system according to claim 7, wherein: The basic chip also includes: a first storage cache module, wherein the first storage cache module is configured to store errors in the transmission process of the first data and the first coded data; a first command module, which receives a first polling instruction and generates a first command signal and a first clock signal; The first storage cache module is further configured to output a first characterization signal based on the first command signal and the first clock signal, where the first characterization signal characterizes an error condition of the first data and the first encoded data during transmission.

9. The storage system according to claim 2, wherein: The basic chip is further configured to generate a second error detection flag signal during the second error detection and correction process, and based on the second error detection flag signal, record errors in the transmission of the third coded data and the first data after the first error detection and correction process; The storage system further includes: The second register is configured to store the third coded data and an error condition of the first data after the first error detection and correction processing during transmission.

10. The storage system according to claim 9, wherein: The basic chip also includes: a second storage cache module, the second storage cache module being configured to store the third coded data and an error condition of the first data after the first error detection and correction processing during transmission; a second command module, which receives a second polling instruction and generates a second command signal and a second clock signal; The second storage cache module is further configured to output a second characterization signal based on the second command signal and the second clock signal, wherein the second characterization signal characterizes the error conditions of the third encoded data and the first data after the first error detection and correction processing during transmission.

11. A semiconductor structure, characterized in that include: a carrier substrate; The storage system according to any one of claims 1 to 10, wherein the basic chips are all located on the surface of the carrier substrate, and the storage chip is located on the surface of the basic chip away from the carrier substrate.

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