A high-voltage SiC power device and its manufacturing method

Abstract

This invention relates to a high-voltage SiC power device and its manufacturing method in the field of semiconductor technology. The device includes a surface electrode, a termination region, and a passivation structure disposed on the termination region. The passivation structure is in contact with the surface electrode and extends from the surface of the termination region to the exposed surface area between the surface electrode and the scribe line. The passivation structure is non-planar, and the creepage path of the passivation structure is greater than the distance between the surface electrode and the scribe line. This invention solves the problem that the passivation layer of the existing termination structure is limited by a two-dimensional plane, making it difficult to improve the partial discharge initiation voltage and long-term reliability without increasing the chip size.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a high-voltage SiC power device and its manufacturing method. Background Art

[0002] High-voltage SiC power devices are widely used in power grids, new energy, and transportation traction due to their high breakdown field strength, high temperature stability, and high switching frequency characteristics. In recent years, through optimized terminal design (such as multi-zone JTE, FLR, etc.), the terminal length of 10kV-level devices has been compressed to approximately 350μm–500μm, meeting the requirements for compact chip area.

[0003] However, outside of the terminal structure, the creepage distance between the scribe line and the ground metal electrode (such as the source) still determines the surface insulation capability of the device. Traditional passivation layers use a planar passivation structure, and their creepage path is basically equal to the geometric spacing, making it difficult to improve PDIV (partial discharge initiation voltage) and long-term reliability without increasing chip size.

[0004] On the other hand, existing technologies use a planar plane. Passivation layer design relies on single-layer, double-layer or multi-layer dielectric passivation to suppress surface electric field. However, its passivation layer is a two-dimensional planar structure, and the surface electric field lines propagate along the shortest path. The creepage distance is basically equal to the geometric spacing, which cannot break through the geometric limitation. In the 10kV and above level, partial discharge is prone to occur in the terminal area, especially in humid, high temperature or polluted environments. Summary of the Invention

[0005] This invention addresses the shortcomings of existing technologies by providing a high-voltage SiC power device and its manufacturing method, solving the problem that the passivation layer of existing terminal structures is limited by a two-dimensional plane, making it difficult to improve the partial discharge initiation voltage and long-term reliability without increasing the chip size.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] A high-voltage SiC power device includes a surface electrode, a terminal region, and a passivation structure disposed on the terminal region. The passivation structure is in contact with the surface electrode and extends from the surface of the terminal region to the exposed surface area between the surface electrode and the scribe line. The passivation structure is non-planar and the creepage path of the passivation structure is greater than the distance between the surface electrode and the scribe line.

[0008] Optionally, the depth direction of the passivation structure is a first direction, the direction of the surface electrode toward the scribe line is a second direction, the length direction of the passivation structure is a third direction, and the first direction, the second direction, and the third direction are perpendicular to each other. The passivation structure is arranged in a concave-convex structure in the second direction and / or the third direction.

[0009] Optionally, the passivation structure includes a first passivation layer, which is disposed on the terminal region and is arranged in a concave-convex structure in a first direction and / or a third direction.

[0010] Optionally, the passivation structure further includes a second passivation layer, which is disposed on the terminal region. The second passivation layer is in contact with the lower surface of the first passivation layer, and the second passivation layer is planar. The second passivation layer and the first passivation layer are made of different passivation materials.

[0011] Optionally, the passivation structure further includes a second passivation layer, which is disposed on the terminal region. The second passivation layer is in contact with the lower surface of the first passivation layer, and the second passivation layer is arranged in a concave-convex structure in a first direction and / or a third direction. The second passivation layer and the first passivation layer are made of different passivation materials.

[0012] Optionally, the passivation structure further includes a third passivation layer, which is disposed on the terminal region. The third passivation layer is in contact with the lower surface of the second passivation layer, and the third passivation layer is planar. The third passivation layer and the second passivation layer are made of different passivation materials.

[0013] Optionally, the passivation structure further includes a third passivation layer, which is disposed on the terminal region. The third passivation layer is in contact with the lower surface of the second passivation layer, and the third passivation layer is arranged in a concave-convex structure in a first direction and / or a third direction. The third passivation layer and the second passivation layer are different passivation materials.

[0014] Optionally, the material of the passivation structure includes any one of inorganic dielectric materials, organic polymer passivation materials, or dielectric passivation materials with a dielectric constant greater than 4.0.

[0015] Optionally, the passivation structure is arranged in a periodic pattern in the second direction and / or the third direction, and the length of each group of periodically arranged concave and convex structures is set to 1 μm ~ 50 μm.

[0016] Optionally, the height of the protrusion in the concave-convex structure is set to 100nm ~ 20μm.

[0017] Optionally, the length of the passivation structure in the second direction is 100 μm to 1000 μm.

[0018] Optionally, the shape of the concave-convex structure includes rectangular steps, wavy shapes, and sawtooth shapes.

[0019] Optionally, it also includes a back electrode, a substrate layer, a buffer layer, an epitaxial layer, a termination structure, and an active region structure. The buffer layer is disposed on the upper surface of the substrate layer, the back electrode is disposed on the lower surface of the substrate layer, the epitaxial layer is disposed on the buffer layer, the termination structure and the active region structure are both embedded in the epitaxial layer, and the sidewall of the termination structure is in contact with the sidewall of the active region structure. The active region structure is also in contact with the surface electrode, and the termination structure is in contact with the passivation structure.

[0020] A method for manufacturing a high-voltage SiC power device, the method comprising the following steps:

[0021] Obtain a substrate layer, and grow a buffer layer and an epitaxial layer on the substrate layer;

[0022] An active region structure is formed on the epitaxial layer, and a terminal structure is formed on the outside of the active region structure;

[0023] A back electrode is deposited and patterned on the lower surface of the substrate, and a surface electrode is deposited and patterned on the active region structure.

[0024] A passivation structure is deposited in the terminal region and its external region, and a three-dimensional concave-convex structure is introduced in the passivation structure by photolithography etching.

[0025] Compared with the prior art, the technical solution provided by this invention has the following advantages:

[0026] By introducing multiple angular variations at the interface through concave-convex structures, the stability of the electric field concentration point is weakened, and the initiation threshold of partial discharge is increased. On the other hand, by introducing periodic or non-periodic concave-convex geometries (such as steps, ripples, grooves, etc.) on the terminal region, this application significantly extends the surface creepage path between the scribe line and the ground metal electrode (i.e., the surface electrode) while maintaining the same geometric distance, thus improving the surface creepage path length compared to the planar passivation layer design. In high-voltage power devices, this can improve PDIV, increase the device's lateral withstand voltage margin, improve packaging reliability, reduce the probability of device surface flashover, and effectively support the electric field safety redundancy design requirements in the context of chip size miniaturization. Attached Figure Description

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 This is a cross-sectional view of the structure of a high-voltage SiC power device proposed in Embodiment 1;

[0029] Figure 2 This is a schematic diagram of the arrangement of the passivation structure proposed in Embodiment 1;

[0030] Figure 3 This is a cross-sectional view of the structure of a high-voltage SiC power device proposed in Embodiment 2;

[0031] Figure 4 This is a cross-sectional view of the structure of a high-voltage SiC power device proposed in Embodiment 3;

[0032] Figure 5 This is a cross-sectional view of the structure of a high-voltage SiC power device proposed in Embodiment 4;

[0033] Figure 6 This is a cross-sectional view of the structure of a high-voltage SiC power device proposed in Embodiment 5;

[0034] Figure 7 This is a cross-sectional view of the structure of a high-voltage SiC power device proposed in Embodiment Six;

[0035] Figure 8 This is a cross-sectional view of the structure of a high-voltage SiC power device proposed in Embodiment 7.

[0036] Reference numerals in the figures: 1. Surface electrode; 2. First passivation layer; 3. Second passivation layer; 4. Third passivation layer; 5. Back electrode; 6. Substrate layer; 7. Buffer layer; 8. Epitaxial layer; 9. Termination structure; 10. Active region structure. Detailed Implementation

[0037] The present invention will be further described in detail below with reference to the embodiments. The following embodiments are explanations of the present invention, but the present invention is not limited to the following embodiments.

[0038] Example 1

[0039] like Figure 1As shown, a high-voltage SiC power device includes a surface electrode 1, a terminal region, and a passivation structure disposed on the terminal region. The passivation structure is in contact with the surface electrode 1 and extends from the surface of the terminal region to the exposed surface area between the surface electrode 1 and the scribe line. The passivation structure is non-planar and the creepage path of the passivation structure is greater than the distance between the surface electrode 1 and the scribe line.

[0040] When the passivation structure extends to the exposed surface area between the surface electrode 1 and the scribe line, the depth of the passivation structure can be lower than the surface electrode 1, the same as the surface electrode 1, or higher than the surface electrode 1. When the depth of the passivation structure is higher than the surface electrode 1, it can also partially cover the surface electrode 1. In this application, the settings can be made according to the actual situation, without specific limitations.

[0041] It also includes a back electrode 5, a substrate layer 6, a buffer layer 7, an epitaxial layer 8, a terminal structure 9, and an active region structure 10. The buffer layer 7 is disposed on the upper surface of the substrate layer 6, the back electrode 5 is disposed on the lower surface of the substrate layer 6, the epitaxial layer 8 is disposed on the buffer layer 7, the terminal structure 9 and the active region structure 10 are both embedded in the epitaxial layer 8, and the sidewall of the terminal structure 9 is in contact with the sidewall of the active region structure 10. The active region structure 10 is also in contact with the surface electrode 1, and the terminal structure 9 is in contact with the passivation structure.

[0042] Furthermore, the depth direction of the passivation structure is set as the first direction y, the direction of the surface electrode 1 toward the scribe line is set as the second direction x, and the length direction of the passivation structure is set as the third direction (in Figure 1 (Not shown in the text, but can be understood as the direction towards the inside of the paper), wherein the first direction, the second direction, and the third direction are perpendicular to each other, and the passivation structure is arranged in a concave-convex structure in the second direction and / or the third direction, the height of the protrusion of the concave-convex structure is set to 100nm ~ 20μm, and the length of the passivation structure in the second direction is 100μm ~ 1000μm.

[0043] The arrangement of the concave and convex structures of the passivation structure in the second direction and / or the third direction can be periodic. When set as periodic, the length of each group of periodic concave and convex structures is set to 1μm ~ 50μm. The arrangement of the concave and convex structures of the passivation structure in the second direction and / or the third direction can also be non-periodic. The non-periodic arrangement can break the electric field concentration tendency of the device, thereby improving the randomness and extensibility of the electrical breakdown path.

[0044] The shapes of concave and convex structures include rectangular steps, wavy shapes, and sawtooth shapes, for example, such as... Figure 2 Figure (a) shows a cross-sectional view of the passivation structure with a periodic arrangement of rectangular steps; Figure 2(b) is a cross-sectional view of the passivation structure with a serrated periodic arrangement; Figure 2 (c) is a cross-sectional view of the passivation structure arranged in a wave-like periodic pattern; Figure 2 (d) is a cross-sectional view of the passivation structure using a non-periodic arrangement of rectangular steps; Figure 2 (e) is a cross-sectional view of the passivation structure arranged in a wave-like periodic pattern in the second and third directions. This combination of bidirectional cross-arrangement in the second and third directions further increases the creepage path and complicates the discharge path. It should be noted that the above is only an example and also includes some composite morphological structures, including but not limited to alternating wave-like and step-like structures, and superimposed sawtooth and step-like structures, which are not listed in this application.

[0045] Furthermore, the material for the passivation structure includes any one of inorganic dielectric materials, organic polymer passivation materials, or dielectric passivation materials with high dielectric constants. Here, high dielectric constant refers to a dielectric constant k greater than 4.0, and the inorganic dielectric material can be SiO2 or SiN. x Silicon oxynitride, Al2O3, etc.; organic polymer passivation materials can be polyimide materials; dielectric passivation materials can be HfO2, Ta2O5, etc.

[0046] Furthermore, the passivation structure includes a first passivation layer 2, which is disposed on the terminal region, and the first passivation layer 2 is arranged in a concave-convex structure in the first direction and / or the third direction. In this embodiment, for example... Figure 1 As shown, the first passivation layer 2 can be made of Polyimide material. In this embodiment, the first passivation layer 2 is made of rectangular steps arranged periodically. To facilitate the manufacturing process, the step height of the first passivation layer 2 can be set to 5 μm, and the length of the periodically arranged steps can be set to 10 μm. The creepage path of the device is shown by the red arrow. In this embodiment, when the first passivation layer 2 extends to the exposed surface area between the surface electrode 1 and the scribe line, the depth of the first passivation layer 2 is set to be lower than the depth of the surface electrode 1.

[0047] At this point, the stepped structure introduces multiple angular changes at the interface, weakening the stability of the electric field concentration point and increasing the initiation threshold of partial discharge. On the other hand, this application introduces periodic or non-periodic concave-convex geometries (such as steps, ripples, grooves, etc.) on the terminal area, which significantly extends the surface creepage path between the scribe line and the ground metal electrode (i.e., surface electrode 1) without changing the geometric distance, thus improving the surface creepage path length compared to the planar passivation layer design. In high-voltage power devices, this can improve PDIV, increase the device's lateral withstand voltage margin, improve packaging reliability, reduce the probability of device surface flashover, and effectively support the electric field safety redundancy design requirements in the context of chip size miniaturization.

[0048] To avoid misinterpreting the "uneven structure" of this invention as a gate trench in the cell structure or a trench etching terminal structure 9 in the terminal structure 9 or a repeating PN junction field-limiting ring structure, it is hereby clarified that: the step or uneven structure of this invention is formed only on the surface of the device passivation layer and does not involve the active cell region or the terminal doped structure body.

[0049] Specifically, firstly, this structure is not used for current carrying or regulating electric field distribution; its sole purpose is to extend the surface creepage path, disperse the lateral electric field intensity, reduce surface leakage, and lower the risk of partial discharge. Secondly, the manufacturing process differs significantly; this structure is achieved through a dielectric deposition layer (such as...). The surface structure is constructed using methods such as surface micro-nano etching or template imprinting, without involving epitaxy, growth, or high-energy ion implantation to form a PN structure; third, there are differences in geometric scale and periodicity. The periodic step / trench size of the cell structure is usually within 1μm–2μm and is located inside the device; the step height of the surface structure described in this invention is 1μm–20μm, the number of periods is dozens, and the whole structure spans the outer edge region of the terminal, with significantly different size spans; fourth, non-functional structures are excluded. This structure does not constitute a channel, does not participate in switching, and does not form junction capacitance. It exists only as a means of optimizing surface electrical insulation.

[0050] Furthermore, the technical terms used in this application are explained as follows:

[0051] Passivation layer: refers to a dielectric layer deposited on the surface of a power semiconductor device, which provides electrical insulation, surface protection, and electric field modulation. Common materials include... wait;

[0052] Terminal region: refers to the device structure region outside the active region used to achieve gradual electric field reduction and uniform edge voltage distribution. It usually includes designs such as JTE (injection termination extension region) or FLR (field limiting loop).

[0053] Dicing line: refers to the non-functional area required for the physical cutting (dicing) of a chip. It is usually located on the outer edge of the chip and is used for cutting isolation between chips. It may be located at the edge of a high-voltage area.

[0054] Partial discharge (PD): refers to the non-penetrating discharge phenomenon that occurs in a local area within or on the surface of an insulation structure under a high-voltage electric field. It is an important cause of insulation system degradation and early breakdown.

[0055] PDIV (Partial Discharge Inception Voltage): The partial discharge initiation voltage represents the minimum voltage at which a measurable PD signal first appears. It is a key indicator for evaluating the insulation performance of device packaging and the quality of terminal design.

[0056] Creepage path: The electrical propagation path along the surface of an insulator from a high-voltage point to a grounding electrode. It is usually longer than the geometric distance and is used to suppress surface discharge.

[0057] Effective Creepage Path: In this patent, it refers to the total path length after the propagation path of electric field lines on the dielectric surface is artificially lengthened by introducing a three-dimensional surface structure, which is used to improve the withstand voltage capability of PDIV and terminals.

[0058] 3D Passivation Topography: refers to the surface microstructure morphology of the passivation layer formed by structural methods such as steps, ripples, and grooves, which is used to extend the surface discharge path and disperse electric field lines.

[0059] Example 2

[0060] like Figure 3 As shown, the difference between this embodiment and Embodiment 1 is that the passivation structure in this embodiment further includes a second passivation layer 3. The second passivation layer 3 is disposed on the terminal area, and the second passivation layer 3 is in contact with the lower surface of the first passivation layer 2. The second passivation layer 3 is planar, and the second passivation layer 3 and the first passivation layer 2 are made of different passivation materials. In addition, in this embodiment, the depth of the passivation structure composed of the first passivation layer 2 and the second passivation layer 3 is set to be higher than the surface electrode 1, which provides versatility in process manufacturing.

[0061] Specifically, the material of the second passivation layer 3 can be SiNx. Compared with Example 1, the multilayer passivation system with multiple deposition media can break the structural symmetry between layers and block the continuous low-impedance discharge path.

[0062] Example 3

[0063] like Figure 4 As shown, the difference between this embodiment and embodiment two is that the second passivation layer 3 in this embodiment is arranged in a concave-convex structure in the first direction and / or the third direction. The second passivation layer 3 and the first passivation layer 2 are different passivation materials. This embodiment not only provides enhancement on the external terminal creepage path of the device, but also introduces geometric complexity and electric field disturbance mechanism on the internal leakage path of the dielectric layer. Overall, it greatly improves the device's resistance to electrical breakdown and long-term insulation stability in the terminal area, and is particularly suitable for application scenarios with high voltage working environment, high dv / dt repeated switching and harsh packaging conditions.

[0064] Furthermore, in this embodiment, in addition to setting the depth of the passivation structure composed of the first passivation layer 2 and the second passivation layer 3 to be higher than the surface electrode 1, the passivation structure is extended to the upper surface of the surface electrode 1, thereby partially covering the surface electrode 1 and providing diversity in process technology.

[0065] Example 4

[0066] like Figure 5 As shown, the difference between this embodiment and Embodiment 2 is that the passivation structure further includes a third passivation layer 4, which is disposed on the terminal area. The third passivation layer 4 is in contact with the lower surface of the second passivation layer 3, and the third passivation layer 4 is planar. The third passivation layer 4 and the second passivation layer 3 are made of different passivation materials. At the same time, the depth of the passivation structure is set to be the same as the depth of the surface electrode 1. In this embodiment, the material of the third passivation layer 4 can be set to SiO2. Compared with Embodiment 2, this embodiment has higher insulation strength and stronger packaging reliability. At the same time, the structural setting provided by this embodiment can provide a more stable electric field shielding and thermomechanical support effect.

[0067] Example 5

[0068] like Figure 6 As shown, the difference between this embodiment and Embodiment 3 is that the passivation structure further includes a third passivation layer 4, which is disposed on the terminal region. The third passivation layer 4 is in contact with the lower surface of the second passivation layer 3, and the third passivation layer 4 is planar. The third passivation layer 4 and the second passivation layer 3 are different passivation materials. In this embodiment, the material of the third passivation layer 4 can be set as SiO2. Compared with Embodiment 3, the multilayer passivation system with multiple deposition media can break the structural symmetry between the layers and block the continuous low-impedance discharge path.

[0069] Furthermore, in this embodiment, the depth of the passivation structure composed of the first passivation layer 2, the second passivation layer 3, and the third passivation layer 4 is set to be higher than that of the surface electrode 1, and the passivation structure is extended to the upper surface of the surface electrode 1. At the same time, when extending to the upper surface of the electrode, the end of the second passivation layer 3 near the surface electrode 1 can be configured to cover the third passivation layer 4, and the end of the first passivation layer 2 near the surface electrode 1 can be configured to cover the second passivation layer 3, thereby realizing that the passivation structure partially covers the surface electrode 1, providing diversity in process processing.

[0070] Example 6

[0071] like Figure 7As shown, the difference between this embodiment and Embodiment 2 is that the passivation structure further includes a third passivation layer 4. The third passivation layer 4 is disposed on the terminal region. The third passivation layer 4 is in contact with the lower surface of the second passivation layer 3. The third passivation layer 4 is arranged in a concave-convex structure in the first direction and / or the third direction. The third passivation layer 4 and the second passivation layer 3 are different passivation materials. Compared with Embodiment 2, the multilayer passivation system with multiple deposition media can break the structural symmetry between the layers and block the continuous low-impedance discharge path.

[0072] Furthermore, in this embodiment, the depth of the passivation structure composed of the first passivation layer 2, the second passivation layer 3, and the third passivation layer 4 is set to be equal to the depth of the surface electrode 1. The end of the second passivation structure near the dicing channel is set to cover the third passivation layer 4, while the end of the first passivation layer 2 near the dicing channel can be set to cover the second passivation layer 3, thereby realizing different structural settings of the passivation structure and providing diversity of process processing.

[0073] Example 7

[0074] like Figure 8 As shown, the difference between this embodiment and embodiment three is that the passivation structure further includes a third passivation layer 4, which is disposed on the terminal area. The third passivation layer 4 is in contact with the lower surface of the second passivation layer 3, and the third passivation layer 4 is arranged in a concave-convex structure in the first direction and / or the third direction. The third passivation layer 4 and the second passivation layer 3 are different passivation materials, and the depth of the passivation structure is set to be the same as the depth of the surface electrode 1.

[0075] Specifically, in this embodiment, the thickness of the first passivation layer 2 is set to 10 μm, the thickness of the second passivation layer 3 is set to 500 nm, and the thickness of the third passivation layer 4 is set to 500 nm. In this embodiment, since in or Introducing steps, grooves, or periodic undulations into the layer transforms the original "planar medium-medium contact interface" into a "three-dimensional non-uniform interface" after subsequent medium coating. Electric field lines cannot simply propagate along a single path, effectively lengthening the leakage path formed along the medium interface.

[0076] Furthermore, the stepped structure introduces multiple angular variations at the interface, weakening the stability of the electric field concentration point and increasing the initiation threshold of partial discharge. For multilayer passivation systems with multiple deposited media, this three-dimensional contact structure can also break the structural symmetry between layers and block continuous low-impedance discharge paths.

[0077] To further illustrate the effect of the structural design of this application on the quantitative improvement of surface creepage path and PDIV, in the three-dimensional passivation structure of this embodiment, by setting a concave-convex step structure with a certain height and period number, the equivalent length of the electric field propagation path along the surface, i.e. the effective creepage distance, can be significantly improved without increasing the horizontal geometric size of the device terminal area, thereby achieving the effect of improving the partial discharge initiation voltage of the device.

[0078] For example, when a stepped structure with a height of 5 μm is constructed on the surface of the first passivation layer 2, and the number of cycles is set to 50, the actual creepage path length on the surface within a horizontal distance of 500 μm in the original terminal region can reach: effective creepage path length ≈ 500 μm + 50 2 5μm = 1000μm, where each step contains an ascending segment and a descending segment, so multiply by two.

[0079] Therefore, the creepage path length is doubled compared to traditional planar passivation structures. Even with termination designs already compressed to within 500μm, constructing a three-dimensional morphology effectively provides an additional creepage path of several hundred micrometers, significantly enhancing the voltage withstand margin of the termination package. This method is particularly suitable for devices used in high dv / dt, high humidity, and high pollution environments. Furthermore, this method is not strongly dependent on the termination area design and is compatible with termination structures such as JTE and FLR. It is an efficient, controllable, and easily integrated surface insulation enhancement technique.

[0080] It should be noted that this embodiment only provides a design with three passivation layers. In actual processing, multiple passivation structures can be set. When setting multiple passivation layers, it is only necessary to ensure that the materials of adjacent passivation layers are different. The multiple passivation layers should at least ensure that the uppermost passivation layer has a concave-convex structure arrangement. The more passivation layers with a concave-convex structure arrangement, the more complex the creepage distance of this application and the higher the starting threshold of partial discharge. In addition, when setting multiple passivation layers, the passivation layer near the scribe line can be set as the upper passivation layer covering the lower passivation layer, thereby achieving diverse settings. When the passivation structure extends to the upper surface of the surface electrode 1, the same covering design can also be set. These will not be listed one by one in this application.

[0081] Example 8

[0082] A method for manufacturing a high-voltage SiC power device, the method being used to prepare a high-voltage SiC power device as described in any one of Examples 1 to 7, comprising the following steps:

[0083] Obtain substrate layer 6, and grow buffer layer 7 and epitaxial layer 8 on substrate layer 6;

[0084] An active region structure 10 is formed on the epitaxial layer 8, and a terminal structure 9 is formed on the outside of the active region structure 10.

[0085] A back electrode 5 is deposited and patterned on the lower surface of the substrate layer 6, and a surface electrode 1 is deposited and patterned on the active region structure 10.

[0086] A passivation structure is deposited in the terminal region and its external region, and a three-dimensional concave-convex structure is introduced into the passivation structure by photolithography etching.

[0087] Specifically, the preparation process is as follows:

[0088] S1. Preparation of substrate layer 6 and growth of epitaxial layer 8: On substrate layer 6 (such as 4H-SiC, GaN, Ga2O3, etc.), a buffer layer 7 and an epitaxial layer 8 of the required thickness are grown. The thickness and doping concentration of epitaxial layer 8 are set according to the target voltage level. The required thickness for power device design is The doping concentration is 1×10⁻⁶. 13 cm -3 ~1×10 17 cm -3 .

[0089] S2. Fabrication of the active region structure 10: Depending on the device type, different active structures are fabricated, including but not limited to MOSFET, JFET, IGBT, SBD, PIN, and other device structures. This step is completed using standard photolithography, doping, etching, and metallization processes. Specifically:

[0090] For MOSFET devices, structures such as source injection region, gate oxide, and polysilicon gate are formed;

[0091] For IGBT devices, structures such as emitter injection region, gate oxide, and polysilicon gate are formed;

[0092] For JFET devices, structures such as the JFET channel region are formed;

[0093] For diode devices, structures such as Schottky contacts (SBDs) or PN junctions are fabricated.

[0094] S3. Termination structure 9 is fabricated outside the active region. For example, multi-region JTE structure, circular FLR (Field Limiting Ring) structure, and variable doping type termination buffer design. Termination structure 9 can be achieved by ion implantation, multiple doping, etching edge control and other methods.

[0095] S4. Fabrication of device metal electrodes: Deposit and pattern source, drain, and gate metals according to structural requirements, including commonly used metals such as Ti, Al, Ni, and Pt.

[0096] S5. Passivation layer preparation and three-dimensional structure introduction: A passivation layer is deposited in the terminal region and its external area, for example: a bottom layer of SiO2 material (formed by thermal oxidation or TEOS process); and an intermediate layer of SiN. x Materials (formed using PECVD process); surface organic passivation layers such as Polyimide materials (spin coating + patterning + baking curing process), in a certain layer of the passivation structure (e.g. , or The surface is etched with a three-dimensional concave-convex structure through photolithography and other methods, so that the passivated surface has a periodic or non-periodic undulation morphology, thereby extending the surface electric field propagation path between the dicing track and the metal electrode.

[0097] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any form or substance. It should be noted that those skilled in the art can make various improvements and additions without departing from the method of the present invention, and these improvements and additions should also be considered within the scope of protection of the present invention. Any modifications, alterations, and equivalent changes made by those skilled in the art based on the above-disclosed technical content without departing from the spirit and scope of the present invention are equivalent embodiments of the present invention. Furthermore, any modifications, alterations, and evolutions made to the above embodiments based on the essential technology of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A high-voltage SiC power device, characterized in that, The device includes a surface electrode, a terminal region, and a passivation structure disposed on the terminal region. The passivation structure is in contact with the surface electrode and extends from the surface of the terminal region to the exposed surface area between the surface electrode and the scribe line. The passivation structure is non-planar, and the creepage path of the passivation structure is greater than the distance between the surface electrode and the scribe line. The depth direction of the passivation structure is a first direction, the direction of the surface electrode toward the scribe line is a second direction, and the length direction of the passivation structure is a third direction. The first direction, the second direction, and the third direction are perpendicular to each other. The passivation structure is arranged in a concave-convex structure in the second direction and / or the third direction. The passivation structure includes a first passivation layer, which is disposed on the terminal region and is arranged in a concave-convex structure in the first direction and / or the third direction.

2. The high-voltage SiC power device according to claim 1, characterized in that, The passivation structure further includes a second passivation layer, which is disposed on the terminal region. The second passivation layer is in contact with the lower surface of the first passivation layer, and the second passivation layer is planar. The second passivation layer and the first passivation layer are made of different passivation materials.

3. The high-voltage SiC power device according to claim 1, characterized in that, The passivation structure further includes a second passivation layer, which is disposed on the terminal region. The second passivation layer is in contact with the lower surface of the first passivation layer, and the second passivation layer is arranged in a concave-convex structure in the first direction and / or the third direction. The second passivation layer and the first passivation layer are different passivation materials.

4. A high-voltage SiC power device according to any one of claims 2 or 3, characterized in that, The passivation structure further includes a third passivation layer, which is disposed on the terminal area. The third passivation layer is in contact with the lower surface of the second passivation layer, and the third passivation layer is planar. The third passivation layer and the second passivation layer are made of different passivation materials.

5. A high-voltage SiC power device according to any one of claims 2 or 3, characterized in that, The passivation structure further includes a third passivation layer, which is disposed on the terminal area. The third passivation layer is in contact with the lower surface of the second passivation layer, and the third passivation layer is arranged in a concave-convex structure in a first direction and / or a third direction. The third passivation layer and the second passivation layer are different passivation materials.

6. A high-voltage SiC power device according to claim 1, characterized in that, The material of the passivation structure includes any one of inorganic dielectric materials, organic polymer passivation materials, or dielectric passivation materials with a dielectric constant greater than 4.

0.

7. A high-voltage SiC power device according to claim 1, characterized in that, The passivation structure is arranged in a periodic pattern in the second direction and / or the third direction, and the length of each periodic arrangement of the concave and convex structures is set to 1 μm ~ 50 μm.

8. A high-voltage SiC power device according to claim 1, characterized in that, The height of the protrusions in the concave-convex structure is set to 100nm ~ 20μm.

9. A high-voltage SiC power device according to claim 1, characterized in that, The passivation structure has a length of 100 μm to 1000 μm in the second direction.

10. A high-voltage SiC power device according to any one of claims 6-9, characterized in that, The shapes of the concave-convex structures include rectangular steps, wavy shapes, and sawtooth shapes.

11. A high-voltage SiC power device according to claim 1, characterized in that, It also includes a back electrode, a substrate layer, a buffer layer, an epitaxial layer, a termination structure, and an active region structure. The buffer layer is disposed on the upper surface of the substrate layer, the back electrode is disposed on the lower surface of the substrate layer, the epitaxial layer is disposed on the buffer layer, the termination structure and the active region structure are both embedded in the epitaxial layer, and the sidewall of the termination structure is in contact with the sidewall of the active region structure. The active region structure is also in contact with the surface electrode, and the termination structure is in contact with the passivation structure.

12. A method for manufacturing a high-voltage SiC power device, characterized in that, The manufacturing method is used to prepare the high-voltage SiC power device as described in any one of claims 1-11, and includes the following steps: Obtain a substrate layer, and grow a buffer layer and an epitaxial layer on the substrate layer; An active region structure is formed on the epitaxial layer, and a terminal structure is formed on the outside of the active region structure; A back electrode is deposited and patterned on the lower surface of the substrate, and a surface electrode is deposited and patterned on the active region structure. A passivation structure is deposited in the terminal region and its external region, and a three-dimensional concave-convex structure is introduced in the passivation structure by photolithography etching.

Images