Single event upset resistant reinforced CML latch, frequency-halving circuit and equipment

Abstract

The invention discloses a reinforced CML latch capable of resisting single event upset, a frequency-halving circuit and equipment, the CML latch comprises a latch circuit composed of NMOS transistors, two input sides of the latch circuit are connected with PMOS transistors used for restraining the jump from 1 to 0 of single event upset, and the two input sides of the latch circuit are connected with a gate. A signal connected with the grid electrode of one PMOS transistor is a frequency division clock signal clk180-o obtained after a 180-degree phase frequency division clock signal clk180 output by the latch circuit is converted from a current mode to a CMOS, and a signal connected with the grid electrode of the other PMOS transistor is a frequency division clock signal clk0-o obtained after a 0-degree phase frequency division clock signal clk0 output by the latch circuit is converted from the current mode to the CMOS. The invention aims to realize the single event upset resistance reinforcement with lower overhead for the CML latch, and improve the anti-radiation reinforcement performance of the CML latch.

Description

Technical Field

[0001] The present invention relates to a radiation-resistant reinforcement technology in the field of circuits, and in particular to a CML latch, a two-way frequency division circuit and a device reinforced against single-event upset. Background Art

[0002] As process geometries shrink, space radiation effects, particularly single-event effects (SEPs), become increasingly severe, posing challenges to aerospace circuit design. Radiation hardening is often required in aerospace integrated circuit design, specifically categorized as digital IC hardening and analog IC hardening. Digital IC hardening is relatively versatile and therefore favored by researchers. Extensive research has been conducted across various process nodes, covering everything from architecture to circuit design and layout. However, research on analog circuit hardening is less extensive due to its difficulty and limited versatility.

[0003] High-speed frequency dividers used in analog circuits often utilize latches. Due to their high speed requirements, they require a design different from digital latches. Common latches in digital circuits consist of two inverters connected end-to-end. Their stable operating points are the power supply and ground voltages, requiring large input voltage changes to flip the latch state, making them difficult to directly apply to analog circuits. Common analog latches build on their digital counterparts by adding current sources or resistors for current limiting and using large transistors to reduce the steady-state voltage difference across the latch, minimizing the voltage change required for flipping and improving latch speed. While there are many solutions for digital latch hardening, such as redundant hardening using DICE and TMR, charge-sharing using DHC and LEAP, and signal filtering using delay cells or RC, these solutions are difficult to directly apply to the hardening design of CML (current-mode logic) latches commonly used in frequency dividers due to speed and structure limitations. Specific hardening measures tailored to the characteristics of analog circuits are needed.

[0004] like Figure 1 As shown in the figure, the traditional high-speed clock divide-by-two circuit consists of two CML latches Latch L and Latch R with the same structure connected end to end. It inputs a pair of differential clocks clk and clkz, and outputs the divided-by-two four-phase clocks clk0, clk90, clk180 and clk270 through the CML latches Latch L and Latch R.

[0005] like Figure 2As shown, the CML latch includes a pair of resistors R1 and R2 and three pairs of NMOS transistors (M1, M2), (M3, M4) and (M5, M6), wherein a pair of NMOS transistors (M5, M6) is controlled by differential clocks clk and clkz to select whether the input side NMOS transistors (M3, M4) are turned on or the holding side NMOS transistors (M1, M2) are turned on.

[0006] According to the principle of single event effect, the reverse-biased PN junction is a sensitive point for single event effect. In the main part of the CML latch, there are only NMOS transistors. Therefore, the single event effect will only occur when the NMOS transistor is turned off and the node stores "1", causing the storage node to flip, that is, "1→0 flip". The circuit is configured to operate at 28GHz. At 0.5ns, a double exponential current source is injected into the drain of the M1 transistor in the latch R to simulate the single event effect. The results are shown below. Figure 3 As shown in the figure, clk0 / clk90 / clk180 / clk270 are the original output clocks of the affected frequency divider circuit, referred to as the original clocks, and clk0-o / clk90-o / clk180-o / clk270-o are the clocks after current-mode to CMOS conversion, referred to as the output clocks. Significant clock jitter can be observed after current injection. When charge is injected into the drain of transistor M1, its potential decreases, reducing the maximum amplitude of the clk180 signal. When transmitted to the corresponding latch L, the lower amplitude affects the normal operation of the M4 transistor within it, causing the minimum value of the clk90 signal to be too high, exceeding the conversion tolerance. After conversion, the output clk90-o generates a single-event upset, resulting in a long "1" signal, while the corresponding clk270-o generates a long "0" signal. Summary of the Invention

[0007] The present invention aims to solve the following technical problems: In response to the above-mentioned problems in the prior art, a CML latch, a two-way frequency division circuit, and a device with SUP hardening are provided. The present invention aims to achieve SUP hardening for the CML latch with low overhead, thereby improving the radiation hardening performance of the CML latch.

[0008] In order to solve the above technical problems, the technical solution adopted by the present invention is: A CML latch reinforced against single-event upsets includes a latch circuit formed of NMOS transistors. Both input sides of the latch circuit are connected to PMOS transistors for suppressing "1→0" transitions caused by single-event upsets. The signal connected to the gate ck2_o of one of the PMOS transistors is a divided clock signal clk180 with a 180-degree phase output by the latch circuit, which is converted from current mode to CMOS, and the signal connected to the gate ckz2_o of the other PMOS transistor is a divided clock signal clk0 with a 0-degree phase output by the latch circuit, which is converted from current mode to CMOS, and the signal connected to the gate ckz2_o of the other PMOS transistor is a divided clock signal clk0-o with a 0-degree phase output by the latch circuit, which is converted from current mode to CMOS.

[0009] Optionally, the latch circuit includes resistors R1-R2, NMOS transistors M1-M6 and PMOS transistors M7-M8. The latch circuit has two power supply terminals, namely power supply terminal in1 and power supply terminal in2. The power supply terminal in1 is connected to the output terminal y of the first output clock signal through the resistor R2. The power supply terminal in2 is connected to the output terminal yz of the second output clock signal through the resistor R1. The output terminal y is respectively connected to the drains of the NMOS transistors M4 and M2 and the gate of M1. The output terminal yz is respectively connected to the drains of the NMOS transistors M1 and M3 and the gate of M2. The NMOS transistors The gate of transistor M3 serves as the input terminal a of the third clock signal, the gate of NMOS transistor M4 serves as the input terminal az of the fourth clock signal, the sources of NMOS transistors M1 and M2 are commonly connected to the drain of NMOS transistor M5, the sources of NMOS transistors M3 and M4 are commonly connected to the drain of NMOS transistor M6, the gate of NMOS transistor M5 is connected to the input clock signal ckz, the gate of NMOS transistor M6 is connected to the input clock signal ck, the clock signal ckz and the clock signal ck form a pair of differential clocks, and the sources of NMOS transistors M5 and M6 are connected to each other.

[0010] Optionally, the PMOS transistor includes a PMOS transistor M7 connected to the drain of the NMOS transistor M3 and a PMOS transistor M8 connected to the drain of the NMOS transistor M4. The signal connected to the gate ck2_o of the PMOS transistor M7 is the divided clock signal clk180 output by the latch circuit after current mode to CMOS conversion, and the signal connected to the gate ckz2_o of the PMOS transistor M8 is the divided clock signal clk0 output by the latch circuit after current mode to CMOS conversion, and the divided clock signal clk0-o.

[0011] Optionally, drains of the PMOS transistor M7 and the PMOS transistor M8 are connected to a power supply port vdda.

[0012] Optionally, sources of the NMOS transistors M5 and M6 are connected to a current source to provide a tail current for the latch circuit.

[0013] In addition, the present invention also provides a two-way frequency division circuit, which is composed of two CML latches Latch L and Latch R with the same structure connected end to end. The inputs of the CML latches Latch L and Latch R are a pair of differential clocks clk and clkz, and the CML latch Latch L includes two output ports for outputting the four-phase clocks clk90 and clk270 after the frequency division. The CML latch Latch R includes two output ports for outputting the four-phase clocks clk0 and clk180 after the frequency division. The CML latches Latch L and Latch R are the CML latches reinforced against single-event upsets.

[0014] Optionally, the input terminal a of the CML latch Latch L is used to input the divided clock signal clk0 with a phase of 0 degree, the input terminal az is used to input the divided clock signal clk180 with a phase of 180 degrees, the output terminal y is used to output the divided clock signal clk90 with a phase of 90 degrees, and the output terminal yz is used to output the divided clock signal clk270 with a phase of 270 degrees; the input terminal a of the CML latch Latch R is used to input the divided clock signal clk270 with a phase of 270 degrees, the input terminal az is used to input the divided clock signal clk90 with a phase of 90 degrees, the output terminal y is used to output the divided clock signal clk0 with a phase of 0 degree, and the output terminal yz is used to output the divided clock signal clk180 with a phase of 180 degrees.

[0015] In addition, the present invention also provides an electronic device, comprising a device body and a circuit module disposed in the device body, wherein the circuit module comprises the CML latch reinforced against single event upset.

[0016] Compared with the prior art, the present invention has the following main advantages: the CML latch of the present invention includes a latch circuit composed of NMOS transistors, both input sides of the latch circuit are connected to PMOS transistors for suppressing "1→0" transitions of single-event upsets, and the signal connected to the gate ck2_o of one of the PMOS transistors is the divided clock signal clk180 with a 180-degree phase output by the latch circuit, which is converted from current mode to CMOS, and the signal connected to the gate ckz2_o of the other PMOS transistor is the divided clock signal clk0 with a 0-degree phase output by the latch circuit, which is converted from current mode to CMOS, and the signal connected to the gate ckz2_o of the other PMOS transistor is the divided clock signal clk0-o with a 0-degree phase output by the latch circuit, which is converted from current mode to CMOS. The present invention can achieve single-event upset hardening for the CML latch with low overhead, thereby improving the radiation hardening performance of the CML latch. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is the circuit schematic diagram of a traditional high-speed clock divide-by-two circuit.

[0018] Figure 2 This is the circuit schematic diagram of a traditional CML latch.

[0019] Figure 3 Schematic diagram of the four-phase clock output of a traditional high-speed clock divide-by-two circuit and the converted four-phase clock output, where (a) is the original four-phase clock output and (b) is the converted four-phase clock output.

[0020] Figure 4 FIG. 4 is a circuit diagram of a CML latch in an embodiment of the present invention.

[0021] Figure 5 Schematic diagram of the four-phase clock output and the converted four-phase clock output of the two-phase frequency divider circuit in an embodiment of the present invention, wherein (a) is the original four-phase clock output and (b) is the converted four-phase clock output. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution of the present invention will be further described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0023] like Figure 4As shown, the CML latch reinforced against single-particle upsets in this embodiment includes a latch circuit composed of NMOS transistors, both input sides of which are connected to PMOS transistors for suppressing the "1→0" transition of single-particle upsets, and the signal connected to the gate ck2_o of one of the PMOS transistors is the divided clock signal clk180 with a 180-degree phase output by the latch circuit, which is the divided clock signal clk180-o after current-mode conversion to CMOS, and the signal connected to the gate ckz2_o of the other PMOS transistor is the divided clock signal clk0 with a 0-degree phase output by the latch circuit, which is the divided clock signal clk0-o after current-mode conversion to CMOS.

[0024] like Figure 4 As shown, the latch circuit in this embodiment includes resistors R1-R2, NMOS transistors M1-M6 and PMOS transistors M7-M8. The latch circuit has two power supply terminals, namely power supply terminal in1 and power supply terminal in2. The power supply terminal in1 is connected to the output terminal y of the first output clock signal through the resistor R2. The power supply terminal in2 is connected to the output terminal yz of the second output clock signal through the resistor R1. The output terminal y is respectively connected to the drains of the NMOS transistors M4 and M2 and the gate of M1. The output terminal yz is respectively connected to the drains of the NMOS transistors M1 and M3 and the gate of M2. The gate of the transistor M3 serves as the input terminal a of the third clock signal, the gate of the NMOS transistor M4 serves as the input terminal az of the fourth clock signal, the sources of the NMOS transistors M1 and M2 are commonly connected to the drain of the NMOS transistor M5, the sources of the NMOS transistors M3 and M4 are commonly connected to the drain of the NMOS transistor M6, the gate of the NMOS transistor M5 is connected to the input clock signal ckz, the gate of the NMOS transistor M6 is connected to the input clock signal ck, the clock signal ckz and the clock signal ck form a pair of differential clocks, and the sources of the NMOS transistors M5 and M6 are connected to each other.

[0025] like Figure 4As shown, the PMOS transistor in this embodiment includes a PMOS transistor M7 connected to the drain of the NMOS transistor M3 and a PMOS transistor M8 connected to the drain of the NMOS transistor M4. The signal connected to the gate ck2_o of the PMOS transistor M7 is the divided clock signal clk180 output by the latch circuit after the current mode is converted to the divided clock signal clk180-o. The signal connected to the gate ckz2_o of the PMOS transistor M8 is the divided clock signal clk0 output by the latch circuit after the current mode is converted to the divided clock signal clk0-o. By adding two PMOS transistors M7 and M8, the "1→0" transition is suppressed. The control signals of the PMOS transistors M7 and M8 are the converted divided clock signals clk180-o (ck2_o) and clk0-o (ckz2_o), respectively. When the drain of the NMOS transistor M1 is bombarded and the potential decreases, the NMOS transistor M7 will increase the injection current to offset the charge collection caused by the single event effect and help the bombarded node maintain the "1" potential. Figure 4 As shown, the drains of the PMOS transistors M7 and M8 in this embodiment are connected to the power supply port vdda. The sources of the NMOS transistors M5 and M6 in this embodiment are connected to a current source to provide a tail current for the latch circuit, which can resist PVT (process, voltage and temperature) disturbances.

[0026] In addition, this embodiment also provides a divide-by-two frequency circuit, which is composed of two CML latches Latch L and Latch R with the same structure connected end to end. The inputs of the CML latches Latch L and Latch R are a pair of differential clocks clk and clkz, and the CML latch Latch L includes two output ports for outputting the four-phase clocks clk90 and clk270 after the frequency division. The CML latch Latch R includes two output ports for outputting the four-phase clocks clk0 and clk180 after the frequency division. The CML latches Latch L and Latch R are the CML latches with single-event upset hardening mentioned above.

[0027] In this embodiment, the input terminal a of the CML latch Latch L is used to input the divided clock signal clk0 with a phase of 0 degrees, the input terminal az is used to input the divided clock signal clk180 with a phase of 180 degrees, the output terminal y is used to output the divided clock signal clk90 with a phase of 90 degrees, and the output terminal yz is used to output the divided clock signal clk270 with a phase of 270 degrees; the input terminal a of the CML latch Latch R is used to input the divided clock signal clk270 with a phase of 270 degrees, the input terminal az is used to input the divided clock signal clk90 with a phase of 90 degrees, the output terminal y is used to output the divided clock signal clk0 with a phase of 0 degrees, and the output terminal yz is used to output the divided clock signal clk180 with a phase of 180 degrees.

[0028] In order to verify the SEP-hardened characteristics of the CML latch in this embodiment, the circuit of the CML latch in this embodiment is configured to operate at 28 GHz. At 0.5 ns, a double exponential current source is injected into the drain of the NMOS transistor M1 in the CML latch Latch R to simulate the SEP effect. The current setting is the same as Figure 3 The final four-phase clock output of the two-frequency divider circuit and the output after conversion are shown in the figure below. Figure 5 See Figure 5 As can be seen, the original clock amplitude changes slightly, and the converted output clock is barely affected, demonstrating the effectiveness of this embodiment's SUP-hardened CML latch reinforcement scheme. Compared to the original circuit, the reinforced circuit achieves significant SUP resistance with lower overhead, increasing the area by only 0.2%.

[0029] In addition, this embodiment further provides an electronic device, including a device body and a circuit module disposed in the device body, wherein the circuit module includes the aforementioned CML latch reinforced against single event upset.

[0030] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A CML latch hardened against single event upset, comprising a latch circuit composed of NMOS transistors, characterized in that: Both input sides of the latch circuit are connected to PMOS transistors for suppressing the "1→0" transition of a single-event upset, and the signal connected to the gate ck2_o of one of the PMOS transistors is the divided clock signal clk180 with a 180-degree phase output by the latch circuit, which is converted from current mode to CMOS, and the signal connected to the gate ckz2_o of the other PMOS transistor is the divided clock signal clk0 with a 0-degree phase output by the latch circuit, which is converted from current mode to CMOS, and the signal connected to the gate ckz2_o of the other PMOS transistor is the divided clock signal clk0-o with a 0-degree phase output by the latch circuit, which is converted from current mode to CMOS.

2. The single event upset hardened CML latch according to claim 1, wherein: The latch circuit includes resistors R1-R2, NMOS transistors M1-M6 and PMOS transistors M7-M8. The latch circuit has two power supply terminals, namely power supply terminal in1 and power supply terminal in2. The power supply terminal in1 is connected to the output terminal y of the first output clock signal through the resistor R2. The power supply terminal in2 is connected to the output terminal yz of the second output clock signal through the resistor R1. The output terminal y is respectively connected to the drains of the NMOS transistors M4 and M2 and the gate of M1. The output terminal yz is respectively connected to the drains of the NMOS transistors M1 and M3 and the gate of M2. The NMOS transistor M The gate of NMOS transistor M3 serves as the input terminal a of the third clock signal, the gate of NMOS transistor M4 serves as the input terminal az of the fourth clock signal, the sources of NMOS transistors M1 and M2 are commonly connected to the drain of NMOS transistor M5, the sources of NMOS transistors M3 and M4 are commonly connected to the drain of NMOS transistor M6, the gate of NMOS transistor M5 is connected to the input clock signal ckz, the gate of NMOS transistor M6 is connected to the input clock signal ck, the clock signal ckz and the clock signal ck form a pair of differential clocks, and the sources of NMOS transistors M5 and M6 are connected to each other.

3. The single event upset hardened CML latch according to claim 2, wherein: The PMOS transistors include a PMOS transistor M7 connected to the drain of the NMOS transistor M3 and a PMOS transistor M8 connected to the drain of the NMOS transistor M4. The signal connected to the gate ck2_o of the PMOS transistor M7 is the divided clock signal clk180 output by the latch circuit after current mode conversion to the divided clock signal clk180-o. The signal connected to the gate ckz2_o of the PMOS transistor M8 is the divided clock signal clk0-o output by the latch circuit after current mode conversion to the divided clock signal clk0.

4. The single event upset hardened CML latch according to claim 3, wherein: The drains of the PMOS transistor M7 and the PMOS transistor M8 are connected to the power supply port vdda.

5. The single event upset hardened CML latch according to claim 3, wherein: The sources of the NMOS transistors M5 and M6 are connected to a current source for providing a tail current for the latch circuit.

6. A divide-by-two frequency circuit, comprising two CML latches (Latch L and Latch R) of identical structure connected end-to-end, wherein the inputs of the CML latches (Latch L and Latch R) are a pair of differential clocks (clk and clkz), and the CML latch (Latch L) includes two output ports for outputting divided-by-two four-phase clocks (clk90 and clk270), and the CML latch (Latch R) includes two output ports for outputting divided-by-two four-phase clocks (clk0 and clk180), wherein: The CML latches Latch L and Latch R are CML latches reinforced against single event upset according to any one of claims 1 to 5.

7. The two-way frequency division circuit according to claim 6, wherein: The input terminal a of the CML latch Latch L is used to input the divided clock signal clk0 with a phase of 0 degrees, the input terminal az is used to input the divided clock signal clk180 with a phase of 180 degrees, the output terminal y is used to output the divided clock signal clk90 with a phase of 90 degrees, and the output terminal yz is used to output the divided clock signal clk270 with a phase of 270 degrees; the input terminal a of the CML latch Latch R is used to input the divided clock signal clk270 with a phase of 270 degrees, the input terminal az is used to input the divided clock signal clk90 with a phase of 90 degrees, the output terminal y is used to output the divided clock signal clk0 with a phase of 0 degrees, and the output terminal yz is used to output the divided clock signal clk180 with a phase of 180 degrees.

8. An electronic device comprising a device body and a circuit module disposed in the device body, characterized in that: The circuit module includes the CML latch hardened against single event upset according to any one of claims 1 to 5.

Images