Apparatus, method and semiconductor device for reducing current slew rate

Abstract

The present disclosure provides a device, a method and a semiconductor device for reducing current change rate, relates to the technical field of semiconductors, and particularly relates to the fields of semiconductor chips, artificial intelligence chips, power control and the like. The implementation scheme is: a virtual data generator configured to generate virtual data that changes with clock cycles; a signal injection controller configured to activate a power maintenance flag signal for providing to a dynamic power logic circuit in a first period and a second period, and control the virtual data to be provided to the dynamic power logic circuit, deactivate the power maintenance flag signal in a third period, and control the data load to be provided to the dynamic power logic circuit; and a multiplexer configured to provide the virtual data to the dynamic power logic circuit in the first period and the second period based on the control of the signal injection controller, and provide the data load to the dynamic power logic circuit in the third period.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, in particular to the fields of semiconductor chips, artificial intelligence (AI) chips, power control, and more particularly to an apparatus, method, and semiconductor device for reducing the current change rate. Background Art

[0002] At advanced process nodes like 28nm, the problem of chip current change rate (di / dt) is becoming increasingly prominent. This is especially true in high-computing, high-integration scenarios. Issues like power supply noise and signal integrity caused by this current change rate can severely impact chip performance and reliability. Furthermore, it can cause localized hotspots and reduce chip lifespan. For example, because AI chips can consume hundreds of watts of instantaneous power at peak computing power, voltage fluctuations caused by this current change rate can trigger resets or logic errors. Summary of the Invention

[0003] The present disclosure provides an apparatus, method, and semiconductor device for reducing a current variation rate.

[0004] According to one aspect of the present disclosure, a device for reducing a current change rate is provided, which is applied to a dynamic power logic circuit that processes a data load. The device includes: a dummy data generator configured to generate dummy data that changes with a clock cycle; a signal injection controller configured to activate a power maintenance flag signal for providing to the dynamic power logic circuit during a first period and a second period, and control the provision of the dummy data to the dynamic power logic circuit, and to deactivate the power maintenance flag signal during a third period, and control the provision of the data load to the dynamic power logic circuit, wherein activation of the power maintenance flag signal is used to instruct a first logic circuit portion associated with an intermediate storage in the dynamic power logic circuit not to perform a data update based on the dummy data, while a second logic circuit portion other than the first logic circuit portion in the dynamic power logic circuit is to perform a data update based on the dummy data, the first period includes a data pause period of the data load, the second period includes a data constant period of the data load, and the third period includes a data change period of the data load other than the data pause period and the data constant period; and a multiplexer configured to, based on control of the signal injection controller, provide the dummy data to the dynamic power logic circuit during the first period and the second period, and provide the data load to the dynamic power logic circuit during the third period.

[0005] In some embodiments, the signal injection controller is further configured to activate a data valid flag signal provided to the dynamic power logic circuit during the second time period, wherein activation of the data valid flag signal is used to instruct the first logic circuit portion in the dynamic power logic circuit to perform a data update based on a previous intermediate storage value.

[0006] In some embodiments, the signal injection controller is further configured to activate the power maintenance flag signal in a fourth period and control the gradual provision of dummy data to the dynamic power logic circuit, wherein the fourth period includes a warm-up period before the data load reaches the dynamic power logic circuit.

[0007] In some embodiments, the second logic circuit portion in the dynamic power logic circuit includes a plurality of sub-cells, wherein the signal injection controller is configured to gradually provide the dummy data to a predetermined number of the plurality of sub-cells based on a predetermined time interval.

[0008] In some embodiments, the signal injection controller is further configured to phase out providing the dummy data to a predetermined number of sub-units based on a predetermined time interval when the data payload ends.

[0009] In some embodiments, the first logic circuit portion of the dynamic power logic circuit includes an accumulator and the second logic circuit portion includes a multiply-accumulator.

[0010] According to another aspect of the present disclosure, a method for reducing the current change rate is provided, which is applied to a dynamic power logic circuit that processes a data load, including: generating virtual data that changes with a clock cycle; activating a power maintenance flag signal for providing to the dynamic power logic circuit in a first time period and a second time period, and controlling the provision of the virtual data to the dynamic power logic circuit, wherein activation of the power maintenance flag signal is used to indicate that a first logic circuit portion associated with an intermediate storage in the dynamic power logic circuit does not perform data updates based on the virtual data, while a second logic circuit portion other than the first logic circuit portion in the dynamic power logic circuit performs data updates based on the virtual data, the first time period includes a data pause period of the data load, and the second time period includes a data constant period of the data load; and deactivating the power maintenance flag signal in a third time period, and controlling the provision of the data load to the dynamic power logic circuit, wherein the third time period includes a data change period of the data load other than the data pause period and the data constant period.

[0011] In some embodiments, the method further includes: activating a data valid flag signal provided to the dynamic power logic circuit during the second time period, wherein activation of the data valid flag signal is used to instruct the first logic circuit portion in the dynamic power logic circuit to perform data update based on the last intermediate storage value.

[0012] In some embodiments, the method further includes: activating a power maintenance flag signal in a fourth time period, and controlling the gradual provision of virtual data to the dynamic power logic circuit, wherein the fourth time period includes a preheating period before the data load reaches the dynamic power logic circuit, and during the preheating period, the virtual data is gradually provided to a predetermined number of sub-units among the multiple sub-units included in the second logic circuit part based on a predetermined time interval.

[0013] According to another aspect of the present disclosure, a semiconductor device is provided, including: a dynamic power logic circuit for processing a data load; and the apparatus for reducing a current change rate as described above.

[0014] According to one or more embodiments of the present disclosure, a dynamic power logic circuit can be maintained at a higher power consumption by utilizing changing virtual data, thereby reducing power consumption jitter and further reducing the current variation rate.

[0015] These and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings illustrate exemplary embodiments and constitute a part of the specification. Together with the text of the specification, they are used to explain exemplary implementation of the embodiments. The embodiments shown are for illustrative purposes only and do not limit the scope of the present disclosure. In all figures, the same reference numerals refer to similar, but not necessarily identical, elements.

[0017] Figure 1 is a schematic diagram illustrating an apparatus for reducing a current change rate according to an exemplary embodiment.

[0018] Figure 2 is a schematic diagram illustrating an apparatus for reducing a current change rate according to another exemplary embodiment.

[0019] Figure 3 is a flow chart illustrating a method for reducing a current change rate according to an exemplary embodiment.

[0020] Figure 4 is a schematic diagram illustrating a current change rate reduction effect according to an exemplary embodiment.

[0021] Figure 5 is a schematic diagram illustrating a semiconductor device according to an exemplary embodiment. DETAILED DESCRIPTION

[0022] The following description of exemplary embodiments of the present disclosure is made in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be appreciated by those skilled in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0023] In this disclosure, unless otherwise specified, the use of terms such as "first" and "second" to describe various elements is not intended to limit the positional relationship, temporal relationship, or importance relationship of these elements. Such terms are only used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of the element, while in some cases, based on the context of the description, they may also refer to different instances.

[0024] The terms used in the description of the various examples described in this disclosure are for the purpose of describing specific examples only and are not intended to be limiting. Unless the context clearly indicates otherwise, if the number of elements is not specifically limited, the element can be one or more. As used herein, the term "plurality" means two or more, and the term "based on" should be interpreted as "based at least in part on". In addition, the terms "and / or" and "at least one of..." cover any one of the listed items and all possible combinations.

[0025] Conventional methods for reducing the rate of current change typically involve detecting current or voltage changes during chip operation and then making adjustments. This process is often relatively lengthy, ultimately impacting the current rate of change. This is because by the time a current or voltage change is detected, the current has already changed, and even adjustments made will experience a lag.

[0026] To this end, the embodiments of the present disclosure provide a more effective method for reducing the current change rate, which can achieve adjustment at the clock cycle level and continuously maintain the power in a relatively stable state, thereby significantly reducing the impact of the current change rate.

[0027] Figure 1 is a schematic diagram illustrating an apparatus 100 for reducing a current change rate according to an exemplary embodiment.

[0028] The apparatus 100 is applied to a dynamic power logic circuit 110. The dynamic power logic circuit 110 is configured to process a data load (Data_workload). For example, the dynamic power logic circuit 110 may be a high-power unit in a semiconductor chip, such as a GPU. The embodiments of the present disclosure reduce power consumption jitter and thus current variation by continuously maintaining the dynamic power logic circuit 110 at a high power consumption.

[0029] like Figure 1 As shown, the apparatus 100 includes a virtual data generator 101 , a signal injection controller 102 and a multiplexer 103 .

[0030] The dummy data generator 101 is configured to generate dummy data Data_dummy that varies with a clock cycle.

[0031] In an example, the dummy data generator 101 may include a module for generating data having different values ​​in each clock cycle, such as a linear feedback shift register (LFSR), a shifter, a counter, etc. Since data flips may occur in the changing data, such data flips may cause power consumption. Therefore, the changing dummy data Data_dummy may be used to maintain a higher power consumption of the dynamic power logic circuit 110.

[0032] In the embodiment of the present disclosure, in order to indicate that the dummy data Data_dummy is invalid data, an additional flag signal is required for identification. Such a flag signal is referred to as a power maintenance flag signal herein. Figure 1 The power maintenance flag signal BurnFlag shown in FIG. 8 is used to indicate that the dummy data Data_dummy is used to maintain power consumption, rather than being real data used for actual processing operations.

[0033] Accordingly, the signal injection controller 102 is configured to activate the power maintenance flag signal BurnFlag for providing to the dynamic power logic circuit 110 during a first period and a second period, and control the provision of dummy data Data_dummy to the dynamic power logic circuit 110. The first period includes a data pause period of the data load Data_workload, and the second period includes a data constant period of the data load Data_workload.

[0034] In this example, the data load Data_workload does not necessarily have data sent to the dynamic power logic circuit 110 in every clock cycle. Such a period when no data is sent may be referred to herein as a data pause period. In addition, the data load Data_workload does not necessarily have data changes in every clock cycle. Such a period when data does not change may be referred to herein as a data constant period.

[0035] Due to the lack of data flipping during both the data pause period and the data constant period, the dynamic power logic circuit 110 may not be able to maintain high power consumption. Therefore, in the embodiment of the present disclosure, during the data pause period and the data constant period, dummy data Data_dummy is provided to the dynamic power logic circuit 110 under the control of the signal injection controller 102 instead of the data load Data_workload. Because the dummy data Data_dummy has the characteristic of varying with the clock cycle, it is possible to ensure that the dynamic power logic circuit 110 can maintain high power consumption even during periods such as the data pause period and the data constant period.

[0036] In an embodiment of the present disclosure, the dynamic power logic circuit 110 includes a first logic circuit portion 110a and a second logic circuit portion 110b. The first logic circuit portion 110a is associated with intermediate storage, such as for intermediate state storage or intermediate data storage. The currently stored content is associated with the next input content for data update. In other words, data updates by the first logic circuit portion 110a result in substantial data processing results. For example, the first logic circuit portion 110a may include logic circuits related to the cache's LRU (Least Recently Used) algorithm, logic circuits related to random access memory (RAM) macrocells, and logic circuits related to functions such as registering and accumulation. The portion of the dynamic power logic circuit 110 other than the first logic circuit portion 110a may be referred to as the second logic circuit portion 110b. The content generated by the data update by the second logic circuit portion 110b is stored in the first logic circuit portion 110a and associated with the next input content. Therefore, the generated content itself does not result in substantial data processing results. For example, the second logic circuit portion 110b may include logic circuits related to calculation or operation, etc. In this document, data update refers to generating new data content after processing data.

[0037] Accordingly, the activation of the power maintenance flag signal BurnFlag instructs the first logic circuit portion 110a not to perform data updates based on the dummy data Data_dummy, while the second logic circuit portion 110b performs data updates based on the dummy data Data_dummy. This means that the first logic circuit portion 110a should not be affected by the dummy data Data_dummy and will not actually generate actual data content based on the dummy data Data_dummy. The second logic circuit portion 110b can use the dummy data Data_dummy to maintain higher power consumption, and the data content it generates will not cause any substantial data processing results. As a result, the dynamic power logic circuit 110 can maintain higher power consumption.

[0038] Meanwhile, the signal injection controller 102 is configured to deactivate the power sustaining flag signal BurnFlag in the third period and control the data load Data_workload to be provided to the dynamic power logic circuit 110. The third period includes a data intermittent period of the data load Data_workload and a data change period outside the data constant period.

[0039] When the data load Data_workload itself has data changes, power consumption may be maintained without the aid of the dummy data Data_dummy, and thus the power maintenance flag signal BurnFlag is deactivated during this period.

[0040] In an example, the power maintenance flag signal BurnFlag may be represented by one bit, for example, a high level may indicate activation, and a low level may indicate deactivation.

[0041] like Figure 1 As shown, the data load Data_workload is also transmitted to the signal injection controller 102. Thus, the signal injection controller 102 can determine whether the current period belongs to the first period, the second period, or the third period based on the data load Data_workload. Furthermore, an appropriate strategy can be used to control the corresponding period to maintain a higher power consumption of the dynamic power logic circuit 110.

[0042] Accordingly, the multiplexer 103 is configured to provide the dummy data Data_dummy to the dynamic power logic circuit 110 in the first and second periods, and provide the data load Data_workload to the dynamic power logic circuit 110 in the third period based on the control of the signal injection controller 102 .

[0043] In an example, the data load Data_workload can be transmitted to the multiplexer 103 via the data pipe 120. The dummy data generator 101 can directly transmit the generated dummy data Data_dummy to the multiplexer 103. When the signal injection controller 102 determines that the current period belongs to the first time period or the second time period, it controls the multiplexer 103 to provide the dummy data Data_dummy to the dynamic power logic circuit 110. When the signal injection controller 102 determines that the current period belongs to the third time period, it controls the multiplexer 103 to provide the data load Data_workload to the dynamic power logic circuit 110.

[0044] Therefore, if Figure 1 The apparatus 100 shown can utilize the changing dummy data Data_dummy to maintain the dynamic power logic circuit 110 at a higher power consumption, thereby reducing power consumption jitter and further reducing the current variation rate.

[0045] In some embodiments, as Figure 2 As shown, the signal injection controller 102 may be further configured to activate, during the second period, a data valid flag signal ValidFlag provided to the dynamic power logic circuit 110. Activation of the data valid flag signal ValidFlag is used to instruct the first logic circuit portion 110a in the dynamic power logic circuit 110 to perform data update based on the last intermediate stored value.

[0046] As mentioned above, in the second period related to the data constant period, the signal injection controller 102 is configured to activate the power maintenance flag signal BurnFlag and control the provision of the virtual data Data_dummy to the dynamic power logic circuit 110, which also means that in the second period, the power maintenance flag signal BurnFlag and the data valid flag signal ValidFlag can be activated at the same time.

[0047] In an example, the data valid flag signal ValidFlag, similar to the power sustaining flag signal BurnFlag, may also be represented by one bit. For example, a high level may indicate activation, and a low level may indicate deactivation.

[0048] In an example, the power maintenance flag signal BurnFlag and the data valid flag signal ValidFlag may also be included in one signal and represented by two bits. For example, the power maintenance flag signal BurnFlag may be represented by the first bit, and the data valid flag signal ValidFlag may be represented by the second bit.

[0049] Because the second period is associated with a data-constant period, dynamic power logic circuit 110 needs to process the data payload, Data_workload. However, since the data does not change during this period, to maintain high power consumption for dynamic power logic circuit 110, changing dummy data, Data_dummy, can be used for second logic circuit portion 110b, while first logic circuit portion 110a is updated based on the last intermediate stored value to ensure actual data processing. This takes advantage of the fact that the data payload, Data_workload, remains the same during each clock cycle during the second period, so first logic circuit portion 110a only needs to update data based on the last stored value.

[0050] In this manner, when the data in the data load Data_workload remains unchanged, the introduction of the further data valid flag signal ValidFlag provides an opportunity to replace the unchanged data with the changed dummy data Data_dummy. This allows the dynamic power logic circuit 110 to maintain a higher power consumption to reduce the current change rate through the dummy data Data_dummy, while also enabling the data load Data_workload to be processed effectively.

[0051] In some embodiments, the signal injection controller 102 may be further configured to activate the power sustaining flag signal BurnFlag during a fourth period and control the gradual provision of dummy data Data_dummy to the dynamic power logic circuit 110 . The fourth period may include a warm-up period before the data load Data_workload reaches the dynamic power logic circuit 110 .

[0052] In an example, the preheating period may also be referred to as a warm-up period, and is used to indicate a specific period of time before the data load Data_workload is actually transmitted to the dynamic power logic circuit 110. In one case, the dynamic power logic circuit 110 may know that the data load Data_workload has begun to be transmitted to it through a signal indicating the start of the data load Data_workload, but may not actually reach the dynamic power logic circuit 110 due to certain circuit delays. Therefore, the period of time before the data load Data_workload actually reaches the dynamic power logic circuit 110 is the preheating period. In another case, when the dynamic power logic circuit 110 is enabled to operate, it may directly enter the preheating period.

[0053] Regardless of the situation, in the fourth period related to the preheating period, similar to the first period related to the data pause period and the second period related to the data constant period, the control strategy is to activate the power maintenance flag signal BurnFlag and control the provision of dummy data Data_dummy to the dynamic power logic circuit 110. This is because there is a lack of changing data at this time, and therefore the dummy data Data_dummy is required to maintain the dynamic power logic circuit 110 at a higher power consumption.

[0054] Furthermore, in this embodiment, gradually providing the dummy data Data_dummy to the dynamic power logic circuit 110 means gradually controlling the activation of the second logic circuit portion 110b from a smaller number to a larger number of the second logic circuit portion 110b in the dynamic power logic circuit 110. For example, the injection rate of the dummy data Data_dummy can be set by software, such as 75%, which indicates that a maximum of 75% of the second logic circuit portion 110b can be activated.

[0055] Therefore, the embodiment of the present disclosure also takes into account the preheating period when the data load Data_workload has not yet arrived, and similarly uses the changing dummy data Data_dummy to maintain the dynamic power logic circuit 110 at a higher power consumption, thereby reducing power consumption jitter and further reducing the current variation rate.

[0056] In some embodiments, the second logic circuit portion 110b in the dynamic power logic circuit 110 may include a plurality of sub-units. The signal injection controller 102 may be configured to gradually provide the dummy data Data_dummy to a predetermined number of the sub-units based on a predetermined time interval.

[0057] In this example, in addition to setting the injection rate through software, the predetermined time interval, i.e., the time step, can also be set through software, such as 20 clock cycles, which means that the dummy data Data_dummy is provided to more sub-units every 20 clock cycles. For example, still taking the injection rate as 75% as an example, assuming that the second logic circuit part 110b includes four sub-units, then one more sub-unit can be activated in each time step, such as providing the dummy data Data_dummy to one sub-unit in the first time step, providing the dummy data Data_dummy to two sub-units in the second time step, and providing the dummy data Data_dummy to three sub-units in the third time step. In other words, at most 75% of the four sub-units, i.e., the predetermined number of sub-units, are activated.

[0058] Therefore, even in the fourth period related to the preheating period, the control strategy can be used to basically maintain the power consumption at a certain higher level. For example, when the injection rate is 75%, the power consumption can be basically maintained at 75% of the peak power consumption to reduce the current change rate.

[0059] In some embodiments, the signal injection controller 102 may be further configured to gradually stop providing the dummy data Data_dummy to a predetermined number of sub-units based on a predetermined time interval when the data load Data_workload ends.

[0060] In this example, the signal injection controller 102 may receive a signal indicating the end of the data load Data_workload. The process of gradually canceling the provision of the dummy data Data_dummy may be the opposite of the activation process described above from one subunit to three subunits. That is, the process may be reduced from three subunits to two subunits in the first time step, then from two subunits to one subunit in the second time step, and finally, the process may be canceled from all subunits in the third time step. At this point, the dummy data generator 101 may also be turned off, and the system may continue to wait for the next warm-up period.

[0061] Therefore, even when the data load Data_workload ends, the power consumption can still be maintained at a relatively stable state by gradually reducing the number of activated sub-units in the second logic circuit part 110b, thereby reducing the current change rate.

[0062] In some embodiments, the first logic circuit portion 110 a of the dynamic power logic circuit 110 may include an accumulator, and the second logic circuit portion 110 b may include a multiplier-accumulator.

[0063] The following will be combined Figure 2 The operation of the apparatus 100 for reducing the current change rate according to the embodiment of the present disclosure is further described when the dynamic power logic circuit 110 includes an accumulator and a multiplier-accumulator.

[0064] Figure 2 is a schematic diagram illustrating an apparatus 100 for reducing a current change rate according to another exemplary embodiment.

[0065] In this embodiment, if Figure 2 As shown, Figure 1Similar features of the apparatus 100 will not be described in detail, such as the dummy data generator 101, the signal injection controller 102, the multiplexer 103, the data pipe 120, the data load Data_workload, the dummy data Data_dummy, the power maintenance flag signal BurnFlag, and the data valid flag signal ValidFlag. Instead, the description will focus on the exemplary operation of the apparatus 100 when the dynamic power logic circuit 110 includes an accumulator and a multiplier-accumulator. For illustrative purposes, this embodiment is described using the example of the second logic circuit portion 110b including four multipliers (i.e., a first multiplier-accumulator 1101, a second multiplier-accumulator 1102, a third multiplier-accumulator 1103, and a fourth multiplier-accumulator 1104) and the first logic circuit portion 110a including one accumulator 1105. However, the apparatus 100 for reducing the current change rate according to the disclosed embodiments is not limited to application to the dynamic power logic circuit 110 shown.

[0066] Before the data load Data_workload reaches the dynamic power logic circuit 110, the injection rate of the dummy data Data_dummy can be first set to 75% through software, that is, at most three multiplier accumulators among the first multiplier accumulator 1101, the second multiplier accumulator 1102, the third multiplier accumulator 1103 and the fourth multiplier accumulator 1104 are activated when the data load Data_workload has not arrived.

[0067] First, when entering the preheating stage, the signal injection controller 102 may begin to gradually send the dummy data Data_dummy into the first multiplication accumulator 1101, the second multiplication accumulator 1102, the third multiplication accumulator 1103, and the fourth multiplication accumulator 1104. For example, when the time step is 20 cycles, one more multiplication accumulator may be activated every 20 clock cycles. For example, the first multiplication accumulator 1101 may be activated first in the first 20 clock cycles, and then the second multiplication accumulator 1102 may be further activated in the next 20 clock cycles, and so on. However, since the injection rate is preset to 75%, a maximum of three multiplication accumulators may be activated, such as the first multiplication accumulator 1101, the second multiplication accumulator 1102, and the third multiplication accumulator 1103, thereby maintaining the power consumption at 75% of the peak power consumption. The activated first multiplier-accumulator 1101, second multiplier-accumulator 1102, and third multiplier-accumulator 1103 can pass the received power maintenance flag signal BurnFlag to the accumulator 1105. Upon receiving the power maintenance flag signal BurnFlag, the accumulator 1105 knows not to perform the accumulation operation to avoid affecting the actual operation result.

[0068] Next, when the data load Data_workload arrives, the signal injection controller 102 can control the multiplexer 103 to transmit the data load Data_workload to the first multiplication and accumulation device 1101, the second multiplication and accumulation device 1102, the third multiplication and accumulation device 1103, and the fourth multiplication and accumulation device 1104, while deactivating the power maintenance flag signal BurnFlag. Accordingly, the first multiplication and accumulation device 1101, the second multiplication and accumulation device 1102, the third multiplication and accumulation device 1103, and the fourth multiplication and accumulation device 1104 operate normally and send the operation results to the accumulator 1105 for accumulation. Since the data in the data load Data_workload is usually changing, that is, it is usually in a data change period, it is not necessary to rely on the virtual data Data_dummy to maintain high power consumption.

[0069] However, since the data load Data_workload does not necessarily have data sent to the multiplier accumulator in every clock cycle, during such a data pause period, the signal injection controller 102 can also control the multiplexer 103 at this time to replace the input data with dummy data Data_dummy to transmit it to up to three of the four multiplier accumulators, such as the first multiplier accumulator 1101, the second multiplier accumulator 1102, and the third multiplier accumulator 1103, and activate the power maintenance flag signal BurnFlag at the same time. When the power maintenance flag signal BurnFlag is activated, the accumulator 1105 will not accumulate the operation results of the first multiplier accumulator 1101, the second multiplier accumulator 1102, and the third multiplier accumulator 1103. Therefore, during the data pause period, the dummy data Data_dummy can still be used to maintain higher power consumption to reduce the current change rate without affecting the actual operation results.

[0070] On the other hand, when the signal injection controller 102 detects that the data load Data_workload has not changed for a long time, such as there has been no data change for five clock cycles, it can also control the multiplexer 103 during such a constant data period to replace the input data with virtual data Data_dummy to transmit it to the first multiplier accumulator 1101, the second multiplier accumulator 1102, the third multiplier accumulator 1103 and the fourth multiplier accumulator 1104, and at the same time activate both the power maintenance flag signal BurnFlag and the data valid flag signal ValidFlag. In this case, the first multiplication and accumulation unit 1101, the second multiplication and accumulation unit 1102, the third multiplication and accumulation unit 1103, and the fourth multiplication and accumulation unit 1104 can maintain higher power consumption through the dummy data Data_dummy, and the accumulator 1105 knows that it needs to perform a normal accumulation operation due to the activation of the data valid flag signal ValidFlag, but the accumulation operation can be performed based on the previous intermediate storage value, because the data load Data_workload received by the first multiplication and accumulation unit 1101, the second multiplication and accumulation unit 1102, the third multiplication and accumulation unit 1103, and the fourth multiplication and accumulation unit 1104 is the same as that of the previous clock cycle. Therefore, in the data constant period, the dummy data Data_dummy can still be used to maintain higher power consumption to reduce the current change rate without affecting the actual operation results.

[0071] Finally, when the data load Data_workload ends, for example, when the signal injection controller 102 receives the end signal, it can gradually reduce the activation of the first multiplication and accumulation unit 1101, the second multiplication and accumulation unit 1102, the third multiplication and accumulation unit 1103, and the fourth multiplication and accumulation unit 1104 according to the above time step. After all the first multiplication and accumulation units 1101, the second multiplication and accumulation units 1102, the third multiplication and accumulation units 1103, and the fourth multiplication and accumulation units 1104 are deactivated, the virtual data generator 101 can stop operating. Accordingly, the signal injection controller 102 can wait for the next warm-up phase to arrive.

[0072] Figure 3 is a flow chart illustrating a method for reducing a current change rate according to an exemplary embodiment.

[0073] like Figure 3 As shown, although Figure 3 The example of executing steps S303 and S304 in parallel is used for illustration, but the scope of the present disclosure is not limited thereto. Steps S303 and S304 may be executed in a sequential order, which depends on the order in which the first time period, the second time period, and the third time period appear.

[0074] In step S301 , dummy data that varies with clock cycles is generated.

[0075] In step S303, a power maintenance flag signal is activated during a first period and a second period for providing the dynamic power logic circuit, and dummy data is provided to the dynamic power logic circuit. The first period includes a data pause period for the data payload, and the second period includes a data constant period for the data payload. Activation of the power maintenance flag signal instructs a first logic circuit portion associated with the intermediate storage in the dynamic power logic circuit not to perform data updates based on the dummy data, while a second logic circuit portion of the dynamic power logic circuit, excluding the first logic circuit portion, to perform data updates based on the dummy data.

[0076] In some embodiments, a data valid flag signal provided to the dynamic power logic circuit may be activated during the second period to instruct the first logic circuit portion in the dynamic power logic circuit to perform data update based on the last intermediate storage value.

[0077] In step S304, the power maintenance flag signal is deactivated during the third period, and the data load is controlled to be provided to the dynamic power logic circuit. The third period includes a data change period of the data load except for the data intermittent period and the data constant period.

[0078] In some embodiments, step S302 may be performed before steps S303 and S304. In step S302, a power maintenance flag signal may be activated during a fourth period, and dummy data may be gradually provided to the dynamic power logic circuit. The fourth period includes a warm-up period before data load reaches the dynamic power logic circuit. During the warm-up period, dummy data is gradually provided to a predetermined number of sub-units of the plurality of sub-units included in the second logic circuit portion based on predetermined time intervals.

[0079] like Figure 3 The details of various aspects of the method for reducing the current change rate shown can also be referred to as Figure 1 and Figure 2 The present invention can be understood from the device for reducing the current change rate shown in the figure, so it will not be described here in detail.

[0080] Figure 4 is a schematic diagram illustrating a current change rate reduction effect according to an exemplary embodiment.

[0081] like Figure 4 As shown, the first curve on the left can represent the slope change of the current change rate under the traditional method or the uncontrolled current change rate, while the second curve on the right can represent the slope change of the current change rate controlled by the device and method according to the embodiment of the present disclosure. Figure 4As can be seen in the figure, the steepness of the slope of the current change rate has been significantly reduced. This is due to the clock cycle-level adjustment mechanism provided by the embodiment of the present disclosure, which can continuously maintain power consumption in a relatively stable state. As a result, the impact of the current change rate on chip operation can be greatly reduced.

[0082] Figure 5 is a schematic diagram illustrating a semiconductor device according to an exemplary embodiment.

[0083] In the embodiments of the present disclosure, the semiconductor device may include, for example, a semiconductor chip. Figure 5 As shown, a semiconductor device may include a dynamic power logic circuit that processes data loads and an apparatus for reducing the current change rate as described above. The dynamic power logic circuit may be, for example, a high-power unit in a semiconductor chip that consumes high power, such as a GPU. According to the mechanism for reducing the current change rate provided by the embodiments of the present disclosure, the dynamic power logic circuit can maintain a higher power consumption, thereby reducing power consumption jitter and, in turn, reducing the current change rate.

[0084] While the disclosure has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative and exemplary and not restrictive, and the disclosure is not limited to the disclosed embodiments.

Claims

1. A device for reducing the rate of change of current, applied to a dynamic power logic circuit for processing data loads, characterized in that: The device comprises: a dummy data generator configured to generate dummy data that varies with a clock cycle; a signal injection controller configured to activate a power maintenance flag signal for providing to the dynamic power logic circuit during a first time period and a second time period, and control providing the dummy data to the dynamic power logic circuit, and to deactivate the power maintenance flag signal during a third time period, and control providing the data payload to the dynamic power logic circuit, wherein activation of the power maintenance flag signal is used to instruct a first logic circuit portion associated with an intermediate storage in the dynamic power logic circuit not to perform data update based on the dummy data, while a second logic circuit portion other than the first logic circuit portion in the dynamic power logic circuit performs data update based on the dummy data, the first time period includes a data pause period of the data payload, the second time period includes a data constant period of the data payload, and the third time period includes a data change period of the data payload other than the data pause period and the data constant period; and a multiplexer configured to provide the dummy data to the dynamic power logic circuit during the first period and the second period, and to provide the data load to the dynamic power logic circuit during the third period, based on control of the signal injection controller; The signal injection controller is further configured to activate a data valid flag signal provided to the dynamic power logic circuit during the second time period, wherein activation of the data valid flag signal is used to instruct the first logic circuit portion in the dynamic power logic circuit to perform data update based on the last intermediate storage value.

2. The device according to claim 1, characterized in that The signal injection controller is further configured to activate the power maintenance flag signal during a fourth period and control the gradual provision of the dummy data to the dynamic power logic circuit, wherein the fourth period includes a warm-up period before the data load reaches the dynamic power logic circuit.

3. The device according to claim 2, characterized in that The second logic circuit portion in the dynamic power logic circuit includes a plurality of sub-units, wherein the signal injection controller is configured to gradually provide the dummy data to a predetermined number of sub-units among the plurality of sub-units based on a predetermined time interval.

4. The device according to claim 3, characterized in that The signal injection controller is further configured to gradually stop providing the dummy data to the predetermined number of sub-units based on the predetermined time interval when the data load ends.

5. The device according to any one of claims 1 to 4, characterized in that The first logic circuit portion of the dynamic power logic circuit includes an accumulator, and the second logic circuit portion includes a multiply-accumulator.

6. A method for reducing the rate of change of current, applied to a dynamic power logic circuit processing a data load, characterized in that: The method comprises: Generate virtual data that changes with clock cycles; activating a power maintenance flag signal for providing to the dynamic power logic circuit during a first period and a second period, and controlling the provision of the dummy data to the dynamic power logic circuit, wherein activation of the power maintenance flag signal is used to instruct a first logic circuit portion associated with an intermediate storage in the dynamic power logic circuit not to perform data update based on the dummy data, while a second logic circuit portion other than the first logic circuit portion in the dynamic power logic circuit performs data update based on the dummy data, the first period including a data pause period of the data payload, and the second period including a data constant period of the data payload; and deactivating the power maintenance flag signal during a third period, and controlling the data load to be provided to the dynamic power logic circuit, wherein the third period includes a data change period of the data load excluding the data intermittent period and the data constant period; The method further comprises: During the second period, a data valid flag signal provided to the dynamic power logic circuit is activated, wherein activation of the data valid flag signal is used to instruct the first logic circuit portion in the dynamic power logic circuit to perform data update based on a previous intermediate storage value.

7. The method according to claim 6, characterized in that The method further comprises: The power maintenance flag signal is activated in a fourth time period, and the dummy data is controlled to be gradually provided to the dynamic power logic circuit, wherein the fourth time period includes a warm-up period before the data load reaches the dynamic power logic circuit, and during the warm-up period, the dummy data is gradually provided to a predetermined number of sub-units among the plurality of sub-units included in the second logic circuit portion based on a predetermined time interval.

8. A semiconductor device, characterized in that: The semiconductor device comprises: Dynamic power logic circuitry to process the data payload; and The device for reducing the rate of change of current according to any one of claims 1 to 5.

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