Multi-channel ultra-low noise phase synchronization frequency selectable clock synthesis device

Abstract

The invention belongs to the technical field of measurement and testing, and relates to a multichannel ultra-low noise phase synchronization frequency selectable clock synthesis device. The device comprises an ultra-low phase noise frequency multiplication unit, an analog discrete phase-locked loop unit, a frequency mixing filtering unit and a multi-path synchronous power division unit which are connected in sequence. An analog microwave device is selected, so that the phase noise influence of a digital device on a clock signal is avoided; and meanwhile, a plurality of analog discrete phase-locked loops are adopted to realize an ultra-low phase noise clock signal, frequency mixing and filtering are performed to obtain a clock signal with the required frequency, and the phase is synchronized with an external reference clock. Functional unitization is carried out, the design logic is clear, and combination design is facilitated.

Description

Technical Field

[0001] The invention belongs to the technical field of measurement and testing, and relates to a multi-channel ultra-low noise phase synchronization frequency selectable clock synthesis device. Background Art

[0002] Ultra-low phase noise clock synthesis technology is a core technology in high-frequency communications, radar detection, navigation and positioning, and precision measurement. Its core goal is to significantly reduce the phase noise of clock signals by optimizing signal generation and control methods, thereby improving system sensitivity, resolution, and reliability. Commonly used methods include direct frequency multiplication, phase-locked loops, digital synthesis, and hybrid architectures. Emerging approaches include photonic frequency synthesis and re-division, catering to diverse application scenarios. Each technology is selected based on comprehensive considerations, such as phase noise, phase synchronization, frequency tunability, and circuit complexity, to determine the most appropriate clock synthesis method.

[0003] Among the currently commonly used sampling clock synthesis methods, the direct frequency multiplication method has the simplest logic. The principle diagram is shown in the attached figure. Figure 1 As shown in the figure, the reference clock is multiplied, filtered, and amplified multiple times to obtain the sampling clock of the required frequency. In order to simplify the clock multiplication level, a phase-locked loop circuit can be selected. The principle diagram is shown in the attached figure. Figure 2 As shown in the figure, the output frequency of the voltage-controlled oscillator (VCO) is the same as the reference clock frequency after passing through a frequency divider (the frequency division ratio can be adjusted including integer or fractional mode). After passing through the phase detector, the output of the very low frequency signal is then filtered through the loop to tune the VCO, so that the VCO output frequency and the reference clock have a corresponding multiple relationship, thereby obtaining the required frequency sampling clock. In order to achieve fine frequency control, digital synthesis (DDS) can be selected. Since the DDS output frequency is relatively low, it is generally used with a phase-locked loop to output the required sampling clock. The principle diagram is shown in the attached figure. Figure 3 As shown in Figure 1, DDS can finely adjust the reference frequency, thereby changing the VCO output frequency. Emerging methods include photonic frequency synthesis, which uses optical frequency comb technology based on silicon nitride photonic chips to generate microwave signals ranging from MHz to over 100 GHz using on-chip microcomb oscillators.

[0004] The output clock frequency of the direct frequency multiplication solution is fixed, and the phase noise index at the far end is poor; the phase-locked loop solution can adjust the output frequency of the broadband VCO through feedback division, directly locking from low frequency to high frequency, and the phase noise at the near end is poor; the DDS and phase-locked loop solution facilitates fine adjustment of the sampling clock, but also has poor near-end phase noise; the photon frequency synthesis solution involves optoelectronic technology and has very high requirements for devices, so it is not widely used at present. Summary of the Invention

[0005] The present invention aims to address the need for multi-channel synchronous ultra-low phase noise sampling clocks with multiple frequencies in a broadband multi-channel transceiver system. The invention provides a multi-channel ultra-low noise phase-synchronized frequency-selectable clock synthesis device. The device comprises an ultra-low phase noise multiplication unit, an analog discrete phase-locked loop unit, a frequency mixing and filtering unit, and a multi-channel synchronous power splitter unit, which are connected in sequence. The ultra-low phase noise multiplication unit multiplies the input ultra-low phase noise reference clock. The analog discrete phase-locked loop unit divides the corresponding frequency signal from the mid-power of the frequency multiplication unit according to the frequency division to use as a phase-locked reference, outputting signals of different frequencies. The clock signal output by the analog discrete phase-locked loop unit is input to the frequency mixing and filtering unit, which, after frequency mixing, outputs signals of multiple frequencies. Unwanted frequency signals are then filtered through a bandpass filter to obtain the desired ultra-low phase noise sampling clock signal of one or more frequencies. Finally, the sampling clock signal output by the frequency mixing and filtering unit is distributed through the multi-channel synchronous power splitter unit, thereby obtaining the multi-channel synchronous ultra-low phase noise sampling clock required by the system.

[0006] Preferably, the frequency multiplication of each stage of the ultra-low phase noise multiplication unit is designed using the following method: first, the number of stages of the multiplication circuit and the multiples of each stage of multiplication need to be determined, and the output frequency of the phase-locked loop is obtained by calculation based on the frequency type of the sampling clock required by the system, and the frequency distribution of each stage of multiplication is further obtained.

[0007] Preferably, the voltage controlled oscillator in the analog discrete phase-locked loop unit has an extremely narrow bandwidth.

[0008] Preferably, the voltage controlled oscillator in the analog discrete phase-locked loop unit is a dielectric resonant oscillator.

[0009] Preferably, two or more analog discrete phase-locked loop units with different frequencies are designed as needed to output signals with different frequencies.

[0010] The present invention has the following beneficial effects: It uses only analog microwave components to avoid the phase noise impact of digital components on the clock signal; it also employs multiple analog discrete phase-locked loops to achieve an ultra-low phase-noise clock signal, which is then mixed and filtered to produce a clock signal of the desired frequency, all with phases synchronized with an external reference clock. The present invention also utilizes functional unitization, resulting in clear design logic and ease of combination design. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 Schematic diagram of direct frequency doubling method; Figure 2 is a schematic diagram of a phase-locked loop; Figure 3 This is a schematic diagram of DDS+phase-locked loop; Figure 4 This is a schematic diagram of the principle framework of the multi-channel synchronous ultra-low phase noise and frequency-selectable sampling clock device provided by the present invention. DETAILED DESCRIPTION

[0012] To facilitate understanding of the present invention, the present invention is described in more detail below with reference to the accompanying drawings and specific embodiments. Preferred embodiments of the present invention are shown in the accompanying drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described in this specification. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0013] The present invention provides a multi-channel synchronous ultra-low phase noise and frequency selectable sampling clock device, which solves the problem of the need for multi-channel synchronous ultra-low phase noise and multiple frequency sampling clocks in broadband multi-channel transceiver systems. The device consists of four units: an ultra-low phase noise frequency multiplication unit, an analog discrete phase-locked loop (APLL) unit, a mixing and filtering unit, and a multi-channel synchronous power splitter unit. Each unit circuit corresponds to different design requirements. The principle framework is shown in the attached figure. Figure 4 shown.

[0014] Among them, the ultra-low phase noise multiplication unit multiplies the input ultra-low phase noise reference clock. First, it is necessary to determine the number of stages of the multiplication circuit and the multiples of each stage. The compatible design can be considered based on the frequency type of the sampling clock required by the system. The output frequency of the phase-locked loop is obtained through calculation, and the frequency distribution design of each stage of the multiplication unit is further obtained.

[0015] The APLL unit divides the corresponding frequency signals (such as f1 and f2) from the intermediate power of the frequency multiplication unit according to the frequency division for phase-locked reference. The phase-locked loop avoids the use of frequency dividers, reducing the increase of phase noise. The VCO in the APLL has an extremely narrow bandwidth. It is recommended to use a dielectric resonant oscillator (DRO) to reduce the far-end phase noise while maintaining ultra-low phase noise at the near end. The APLL unit can be designed with two or even more different frequencies as needed to output signals of different frequencies, such as the attached Figure 4 f1 and f2 in .

[0016] The clock signal output by the APLL unit is input into the mixing and filtering unit. After mixing, it can output signals with frequencies of f1, f2, f1+f2, and f2-f1. Then, the signals with unnecessary frequencies are filtered out through a bandpass filter to obtain ultra-low phase noise sampling clock signals of one or more required frequencies. Finally, the signals are amplified and output.

[0017] The sampling clock signal output by the mixing and filtering unit is finally distributed through a multi-channel synchronous power division unit, thereby obtaining the multi-channel synchronous ultra-low phase noise sampling clock required by the system.

[0018] The design of each unit in this invention should be uniformly divided and designed based on the system's required clock frequency and phase noise, while also taking compatibility into consideration. For example, if two sampling clock frequencies, fc1 and fc2, are required, based on the principle of the mixer-filter unit, fc1 = f2 + f1 and fc2 = f2 - f1 can be considered, where f1 and f2 are the frequencies of the APLL unit. The frequency multiplication unit must design the signal outputs of f2 and f1.

Claims

1. A multi-channel ultra-low noise phase-synchronized frequency-selectable clock synthesis device, characterized by: It includes an ultra-low phase noise frequency multiplication unit, an analog discrete phase-locked loop unit, a mixing filter unit, and a multi-channel synchronous power division unit connected in sequence; the ultra-low phase noise frequency multiplication unit multiplies the input ultra-low phase noise reference clock; The analog discrete phase-locked loop unit extracts the corresponding frequency signal from the intermediate power of the frequency multiplication unit according to the frequency division method for phase-lock reference, and outputs signals of different frequencies. The clock signal output by the analog discrete phase-locked loop unit is input into the mixing and filtering unit, which outputs multiple frequency signals after mixing. The signals of unnecessary frequencies are then filtered out through a bandpass filter to obtain the ultra-low phase noise sampling clock signal of one or more required frequencies. Finally, the signal is amplified and output. The sampling clock signal output by the mixing and filtering unit is distributed through a multi-channel synchronous power division unit, thereby obtaining the multi-channel synchronous ultra-low phase noise sampling clock required by the system.

2. The multi-channel ultra-low noise phase-synchronized frequency-selectable clock synthesis device according to claim 1, characterized in that: The frequency multiplication of each stage of the ultra-low phase noise multiplication unit is designed using the following method: first, it is necessary to determine the number of stages of the multiplication circuit and the multiple of each stage of multiplication. Through the frequency type of the sampling clock required by the system, the output frequency of the phase-locked loop is calculated, and the frequency distribution of each stage of multiplication is further obtained.

3. The multi-channel ultra-low noise phase-synchronized frequency-selectable clock synthesis device according to claim 1, characterized in that: The voltage controlled oscillator in the analog discrete phase-locked loop unit has an extremely narrow bandwidth.

4. The multi-channel ultra-low noise phase-synchronized frequency-selectable clock synthesis device according to claim 1, characterized in that: The voltage controlled oscillator in the analog discrete phase-locked loop unit is a dielectric resonant oscillator.

5. The multi-channel ultra-low noise phase-synchronized frequency-selectable clock synthesis device according to claim 1, characterized in that: Design two or more analog discrete phase-locked loop units with different frequencies as needed to output signals of different frequencies.

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