Big endian infinite bandwidth network codec layer processing system

Abstract

The application discloses a large-bit-width InfiniBand network encoding and decoding layer processing system, which comprises a transmitter module, a transmission channel synchronization module, a scrambling module, an alignment module, a descrambling module, a receiving channel synchronization module and a receiver module; each module comprises two data paths of 8b10b encoding and 64b66b encoding, so as to be selected according to actual rate requirements, the bit width of each channel data path is 64b under 8b10b encoding, and the bit width of each channel data path is 256b under 64b66b encoding, and the 8b10b encoding data path bypasses the scrambling module and the descrambling module. The large-bit-width InfiniBand network encoding and decoding layer processing system has full-duplex data transmission mode, has 8b10b and 64b66b physical layer data encoding and decoding functions, supports large-bit-width multi-channel IB protocols, realizes channel alignment and inter-channel skew elimination technology, and can provide high-bandwidth and low-delay data transmission services in combination with IB upper layer design.

Description

Technical Field

[0001] The present invention belongs to the fields of network technology and FPGA technology, and in particular relates to a large-bit-width infinite bandwidth network encoding and decoding layer processing system. Background Art

[0002] InfiniBand (IB) technology is a high-performance computing network communication standard for connecting computers and I / O devices. It offers extremely high bandwidth, extremely low latency, and high scalability. Similar to the universal OSI model, InfiniBand employs a layered architecture consisting of the protocol layer, function layer, transport layer, network layer, link layer, and physical layer. The physical layer can be optionally aggregated into up to 12 high-speed channel units to achieve ultra-high-bandwidth, efficient data transmission.

[0003] Infiniband technology has been widely adopted in the commercial sector, encompassing high-performance computing, data centers, and public clouds. The current mainstream Infiniband rates (single channel) include SDR (2.5G), DDR (5G), QDR (10G), FDR (14G), EDR (25G), HDR (50G), and NDR (100G). Mechanisms such as forward error correction (FEC) and link training are used to ensure data reliability at high speeds. However, the increasing transmission rates required by the IB protocol within multiple high-speed channels necessitate the implementation of a correspondingly large-bitwidth Infiniband network codec layer protocol processing engine to control the increase in physical layer clock frequency and reduce the complexity of hardware design layout and routing. Summary of the Invention

[0004] The present invention provides a large-bitwidth infinite bandwidth network codec layer processing system to solve the above-mentioned technical problems, specifically adopting the following technical solutions:

[0005] A large-bitwidth infinite bandwidth network codec layer processing system, comprising: a transmitter module, a transmission channel synchronization module, a scrambling module, an alignment module, a descrambling module, a receiving channel synchronization module and a receiver module;

[0006] The transmitter module is configured to generate transmission data according to an input transmission control signal, user data and test data;

[0007] The transmission channel synchronization module is used to synchronize the transmission data from the codec layer clock to the parallel clock of each channel of the high-speed serial transceiver;

[0008] The scrambling module is used to scramble the transmission data and send it to the high-speed serial transceiver;

[0009] The alignment module is used to align and reorganize the high bits of the data received by the high-speed serial transceiver according to the synchronization header;

[0010] The descrambling module is used to descramble the received data and send it to the receiving channel synchronization module;

[0011] The receiving channel synchronization module is used to synchronize the received data from the parallel clock of each channel to the codec layer clock, and complete the de-skew alignment of the data beat between channels according to the SKP ordered set. The receiving channel synchronization module can also reverse the order of the receiving channels;

[0012] The receiver module is used to determine the channel ID correspondence, receive data type, polarity and bit error, control channel reversal, polarity flip and bit error reset, and output user / idle data, test data and receive control signals;

[0013] Each module includes two data paths: 8b10b encoding and 64b66b encoding, which can be selected according to actual rate requirements. Under 8b10b encoding, the bit width of each channel data path is 64b, and under 64b66b encoding, the bit width of each channel data path is 256b. The 8b10b encoding data path bypasses the scrambling module and the descrambling module.

[0014] Furthermore, the data link is optional with 1 channel, 2 channels, 4 channels, 8 channels, and 12 channels in parallel;

[0015] The number of the transmitter module, the scrambling module, the alignment module, the descrambling module and the receiver module is the same as the number of data channels used, their connections correspond one-to-one to the data channels used, and all channels share the transmitting channel synchronization module and the receiving channel synchronization module.

[0016] Further, the transmitter module transmits the ordered set, pseudo-random code test data, user data or idle data according to the transmission control signal;

[0017] The transmitter module inserts an IB control symbol according to a sending control signal when sending user data;

[0018] The transmitter module generates a K code according to the transmitted data under 8b10b encoding and generates a synchronization header according to the transmitted data under 64b66b encoding;

[0019] The transmitter module inserts three consecutive ordered sets SKP into the transmitted data every 544 to 576 clock cycles under 8b10b encoding, and inserts three consecutive ordered sets SKP into the transmitted data every 1088 to 1152 clock cycles under 64b66b encoding.

[0020] Furthermore, the transmitter module includes:

[0021] SKP timing module, used to periodically control the sending of ordered sets SKP;

[0022] The transmit data arbitration state machine is used to instruct the transmit data generation module to select and output the generated ordered set data, the input pseudo-random code test data, the input user data, or the generated idle data according to the control signal;

[0023] The transmit data generation module is used to generate ordered set data and idle data, insert IB control characters into user data, generate K codes in 8b10b encoding, and generate synchronization headers in 64b66b encoding.

[0024] Furthermore, the transmission data arbitration state machine has the following transmission priority: ordered set data>pseudo-random code test data>user data>idle data.

[0025] Furthermore, the transmitting channel synchronization module uses an asynchronous FIFO to safely convert the codec layer clock domain data to the same frequency high-speed serial transceiver clock domain.

[0026] Furthermore, the scrambling module bypasses the transmitted data under 8b10b encoding;

[0027] The scrambling module uses a self-synchronizing scrambling encoder under 64b66b encoding to scramble each 64b data block individually in a large bit width infinite bandwidth network codec layer processing system;

[0028] The alignment module shifts the data according to the COMMA position under 8b10b encoding so that COMMA is fixed at the first byte;

[0029] The alignment module outputs a slip control signal according to the validity of the 64b66b synchronization header under 64b66b encoding, controls the asynchronous transmission in the high-speed serial transceiver to shift the data, and ensures that a single 64b data block is not split into two clock cycles.

[0030] The descrambling module bypasses the received data under 8b10b encoding;

[0031] The descrambling module descrambles each 64b data block individually using a self-synchronizing scrambling decoder in 64b66b encoding.

[0032] Furthermore, the receiving channel synchronization module uses an asynchronous FIFO to safely convert the high-speed serial transceiver clock domain data to the same frequency codec layer clock domain;

[0033] The receiving channel synchronization module controls the asynchronous FIFO writing according to the identification of the received data ordered set SKP, thereby completing the de-skew alignment of the data beat between channels;

[0034] The receiving channel synchronization module reverses the connection order of the input channel and the output channel according to the channel reverse control signal.

[0035] Furthermore, when the receiver module inputs the ordered set, it determines the polarity according to the ordered set data content and controls the high-speed serial transceiver to flip the polarity;

[0036] When the receiver module inputs an ordered set, it compares the ordered set channel ID field and the receiver ID to determine the channel sequence, and controls the receiving channel synchronization module to reverse the sequence;

[0037] After the link is established, the receiver module inputs an ordered set, determines the error condition according to the ordered set data content and the synchronization header, and controls the reset of the receiving related modules;

[0038] When the receiver module inputs pseudo-random code test data, it outputs pseudo-random code test data;

[0039] When the receiver module inputs user data or idle data, it outputs a receiving control signal according to the IB control character and outputs user / idle data;

[0040] Furthermore, the receiver module comprises:

[0041] The data discrimination module is used to determine whether the received data belongs to ordered set data, pseudo-random code test data, user / idle data or error data, and generate the corresponding receiving control signal output;

[0042] The error processing module is used to count the polarity deviation, unknown code and ordered set data content errors under 8b10b encoding, and the synchronization header and ordered set data content errors under 64b66b encoding after the link is established, and reset the relevant modules on the receiving side;

[0043] The ordered set processing module is used to determine the polarity and channel sequence according to the ordered set data content, and control the polarity flipping of the high-speed serial transceiver and the channel sequence reversal of the receiving channel synchronization module.

[0044] The present invention is beneficial in that it provides a large-bitwidth infinite bandwidth network codec layer processing system with full-duplex data transmission, 8b10b and 64b66b physical layer data codec functions, support for large-bitwidth multi-channel IB protocols, implements intra-channel alignment and inter-channel de-skew technology, and, combined with IB upper-layer design, can provide high-bandwidth and low-latency data transmission services. In response to the ever-increasing transmission rate requirements of the IB protocol, the large-bitwidth data path slows down the growth rate of the physical layer clock frequency, reducing the difficulty of hardware design layout and wiring.

[0045] The invention is beneficial in that the provided large-bit-width infinite bandwidth network codec layer processing system can detect data coding, polarity and sequence errors during data reception and has certain error detection and recovery capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0047] Figure 1 This is a schematic diagram of the structure of a large-bitwidth infinite bandwidth network codec layer processing system of the present application;

[0048] Figure 2 This is a schematic diagram of the coding structure of a large-bit-width infinite bandwidth network codec layer processing system of the present application;

[0049] Figure 3 This is a schematic diagram of a multi-channel structure of a large-bitwidth infinite bandwidth network codec layer processing system of the present application;

[0050] Figure 4 This is a schematic diagram of the transmitter module structure of a large-bit-width infinite bandwidth network codec layer processing system of the present application;

[0051] Figure 5 This is a schematic diagram of a data arbitration state machine for a large-bit-width infinite bandwidth network codec layer processing system of the present application;

[0052] Figure 6 This is a schematic diagram of data generation module sending for a large-bit-width infinite bandwidth network encoding and decoding layer processing system of the present application;

[0053] Figure 7 The present application discloses a data filling solution for a data generation module in a large-bitwidth infinite bandwidth network codec layer processing system;

[0054] Figure 8 Schematic diagram of a large-bitwidth infinite bandwidth network codec layer processing system sending data, K code and synchronization header;

[0055] Figure 9 This is a structural diagram of a sending channel synchronization module of a large-bit-width infinite bandwidth network codec layer processing system of the present application;

[0056] Figure 10 This is a schematic diagram of the structure of a scrambling module in a large-bit-width infinite bandwidth network codec layer processing system of the present application;

[0057] Figure 11 This is a schematic diagram of the alignment module structure of a large-bitwidth infinite bandwidth network codec layer processing system of the present application;

[0058] Figure 12 This is a schematic diagram of a 64b66b encoding synchronization header alignment state machine of an alignment module of a large-bit-width infinite bandwidth network codec layer processing system of the present application;

[0059] Figure 13 This is a schematic diagram of the structure of a descrambling module in a large-bitwidth infinite bandwidth network codec layer processing system of the present application;

[0060] Figure 14 This is a structural diagram of a receiving channel synchronization module of a large-bit-width infinite bandwidth network codec layer processing system of the present application;

[0061] Figure 15 This is a structural diagram of a receiver module of a large-bit-width infinite bandwidth network encoding and decoding layer processing system of the present application. DETAILED DESCRIPTION

[0062] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0063] In addition, the terms "first" and "second" in the specification, claims and drawings of this application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an unexpected order other than those described herein. At the same time, the terms "including" and "having" in this application and any variations thereof are intended to cover non-exclusive inclusions. Unless otherwise clearly specified and limited, the terms "setting", "arrangement", "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be the internal connection of two original components, or it can be an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two original components. For ordinary technicians in this field, the specific meanings of the above terms in this case can be understood based on the specific circumstances and in combination with the existing technology.

[0064] The "coding" described in this application refers to the 8b10b coding (also compliant with IEEE 802.3 Gigabit Ethernet) and the 64b66b coding (also compliant with IEEE 802.3 10 Gigabit Ethernet) specified in the IB protocol.

[0065] The "rate" described in this application refers to the line rate defined in the IB protocol, including SDR (2.5Gb / s), DDR (5Gb / s), QDR (10Gb / s), FDR (14Gb / s), EDR (25Gb / s), HDR (50Gb / s), etc., among which SDR, DDR, and QDR use 8b10b encoding, and the other rates use 64b66b encoding.

[0066] The "lane" described in this application refers to the actual physical transmission differential signal pair used. Each lane ID is defined by the IB protocol Lane Identifiers, and the content of a single data packet is split across all lanes for simultaneous transmission.

[0067] The "control symbols" and "ordered-sets" described in this application are defined by the Control symbols / blocksand ordered-sets in the IB protocol and are used for IB link training, data packet segmentation and padding, and clock deviation compensation.

[0068] The "pseudo-random code" described in this application refers to the pseudo-random binary sequence PRBS23, which is a commonly used disguised data for testing high-speed serial system performance and errors, and is used in link quality testing.

[0069] The "high-speed serial transceiver" described in this application refers to the dynamically configurable FPGA physical layer high-speed serial interface defined by Xilinx, which implements functions such as signal serialization and deserialization, encoding and decoding, and clock recovery.

[0070] It should be noted that the rates, control symbols and ordered sets, pseudo-random codes, and high-speed serial transceivers include but are not limited to those listed above.

[0071] like Figure 1Figure 1 shows a schematic diagram of the architecture of a large-bitwidth infinitebandwidth network codec layer processing system according to the present application. This large-bitwidth infinitebandwidth network codec layer processing system is designed to implement large-bitwidth data generation, recognition, and synchronization based on the IB protocol standard and the requirements of large bitwidth and multiple channels. This system can be implemented within an FPGA and should be installed in the devices of both communicating parties to facilitate data transmission. Specifically, the large-bitwidth infinitebandwidth network codec layer processing system includes a transmitter module, a transmit channel synchronization module, a scrambling module, an alignment module, a descrambling module, a receive channel synchronization module, and a receiver module. The transmitter module generates transmit data based on input transmit control signals, user data, and test data. Specifically, the transmitter module receives transmit control instructions from an upper layer, selects the type of data to be transmitted based on priority, combines this with an internal timer, fills the transmit data with the corresponding data, and generates the corresponding K code or synchronization header. The transmit channel synchronization module synchronizes the transmit data from the codec layer clock to the parallel clocks of each channel of the high-speed serial transceiver. Specifically, the transmit channel synchronization module synchronizes data, K code, or synchronization header from the codec clock domain to the high-speed serial transceiver channel clock domain via an asynchronous FIFO. The scrambling module scrambles the transmit data and sends it to the high-speed serial transceiver. The scrambling module uses a self-synchronizing scrambling encoder to scramble the 64b66b encoded data and then outputs the data, K code, and synchronization header to the high-speed serial transceiver for data transmission. The other receiving node uses the alignment module to realign the received data from the high-speed serial transceiver to obtain the data, K code, or synchronization header. The descrambling module descrambles the received data and sends it to the receive channel synchronization module. The receive channel synchronization module synchronizes the received data from the parallel clock of each channel to the codec layer clock and performs inter-channel data skew alignment based on the SKP ordered set. (The receive channel synchronization module can also reverse the receive channel order.) The receiver module determines channel ID correspondence, receives data type, polarity, and bit errors, controls channel sequence reversal, polarity inversion, and bit error reset, and outputs user / idle data, test data, and receive control signals. Specifically, the descrambling module uses a self-synchronizing descrambler to descramble the 64b66b encoded data. It then uses the receive channel synchronization module to synchronize the data, K code, or synchronization header from the high-speed serial transceiver channel clock domain to the codec clock domain via an asynchronous FIFO (simultaneously reversing the channel sequence). Finally, the receiver module compares the channel IDs, determines data polarity and bit errors, and controls the receive channel synchronization module to reverse the channel sequence, reverse the polarity of the high-speed serial transceiver, and reset the receiver module. Furthermore, based on the input data content, K code, or synchronization header, it outputs user data, test data, and receive control signals to the upper layer.

[0072] Any of the above modules has the encoding processing function of 8b10b and 64b66b at the same time. Since the data processing process of the two encodings is basically the same, the specific implementation of the sub-modules, modules and engines can be the resources that share most of the common functions of the two encodings, including but not limited to connecting lines, registers, FIFOs, state machines, modules, etc., and the encoding switching and encoding-specific functions (such as Figure 2 (a) in the figure), or two encodings using completely independent resources (such as Figure 2 Therefore, in order to reduce duplication and avoid confusion, Figure 1 The data flow arrows for the two encoding schemes are not separately labeled, instead focusing on the common parts that are independent of the encoding type. This practice will continue below, with only common descriptions provided where the two encoding schemes are similar (different only in data bit width, K code, or synchronization header), and separate descriptions provided where the two encoding schemes differ. Those skilled in the art can understand specific implementations by combining the common descriptions with the separate descriptions, depending on the specific situation.

[0073] like Figure 3 As shown in the figure, the large-bitwidth Infiniband network codec layer processing system can be configured with 1, 2, 4, 8, or 12 channels. When there are multiple channels, each channel has its own transmitter module, scrambling module, alignment module, descrambling module, and receiver module. All channels share the transmit channel synchronization module and the receive channel synchronization module.

[0074] The transmitter module is used to select the data type that needs to be sent according to the arbitration of the control signal, and generate and send the corresponding type of continuous data stream according to the arbitration result. Figure 4 As shown in the figure, as a preferred embodiment, the transmitter module includes a SKP timing module, a transmit data arbitration state machine, and a transmit data generation module. The upper-layer transmit control interface controls the activation of SKP timing, sends the data type and start and end flags to be sent, and passes user data and test data to the corresponding data interface. The transmit data arbitration state machine arbitrates the requested data type and notifies the transmit data generation module to process the user data and test data, generating the transmit data and K code / synchronization header.

[0075] The SKP timing module is enabled and controlled by the upper layer and uses two cyclic counters to count input clock edges. Counter 0 counts every 544 clock cycles and reports an 8b10b SKP request to the transmit data arbitration state machine and clears the counter. Counter 1 reports a 64b66b SKP request to the transmit data arbitration state machine and clears the counter every 1088 clock cycles. This ensures the lower bound of the clock cycle interval for sending ordered set SKPs. Because the transmit data arbitration state machine cannot interrupt and insert SKPs during data packet transmission, the SKP request is maintained until the transmit data arbitration state machine returns an SKP response, at which point counting begins again.

[0076] In the example, the sending data arbitration is controlled by a finite state machine, but the present invention does not limit its implementation. Figure 5As shown in the figure, the transmit data arbitration state machine consists of four states: IDLE, SKP, TS, and DATA. When the transmit data arbitration state machine is reset and released, it enters the IDLE state. It then checks, based on priority, whether it has received a transmit request for an ordered set SKP, an ordered set TS (including TS1, TS2, and TS3), test data, or user data. If a transmit request for an ordered set SKP is received, it sends an SKP response to the SKP timing module and instructs the transmit data generation module to transmit the ordered set SKP. Because the ordered set SKP length in 8b10b encoding is 32 bits and the data width is 64 bits, three consecutive ordered set SKPs require two clock cycles to transmit. In 64b66b encoding, the ordered set SKP length is 64 bits (the lower 32 bits are reserved) and the data width is 256 bits. Therefore, three consecutive ordered set SKPs require one clock cycle to transmit. Therefore, the SKP state is then entered in 8b10b encoding, and the IDLE state is then entered in 64b66b encoding. In the SKP state, the transmit data generation module sends the remaining ordered set SKP and idle data, then enters the IDLE state. In the IDLE state, if a request to send an ordered set TS is received, the transmit data generation module sends the corresponding ordered set TS. Since the length of an ordered set TS in 8b10b encoding is 128 bits and the data width is 64 bits, transmission requires two clock cycles. In 64b66b encoding, the length of an ordered set TS is 64 bits (the lower 32 bits are reserved) and the data width is 256 bits, requiring one clock cycle to complete transmission. Therefore, the TS state is entered in 8b10b encoding, and the IDLE state is entered in 64b66b encoding. In the TS state, the transmit data generation module sends the corresponding ordered set TS, then enters the IDLE state. In the IDLE state, if a test data send request is received, the transmit data generation module sends the test data, then enters the IDLE state. In the IDLE state, if a user data send start request is received, the transmit data generation module sends the user data, then enters the DATA state. In the DATA state, the data transmission generation module is instructed to send user data. If a user data transmission end request is received, the IDLE state is entered; otherwise, the DATA state remains. In the IDLE state, if none of the above transmission requests are received, the data transmission generation module is instructed to send idle data and enter the ILDE state, ensuring the continuity of data transmission. The DATA and TS states cannot immediately respond to SKP transmission requests, which may cause SKP transmission delays.The maintenance of SKP requests and the highest priority of ordered set SKP transmission ensure that SKP can be sent immediately in the IDLE state after exiting the DATA or TS state. At the same time, the maximum length of the ordered set TS and user data packets ensures the upper bound of the clock cycle interval for ordered set SKP transmission, which is less than or equal to 576 clock cycles under 8b10b encoding and less than or equal to 1152 clock cycles under 64b66b encoding.

[0077] like Figure 6 As shown in the figure, the transmit data generation module receives the encoding instruction and data selection from the transmit data arbitration state machine, fills in the transmit data, K code or synchronization header, and sends it. Under 8b10b encoding, the data bit width is 64b, and it is filled in units of 8b (SYMBOL), and a 1b K code is generated accordingly; similarly, under 64b66b encoding, the data bit width is 256b, and it is filled in units of 64b (BLOCK), and a 2b synchronization header is generated accordingly. Figure 7 As shown in the figure, the data selection of the transmit data arbitration state machine corresponds to the padding of SYMBOL and BLOCK. In the 8b10b encoding, the ordered sets SKP and TS require two clock cycles with different padding. In addition, when filling user data, the padding of the corresponding SYMBOL or BLOCK needs to be changed from DATA to SDP (SLP) or EGP (EBP, PAD) according to the start and end of the data. The control signal for this padding change is given by the upper-layer transmit control interface. The source of the padding data can be external input (LANE ID, TS3, TEST, DATA) or internal ROM (see the details of the padding data, K code and synchronization header for details). Figure 8 ).

[0078] like Figure 9 As shown in the figure, using four channels as an example, the transmit channel synchronization module uses an asynchronous FIFO to securely synchronize transmit data and K-code / synchronization header from the coding layer clock domain to the high-speed serial transceiver clock domain. Writing to the asynchronous FIFO remains enabled after a reset, and reading remains enabled after the FIFO clears the empty watermark. Because the coding layer clock and the high-speed serial transceiver clocks of each channel have the same frequency but different phases, bit width conversion or other read / write control is unnecessary, and clock domain conversion can be completed directly without write-full or read-empty errors.

[0079] like Figure 10As shown, the scrambling module does not process 8b10b encoded data, but scrambles 64b66b encoded data and then selects one of the two data streams for output. The scrambling module distinguishes the data encoding type based on the K code and synchronization header. When the input K code is valid, it indicates 8b10b encoded data and directly outputs the input data and K code. When the input synchronization header is valid, it indicates 64b66b encoded data and outputs the scrambled data and synchronization header. The scrambling module uses a self-synchronizing scrambling encoder (LFSR) (scrambling polynomial G(x) = 1 + x^39 + x^58) to individually scramble each 64b66b encoded block.

[0080] The alignment module completes the alignment of received data at the SYMBOL / BLOCK level. Figure 11 As shown in the figure, as a preferred embodiment, the alignment module includes an 8b10b shift module and a 64b66b sync header alignment state machine. When transmitting and receiving test data, the 64b66b sync header alignment state machine is bypassed by upper-layer control signals. The input of the 8b10b shift module ensures a one-to-one correspondence between each bit of the K code / comma and each symbol of the data. The order from MSB to LSB is defined as bytes 7 to 0. If a comma exists in the input data but does not correspond to the most significant byte (byte 7), the data is shifted according to the comma position, fixing the comma at the most significant byte. Specifically, the 8b10b shift module scans the input rxchariscomma from the highest bit to the lowest bit to determine the position corresponding to the first COMMA. If the COMMA corresponds to the 7th byte, the data and K code are directly output without shifting. If the COMMA corresponds to the 6th byte, the 6th to 0th bytes of the current clock cycle and the 7th byte of the next clock cycle are recombined into a new 8-byte output. The 6th to 0th bytes of the current clock cycle occupy the 7th to 1st bytes of the new 8 bytes, and the 7th byte of the next clock cycle occupies the 0th byte of the new 8 bytes. The K code is also recombined along with the corresponding data, that is, the data is shifted to the left by 1 byte. The shift operation corresponding to COMMA at other byte positions is analogous. When the input data does not contain COMMA, the shift operation of the previous clock cycle continues until COMMA appears again. Referring to the scrambling module, the alignment module determines the data encoding type based on the K code / synchronization header, and then selects one output of the corresponding encoding type from the two data outputs of the input data and the 8b10b shift module, and selects one output of the corresponding encoding type from the two input synchronization headers and the 8b10b shift module output K code.

[0081] like Figure 12As shown in the figure, the 64b66b synchronization header alignment state machine consists of four states: IDLE, VALID, INVALID, and SLIP. When the 64b66b synchronization header alignment state machine is reset and released, it enters the IDLE state. The synchronization header counter sh_cnt is incremented by 1 to check whether the current synchronization header is valid. A valid synchronization header is 2'b01 or 2'b10. If valid, the state enters the VALID state. Otherwise, the invalid synchronization header counter invalid_cnt is incremented by 1, and the state enters the INVALID state. In the VALID state, if sh_cnt reaches 64, the sh_cnt and invalid_cnt counts are cleared, and the state enters the IDLE state. Otherwise, the synchronization header counter sh_cnt is incremented by 1 to check whether the current synchronization header is valid. If valid, the state enters the VALID state. Otherwise, the invalid synchronization header counter invalid_cnt is incremented by 1, and the state enters the INVALID state. In the INVALID state, if the invalid_cnt count reaches 16, the SLIP state is entered. Otherwise, if the sh_cnt count reaches 64, the sh_cnt and invalid_cnt counts are cleared, and the IDLE state is entered. Otherwise, the sync header count sh_cnt is incremented by 1 to check whether the current sync header is valid. If valid, the VALID state is entered. Otherwise, the invalid sync header count invalid_cnt is incremented by 1, and the INVALID state is entered. In the SLIP state, the SLIP signal is set to 1 to control the asynchronous transmission within the high-speed serial transceiver to shift 1 bit of data, and the clock cycle count slip_cnt is started. If the slip_cnt count reaches 16, the sh_cnt, invalid_cnt, and slip_cnt counts are cleared, and the IDLE state is entered. Otherwise, the SLIP state remains in the SLIP state, waiting for the high-speed serial transceiver to complete the slip.

[0082] like Figure 13 As shown, the descrambling module does not process 8b10b encoded data, but descrambles 64b66b encoded data, then selects one of the two data streams for output. The descrambling module distinguishes the data encoding type based on the K code and synchronization header. When the input K code is valid, it indicates 8b10b encoded data and directly outputs the input data and K code. When the input synchronization header is valid, it indicates 64b66b encoded data and outputs the descrambled input data and synchronization header. The descrambling module uses a self-synchronizing scrambling decoder (LFSR) (scrambling polynomial G(x) = 1 + x^39 + x^58) to individually descramble each 64b66b encoded block.

[0083] like Figure 14 As shown, taking 4 channels as an example, as a preferred embodiment, the receiving channel synchronization module includes a SKP de-skew module, an asynchronous FIFO and a channel reverse order multiplexer. The SKP de-skew module compares the input data and the K code / synchronization header. Figure 8 , identifying the SYMBOL / BLOCK of the ordered set SKP. In 8b10b encoding, if the input data contains an ordered set SKP but its COMMA does not correspond to the most significant byte, the data is shifted using the 8b10b shift module to fix the COMMA to the most significant byte. In 64b66b encoding, the shift is performed block by block, fixing the ordered set SKP to the most significant block. If the input data does not contain an ordered set SKP, the shifting operation from the previous clock cycle continues until the ordered set SKP appears again. The SKP alignment module thus utilizes the periodic occurrence of ordered sets SKP in the data to de-skew and align the receive data between channels. The asynchronous FIFO securely synchronizes the receive data and K code / sync header from the high-speed serial transceiver clock domain to the coding layer clock domain. The asynchronous FIFO remains enabled for writes after a reset, and for reads after the FIFO clears the watermark. Because the high-speed serial transceiver clock and coding layer clock of each channel have the same frequency but different phases, there is no need for bit width conversion or read / write control, and clock domain conversion can be completed directly without write-over or read-empty errors. The channel reverse multiplexer outputs the asynchronous FIFO data and K code / sync header in sequential or reverse order based on the channel reverse control signal. For lane IDs of 0, 1, 2, ..., N, the channel reverse multiplexer for lane n (0 ≤ n ≤ N) selects an output from the asynchronous FIFOs of lanes n and Nn based on the channel reverse control signal.

[0084] like Figure 15 As shown in the figure, as a preferred embodiment, the receiver module includes a data identification module, an ordered set processing module and an error processing module. The data identification module compares the input data and the K code / synchronization header. Figure 8, identifying data as ordered set data, user / idle data, test data, or bit errors, and outputting the data and corresponding receive control signals based on the data type. Specifically, if the K code is 1 or the synchronization header is 10, the data type is determined based on the data content. If it is an ordered set SKP, TS1, TS2, or TS3, it is output to the ordered set processing module and the corresponding receive control signal is set to 1. If it is SDP, SLP, EGP, or EBP, user / idle data is output, along with the corresponding user data start signal or user data end signal. If the K code is 0 or the synchronization header is 01, test data is output when the link is in test mode; otherwise, user / idle data is output. Subsequent upper-layer modules can separate user data from idle data based on the user data start signal and user data end signal. If the data contains a Running Disparity or Not in Table error, or if the data type cannot be identified using the above methods, it is a bit error. If the link is in the established state, the error indicator is set to 1, and no data or control signals are output.

[0085] The ordered set processing module identifies whether the incoming ordered set data contains polarity reversal and controls the high-speed serial transceiver to reverse the polarity. Specifically, if the received ordered set TS1 contains 8'h4A, the data is normally transmitted without polarity reversal. If it contains 8'hB5, the data is transmitted with polarity reversal. The ordered set processing module compares the incoming ordered set's LANE ID with the LANE ID of the channel. If there is a mismatch, the receiving channel synchronization module controls the channel sequence reversal.

[0086] The error handling module receives and counts error indications from the data identification module. If the count reaches 8, it resets the relevant modules on the receiving side and cancels the link establishment state. After link establishment, the error handling module counts polarity deviation, unknown encoding, and ordered set data content errors in 8b10b encoding, and synchronization header and ordered set data content errors in 64b66b encoding, and resets the relevant modules on the receiving side.

[0087] In summary, the large-bitwidth infinitebandwidth network codec layer processing system provided by this invention features 8b10b and 64b66b physical layer data encoding and decoding capabilities, supports the large-bitwidth multi-channel IB protocol, implements intra-channel alignment and inter-channel de-skew technology, and, combined with IB upper-layer design, provides high-bandwidth, low-latency data transmission services. To meet the growing transmission rate requirements of the IB protocol, the large-bitwidth data path mitigates the growth of the physical layer clock frequency, reducing the difficulty of hardware design layout and routing. Furthermore, during data reception, this solution detects data encoding, polarity, and sequence errors, demonstrating robust error detection and recovery capabilities.

[0088] The preferred embodiments of the present invention disclosed above are only used to help illustrate the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific implementation scheme described. Obviously, many modifications and changes can be made based on the contents of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that people in the relevant technical field can better understand and use the present invention. The present invention is only limited by the claims and their full scope and equivalents. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0089] Those skilled in the art will understand that, in addition to implementing the system, device, and various modules provided by the present invention in pure computer-readable program code, it is entirely possible to implement the same program in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. by logically programming the method steps. Therefore, the system, device, and various modules provided by the present invention can be considered a hardware component, and the modules included therein for implementing various programs can also be considered as structures within the hardware component; the modules for implementing various functions can also be considered as both software programs for implementing the method and structures within the hardware component.

[0090] In addition, all or part of the steps in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a program. The program is stored in a storage medium and includes a number of instructions for causing a single-chip microcomputer, chip, or processor to execute all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc., various media that can store program code.

[0091] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the above embodiments do not limit the present invention in any form, and any technical solutions obtained by equivalent replacement or equivalent transformation fall within the scope of protection of the present invention.

Claims

1. A large bit width infinite bandwidth network codec layer processing system, characterized in that: include: Transmitter module, transmit channel synchronization module, scrambling module, alignment module, descrambling module, receive channel synchronization module and receiver module; The transmitter module is configured to generate transmission data according to an input transmission control signal, user data and test data; The transmission channel synchronization module is used to synchronize the transmission data from the codec layer clock to the parallel clock of each channel of the high-speed serial transceiver; The scrambling module is used to scramble the transmission data and send it to the high-speed serial transceiver; The alignment module is used to align and reorganize the high bits of the data received by the high-speed serial transceiver according to the synchronization header; The descrambling module is used to descramble the received data and send it to the receiving channel synchronization module; The receiving channel synchronization module is used to synchronize the received data from the parallel clock of each channel to the codec layer clock, and complete the de-skew alignment of the data beat between channels according to the SKP ordered set. The receiving channel synchronization module can also reverse the order of the receiving channels; The receiver module is used to determine the channel ID correspondence, receive data type, polarity and bit error, control channel reversal, polarity flip and bit error reset, and output user / idle data, test data and receive control signals; The transmitter module, the transmit channel synchronization module, the scrambling module, the alignment module, the descrambling module, the receive channel synchronization module, and the receiver module each include two data paths: 8b10b encoding and 64b66b encoding, for selection based on actual rate requirements. Under 8b10b encoding, the data path bit width per channel is 64b, and under 64b66b encoding, the data path bit width per channel is 256b. The 8b10b encoding data path bypasses the scrambling module and the descrambling module. The transmitter module transmits an ordered set, pseudo-random code test data, user data or idle data according to a transmission control signal; The transmitter module inserts an IB control symbol according to a sending control signal when sending user data; The transmitter module generates a K code according to the transmitted data under 8b10b encoding and generates a synchronization header according to the transmitted data under 64b66b encoding; The transmitter module inserts three consecutive ordered sets SKP into the transmitted data every 544 to 576 clock cycles under 8b10b encoding, and inserts three consecutive ordered sets SKP into the transmitted data every 1088 to 1152 clock cycles under 64b66b encoding.

2. The large bit-width infinite bandwidth network codec layer processing system according to claim 1, characterized in that: The data link is parallel 2-channel, 4-channel, 8-channel or 12-channel; The number of the transmitter module, the scrambling module, the alignment module, the descrambling module and the receiver module is the same as the number of data channels used, their connections correspond one-to-one to the data channels used, and all channels share the transmitting channel synchronization module and the receiving channel synchronization module.

3. The large bit-width infinite bandwidth network codec layer processing system according to claim 1, characterized in that: The transmitter module comprises: SKP timing module, used to periodically control the sending of ordered sets SKP; The transmit data arbitration state machine is used to instruct the transmit data generation module to select and output the generated ordered set data, the input pseudo-random code test data, the input user data, or the generated idle data according to the control signal; The transmit data generation module is used to generate ordered set data and idle data, insert IB control characters into user data, generate K codes in 8b10b encoding, and generate synchronization headers in 64b66b encoding.

4. The large bit-width infinite bandwidth network codec layer processing system according to claim 3, characterized in that: The transmission data arbitration state machine has the following transmission priority: ordered set data>pseudo-random code test data>user data>idle data.

5. The large bit-width infinite bandwidth network codec layer processing system according to claim 1, characterized in that: The transmitting channel synchronization module uses an asynchronous FIFO to safely convert the codec layer clock domain data to the same frequency high-speed serial transceiver clock domain.

6. The large bit-width infinite bandwidth network codec layer processing system according to claim 1, characterized in that: The scrambling module bypasses the transmitted data under 8b10b encoding; The scrambling module uses a self-synchronizing scrambling encoder under 64b66b encoding to scramble each 64b data block individually in a large bit width infinite bandwidth network codec layer processing system; The alignment module shifts the data according to the COMMA position under 8b10b encoding so that COMMA is fixed at the first byte; The alignment module outputs a slip control signal according to the validity of the 64b66b synchronization header under 64b66b encoding, controls the asynchronous transmission in the high-speed serial transceiver to shift the data, and ensures that a single 64b data block is not split into two clock cycles. The descrambling module bypasses the received data under 8b10b encoding; The descrambling module descrambles each 64b data block individually using a self-synchronizing scrambling decoder in 64b66b encoding.

7. The large bit-width infinite bandwidth network codec layer processing system according to claim 1, characterized in that: The receiving channel synchronization module uses an asynchronous FIFO to safely convert the high-speed serial transceiver clock domain data to the same frequency codec layer clock domain; The receiving channel synchronization module controls the asynchronous FIFO writing according to the identification of the received data ordered set SKP, thereby completing the de-skew alignment of the data beat between channels; The receiving channel synchronization module reverses the connection order of the input channel and the output channel according to the channel reverse control signal.

8. The large bit-width infinite bandwidth network codec layer processing system according to claim 1, characterized in that: When the receiver module inputs an ordered set, it determines the polarity according to the ordered set data content and controls the high-speed serial transceiver to flip the polarity; When the receiver module inputs an ordered set, it compares the ordered set channel ID field and the receiver ID to determine the channel sequence, and controls the receiving channel synchronization module to reverse the sequence; After the link is established, the receiver module inputs an ordered set, determines the error condition according to the ordered set data content and the synchronization header, and controls the reset of the receiving related modules; When the receiver module inputs pseudo-random code test data, it outputs pseudo-random code test data; When the receiver module inputs user data or idle data, it outputs a receiving control signal according to the IB control character and outputs user / idle data.

9. The large bit-width infinite bandwidth network codec layer processing system according to claim 1, characterized in that: The receiver module comprises: The data discrimination module is used to determine whether the received data belongs to ordered set data, pseudo-random code test data, user / idle data or error data, and generate the corresponding receiving control signal output; The error processing module is used to count the polarity deviation, unknown code and ordered set data content errors under 8b10b encoding, and the synchronization header and ordered set data content errors under 64b66b encoding after the link is established, and reset the relevant modules on the receiving side; The ordered set processing module is used to determine the polarity and channel sequence according to the ordered set data content, and control the polarity flipping of the high-speed serial transceiver and the channel sequence reversal of the receiving channel synchronization module.

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