Fin fet device and method of manufacturing the same

Abstract

The application provides a Fin Fet device and a manufacturing method thereof, and relates to the technical field of semiconductor devices, and comprises, from bottom to top: a substrate; an epitaxial layer located on the top of the substrate; a fin-shaped well region located on the top of the epitaxial layer, the fin-shaped well region comprises a plurality of fins formed side by side along a first direction and the fins extend in a second direction, the second direction is perpendicular to the first direction, and the inner part of each fin is respectively epitaxially provided with a stress material layer; an STI layer located on the top of the epitaxial layer and deposited between every two adjacent fins; an etching stop layer formed on the part of the side of the fin not in contact with the STI layer and the top of the fin; and a gate layer structure arranged on the top of the fin-shaped well region and the STI layer, arranged along the second direction and extending in the first direction. The application has the advantages of increasing the driving current and improving the migration rate of the carrier of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and in particular, to a Fin Fet device and a manufacturing method thereof. BACKGROUND

[0002] With the development of integrated circuit industry, the structure of MOS transistor gradually changes from 2D to 3D structure, and the current mainstream 3D MOS structure is Fin Fet, which is a new complementary metal-oxide-semiconductor transistor.

[0003] From the perspective of structure, the Source / Drain of Fin Fet device is vertically arranged in a structure similar to fish fin. In Fin Fet, increasing driving current and improving carrier mobility is one of the important research topics. In the traditional scheme, the performance of Fin Fet can be optimized by increasing the channel width and applying stress in the channel region. However, with the continuous reduction of the size of Fin Fet device, it faces great challenges to continue to improve the performance of Fin Fet.

[0004] Therefore, it is necessary to optimize the structure of Fin Fet device to increase the driving current and improve the migration rate of device carriers. SUMMARY

[0005] The purpose of the present application is to provide a Fin Fet device and a manufacturing method thereof, which realizes increasing driving current and improving the migration rate of device carriers.

[0006] The present application is realized by the following technical scheme:

[0007] The present application provides a Fin Fet device, comprising, from bottom to top, in sequence:

[0008] a substrate;

[0009] an epitaxial layer located on the top of the substrate;

[0010] a fin-shaped well region located on the top of the epitaxial layer, the fin-shaped well region comprising a plurality of fins formed side by side along a first direction and extending in a second direction, the second direction being perpendicular to the first direction, and each fin having a stress material layer epitaxially grown on the inside thereof;

[0011] an STI layer located on the top of the epitaxial layer and deposited between every two adjacent fins, and the side surface of the STI layer being in contact with the side surface of the fin;

[0012] an etch stop layer formed on the part of the side surface of the fin not in contact with the STI layer and on the top of the fin;

[0013] The gate layer structure is deposited on the fin-shaped well region and the STI layer, arranged along the second direction and extending toward the first direction.

[0014] Preferably, the fin-shaped well region includes a plurality of P-type well regions and a plurality of N-type well regions, and each of the P-type well regions and each of the N-type well regions constitutes one of the fins.

[0015] Preferably, the stress material layer is selected from:

[0016] When the fin is an N-type well region, the stress material layer is made of silicon germanium;

[0017] When the fin is a P-type well region, the stress material layer is made of silicon germanium or silicon carbide.

[0018] Preferably, a groove is provided on the upper surface of the fin, and the stress material layer is epitaxially formed in the groove.

[0019] Preferably, the channel width of the FinFet device is controlled by controlling the thickness of the stress material layer.

[0020] The present invention also provides a method for manufacturing a Fin FET device, which is used to manufacture the above-mentioned Fin FET device. The method for manufacturing the fin-shaped well region comprises the following steps:

[0021] The fin is formed on the epitaxial layer, wherein a groove is provided on the fin, and an oxide layer and a silicon nitride layer formed in the process of forming the fin remain on the top of the non-groove portion of the fin;

[0022] A TEOS layer is deposited on the epitaxial layer to wrap around the fin, and a planarization process is performed to make the upper surface of the TEOS layer flush with the upper surface of the silicon nitride layer. The deposition method can be a chemical vapor deposition method, and the planarization method can be a grinding method;

[0023] The TEOS layer is etched back from the top, and the etched back thickness h' is the thickness difference between the top of the TEOS layer and the bottom of the trench, and the remaining TEOS layer after the etch back forms the STI layer;

[0024] epitaxially forming the stress material layer in the trench;

[0025] removing the remaining oxide and silicon nitride layers;

[0026] The etching stop layer is formed on the fin and the gate layer structure is manufactured.

[0027] Preferably, the fin is formed by:

[0028] Performing ion implantation on the epitaxial layer to form a well region;

[0029] forming an oxide layer, a silicon nitride layer and a sacrificial layer on the upper surface of the well region in sequence from bottom to top, forming a photoresist layer along the first direction and extending to the second direction on the sacrificial layer, the photoresist layer comprising a bottom anti-reflective coating and a photoresist layer stacked in sequence from bottom to top, and then performing exposure;

[0030] manufacturing a plurality of fin structures on the upper surface of the well region by dry etching, and removing the oxide layer and the silicon nitride layer on the fin structures by wet etching;

[0031] forming an oxide layer and a silicon nitride layer on the upper surface of the well region in sequence from bottom to top;

[0032] removing the oxide layer and the silicon nitride layer in the horizontal direction by dry etching;

[0033] removing a portion with a thickness h of the well region from the upper surface by dry etching, the thickness h being the thickness of the non-fin structure portion of the well region, and forming a plurality of the fins with grooves.

[0034] Preferably, the well region comprises a P-type well region and an N-type well region.

[0035] The P-type well region and the N-type well region are respectively formed by different ion implantation.

[0036] Preferably, the method for forming the etching stop layer is:

[0037] forming an oxide layer on the portion of the side surface of the fin not in contact with the STI layer and on the upper surface of the fin by thermal oxidation, as the etching stop layer.

[0038] Preferably, the method for manufacturing the gate layer structure is:

[0039] depositing a gate layer material wrapping the STI layer and the fin, and performing planarization treatment on the upper surface of the gate layer material;

[0040] forming a sacrificial layer on the upper surface of the gate layer material;

[0041] forming a photoresist layer along the second direction and extending to the first direction on the upper surface of the sacrificial layer, the photoresist layer comprising a bottom anti-reflective coating and a photoresist layer stacked in sequence from bottom to top, and obtaining the gate layer structure by exposure.

[0042] The technical solution of the present application has the unexpected effects that:

[0043] The present application can generate stress effect on the channel direction and the direction perpendicular to the channel of the fin respectively by manufacturing stress material in the fin, thereby improving the migration rate of the carrier of the device.

[0044] The stress material of the present invention can form an epitaxial layer gradually formed in three directions. The stress in this epitaxial structure is more uniform and has fewer dislocations, which can further improve the migration rate of device carriers.

[0045] The present invention can increase the width of the channel by reasonably controlling the thickness of the stress material, thereby increasing the driving current of the device. At the same time, the method for controlling the channel width is simple and more flexible and adaptable.

[0046] The present invention forms a placeholder dummy gate based on the gate layer structure. The dummy gate can be conveniently removed later to manufacture the gate and is compatible with all subsequent gate manufacturing processes of FinFet devices. In addition, the present invention can form an epitaxial structure not only in the source and drain regions, but also in the area below the subsequently manufactured gate through a simple process, thereby greatly improving the response speed and performance of the FinFet device, saving process flow and reducing process costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A schematic structural diagram of the FinFet device provided in Example 1;

[0048] Figure 2 A schematic diagram of forming an oxide layer on the epitaxial layer provided in Example 1;

[0049] Figure 3 A schematic diagram of obtaining a P-type well region provided in Example 1;

[0050] Figure 4 A schematic diagram of obtaining an N-type well region provided in Example 1;

[0051] Figure 5 A schematic diagram of exposure in the well region provided in Example 1;

[0052] Figure 6 A schematic diagram of multiple fin structures manufactured according to Example 1;

[0053] Figure 7 Schematic diagram of removing the oxide layer and silicon nitride layer on the fin structure provided in Example 1;

[0054] Figure 8 A schematic diagram of forming an oxide layer and a silicon nitride layer provided in Example 1;

[0055] Figure 9 A schematic diagram of removing the horizontal oxide layer and silicon nitride layer provided in Example 1;

[0056] Figure 10 A schematic diagram of forming multiple fins provided in Example 1;

[0057] Figure 11 Schematic diagram of depositing TEOS layer for example 1;

[0058] Figure 12 Schematic diagram of etching back TEOS layer for example 1;

[0059] Figure 13 Schematic diagram of epitaxial silicon germanium in trench for example 1;

[0060] Figure 14 Schematic diagram of removing remaining oxide and silicon nitride layer for example 1;

[0061] Figure 15 Schematic diagram of fabricating gate material for example 1;

[0062] Figure 16 Schematic diagram of exposing to obtain gate structure for example 1;

[0063] Figure 17 Schematic diagram of exposing on TEOS layer for example 2;

[0064] Figure 18 Schematic diagram of obtaining fin with trench at N-type well region for example 2;

[0065] Figure 19 Schematic diagram of epitaxial silicon germanium for example 2;

[0066] Figure 20 Schematic diagram of exposing device of example 2; Figure 19

[0067] Figure 21 Schematic diagram of obtaining fin with trench at P-type well region for example 2;

[0068] Figure 22 Schematic diagram of epitaxial silicon carbide for example 2;

[0069] Figure 23 Schematic diagram of removing remaining organic medium layer and silicon nitride layer for example 2;

[0070] Figure 24 Schematic diagram of etching back multiple TEOS layers for example 2;

[0071] Figure 25 Schematic diagram of structure of Fin Fet device for example 2;

[0072] Figure 26 Schematic diagram of structure of Fin Fet device for example 3; ​

[0073] Figure 27 Structure diagram of Fin Fet device provided for Embodiment 4;

[0074] Figure: 101-substrate, 102-epitaxial layer, 103-STI layer, 104-fin, 105-stress material layer, 106-etching stop layer, 107-gate layer structure, 301-oxide layer, 302-photoretist, 303-top anti-reflective coating, 304-P-type well region, 305-N-type well region, 306-silicon nitride layer, 307-sacrificial layer, 308-bottom anti-reflective coating, 401-TEOS layer, 402-gate layer material, 403-organic dielectric layer. DETAILED DESCRIPTION

[0075] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme of the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations.

[0076] In the description of the structure of the device, the following embodiments will use the expression "on" to describe that one layer or region is directly on another layer or region;

[0077] In the description of the direction, the first direction of the following embodiments is parallel to the x-axis direction in Figure 1 , the second direction is parallel to the z-axis direction, and the z-axis is perpendicular to the x-axis and y-axis in Figure 1 , and the third direction is parallel to the y-axis direction.

[0078] Embodiment 1

[0079] The present embodiment provides a Fin Fet device, referring to Figure 1 , comprising, from bottom to top, in sequence:

[0080] Substrate 101;

[0081] Epitaxial layer 102, located on the substrate 101;

[0082] Fin-shaped well region, located on the epitaxial layer 102, the fin-shaped well region comprises a plurality of fins 104 formed side by side along a first direction, and the fins 104 thereof extend in a second direction, the second direction being perpendicular to the first direction, and each fin 104 has a stress material layer 105 epitaxially formed on the inside thereof;

[0083] An STI layer 103 is located on the epitaxial layer 102 and is deposited between each two adjacent fins 104 , with the side surfaces of the STI layer 103 contacting the side surfaces of the fins 104 . STI stands for shallow trench isolation and is a process for achieving electrical isolation between devices.

[0084] an etch stop layer 106 formed on a portion of the side of the fin 104 that is not in contact with the STI layer 103 and on a top surface of the fin 104 ;

[0085] The gate layer structure 107 is deposited on the fin-shaped well region and the STI layer 103 , arranged along the second direction and extending toward the first direction.

[0086] In this embodiment, the fin-shaped well region includes a plurality of P-type well regions 304 and a plurality of N-type well regions 305 , and each of the P-type well regions 304 and each of the N-type well regions 305 constitutes one of the fins 104 .

[0087] by Figure 1 Taking the Fin Fet device as an example, the Fin Fet device can include two structures: NMOS and PMOS. Figure 1 The left side of the FinFet device is NMOS, and the right side is PMOS. The well region of the NMOS is a P-type well region 304, and the well region of the PMOS is an N-type well region 305.

[0088] When specifically selecting the stress material layer 105 , as a feasible implementation scheme, silicon germanium (SiGe) can be used in the well regions of both PMOS and NMOS.

[0089] With the development of technology and performance optimization, the size of Fin Fet devices has been reduced and the size of fins has been optimized. It has become increasingly difficult to apply stress to the channel. Traditional solutions usually set the stress material layer in other areas of the Fin Fet device, such as near the channel and at the gate layer. However, the traditional stress material setting method is difficult to apply effective and reliable stress to the channel area of ​​higher-performance Fin Fet devices.

[0090] Therefore, this embodiment provides a Fin Fet device as described above. Compared with the traditional solution, the unexpected effect is that the setting method of this embodiment is more direct and effective in regulating the carrier mobility. Since the fin 104 in the Fin Fet device is the channel body, the setting of this embodiment is equivalent to directly embedding stress into the channel area, which solves the problem that external stress is difficult to effectively penetrate the Fin Fet device with narrow width fin 104, and also solves the problem of uneven stress caused by edge effect and local bending. In this embodiment, the stress material layer 105 epitaxial in the fin 104 can simultaneously apply compressive stress in two directions of the Fin Fet device to improve the mobility of the device carriers, one direction is the first direction, and the other direction is the second direction. At the same time, the stress material embedded in the fin 104 is isolated and independent from the other layer structures of the Fin Fet device, which is convenient for modular design and process optimization. It can also improve the stress transfer efficiency and reduce attenuation by making the stress field act more directly on the channel area.

[0091] In summary, the Fin Fet device provided in this embodiment sets the stress material inside the Fin structure, which can make the stress act on the channel area more directly and effectively, and has higher stress transfer efficiency and directional control capability.

[0092] The manufacturing method of the FinFet device of this embodiment can adopt the following method:

[0093] Step S201: growing an oxide layer 301 on the epitaxial layer 102 to obtain Figure 2 Then, the photoresist 302 and the top anti-reflective coating 303 are sequentially covered on the right area above the oxide layer 301 from bottom to top, and then B ions and BF2 ions are implanted into the FinFet device from top to bottom to obtain a P-type well region 304. The resulting structure can be referred to Figure 3 Next, the left area above the oxide layer 301 is covered with photoresist 302 and top anti-reflective coating 303 from bottom to top, and then P ions and AS ions are implanted into the Fin Fet device from top to bottom to obtain an N-type well region 305. The specific structure can be found in Figure 4 After the above ion implantation is completed, the oxide layer 301 and the residual photoresist 302 can be removed, and the lattice can be repaired by rapid thermal annealing to activate the P-type well region 304 and the N-type well region 305;

[0094] Step S202: An oxide layer 301, a silicon nitride layer 306, and a sacrificial layer 307 are sequentially formed on the well region from bottom to top. A photoresist layer arranged along the first direction and extending toward the second direction is formed on the sacrificial layer 307. The photoresist layer includes a bottom anti-reflective coating layer 308 and a photoresist layer 302 stacked sequentially from bottom to top. The resulting structure is then exposed. Figure 5 , PW and NW in the figure are the abbreviations of P-type well region and N-type well region respectively;

[0095] Step S203: A plurality of fin structures are manufactured on the well region by dry etching. The obtained results can be referred to Figure 6 Then, the oxide layer 301 and the silicon nitride layer 306 on the fin structure are removed by wet etching to obtain Figure 7 structure;

[0096] Step S204: forming an oxide layer 301 and a silicon nitride layer 306 in sequence from bottom to top on the well region to obtain Figure 8 The structure shown;

[0097] Step S205: Remove the oxide layer 301 and the silicon nitride layer 306 in the horizontal direction by dry etching to obtain Figure 9 The structure shown;

[0098] Step S206: Remove the portion of the well region with a thickness of h from the top by dry etching. The thickness h is the thickness of the non-fin structure portion of the well region. After the removal, the remaining well region can form a plurality of fins 104 with a groove having a thickness of h. The structure is as follows: Figure 10 As shown, at this time, the oxide layer 301 and the silicon nitride layer 306 still remain on the top of the non-groove portion of the fin 104;

[0099] Step S207: Fill the epitaxial layer 102 with a TEOS layer 401 that wraps the fin 104 by chemical vapor deposition. TEOS is tetraethyl orthosilicate or ethyl orthosilicate. At this time, the groove is also filled with the TEOS layer. Chemical mechanical polishing is performed to make the top of the TEOS layer 401 flush with the top of the silicon nitride layer 306. High temperature annealing can also be used here to make the formed TEOS more dense. The resulting structure can be referred to. Figure 11 , Figure 11 The left side of the figure is the fin 104 formed by the P-type well region 304, and the right side is the fin 104 formed by the N-type well region 305;

[0100] Step S208a: The TEOS layer 401 is etched back from the top by dry etching. The etched back thickness h' is the thickness difference between the top of the TEOS layer 401 and the groove. The remaining TEOS layer 401 after the etch back forms the STI layer 103. The obtained structure can be referred to Figure 12 ;

[0101] Step S209a: epitaxially growing the stress material layer 105 in the trench, and the structure obtained here is shown in Figure 13 Silicon germanium is grown in the fins 104 in PMOS and NMOS, so it can be grown directly and simultaneously;

[0102] Step S210a: removing the remaining oxide layer 301 and silicon nitride layer 306 by wet etching, and the structure obtained is shown in Figure 14 ;

[0103] Step S211: performing thermal oxidation on the portions of the sides of the fins 104 that are not in contact with the STI layer 103 and the top of the fins to form the etching stop layer 106, and then manufacturing the gate layer material 402 that wraps around the STI layer 103 and the fins 104 by chemical vapor deposition, and polishing the top of the gate layer material 402 by chemical mechanical polishing, the gate layer material 402 can be amorphous silicon or polysilicon, and the structure obtained is shown in Figure 15 ;

[0104] Step S212: forming the sacrificial layer 307 on the top of the gate layer material 402;

[0105] forming a photoetching layer on the top of the sacrificial layer 307, the photoetching layer is arranged along the second direction and extends to the first direction, and the photoetching layer includes a bottom anti-reflective coating 308 and a photoresist 302 layer stacked in order from bottom to top, and the structure can be referred to Figure 16 , and then performing exposure to obtain the gate layer structure 107, at this time, the Fin Fet device shown in Figure 1 is obtained, and Figure 1 The stress material layers 105 in the P-type well region and the N-type well region in the embodiment are both silicon germanium.

[0106] Embodiment 2

[0107] The embodiment provides a Fin Fet device, and the structure obtained is shown in Figure 25 The difference between the Fin Fet device of the embodiment and the Fin Fet device of Embodiment 1 is mainly that the stress material layer 105 in the well region of the PMOS is silicon germanium SiGe, and the stress material layer 105 in the well region of the NMOS is silicon carbide SiC.

[0108] The embodiment respectively selects stress materials for the N-type well region 305 and the P-type well region 304, and the unexpected effect is that optimal stress regulation for different types of well regions can be achieved, and the asymmetry between the NMOS and the PMOS can be improved by respectively regulating, and the stability and switching speed of the overall circuit are further improved.

[0109] Compared with the manufacturing method of the Fin Fet device in Example 1, the manufacturing method of the Fin Fet device in this embodiment first follows steps S201 to S207 of Example 1, and then replaces steps S208a to S210a of Example 1 with the following steps S208b to S210b:

[0110] Step S208b: A silicon nitride mask is deposited on the device formed in step S207, and then a bottom anti-reflective coating 308 and a photoresist 302 are coated on the mask from bottom to top. The bottom anti-reflective coating 308 and the photoresist 302 do not cover the area corresponding to the groove of the fin 104 in the N-type well region 305. For the specific coating method and the structure after exposure, please refer to Figure 17 , then dry etching can be performed to obtain Figure 18 The structure is obtained, that is, the fin with grooves in the N-type well region is obtained. At this time, the TEOS layer 401 in the grooves of the fin 104 in the N-type well region 305 is completely removed, and then silicon germanium can be epitaxially grown in the grooves of the fin 104 in the N-type well region 305 to obtain Figure 19 structure;

[0111] Step 209b: First, Figure 19 The device is covered with an organic dielectric layer 403, and then covered with a bottom anti-reflective coating 308, and then covered with a photoresist 302 on the bottom anti-reflective coating 308. The photoresist 302 does not cover the area corresponding to the fin 104 groove at the P-type well region 304 and is exposed. Figure 20 The structure shown in Figure 1 is obtained after multiple steps of dry etching and cleaning process. Figure 21 As a result, a fin 104 with a groove in the P-type well region is obtained. The TEOS layer 401 in the groove of the fin 104 in the P-type well region 304 is completely removed. At this time, an organic dielectric layer 403 remains on the device. Next, silicon carbide can be epitaxially grown inside and outside the groove of the fin 104 in the P-type well region 304 as a stress material layer 105. The resulting structure is shown in FIG. Figure 22 ;

[0112] Step S210b: using wet etching to sequentially remove the remaining organic dielectric layer 403 and silicon nitride layer 306 to obtain Figure 23 The structure is particularly noted that sulfuric acid solution or tetramethylammonium hydroxide TMAH can be used to remove the organic dielectric layer 403, and phosphoric acid solution is used to remove the silicon nitride layer 306. Then, the oxide layer 301 and the TEOS layer 401 are etched back by dry etching. Figure 24 The NMOS and PMOS respectively use structures with different stress material layers 105 , and the remaining TEOS layer 401 forms the STI layer 103 .

[0113] Then, follow the steps S211 to S212 of Example 1 to obtain the following: Figure 25 In the structure shown, the stress material layer 105 in the well region of the PMOS is made of silicon germanium SiGe, and the stress material layer 105 in the well region of the NMOS is made of silicon carbide SiC.

[0114] Based on the manufacturing method of this embodiment, different epitaxial materials are formed on the fins of the NMOS region and the PMOS region respectively to improve the carrier migration rates of the NMOS and PMOS regions respectively.

[0115] Example 3

[0116] This embodiment is based on the technical solution of Example 1 and further explains the position and size setting of the stress material layer 105 .

[0117] In this embodiment, the channel width of the Fin Fet device can be controlled by controlling the thickness of the stress material layer 105. A case of a Fin Fet device can be referred to Figure 26 The thickness of the stress material layer 105 of the structure is less than Figure 1 The thickness of the stress material layer 105 of the Fin Fet device is the same as that of the other structures. Figure 1 The same as the FinFet device.

[0118] because Figure 26 In the device, the stress material layer 105 in the well region of the PMOS and the stress material layer 105 in the well region of the NMOS are both made of silicon germanium SiGe. The difference between its manufacturing method and the Fin Fet device manufacturing method provided in Example 1 is mainly that: when the epitaxial stress material layer 105 material is grown in step S209a, the epitaxial thickness is reduced, and the remaining steps are the same as in Example 1.

[0119] The channel width of the Fin Fet device is the thickness of the fin in the third direction. In the above embodiment, the unexpected effect is that by changing the thickness of the stress material inside the fin 104, the propagation path of the current in the channel area can be effectively changed. For example, under the premise of keeping the lateral size of the fin 104 unchanged, the channel width can be expanded in the third direction by increasing the thickness of the stress material layer 105, thereby increasing the equivalent conductive cross-sectional area of ​​the channel and enhancing the driving current capability. In other words, the degree of expansion of the channel width can be adjusted by controlling the thickness of the stress material, and then the degree of enhancement of the driving current capability can be controlled according to demand. Based on this design, the thickness of the stress material can be flexibly selected according to the design goal of the Fin Fet device (such as high performance or low power consumption). Without changing the structure of the Fin Fet device, without destroying the structural integrity of the fin 104 or increasing the lithography burden, an adjustable design of the channel width can be achieved, which has good design freedom and process compatibility.

[0120] Example 4

[0121] This embodiment is based on the technical solution of Example 2 and further explains the position and size setting of the stress material layer 105 .

[0122] In this embodiment, the channel width of the Fin Fet device can be controlled by controlling the thickness of the stress material layer 105. A case of a Fin Fet device can be referred to Figure 27 The thickness of the stress material layer 105 of the structure is less than Figure 25 The thickness of the stress material layer 105 of the Fin Fet device is the same as that of the other structures. Figure 25 The same as the FinFet device.

[0123] Figure 27 In the device, the stress material layer 105 in the well region of the PMOS is made of silicon germanium SiGe, and the stress material layer 105 in the well region of the NMOS is made of silicon carbide SiC. The difference between its manufacturing method and the Fin Fet device manufacturing method provided in Example 2 is mainly that: when the epitaxial stress material layer 105 material is grown in step S209b, the epitaxial thickness is reduced, and the remaining steps are the same as in Example 2.

[0124] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A FinFet device, characterized in that: Including the following settings from bottom to top: substrate; an epitaxial layer located on the substrate; a fin-shaped well region located above the epitaxial layer, the fin-shaped well region including a plurality of fins formed side by side along a first direction and extending in a second direction perpendicular to the first direction, and a stress material layer epitaxially grown inside each fin; An STI layer is located on the epitaxial layer and deposited between every two adjacent fins, and a side surface of the STI layer contacts a side surface of the fin; an etch stop layer formed on a portion of a side surface of the fin that is not in contact with the STI layer and on an upper surface of the fin; The gate layer structure is deposited on the fin-shaped well region and the STI layer, arranged along the second direction and extending toward the first direction.

2. A Fin Fet device according to claim 1, characterized in that: The fin-shaped well region includes a plurality of P-type well regions and a plurality of N-type well regions, and each of the P-type well regions and each of the N-type well regions constitutes a fin.

3. A Fin Fet device according to claim 2, characterized in that: The stress material layer is selected as follows: When the fin is an N-type well region, the stress material layer is made of silicon germanium; When the fin is a P-type well region, the stress material layer is made of silicon germanium or silicon carbide.

4. A Fin Fet device according to claim 1, characterized in that: A groove is provided on the upper surface of the fin, and the stress material layer is epitaxially arranged in the groove.

5. The Fin Fet device according to claim 1, characterized in that: The channel width of the FinFet device is controlled by controlling the thickness of the stress material layer.

6. A method for manufacturing a FinFet device, for manufacturing a FinFet device according to any one of claims 1 to 5, characterized in that: The method for manufacturing the fin-shaped well region comprises the following steps: The fin is formed on the epitaxial layer, wherein a groove is provided on the fin, and an oxide layer and a silicon nitride layer formed in the process of forming the fin remain on the top of the non-groove portion of the fin; A TEOS layer is deposited on the epitaxial layer to wrap the fin, and a planarization process is performed to make the upper surface of the TEOS layer flush with the upper surface of the silicon nitride layer; The TEOS layer is etched back from the top, and the etched back thickness h' is the thickness difference from the top of the TEOS layer to the bottom of the trench, and the remaining TEOS layer after the etch back forms the STI layer; epitaxially forming the stress material layer in the trench; removing the remaining oxide and silicon nitride layers; The etching stop layer is formed on the surface of the fin and the gate layer structure is manufactured.

7. The method for manufacturing a FinFet device according to claim 6, wherein: The fin is formed by: Performing ion implantation on the epitaxial layer to form a well region; An oxide layer, a silicon nitride layer, and a sacrificial layer are sequentially formed on the well region from bottom to top, and a photoresist layer is formed on the sacrificial layer, the photoresist layer being arranged along the first direction and extending toward the second direction, wherein the photoresist layer comprises a bottom anti-reflective coating layer and a photoresist layer sequentially stacked from bottom to top, and then exposed; Manufacturing a plurality of fin-shaped structures on the well region by dry etching, and removing the oxide layer and the silicon nitride layer on the fin-shaped structures by wet etching; forming an oxide layer and a silicon nitride layer in sequence from bottom to top on the well region; The oxide layer and silicon nitride layer in the horizontal direction are removed by dry etching; A portion of the well region with a thickness of h is removed from the top by dry etching, where the thickness h is the thickness of the non-fin structure portion of the well region, to form a plurality of fins with grooves.

8. The method for manufacturing a FinFet device according to claim 7, wherein: The well region includes a P-type well region and an N-type well region; The P-type well region and the N-type well region are formed by different ion implantations.

9. The method for manufacturing a FinFet device according to claim 6, wherein: The method for forming the etching stop layer is as follows: An oxide layer is formed on the side of the fin that is not in contact with the STI layer and on the top of the fin by thermal oxidation to serve as the etching stop layer.

10. The method for manufacturing a FinFet device according to claim 6, wherein: The manufacturing method of the gate layer structure is as follows: Depositing and forming a gate layer material that wraps the STI layer and the fin, and performing a planarization process on the top surface of the gate layer material; forming a sacrificial layer on the gate layer material; A photoresist layer is formed on the sacrificial layer, which is arranged along the second direction and extends toward the first direction. The photoresist layer includes a bottom anti-reflective coating and a photoresist layer stacked sequentially from bottom to top. The gate layer structure is obtained by exposure.

Images