A semiconductor device and a method of fabricating the same

Abstract

The application provides a semiconductor device and a preparation method thereof, which comprises a gate structure arranged on a substrate, a source doped region and a drain doped region arranged in the substrate outside the gate structure, a first dielectric layer arranged on the substrate outside the gate structure, a surface of the first dielectric layer being flush with a surface of the gate structure, a cavity arranged on the substrate between the first dielectric layer and the gate structure, the cavity exposing at least the source doped region and the drain doped region, a second dielectric layer formed on the first dielectric layer and the gate structure, the second dielectric layer covering the cavity, a first groove and a second groove arranged in the second dielectric layer, the first groove exposing part of the cavity, the second groove exposing the gate structure, a first conductive column formed in the cavity below the first groove and the first groove, and a second conductive column formed in the second groove, so that there is a cavity outside the first conductive column, and the parasitic capacitance of the semiconductor device is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a preparation method thereof. Background Art

[0002] like Figure 1 As shown in the figure, in a semiconductor device, after the gate structure is formed on the substrate, a metal silicide layer (silicide) is formed on the surface of the source region S, drain region D and gate G, and an SPT (stress proximity process) process is performed to reduce the width of the sidewalls on both sides of the gate G in the lateral direction, and finally a contact hole CT is formed. However, as the process requirements continue to shrink, the CD (line width) size of the contact hole CT is getting smaller and smaller, which makes the process of etching to form the contact hole CT more and more difficult, and the contact hole CT open circuit problem often occurs on the active area (AA), such as the problem that the contact hole CT cannot be connected to the source region S, drain region D or gate G in the MOS tube (such as Figure 2 As shown in the figure, the yield is affected, and there is also the problem of large parasitic capacitance of semiconductor devices. Summary of the Invention

[0003] One of the objectives of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can reduce the parasitic capacitance of the semiconductor device.

[0004] Another object of the present invention is to reduce the process difficulty of contact hole lithography and etching, expand the process window of the contact hole, and solve the problems caused by contact hole etching.

[0005] In order to solve the above problems, the present invention provides a semiconductor device, including a gate structure arranged on a substrate, a source doped region and a drain doped region being arranged in the substrate outside the gate structure, a first dielectric layer being arranged on the substrate outside the gate structure, a surface of the first dielectric layer being flush with the surface of the gate structure, a cavity being arranged on the substrate between the first dielectric layer and the gate structure, the cavity exposing at least the source doped region and the drain doped region, a second dielectric layer being formed on the first dielectric layer and the gate structure, the second dielectric layer covering the cavity, a first groove and a second groove being arranged in the second dielectric layer, the first groove exposing a portion of the cavity, the second groove exposing the gate structure, a first conductive pillar being formed in the first groove and in the cavity below the first groove, and a second conductive pillar being formed in the second groove.

[0006] Optionally, the cavity includes a first cavity and a second cavity, the first cavity is located below the first groove and covers the source doping region and the drain doping region, the second cavity is located outside the first cavity and is connected to the first cavity, and the first conductive column is arranged in the first cavity and the first groove.

[0007] Further, a first filling material is arranged in the second cavity, and the first filling material occupies part of the space of the second cavity.

[0008] In another aspect, the application provides a method for manufacturing a semiconductor device, and the semiconductor device is manufactured by the following steps:

[0009] A substrate is provided, and a gate structure is arranged on the substrate, and a source doped region and a drain doped region are arranged in the substrate outside the gate structure;

[0010] A cavity material layer and a first dielectric layer are formed outside the gate structure, the cavity material layer is arranged on the substrate between the gate structure and the first dielectric layer, and the cavity material layer covers at least the source doped region and the drain doped region, wherein the surface of the first dielectric layer is flush with the surface of the cavity material layer and the surface of the gate structure;

[0011] A second dielectric layer is formed on the first dielectric layer and the gate structure, and a first recess and a second recess are formed in the second dielectric layer, the first recess exposes part of the cavity material layer, and the second recess exposes the gate structure;

[0012] The cavity material layer at the bottom of the first recess is removed, and a first conductive column is formed in the first recess and the cavity below the first recess, and a second conductive column is formed in the second recess;

[0013] The remaining cavity material layer is removed.

[0014] Optionally, the cavity material layer is a material with poor thermal stability and can be gasified.

[0015] Further, the material of the cavity material layer is amorphous carbon, fluorinated amorphous carbon, silica gel or cis-butadiene rubber.

[0016] In another aspect, the application provides a method for manufacturing a semiconductor device, and the semiconductor device is manufactured by the following steps:

[0017] A substrate is provided, and a gate structure is arranged on the substrate, and a source doped region and a drain doped region are arranged in the substrate outside the gate structure;

[0018] A cavity material layer and a first dielectric layer are formed outside the gate structure, the cavity material layer is arranged on the substrate between the gate structure and the first dielectric layer, and the cavity material layer covers at least the source doped region and the drain doped region, wherein the surface of the first dielectric layer is flush with the surface of the cavity material layer and the surface of the gate structure;

[0019] forming a second dielectric layer on the first dielectric layer and the gate structure, wherein a first groove and a second groove are formed in the second dielectric layer, wherein the first groove exposes a portion of the cavity material layer, and the second groove exposes the gate structure;

[0020] Removing the cavity material layer from the first groove to form a cavity, filling the cavity outside the first groove with a first filling material, forming a first conductive pillar in the first groove and the cavity below, and forming a second conductive pillar in the second groove;

[0021] The first filling material is subjected to a shrinkage treatment to obtain a shrunken first filling material, wherein the shrunken first filling material occupies a portion of the space of the cavity outside the first groove.

[0022] Optionally, the cavity material layer is a gasifiable material with poor thermal stability.

[0023] Optionally, the first filling material filled in the cavity outside the first groove includes a first solute and a first solvent, the material of the first solute is a polymer material, and the material of the first solvent is an ethanol solution; or, the material of the first solute is silicon dioxide, and the material of the first solvent is n-butyl ether.

[0024] Optionally, the first filling material after shrinkage treatment includes only a first solute, and the material of the first solute is a high molecular polymer material or silicon dioxide.

[0025] Compared with the prior art, the present invention has the following unexpected technical effects:

[0026] The present invention provides a semiconductor device and a method for manufacturing the same, comprising a gate structure disposed on a substrate, a source doped region and a drain doped region disposed in the substrate outside the gate structure, a first dielectric layer disposed on the substrate outside the gate structure, the surface of the first dielectric layer being flush with the surface of the gate structure, a cavity disposed in the substrate between the first dielectric layer and the gate structure, the cavity exposing at least the source doped region and the drain doped region, a second dielectric layer formed on the first dielectric layer and the gate structure, the second dielectric layer covering the cavity, a first recess and a second recess disposed in the second dielectric layer, the first recess exposing a portion of the cavity, the second recess exposing the gate structure, a first conductive pillar formed in the first recess and in the cavity below the first recess, and a second conductive pillar formed in the second recess. The present invention reduces the parasitic capacitance of the semiconductor device by utilizing the cavity not filled by the first conductive pillar, i.e., the cavity outside the first conductive pillar.

[0027] In the semiconductor device fabrication method provided by the present invention, the first and second recesses are formed simultaneously, and the surface of the first dielectric layer, the cavity material layer, and the surface of the gate structure are flush, so that the etching depths of the first and second recesses are on the same horizontal plane. This reduces the process difficulty of the photolithography and etching processes for forming the contact holes, reduces the process difficulty and cost of the contact hole manufacturing process, increases the contact hole etching process window, and solves problems such as open conductive pillars that occur during the contact hole etching process, thereby improving yield, reducing contact hole overlay alignment requirements, and reducing process costs by omitting the sidewall removal (i.e., SPT process). Simultaneously, a cavity is formed outside the first conductive pillar, reducing the parasitic capacitance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Schematic diagram of the structure of a semiconductor device in the prior art.

[0029] Figure 2 This is a schematic diagram of a contact hole open in the prior art.

[0030] Figure 3 This is a schematic structural diagram of a substrate provided in Example 1 of the present invention.

[0031] Figure 4 This is a schematic diagram of the structure after the oxide sidewalls are formed according to the first embodiment of the present invention.

[0032] Figure 5 This is a schematic structural diagram of the first embodiment of the present invention after the cavity material film layer is formed.

[0033] Figure 6 This is a schematic structural diagram of the first embodiment of the present invention after the cavity material layer is formed.

[0034] Figure 7 This is a schematic structural diagram after forming the first dielectric layer according to the first embodiment of the present invention.

[0035] Figure 8 This is a schematic structural diagram of the first embodiment of the present invention after a patterned photoresist layer is formed.

[0036] Figure 9 This is a schematic structural diagram after the first transition groove and the second transition groove are formed in the first embodiment of the present invention.

[0037] Figure 10 This is a schematic structural diagram of the first groove and the second groove formed in the first embodiment of the present invention.

[0038] Figure 11 This is a schematic structural diagram of the first embodiment of the present invention after the first cavity is formed.

[0039] Figure 121 is a structural diagram of the positional relationship between the first conductive pillar and the cavity material layer after the first conductive pillar is formed according to the first embodiment of the present invention.

[0040] Figure 13 for Figure 11 Schematic cross-section along AA′.

[0041] Figure 14 for Figure 11 Schematic cross-section along BB′.

[0042] Figure 15 This is a schematic structural diagram of the first embodiment of the present invention after the second cavity is formed.

[0043] Figure 16 Schematic diagram of the positional relationship between the first conductive pillar and the second cavity after the second cavity is formed in the first embodiment of the present invention.

[0044] Figure 17 Schematic diagram of the positional relationship between the cavity-back cavity and the gate structure formed in the second embodiment of the present invention.

[0045] Figure 18 This is a schematic diagram of the structure after the cavity is formed in the second embodiment of the present invention.

[0046] Figure 19 This is a structural schematic diagram of the positional relationship between the first cavity and the first filling material after the first filling material in the first cavity is removed according to the second embodiment of the present invention.

[0047] Figure 20 This is a schematic structural diagram of the second embodiment of the present invention after the first filling material in the first cavity is removed.

[0048] Figure 21 This is a schematic structural diagram of the second embodiment of the present invention after forming the first conductive pillar and the second conductive pillar;

[0049] Figure 22 This is a schematic structural diagram of the second embodiment of the present invention after shrinking the first filling material through shrinkage treatment.

[0050] Description of reference numerals:

[0051] I-first active region; II-second active region; 100-substrate; 101-first well region; 102-second well region; 103-shallow trench isolation structure; 104-first source doping region; 105-first drain doping region; 106-second source doping region; 107-second drain doping region; 108-first metal silicide layer; 210-gate structure; 201-gate oxide layer; 202-polysilicon gate; 203-sidewall; 220-second metal silicide layer; 230- Oxide sidewall; 240′-cavity material film layer; 240-cavity material layer; 250-first dielectric layer; 310-etching stop layer; 320-second dielectric layer; 330-pattern transfer layer; 340-photoresist layer; 351-first transition groove; 352-second transition groove; 353-first groove; 354-second groove; 410-first conductive column; 420-second conductive column; 510-first cavity; 520-second cavity; 600-first filling material. DETAILED DESCRIPTION

[0052] The following is a further detailed description of a semiconductor device and a method for manufacturing the same according to the present invention. The present invention will be described in more detail below with reference to the accompanying drawings, which illustrate preferred embodiments of the present invention. It should be understood that those skilled in the art may modify the present invention described herein while still achieving the advantageous effects of the present invention. Therefore, the following description should be understood as a general guide for those skilled in the art and not as a limitation of the present invention.

[0053] For the sake of clarity, not all features of actual embodiments are described. In the following description, well-known functions and structures are not described in detail because they would obscure the present invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific goals, such as adapting from one embodiment to another to accommodate system or business constraints. Furthermore, it should be understood that such development work may be complex and time-consuming, but is nevertheless a routine undertaking for those skilled in the art.

[0054] In order to make the purpose and features of the present invention more obvious and easy to understand, the specific embodiments of the present invention are further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0055] The present invention provides a semiconductor device, comprising a gate structure disposed on a substrate, wherein a source doped region and a drain doped region are disposed in the substrate outside the gate structure, a first dielectric layer is disposed on the substrate outside the gate structure, a surface of the first dielectric layer being flush with a surface of the gate structure, a cavity being disposed on the substrate between the first dielectric layer and the gate structure, the cavity exposing at least the source doped region and the drain doped region, a second dielectric layer being formed on the first dielectric layer and the gate structure, the second dielectric layer covering the cavity, a first groove and a second groove being disposed in the second dielectric layer, the first groove exposing a portion of the cavity, the second groove exposing the gate structure, a first conductive pillar being formed in the first groove and in the cavity below the first groove, and a second conductive pillar being formed in the second groove.

[0056] The present invention reduces the parasitic capacitance of the semiconductor device by using the cavity not filled by the first conductive column, that is, the cavity outside the first conductive column. At the same time, the surface of the first dielectric layer is flush with the surface of the gate structure, so that the first groove and the second groove have no steps, which reduces the process difficulty of the first groove and the second groove, reduces the process difficulty and cost of the contact hole, improves the etching process window of the contact hole, and solves the open circuit problem that occurs in the contact hole etching process, thereby improving the yield and reducing the contact hole overlay alignment specification requirements. Example

[0057] This embodiment provides a method for manufacturing a semiconductor device, comprising the following steps:

[0058] Step S11: providing a substrate, on which a gate structure is provided, and a source doping region and a drain doping region are provided in the substrate outside the gate structure;

[0059] Step S12: forming a cavity material layer and a first dielectric layer outside the gate structure, wherein the cavity material layer is located on the substrate between the gate structure and the first dielectric layer, and the cavity material layer at least covers the source doped region and the drain doped region, wherein the surfaces of the first dielectric layer and the cavity material layer are flush with the surface of the gate structure;

[0060] Step S13: forming a second dielectric layer on the first dielectric layer and the gate structure, wherein a first groove and a second groove are formed in the second dielectric layer, wherein the first groove exposes a portion of the cavity material layer, and the second groove exposes the gate structure;

[0061] Step S14: removing the cavity material layer at the bottom of the first groove, and forming a first conductive pillar in the first groove and the cavity below the first groove, and forming a second conductive pillar in the second groove;

[0062] Step S15: removing the remaining cavity material layer.

[0063] In this embodiment, the first and second recesses are formed simultaneously, and the surface of the first dielectric layer, the cavity material layer, and the surface of the gate structure are flush, ensuring that the etching depths of the first and second recesses are on the same level. This reduces the process difficulty and cost of forming the contact hole through photolithography and etching, improves the etching process window for the contact holes, and resolves issues such as open conductive pillars that can occur during the contact hole etching process. This improves yield, reduces contact hole overlay alignment requirements, and reduces process costs by omitting the sidewall removal (i.e., SPT process). Furthermore, a cavity is formed outside the first conductive pillar, reducing the parasitic capacitance of the semiconductor device.

[0064] The following combination Figure 3-Figure 16 A method for manufacturing a semiconductor device provided in this embodiment is described in detail.

[0065] like Figure 3 As shown, step S11 is first performed to provide a substrate 100 , on which a gate structure 210 is disposed. A source doping region and a drain doping region are disposed in the substrate 100 outside the gate structure 210 .

[0066] An active area is provided in the substrate 100, and a shallow trench isolation structure 103 is provided around the outside of the active area. A well region is formed in the substrate 100 of the active area, and the well region extends from one side of the substrate 100 into the substrate 100 and stops in the substrate 100. A gate structure 210 is formed on the surface of one side of the substrate 100. The gate structure 210 includes a gate oxide layer 201, a polysilicon gate 202 and a sidewall 203. The gate oxide layer 201 is located on the surface of the substrate 100, and the polysilicon gate 202 is stacked on the gate oxide layer 201. The sidewall 203 is located on both sides of the gate oxide layer 201 and the polysilicon gate 202, and covers the sidewalls of the gate oxide layer 201 and the polysilicon gate 202. The sidewall spacer 203 includes a first silicon oxide layer, a first silicon nitride layer, a second silicon oxide layer, and a second silicon nitride layer in sequence from a side close to the polysilicon gate 202 to a side away from the polysilicon gate 202 .

[0067] A source doping region and a drain doping region are respectively formed in the substrate 100 on both sides of the gate structure 210. A source extension doping region and a drain extension doping region are further arranged between the source doping region and the drain doping region. The source extension doping region is arranged in contact with the source doping region, and the drain doping region is arranged in contact with the drain doping region.

[0068] A source extension doping region is provided in the substrate 100 on the side of the source doping region close to the drain doping region, and a drain extension doping region is provided in the substrate 100 on the side of the drain doping region close to the source doping region, so that the source extension doping region and the drain extension doping region are both located below the gate structure 210, and a pocket doping region is also provided in the substrate 100 below the source extension doping region and the drain extension doping region.

[0069] In this embodiment, the substrate 100 includes a first active region I and a second active region II for forming low-voltage devices. The first active region I is used to form a low-voltage NMOS transistor, and the second active region II is used to form a low-voltage PMOS transistor. The first active region I and the second active region II are adjacent to each other, and shallow trench isolation structures 103 are provided around the outer sides of the first active region I and the outer sides of the second active region II. A first well region 101 is formed in the substrate 100 in the first active region I. The first well region 101 extends from one surface of the substrate 100 to the other surface and stops within the substrate 100. A second well region 102 is formed in the substrate 100 of the second active region II, and the second well region 102 is arranged on the same side as the first well region 101, and the second well region 102 also extends from one side surface of the substrate 100 to the other side surface and stops in the substrate 100. Preferably, the depth of the second well region 102 is the same as the depth of the first well region 101, wherein the first well region 101 is doped with P-type ions and the second well region 102 is doped with N-type ions, and the height of the shallow trench isolation structure 103 is greater than the depth of the first well region 101 and also greater than the depth of the second well region 102.

[0070] In the first active region I, a first source doping region 104 and a first drain doping region 105 are formed in the substrate 100 on both sides of the gate structure 210, wherein the first source doping region 104 and the first drain doping region 105 are both doped with N-type ions. In the second active region II, a second source doping region 106 and a second drain doping region 107 are formed in the substrate 100 on both sides of the gate structure 210, wherein the second source doping region 106 and the second drain doping region 107 are both doped with P-type ions.

[0071] A first metal silicide layer 108 (silicide) is provided on the source doping region and the drain doping region, and a second metal silicide layer 220 is provided on the polysilicon gate 202. The surface of the second metal silicide layer 220 is flush with the sidewall 203, and the surface of the first metal silicide layer 108 is flush with the surface of the substrate 100.

[0072] See also Figure 4-Figure 7Then, step S12 is performed to form a cavity material layer 240 and a first dielectric layer 250 outside the gate structure 210, wherein the cavity material layer 240 is located on the substrate 100 between the gate structure 210 and the first dielectric layer 250, and the cavity material layer 240 at least covers the source doping region and the drain doping region, wherein the surface of the first dielectric layer 250 and the cavity material layer 240 are flush with the surface of the gate structure 210.

[0073] This step specifically includes:

[0074] like Figure 4 As shown, first, a first oxide layer is formed on the substrate 100. The first oxide layer covers the surface of the gate structure 210, that is, the sidewalls and upper surface of the spacer 203 and the upper surface of the second metal silicide layer 220. The first oxide layer also covers the first metal silicide layer 108. In this embodiment, the first oxide layer is approximately 70 Å.

[0075] Next, the first oxide layer is etched to form oxide spacers 230 outside the spacers 203, exposing the substrate 100 outside the oxide spacers 230 and also exposing the second metal silicide layer 220. The contact between the oxide spacers 230 and the subsequently formed first conductive pillars 410 is better than the contact between the second silicon nitride layer and the first conductive pillars 410.

[0076] like Figure 5 As shown, a cavity material film layer 240' is then formed on the substrate 100. The cavity material film layer 240' covers the surface of the substrate 100, the sidewalls of the oxide spacer 230, and the surface of the second metal silicide layer 220. The cavity material film layer 240' can be made of a material with poor thermal stability and can be vaporized, i.e., a substance that decomposes easily when heated (such as amorphous carbon aC, fluorinated amorphous carbon FC, silica gel, polybutylene rubber (PB), etc.) or a substance that decomposes easily when exposed to light (such as SOC and carbon black polymer). The thickness of the cavity material film layer 240' is 30nm to 60nm, and the thickness can be adjusted according to the gap between the polysilicon gates 202.

[0077] like Figure 6As shown, the cavity material film layer 240′ is then etched to form a cavity material layer 240. The cavity material layer 240 exposes the second metal silicide layer 220, the upper surface of the sidewall spacer 203, the upper surface of the oxide sidewall spacer 230, and the outer surface of the substrate 100. The cavity material layer 240 covers a portion of the first metal silicide layer 108 and is disposed against the oxide sidewall spacer 230. The cavity material film layer 240 is disposed around the outer side of the gate structure 210, so that the cavity material film layer 240 has a rectangular ring shape, for example.

[0078] like Figure 7 As shown, then, a first dielectric layer 250 is formed on the substrate 100, and the first dielectric layer 250 covers the substrate 100 outside the cavity material layer 240, and the surface of the first dielectric layer 250, the surface of the cavity material layer 240 and the surface of the second metal silicide layer 220 are flush.

[0079] See also Figures 8-10 Then, step S13 is performed to form a second dielectric layer 320 on the first dielectric layer 250 and the gate structure 210. A first groove 353 and a second groove 354 are formed in the second dielectric layer 320. The first groove 353 exposes a portion of the cavity material layer 240, and the second groove 354 exposes the gate structure 210.

[0080] This step specifically includes:

[0081] like Figure 8 As shown, first, an etching stop layer 310, a second dielectric layer 320, a pattern transfer layer 330 and a patterned photoresist layer 340 are formed on the first dielectric layer 250, the cavity material layer 240, the oxide sidewall 230, the sidewall and the second metal silicide layer 220, and the patterned photoresist layer 340 has openings above the cavity material layer 240 and the second metal silicide layer 220.

[0082] In this embodiment, the patterned photoresist layer 340 has openings on the cavity material layer 240 on the first source doping region 104 of the first active region I, the cavity material layer 240 of the first drain doping region 105, and above the polysilicon gate 202, and also has openings on the cavity material layer 240 of the second source doping region 106 of the second active region II, the cavity material layer 240 of the second drain doping region 107, and above the polysilicon gate 202.

[0083] The second dielectric layer 320 is an oxide layer, the etching stop layer 310 is silicon nitride, and the pattern transfer layer 330 includes, from bottom to top, an alpha carbon film layer, a silicon oxynitride layer, a first silicon oxide layer, and a BARC layer. The second dielectric layer 320 is formed by, for example, TEOS or high aspect ratio process (HARP) deposition, and thus is a very loose oxide layer, that is, the second dielectric layer 320 has large voids to allow gas to flow. The etching stop layer 310 is formed by using a precursor containing silicon, such as trimethylsilane, and NH3 or N2 in a plasma environment to perform a plasma enhanced chemical vapor deposition (PECVD) process to form at least one of silicon nitride, silicon oxynitride, and silicon carbon nitride with a high selectivity to silicon dioxide. The etching stop layer 310 is a porous film with nanoscale pores, thereby reducing the density of the film. The etching stop layer 310 can also be formed by a low pressure chemical vapor deposition (LPCVD) process in which Ar or He is added as a dilution gas in a reaction gas (a mixture of SiH2Cl2 and NH3) to inhibit the densification process and generate a loose silicon nitride layer.

[0084] As shown in Figure 9 , then, the patterned photoresist layer 340 is used as a mask to etch the pattern transfer layer 330, the second dielectric layer 320, and the etching stop layer 310 in the opening by a multi-step etching process to expose the cavity material layer 240 and form a first transition groove 351, and to expose the second metal silicide layer 220 and form a second transition groove 352. At this time, the first transition groove 351 exposes a part of the cavity material layer 240, for example, a pair of opposite edges of the rectangular ring of the cavity material layer 240, and another pair of opposite edges of the rectangular ring are outside the first transition groove 351 and are not exposed.

[0085] As shown in Figure 10 , then, the photoresist layer 340 and the pattern transfer layer 330 are removed to expose the second dielectric layer 320 and form a first groove 353 and a second groove 354.

[0086] As shown in Figure 11-14 , then, the photoresist layer 340 and the pattern transfer layer 330 are removed to expose the second dielectric layer 320 and form a first groove 353 and a second groove 354.

[0087] This step specifically includes:

[0088] As shown in Figure 11As shown, first, the cavity material layer 240 under the first groove 353 is removed by a dry etching process to expose the first metal silicide layer 108 under the first groove 353 to form a first cavity 510, which is located at the bottom of the first groove 353 and is connected to the first groove 353.

[0089] like Figure 12-14 As shown, a first conductive layer is then formed on the inner wall of the first groove 353, the inner wall of the first cavity 510, the inner wall of the second groove 354 and the surface of the second dielectric layer 320. The first conductive layer sequentially includes a titanium film layer and a titanium nitride film layer.

[0090] Next, metal material is filled into the first groove 353 , the first cavity 510 and the second groove 354 through an etching process or a CVD (Chemical Vapor Deposition) process.

[0091] Finally, the metal material on the second dielectric layer 320 is removed by a CMP process to expose the second dielectric layer 320, thereby forming a first conductive pillar 410 in the first groove 353 and the first cavity 510, and a second conductive pillar 420 in the second groove 354. At this time, the first conductive pillar 410 and the cavity material layer 240 are connected and surrounded in sequence outside the gate structure 210 (as shown in FIG. Figure 12 It is worth noting that the attached Figure 12 The first conductive column 410 completely occupies two sides of the "rectangular ring". In fact, the first conductive column 410 can also only define a small part of the source and drain positions as in the existing contact hole process, occupying a small part of the two sides of the "rectangular ring".

[0092] See also Figure 15-16 Then, step S15 is performed to remove the remaining cavity material layer 240.

[0093] Specifically, the semiconductor device is placed in a high-temperature environment, so that the remaining cavity material layer 240 is vaporized or decomposed into small molecules at high temperature, and finally overflows from the gaps in the second dielectric layer 320, or diffuses into the surrounding environment, such as the first conductive column 410 and the first dielectric layer 250, thereby forming a second cavity 520 outside the first conductive column 410, wherein the first cavity 510 and the second cavity 520 form a rectangular ring, the shape of which is the same as that of the cavity material layer 240, and occupies the position of the cavity material layer 240.

[0094] See also Figure 15-16This embodiment provides a semiconductor device, including a gate structure 210 disposed on a substrate 100, wherein a source doping region and a drain doping region are disposed in the substrate 100 outside the gate structure 210, a first dielectric layer 250 is disposed on the substrate 100 outside the gate structure 210, the surface of the first dielectric layer 250 is flush with the surface of the gate structure 210, and a cavity is disposed on the substrate 100 between the first dielectric layer 250 and the gate structure 210, wherein the cavity exposes at least the source doping region and the drain doping region. In the region, a second dielectric layer 320 is formed on the first dielectric layer 250 and the gate structure 210, the second dielectric layer 320 covers the cavity, a first groove 353 and a second groove 354 are provided in the second dielectric layer 320, the first groove 353 exposes a portion of the cavity, the second groove 354 exposes the gate structure 210, a first conductive pillar 410 is formed in the first groove 353 and the cavity below the first groove 353, and a second conductive pillar 420 is formed in the second groove 354.

[0095] Oxide spacers 230 are formed on the sidewalls of the gate structure 210. A cavity is formed outside the oxide spacers 230. The cavity includes a first cavity 510 and a second cavity 520. The first cavity 510 and the second cavity 520 form a ring shape (e.g., a rectangular ring). The first cavity 510 is located below the first recess 353 and covers the source and drain doped regions. The second cavity is located outside the first cavity 510 and communicates with the first cavity 510. The first conductive pillar 410 is disposed within the first cavity 510 and the first recess 353. A first dielectric layer 250 is formed on the substrate 100 outside the cavity. The surface of the first dielectric layer 250 is flush with the surface of the gate structure 210.

[0096] An etch-stop layer 310 and a second dielectric layer 320 are formed on the first dielectric layer 250. A first groove 353 and a second groove 354 are formed in the second dielectric layer 320. The first groove 353 passes through the etch-stop layer 310 and exposes the first cavity 510. The second groove 354 passes through the etch-stop layer 310 and exposes the gate structure 210. The first conductive pillar 410 is located in the first cavity 510 and the first groove 353. Example

[0097] See also Figures 17-22 Compared with the first embodiment, this embodiment provides a method for preparing a semiconductor device, comprising the following steps:

[0098] Step S21: providing a substrate 100 , on which a gate structure 210 is disposed, and a source doping region and a drain doping region are disposed in the substrate 100 outside the gate structure 210 ;

[0099] Step S22: forming a cavity material layer 240 and a first dielectric layer 250 outside the gate structure 210, wherein the cavity material layer 240 is located on the substrate 100 between the gate structure 210 and the first dielectric layer 250, and the cavity material layer 240 at least covers the source doped region and the drain doped region, wherein the surfaces of the first dielectric layer 250 and the cavity material layer 240 are flush with the surface of the gate structure 210;

[0100] Step S23: forming a second dielectric layer 320 on the first dielectric layer 250 and the gate structure 210 , wherein a first groove 353 and a second groove 354 are formed in the second dielectric layer 320 , wherein the first groove 353 exposes a portion of the cavity material layer 240 , and the second groove 354 exposes the gate structure 210 ;

[0101] Step S24: removing the cavity material layer 240 from the first groove 353 to form a cavity, filling the cavity outside the first groove 353 with a first filling material 600, forming a first conductive pillar 410 in the first groove 353 and the cavity below, and forming a second conductive pillar 420 in the second groove 354;

[0102] Step S25 : shrinking the first filling material 600 to obtain a shrunk first filling material 600 . The shrunk first filling material 600 occupies part of the space of the cavity outside the first groove 353 .

[0103] Here, steps S21 to S23 of this embodiment may refer to steps S11 to S13 in the first embodiment.

[0104] Step S24 specifically includes:

[0105] like Figure 17-18 As shown, first, the cavity material layer 240 is removed from the first groove 353 by an ashing process to form a cavity. The cavity includes a first cavity 510 located below the first groove 353 and a second cavity 520 located outside the first groove 353. The first cavity 510 is connected to the second cavity 520.

[0106] like Figure 19-20As shown, the cavity is then filled with a first filling material 600 via a flowable chemical vapor deposition (FCVD) process or a spin coating (SOD) process. The first filling material 600 is a shrinkable material and includes a first solute and a first solvent. In one embodiment, the first solute is a polymer material, such as phenolic resin, and the first solvent is an ethanol solution. The polymer material absorbs the ethanol solution to form the first filling material 600. In another embodiment, the first solute is silicon dioxide, and the first solvent is n-butyl ether.

[0107] Please continue reading Figure 20 Then, the first filling material 600 in the first cavity 510 is removed by a dry etching process or a development method.

[0108] Next, a first conductive pillar 410 is formed in the first cavity 510 and the first groove 353 , and a second conductive pillar 420 is formed in the second groove 354 .

[0109] like Figure 21-22 As shown, step S25 specifically includes:

[0110] The heat treatment shrinks the first filling material 600. The first solvent in the first filling material 600 evaporates and escapes from the second dielectric layer 320, leaving a first filling material 600 containing only the first solute. The volume of the first filling material 600 shrinks, so that only a portion of the second cavity 520 is filled with the first filling material 600. The heat treatment temperature is 100°C to 1000°C.

[0111] Compared with the first embodiment, a first filling material 600 is provided in the second cavity 520 of the semiconductor device provided in this embodiment, and the first filling material 600 occupies part of the space of the second cavity 520 .

[0112] In summary, the present invention provides a semiconductor device and a method for manufacturing the same, comprising a gate structure disposed on a substrate, a source doped region and a drain doped region disposed in the substrate outside the gate structure, a first dielectric layer disposed on the substrate outside the gate structure, the surface of the first dielectric layer being flush with the surface of the gate structure, a cavity disposed on the substrate between the first dielectric layer and the gate structure, the cavity exposing at least the source doped region and the drain doped region, a second dielectric layer formed on the first dielectric layer and the gate structure, the second dielectric layer covering the cavity, a first recess and a second recess disposed in the second dielectric layer, the first recess exposing a portion of the cavity, the second recess exposing the gate structure, a first conductive pillar formed in the first recess and in the cavity below the first recess, and a second conductive pillar formed in the second recess. The present invention reduces the parasitic capacitance of the semiconductor device by utilizing the cavity not filled by the first conductive pillar, i.e., the cavity outside the first conductive pillar.

[0113] In the semiconductor device fabrication method provided by the present invention, the first and second recesses are formed simultaneously, and the surface of the first dielectric layer, the cavity material layer, and the surface of the gate structure are flush, so that the etching depths of the first and second recesses are on the same horizontal plane. This reduces the process difficulty of the photolithography and etching processes for forming the contact holes, reduces the process difficulty and cost of the contact hole manufacturing process, increases the contact hole etching process window, and solves problems such as open conductive pillars that occur during the contact hole etching process, thereby improving yield, reducing contact hole overlay alignment requirements, and reducing process costs by omitting the sidewall removal (i.e., SPT process). Simultaneously, a cavity is formed outside the first conductive pillar, reducing the parasitic capacitance of the semiconductor device.

[0114] In addition, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0115] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A semiconductor device comprising a gate structure disposed on a substrate, wherein a source doping region and a drain doping region are disposed in the substrate outside the gate structure, wherein: A first dielectric layer is provided on the substrate outside the gate structure, and the surface of the first dielectric layer is flush with the surface of the gate structure. A cavity is provided on the substrate between the first dielectric layer and the gate structure, and the cavity at least exposes the source doping region and the drain doping region. A second dielectric layer is formed on the first dielectric layer and the gate structure, and the second dielectric layer covers the cavity. A first groove and a second groove are provided in the second dielectric layer, and the first groove exposes part of the cavity, and the second groove exposes the gate structure. A first conductive column is formed in the first groove and the cavity below the first groove, and a second conductive column is formed in the second groove.

2. The semiconductor device according to claim 1, wherein The cavity includes a first cavity and a second cavity, the first cavity is located below the first groove and covers the source doping region and the drain doping region, the second cavity is located outside the first cavity and is connected to the first cavity, and the first conductive column is arranged in the first cavity and the first groove.

3. The semiconductor device according to claim 2, wherein A first filling material is disposed in the second cavity, and the first filling material occupies a portion of the space of the second cavity.

4. A method for preparing a semiconductor device, comprising preparing the semiconductor device according to claim 1 or 2, wherein: The following steps are involved: Providing a substrate, on which a gate structure is disposed, and a source doping region and a drain doping region are disposed in the substrate outside the gate structure; forming a cavity material layer and a first dielectric layer outside the gate structure, wherein the cavity material layer is located on the substrate between the gate structure and the first dielectric layer, and the cavity material layer at least covers the source doped region and the drain doped region, wherein the surfaces of the first dielectric layer and the cavity material layer are flush with the surface of the gate structure; forming a second dielectric layer on the first dielectric layer and the gate structure, wherein a first groove and a second groove are formed in the second dielectric layer, wherein the first groove exposes a portion of the cavity material layer, and the second groove exposes the gate structure; removing the cavity material layer at the bottom of the first groove, and forming a first conductive pillar in the first groove and the cavity below the first groove, and forming a second conductive pillar in the second groove; The remaining cavity material layer is removed.

5. The method for preparing a semiconductor device according to claim 4, wherein: The cavity material layer is a gasifiable material with poor thermal stability.

6. The method for preparing a semiconductor device according to claim 5, wherein: The material of the cavity material layer is amorphous carbon, fluorinated amorphous carbon, silica gel or butadiene rubber.

7. A method for preparing a semiconductor device, comprising preparing the semiconductor device according to claim 3, wherein: The following steps are involved: Providing a substrate, on which a gate structure is disposed, and a source doping region and a drain doping region are disposed in the substrate outside the gate structure; forming a cavity material layer and a first dielectric layer outside the gate structure, wherein the cavity material layer is located on the substrate between the gate structure and the first dielectric layer, and the cavity material layer at least covers the source doped region and the drain doped region, wherein the surfaces of the first dielectric layer and the cavity material layer are flush with the surface of the gate structure; forming a second dielectric layer on the first dielectric layer and the gate structure, wherein a first groove and a second groove are formed in the second dielectric layer, wherein the first groove exposes a portion of the cavity material layer, and the second groove exposes the gate structure; Removing the cavity material layer from the first groove to form a cavity, filling the cavity outside the first groove with a first filling material, forming a first conductive pillar in the first groove and the cavity below, and forming a second conductive pillar in the second groove; The first filling material is subjected to a shrinkage treatment to obtain a shrunken first filling material, wherein the shrunken first filling material occupies a portion of the space of the cavity outside the first groove.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The cavity material layer is a gasifiable material with poor thermal stability.

9. The method for preparing a semiconductor device according to claim 7, wherein: The first filling material filled in the cavity outside the first groove includes a first solvent and a first solute, the material of the first solute is a polymer material, and the material of the first solvent is an ethanol solution; or the material of the first solute is silicon dioxide, and the material of the first solvent is n-butyl ether.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The first filling material after shrinkage treatment only includes a first solute, and the material of the first solute is a high molecular polymer material or silicon dioxide.

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