Display device having pixel region

Abstract

A display device having a pixel area is provided. The pixel region may be disposed between the first gate line and the second gate line. Each pixel region may include a first sub-pixel controlled by a first gate line and a second sub-pixel controlled by a second gate line. The second sub-pixel may display a different color from the first sub-pixel of the corresponding pixel region. The first sub-pixel / second sub-pixel of each pixel region may include a first driving circuit / second driving circuit disposed close to the first gate line / second gate line. The second driving circuit of each pixel region may share a data line with the first driving circuit of an adjacent pixel region. The second drive circuit of each pixel region may have a symmetric arrangement with the first drive circuit of an adjacent pixel region. Accordingly, a deviation in coupling capacitance occurring between each driving circuit and a gate line coupled to the corresponding driving circuit may be reduced or minimized.

Description

Technical Field

[0001] The present disclosure relates to a display device in which each pixel region is electrically connected to a pad region through one of the connection lines. Background Art

[0002] Typically, a display device provides an image to a user. For example, a display device may include multiple pixel regions. Each pixel region may display a variety of colors. For example, each pixel region may include multiple sub-pixels. The sub-pixels in each pixel region may display different colors. For example, each pixel region may include a first sub-pixel and a second sub-pixel that displays a different color than the first sub-pixel.

[0003] The second subpixel of each pixel region can be controlled independently of the first subpixel of the corresponding pixel region. For example, the first subpixel of each pixel region can include a first driver circuit, and the second subpixel of each pixel region can include a second driver circuit. The first subpixel and the second subpixel of each pixel region can be controlled by different gate signals. For example, the first driver circuit of each pixel region can be electrically connected to a first gate line, and the second driver circuit of each pixel region can be electrically connected to a second gate line.

[0004] The pixel region may be arranged between the first gate line and the second gate line. Therefore, the second drive circuit of each pixel region may have a different arrangement than the first drive circuit of the corresponding pixel region. For example, each of the first drive circuit and the second drive circuit in each pixel region may include a drive thin film transistor, and the distance between the drive thin film transistor of the second drive circuit and the second gate line may be different from the distance between the drive thin film transistor of the first drive circuit and the first gate line. Summary of the Invention

[0005] In a display device, coupling capacitance may occur between each driving circuit and a gate line electrically connected to the corresponding driving circuit. The coupling capacitance may be proportional to the distance between the driving thin film transistor of each driving circuit and the gate line electrically connected to the corresponding driving circuit. Therefore, in the display device, the second sub-pixel of each pixel area may have a different coupling capacitance than the first sub-pixel of the corresponding pixel area. That is, in the display device, the light emitted by the second sub-pixel of each pixel area may have a different brightness than the light emitted by the first sub-pixel of the corresponding pixel area. Therefore, according to the display device in the related art, the quality of the image may be reduced due to the brightness deviation of the light emitted by the sub-pixels in each pixel area. Therefore, the present disclosure relates to a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of the related art.

[0006] One benefit of the present disclosure is to provide a display device capable of reducing luminance deviation of light emitted from sub-pixels of each pixel region.

[0007] Another benefit of the present disclosure is to provide a display device capable of reducing the deviation in coupling capacitance of sub-pixels in each pixel area.

[0008] Additional advantages, benefits, and features of the present disclosure will be described in part in the following description and will become apparent to those skilled in the art after reviewing the following or from practice of the present disclosure. The benefits and other advantages of the present disclosure can be realized and achieved through the structures particularly pointed out in this specification and claims and the accompanying drawings.

[0009] To achieve these benefits and other advantages and in accordance with the purposes of the present disclosure, as embodied and broadly described herein, a display device is provided, comprising a first gate line, a first data line, and a second gate line. The first gate line and the second gate line extend in a first direction. The second gate line is arranged parallel to the first gate line. The data line extends in a second direction. The second direction is perpendicular to the first direction. The data line crosses the first gate line and the second gate line. A first drive circuit for a first subpixel is electrically connected to the first gate line and the first data line. A second drive circuit for a second subpixel is electrically connected to the first data line and the second gate line. The first data line passes between the first subpixel and the second subpixel. A first light-emitting area of ​​the first subpixel is arranged between the first drive circuit and the second gate line. A second light-emitting area of ​​the second subpixel is arranged between the first gate line and the second drive circuit. The second light-emitting area displays a different color from the first light-emitting area. The second drive circuit has a symmetrical arrangement with the first drive circuit.

[0010] The second light emitting region may be disposed along the first direction with the first light emitting region.

[0011] Each of the first driving circuit and the second driving circuit may include a driving thin film transistor, and a gate electrode of the driving thin film transistor may be arranged in parallel with the first gate line and the second gate line.

[0012] The semiconductor pattern of the driving thin film transistor may be disposed parallel to the first data line.

[0013] The second data line may be arranged parallel to the first data line. The third drive circuit of the third subpixel may be electrically connected to the first gate line and the second data line. The fourth drive circuit of the fourth subpixel may be electrically connected to the second data line and the second gate line. The first subpixel may be arranged between the second data line and the third subpixel. The fourth subpixel may be arranged between the second subpixel and the first data line. The fourth drive circuit may be arranged along the first direction with the second drive circuit. The third drive circuit may be arranged along the first direction with the first drive circuit. The fourth drive circuit may be arranged symmetrically with the third drive circuit.

[0014] The third drive circuit may have a symmetrical arrangement with the first drive circuit, and the fourth drive circuit may have a symmetrical arrangement with the second drive circuit.

[0015] The third light-emitting region of the third subpixel may be disposed between the third driving circuit and the second gate line. The third light-emitting region may display a different color from the first and second light-emitting regions. The fourth light-emitting region of the fourth subpixel may be disposed between the first gate line and the fourth driving circuit. The fourth light-emitting region may display a different color from the first, second, and third light-emitting regions.

[0016] The reference voltage supply line may be arranged parallel to the first data line and the second data line. The first subpixel may be arranged between one of the reference voltage supply lines and the second data line. The fourth subpixel may be arranged between one of the reference voltage supply lines and the first data line.

[0017] In another embodiment, a display device is provided, comprising a first data line intersecting a first gate line. A second data line is disposed between the first data lines. The second data line intersects the first gate line. A second gate line extending parallel to the first gate line intersects the first data line and the second data line. A pixel region is disposed between the first data line and the second data line. Each pixel region includes a first subpixel and a second subpixel disposed along the first gate line and the second gate line. A first light-emitting region of the first subpixel is disposed between a first drive circuit and a second gate line of the first subpixel. A second light-emitting region of the second subpixel is disposed between the first gate line and the second drive circuit of the second subpixel. The first drive circuit is electrically connected to one of the first data lines and the first gate line. The second drive circuit is electrically connected to one of the second data lines and the second gate line. The second drive circuit has a symmetrical arrangement with the first drive circuit.

[0018] The second subpixel of each pixel region can display a different color than the first subpixel of the corresponding pixel region. The first subpixel of each pixel region can display the same or substantially the same color as the first subpixel of an adjacent pixel region. The second subpixel of each pixel region can display the same or substantially the same color as the second subpixel of an adjacent pixel region.

[0019] Each of the first and second sub-pixels in each pixel region may include a first switching thin film transistor and a second switching thin film transistor. The semiconductor pattern of the first switching thin film transistor may cross the first gate line or the second gate line.

[0020] The first light emitting region and the second light emitting region of each pixel region may be disposed between the first gate line and the second gate line.

[0021] The gate electrode of the second switching thin film transistor may have a shape protruding from the first gate line or the second gate line.

[0022] The semiconductor pattern of the second switching thin film transistor may be disposed parallel to the first gate line and the second gate line.

[0023] The reference voltage supply line may be disposed between the first data line and the second data line. The reference voltage supply line may cross the first gate line and the second gate line. Each reference voltage supply line may pass between the first sub-pixel and the second sub-pixel in one pixel region of the pixel region.

[0024] Each reference voltage supply line may include a main wiring, an auxiliary wiring, and a connecting wiring. The auxiliary wiring may be arranged parallel to the main wiring. The connecting wiring may be arranged between the main wiring and the auxiliary wiring. The auxiliary wiring may be electrically connected to the main wiring via the connecting wiring. Each of the first and second sub-pixels may include a light-emitting device that overlaps with the corresponding light-emitting region. The first electrode of each light-emitting device may include a portion that overlaps with the auxiliary wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0026] Figure 1 is a view schematically illustrating a display device according to an embodiment of the present disclosure;

[0027] Figure 2 is a diagram illustrating a circuit of a pixel region in a display device according to an embodiment of the present disclosure;

[0028] Figure 3 yes Figure 1Enlarged view of the middle R region;

[0029] Figure 4 yes Figure 3 A magnified view of the middle K1 area;

[0030] Figure 5 yes Figure 3 A magnified view of the middle K2 area;

[0031] Figure 6 It is along Figure 4 A view taken from I-I'; and

[0032] Figure 7 and Figure 8 is a view illustrating a display device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] Hereinafter, by referring to the following detailed description of the accompanying drawings illustrating some embodiments of the present disclosure, details related to the above-mentioned benefits, technical configurations and operational effects of the embodiments of the present disclosure will be clearly understood. Here, the embodiments of the present disclosure are provided to enable the technical spirit of the present disclosure to be satisfactorily conveyed to those skilled in the art, and therefore the present disclosure may be embodied in other forms and is not limited to the embodiments described below.

[0034] In addition, throughout the specification and drawings, the same or very similar elements may be represented by the same reference numerals, and the lengths and thicknesses of layers and regions may be exaggerated for convenience. It will be understood that when a first element is referred to as being "on" a second element, although the first element may be disposed on the second element to contact the second element, a third element may be interposed between the first and second elements.

[0035] Here, terms such as "first" and "second" may be used to distinguish any one element from another element. However, without departing from the technical spirit of the present disclosure, the first element and the second element may be arbitrarily named according to the convenience of those skilled in the art.

[0036] The terms used in the specification of the present disclosure are only used to describe specific embodiments and are not intended to limit the scope of the present disclosure. For example, unless the context clearly indicates otherwise, an element described in the singular is intended to include a plurality of elements. In addition, in the specification of the present disclosure, it will be further understood that the terms "comprise" and "include" specify the presence of the features, integers, steps, operations, elements, components and / or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations.

[0037] Also, unless “directly” is used, the terms “connected” and “coupled” may include two components being “connected” or “coupled” via one or more other components disposed between the two components.

[0038] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments belong. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0039] (Implementation Method)

[0040] Figure 1 is a view schematically illustrating a display device according to an embodiment of the present disclosure. Figure 2 is a view showing a circuit of a pixel area in a display device according to an embodiment of the present disclosure.

[0041] Reference Figure 1 and Figure 2 A display device according to an embodiment of the present disclosure may include a display panel DP. The display panel DP may generate an image provided to a user. For example, a pixel area PA and signal wirings GL1, GL2 (GL), DL1, DL2 (DL), PL, and RL may be provided in the display panel DP. Various signals may be provided in each pixel area PA via the signal wirings GL1, GL2, DL1, DL2, PL, and RL. For example, the signal wirings GL1, GL2, DL1, DL2, PL, and RL may include gate lines GL1 and GL2 for applying a gate signal, data lines DL1 and DL2 for applying a data signal, a power supply voltage supply line PL for supplying a power supply voltage, and a reference voltage supply line RL for supplying a reference voltage. The data lines DL1 and DL2 may extend in a direction intersecting the gate lines GL1 and GL2. The power supply voltage supply line PL and the reference voltage supply line RL may extend parallel to the data lines DL1 and DL2.

[0042] The gate lines GL1 and GL2 may be electrically connected to a gate driver GD. The data lines DL1 and DL2 may be electrically connected to a data driver DD. The gate driver GD and the data driver DD may be electrically connected to a timing controller TC. The gate driver GD and the data driver DD may be controlled by the timing controller TC. For example, the gate driver GD may receive a clock signal, a reset signal, and a start signal from the timing controller TC, and the data driver DD may receive digital video data and a source timing signal from the timing controller TC. The power supply voltage line PL and the reference voltage supply line RL may be electrically connected to a power supply unit PU.

[0043] The display panel DP may include a display area AA in which a pixel area PA is provided and a border area BZ provided outside the display area AA. The border area BZ may be provided outside the pixel area PA. For example, the display area AA may be surrounded by the border area BZ. The gate driver GD, the data driver DD, the timing controller TC, and the power supply unit PU may be provided outside the display area AA. For example, each of the signal wirings GL1, GL2, DL1, DL2, PL, and RL may include an area provided on the border area BZ. At least one of the gate driver GD, the data driver DD, the timing controller TC, and the power supply unit PU may be provided on the border area BZ. For example, the display device according to an embodiment of the present disclosure may be a GIP (gate within panel) type display device in which the gate driver GD is formed on the border area BZ.

[0044] The pixel areas PA may be arranged side by side in a first direction and a second direction. The second direction may be a direction perpendicular to the first direction. Each pixel area PA may realize various colors. For example, each pixel area PA may include a plurality of sub-pixels R-SP, G-SP, W-SP, and B-SP. The sub-pixels R-SP, G-SP, W-SP, and B-SP in each pixel area PA may display different colors. For example, each pixel area PA may include a red sub-pixel R-SP that displays red, a green sub-pixel G-SP that displays green, a white sub-pixel W-SP that displays white, and a blue sub-pixel B-SP that displays blue.

[0045] The sub-pixels R-SP, G-SP, W-SP, and B-SP of each pixel region PA may be controlled by signals applied through the signal wirings GL1, GL2, DL1, DL2, PL, and RL. For example, driving circuits R-DC, G-DC, W-DC, and B-DC electrically connected to the light-emitting devices 300R, 300G, 300W, and 300B may be provided in each of the sub-pixels R-SP, G-SP, W-SP, and B-SP of each pixel region PA.

[0046] The driving circuits R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP can control the light-emitting devices 300R, 300G, 300W, and 300B of the corresponding sub-pixels R-SP, G-SP, W-SP, and B-SP by signals applied through the signal wirings GL1, GL2, DL1, DL2, PL, and RL. The driving circuits R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be electrically connected to one of the gate lines GL1 and GL2, one of the data lines DL1 and DL2, one of the power supply lines PL, and one of the reference voltage supply lines RL. For example, the driving circuits R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP can supply a driving current corresponding to a data signal to the light-emitting devices 300R, 300G, 300W, and 300B of the corresponding sub-pixels R-SP, G-SP, W-SP, and B-SP according to a gate signal. The driving current supplied by the driving circuits R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be maintained for one frame. The driving circuits R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP can have the same or substantially the same structure. For example, the driving circuits R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP can include a first thin film transistor TR1, a second thin film transistor TR2, a third thin film transistor TR3, and a storage capacitor Cst.

[0047] Figure 3 yes Figure 1 Magnified view of the middle R region. Figure 4 yes Figure 3 A magnified view of the K1 region. Figure 5 yes Figure 3 A magnified view of the K2 region. Figure 6 It is along Figure 4 The view taken from I-I'.

[0048] Reference Figures 2 to 6, the first thin film transistor TR1 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can transmit a data signal to the second thin film transistor TR2 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP according to a gate signal. For example, the first thin film transistor TR1 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can function as a switching thin film transistor. The first thin film transistor TR1 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include a first semiconductor pattern 211 and a first gate electrode 213. The first semiconductor pattern 211 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include a first drain region, a first channel region, and a first source region. The first channel region may be disposed between the first drain region and the first source region. The first drain region and the first source region may have a lower resistance than the first channel region. The first gate electrode 213 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be disposed on the first channel region of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the first gate electrode 213 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be electrically connected to the corresponding gate lines GL1 and GL2, and the first drain region of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be electrically connected to the corresponding data lines DL1 and DL2.

[0049] The second thin film transistor TR2 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can generate a driving current corresponding to the data signal. For example, the second thin film transistor TR2 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can serve as a driving thin film transistor. The second thin film transistor TR2 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can have the same or substantially the same structure as the first thin film transistor TR1 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the second thin film transistor TR2 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include a second semiconductor pattern 221 and a second gate electrode 223.

[0050] The second semiconductor pattern 221 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include a semiconductor material. For example, the second semiconductor pattern 221 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include low-temperature polysilicon (LPTS) or an oxide semiconductor such as IGZO. The second semiconductor pattern 221 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include a second drain region 221d, a second channel region 221c, and a second source region 221s. The second channel region 221c may be disposed between the second drain region 221d and the second source region 221s. The second drain region 221d and the second source region 221s may have a lower resistance than the second channel region 221c. For example, the second drain region 221d and the second source region 221s may include a conductive region of an oxide semiconductor. The second channel region 221c may be a non-conductive region of the oxide semiconductor.

[0051] The first semiconductor pattern 211 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include the same or substantially the same material as the second semiconductor pattern 221 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The first semiconductor pattern 211 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be disposed on the same layer as the second semiconductor pattern 221 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The first semiconductor pattern 211 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be formed using the same or substantially the same process as the second semiconductor pattern 221 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The first semiconductor pattern 211 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be formed simultaneously with the second semiconductor pattern 221 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The second drain region 221 d of each of the sub-pixels R-SP, G-SP, W-SP, and B-SP may be electrically connected to one of the power voltage supply lines PL.

[0052] The second gate electrode 223 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be disposed on the second semiconductor pattern 221 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the second gate electrode 223 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may overlap with the second channel region 221c of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The second drain region 221d and the second source region 221s of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be disposed outside the second gate electrode 223 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The second gate electrode 223 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include a conductive material. For example, the second gate electrode 223 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The second gate electrode 223 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be spaced apart from the second semiconductor pattern 221 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The second gate electrode 223 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be insulated from the second semiconductor pattern 221 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the second channel region 221 c of each sub-pixel R-SP, G-SP, W-SP, and B-SP may have a conductivity corresponding to the voltage applied to the second gate electrode 223 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The second gate electrode 223 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be electrically connected to the first source region of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP.

[0053] The first gate electrode 213 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can include the same or substantially the same material as the second gate electrode 223 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The first gate electrode 213 and the second gate electrode 223 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be arranged on the same layer. The first gate electrode 213 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be formed by the same or substantially the same process as the second gate electrode 223 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the first gate electrode 213 and the second gate electrode 223 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be formed simultaneously.

[0054] The storage capacitor Cst of each sub-pixel R-SP, G-SP, W-SP, and B-SP can maintain the voltage applied to the second gate electrode 223 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP for one frame. For example, the storage capacitor Cst of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be electrically connected to the second source region 221s and the second gate electrode 223 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The storage capacitor Cst of each sub-pixel R-SP, G-SP, W-SP, and B-SP can have a stacked structure of capacitor electrodes. For example, the storage capacitor Cst of each sub-pixel R-SP, G-SP, W-SP, and B-SP includes a first capacitor electrode electrically connected to the second source region 221s of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP and a second capacitor electrode electrically connected to the second gate electrode 223 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. At least one of the first capacitor electrode and the second capacitor electrode in each sub-pixel R-SP, G-SP, W-SP, and B-SP can be formed by using the process of forming the second thin film transistor TR2 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. Therefore, in the display device according to the embodiment of the present disclosure, the process of forming the driving circuit R-DC, G-DC, W-DC, and B-DC in each sub-pixel R-SP, G-SP, W-SP, and B-SP can be simplified.

[0055] The third thin-film transistor TR3 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can initialize the storage capacitor Cst of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP according to a gate signal. For example, a reference voltage can be applied to the storage capacitor Cst of each sub-pixel R-SP, G-SP, W-SP, and B-SP by the third thin-film transistor TR3 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP according to the gate signal. The third thin-film transistor TR3 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can function as a switching thin-film transistor. The third thin-film transistor TR3 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can have the same or substantially the same structure as the first thin-film transistor TR1 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the third thin-film transistor TR3 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can include a third semiconductor pattern 231 and a third gate electrode 233. The third gate electrode 233 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include a third drain region, a third channel region, and a third source region. The third gate electrode 233 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be electrically connected to corresponding gate lines GL1 and GL2, and the third drain region of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be electrically connected to a corresponding reference voltage supply line RL. The gate lines GL1 and GL2 electrically connected to the third gate electrode 233 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be the same as or substantially the same as the gate lines GL1 and GL2 electrically connected to the first gate electrode 213 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the first thin-film transistor TR1 and the third thin-film transistor TR3 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be turned on and off simultaneously.

[0056] The light-emitting devices 300R, 300G, 300W, and 300B of each sub-pixel R-SP, G-SP, W-SP, and B-SP can emit light of a specific color according to the driving current applied by the driving circuits R-DC, G-DC, W-DC, and B-DC of the corresponding sub-pixels R-SP, G-SP, W-SP, and B-SP. The light-emitting devices 300R, 300G, 300W, and 300B of each sub-pixel R-SP, G-SP, W-SP, and B-SP can have the same or substantially the same structure. For example, the light-emitting devices 300R, 300G, 300W, and 300B of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include a first electrode 310, a light-emitting layer 320, and a second electrode 330 stacked in sequence.

[0057] The first electrode 310 may include a conductive material. The first electrode 310 may include a material having high transmittance. For example, the first electrode 310 may be a transparent electrode made of a transparent conductive material such as ITO and IZO.

[0058] The light-emitting layer 320 may generate light having a brightness corresponding to the voltage difference between the first electrode 310 and the second electrode 330. For example, the light-emitting layer 320 may include at least one light-emitting material layer (EML). The light-emitting material layer may include an organic light-emitting material, an inorganic light-emitting material, or a mixed light-emitting material. For example, the display device according to an embodiment of the present disclosure may be an organic light-emitting display device including an organic light-emitting material. The light-emitting layer 320 may have a multilayer structure. For example, the light-emitting layer 320 may include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). Therefore, in the display device according to an embodiment of the present disclosure, the efficiency of the light-emitting layer 320 may be improved.

[0059] The second electrode 330 may include a conductive material. The second electrode 330 may include a material different from that of the first electrode 310. The reflectivity of the second electrode 330 may be greater than the reflectivity of the first electrode 310. For example, the second electrode 330 may include a metal such as aluminum (Al) and silver (Ag). Therefore, in the display device according to the embodiment of the present disclosure, the light generated by the light-emitting layer 320 may be emitted to the outside through the first electrode 310. The second electrode 330 may have a lower work function than the first electrode 310. For example, the first electrode 310 may serve as an anode, and the second electrode 330 may serve as a cathode.

[0060] The light-emitting devices 300R, 300G, 300W, and 300B of each sub-pixel R-SP, G-SP, W-SP, and B-SP, and the driving circuits R-DC, G-DC, W-DC, and B-DC may be disposed on a device substrate 100. The device substrate 100 may include an insulating material. For example, the device substrate 100 may include glass or plastic.

[0061] A plurality of insulating layers 110, 120, 130, 140, and 150 for reducing or preventing unnecessary electrical connections may be disposed on the device substrate 100. For example, a buffer insulating layer 110, a gate insulating layer 120, a device passivation layer 130, a planarization layer 140, and a bank insulating layer 150 may be disposed on the device substrate 100.

[0062] A buffer insulating layer 110 may be disposed on the device substrate 100. The buffer insulating layer 110 may reduce or prevent contamination caused by the device substrate 100 during the process of forming the driving circuits R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the upper surface of the device substrate 100 facing the driving circuits R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be completely covered by the buffer insulating layer 110. The driving circuits R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be disposed on the buffer insulating layer 110. The buffer insulating layer 110 may include an insulating material. For example, the buffer insulating layer 110 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The buffer insulating layer 110 may have a multilayer structure. For example, the buffer insulating layer 110 may have a structure in which an inorganic insulating layer made of silicon oxide (SiOx) and an inorganic insulating layer made of silicon nitride (SiNx) are stacked.

[0063] A light shielding pattern 105 may be provided between the device substrate 100 and the buffer insulating layer 110 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. The light shielding pattern 105 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include a material capable of blocking light. For example, the light shielding pattern 105 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The light shielding pattern 105 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may overlap with the second semiconductor pattern 221 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. Therefore, in the display device according to the embodiment of the present disclosure, light traveling toward the second semiconductor pattern 221 of each sub-pixel R-SP, G-SP, W-SP, and B-SP through the device substrate 100 can be blocked by the light shielding pattern 105 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. Therefore, in the display device according to the embodiment of the present disclosure, changes in the characteristics of the second thin film transistor TR2 in each sub-pixel R-SP, G-SP, W-SP, and B-SP due to external light can be reduced or prevented.

[0064] A specific voltage may be applied to the light shielding pattern 105 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, a source connection electrode 240 for electrically connecting the light shielding pattern 105 to the second source region 221s may be provided in the sub-pixels R-SP, G-SP, W-SP, and B-SP. The source connection electrode 240 of the sub-pixels R-SP, G-SP, W-SP, and B-SP may include a conductive material. The source connection electrode 240 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include a material having a relatively low resistance. For example, the source connection electrode 240 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The source connection electrode 240 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be disposed on the same layer as the second gate electrode 223 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The second gate electrode 223 and the source connection electrode 240 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be made of the same or substantially the same material. The source connection electrode 240 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be formed using the same or substantially the same process as the second gate electrode 223 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the second gate electrode 223 and the source connection electrode 240 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be formed simultaneously. Therefore, in a display device according to an embodiment of the present disclosure, variations in the characteristics of the second thin film transistor TR2 in each sub-pixel R-SP, G-SP, W-SP, and B-SP can be effectively reduced or prevented.

[0065] The gate insulating layer 120 may be disposed on the buffer insulating layer 110. The first gate electrode 213 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be insulated from the first semiconductor pattern 211 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP by the gate insulating layer 120. The second gate electrode 223 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be insulated from the second semiconductor pattern 221 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP by the gate insulating layer 120. The third gate electrode 233 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be insulated from the third semiconductor pattern 231 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP by the gate insulating layer 120. For example, the gate insulating layer 120 may cover the first semiconductor pattern 211, the second semiconductor pattern 221, and the third semiconductor pattern 231 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. The first gate electrode 213, the second gate electrode 223, and the third gate electrode 233 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be disposed on the gate insulating layer 120. The source connection electrode 240 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be disposed on the gate insulating layer 120. The gate insulating layer 120 may include an insulating material. For example, the gate insulating layer 120 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx).

[0066] The device passivation layer 130 may be disposed on the gate insulating layer 120. The device passivation layer 130 may reduce or prevent damage to the driving circuits R-DC, G-DC, W-DC, and B-DC in each sub-pixel R-SP, G-SP, W-SP, and B-SP due to external impact and moisture. For example, the first gate electrode 213, the second gate electrode 223, and the third gate electrode 233 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be covered by the device passivation layer 130. The device passivation layer 130 may include an insulating material. For example, the device passivation layer 130 may be a linear insulating layer made of an inorganic insulating material.

[0067] A planarization layer 140 may be disposed on the device passivation layer 130. The planarization layer 140 may eliminate thickness differences caused by the driving circuits R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the upper surface of the planarization layer 140 opposite the device substrate 100 may be flat. The upper surface of the planarization layer 140 may be parallel to the upper surface of the device substrate 100. The planarization layer 140 may include an insulating material. The planarization layer 140 may include a material different from that of the device passivation layer 130. The planarization layer 140 may include a material having relatively high fluidity. For example, the planarization layer 140 may include an organic insulating material.

[0068] The bank insulating layer 150 may be disposed on the planarization layer 140. The bank insulating layer 150 may include an insulating material. For example, the bank insulating layer 150 may include an organic insulating material. The bank insulating layer 150 may include a material different from that of the planarization layer 140.

[0069] The light-emitting devices 300R, 300G, 300W, and 300B of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be disposed on the planarization layer 140. The first electrode 310 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be insulated from the first electrodes 310 of adjacent sub-pixels R-SP, G-SP, W-SP, and B-SP by the bank insulation layer 150. For example, an edge of the first electrode 310 in each sub-pixel R-SP, G-SP, W-SP, and B-SP may be covered by the bank insulation layer 150. The first electrode 310 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be partially exposed by the bank insulation layer 150. For example, the bank insulation layer 150 may define a light-emitting area R-EA, G-EA, W-EA, and B-EA in each sub-pixel R-SP, G-SP, W-SP, and B-SP. The light-emitting layer 320 and the second electrode 330 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be stacked on a portion of the first electrode 310 that overlaps with the light-emitting regions R-EA, G-EA, W-EA, and B-EA of the corresponding sub-pixels R-SP, G-SP, W-SP, and B-SP. For example, the light-emitting layer 320 may be in direct contact with the first electrode 310 and the second electrode 330 in the light-emitting regions R-EA, G-EA, W-EA, and B-EA of each sub-pixel R-SP, G-SP, W-SP, and B-SP.

[0070] The first electrode 310 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be electrically connected to the driving circuit R-DC, G-DC, W-DC, and B-DC of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the first electrode 310 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can directly contact the source connection electrode of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP by penetrating the device passivation layer 130 and the planarization layer 140. The device passivation layer 130 and the planarization layer 140 may include a pixel contact hole that exposes a portion of the source connection electrode 240 in each sub-pixel R-SP, G-SP, W-SP, and B-SP. The first electrode 310 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be electrically connected to the source connection electrode 240 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP through one of the pixel contact holes. The pixel contact hole may be provided outside the emission regions R-EA, G-EA, W-EA, and B-EA defined in each sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the pixel contact hole may overlap with the bank insulating layer 150. Therefore, in the display device according to an embodiment of the present disclosure, a change in the position of the first electrode 310 within the emission regions R-EA, G-EA, W-EA, and B-EA of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be reduced or minimized. For example, a portion of the first electrode 310 overlapping with the emission regions R-EA, G-EA, W-EA, and B-EA of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be in direct contact with the upper surface of the planarization layer 140. Therefore, in the display device according to the embodiment of the present disclosure, the brightness deviation according to the generation position of the light emitted from the light-emitting areas R-EA, G-EA, W-EA and B-EA of each sub-pixel R-SP, G-SP, W-SP and B-SP can be reduced or prevented.

[0071] The light emitting devices 300R, 300G, 300W, and 300B of each sub-pixel R-SP, G-SP, W-SP, and B-SP may emit light of a different color from the light emitting devices 300R, 300G, 300W, and 300B of adjacent sub-pixels R-SP, G-SP, W-SP, and B-SP. The light emitting layer 320 of the light emitting devices 300R, 300G, 300W, and 300B in each sub-pixel R-SP, G-SP, W-SP, and B-SP may be spaced apart from the light emitting layer 320 of the light emitting devices 300R, 300G, 300W, and 300B in adjacent sub-pixels R-SP, G-SP, W-SP, and B-SP. For example, the light emitting layer 320 of the light emitting devices 300R, 300G, 300W, and 300B in each sub-pixel R-SP, G-SP, W-SP, and B-SP may include different materials. The light emitting layer 320 of the light emitting devices 300R, 300G, 300W, and 300B in each sub-pixel R-SP, G-SP, W-SP, and B-SP may have a different stacking structure from the light emitting layer 320 of the light emitting devices 300R, 300G, 300W, and 300B in the adjacent sub-pixels R-SP, G-SP, W-SP, and B-SP. The light emitting layer 320 of the light emitting devices 300R, 300G, 300W, and 300B in each sub-pixel R-SP, G-SP, W-SP, and B-SP may include an end portion disposed on the bank insulating layer 150.

[0072] The voltage applied to the second electrode 330 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be the same or substantially the same as the voltage applied to the second electrode 330 of the adjacent sub-pixels R-SP, G-SP, W-SP, and B-SP. For example, the second electrode 330 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be electrically connected to the second electrode 330 of the adjacent sub-pixels R-SP, G-SP, W-SP, and B-SP. The second electrode 330 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can include the same or substantially the same material as the second electrode 330 of the adjacent sub-pixels R-SP, G-SP, W-SP, and B-SP. The second electrode 330 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be formed using the same or substantially the same process as the second electrode of the adjacent sub-pixels R-SP, G-SP, W-SP, and B-SP. For example, the second electrode 330 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be formed simultaneously with the second electrode 330 of the adjacent sub-pixels R-SP, G-SP, W-SP, and B-SP. The second electrode 330 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be in direct contact with the second electrode 330 of the adjacent sub-pixels R-SP, G-SP, W-SP, and B-SP. Therefore, in the display device according to the embodiment of the present disclosure, the process of forming the second electrode 330 in each sub-pixel R-SP, G-SP, W-SP, and B-SP can be simplified.

[0073] The color filter 400 may be provided on a path of light emitted from the light emitting devices 300R, 300G, 300W, and 300B in each of the sub-pixels R-SP, G-SP, W-SP, and B-SP. For example, the color filter 400 of each of the sub-pixels R-SP, G-SP, W-SP, and B-SP may be provided between the device passivation layer 130 and the planarization layer 140. A thickness difference caused by the color filter 400 of each of the sub-pixels R-SP, G-SP, W-SP, and B-SP may be removed by the planarization layer 140. Light passing through the color filter 400 of each of the sub-pixels R-SP, G-SP, W-SP, and B-SP may display the same or substantially the same color as light generated by the light emitting devices 300R, 300G, 300W, and 300B of the corresponding sub-pixels R-SP, G-SP, W-SP, and B-SP. Therefore, in the display device according to the embodiment of the present disclosure, color reproduction of light emitted from each of the sub-pixels R-SP, G-SP, W-SP, and B-SP may be improved.

[0074] The covering layer 160 may be disposed on the light-emitting devices 300R, 300G, 300W, and 300B of each sub-pixel R-SP, G-SP, W-SP, and B-SP. The covering layer 160 may reduce or prevent damage to the light-emitting devices 300R, 300G, 300W, and 300B in each sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the light-emitting devices 300R, 300G, 300W, and 300B of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be covered by the covering layer 160. The covering layer 160 may include an insulating material. For example, the covering layer 160 may include an inorganic insulating material and / or an organic insulating material. The covering layer 160 may have a multilayer structure. For example, the covering layer 160 may have a structure in which an inorganic insulating layer made of an inorganic insulating material and an organic insulating layer made of an organic insulating material are stacked. Therefore, in the display device according to the embodiment of the present disclosure, damage of the light emitting devices 300R, 300G, 300W, and 300B in each sub-pixel R-SP, G-SP, W-SP, and B-SP can be effectively reduced or prevented by the cover layer 160.

[0075] The encapsulation layer 500 and the encapsulation substrate 600 may be stacked on the cover layer 160. The encapsulation substrate 600 may include a different material from the device substrate 100. The encapsulation substrate 600 may include a material having relatively high heat dissipation properties. For example, the encapsulation substrate 600 may include a metal such as aluminum (Al) and nickel (Ni).

[0076] The encapsulation layer 500 may include an insulating material. The encapsulation layer 500 may include an adhesive material. For example, the encapsulation substrate 600 may be coupled to the device substrate 100 in which the cover layer 160 is covered by the encapsulation layer 500. The encapsulation layer 500 may block or delay the movement of external moisture. For example, the encapsulation layer 500a includes absorbing particles. The encapsulation layer 500 may have a multi-layer structure. For example, the encapsulation layer 500 may include a lower encapsulation layer 510 and an upper encapsulation layer 520 disposed on the lower encapsulation layer 510. The lower encapsulation layer 510 may be disposed between the cover layer 160 and the upper encapsulation layer 520. The absorbing particles may be dispersed in the upper encapsulation layer 520. Therefore, in the display device according to an embodiment of the present disclosure, the stress applied in the direction of the device substrate 100 due to the expansion of the absorbing particles can be alleviated by the lower encapsulation layer 510. The upper encapsulation layer 520 may include a different material from the lower encapsulation layer 510. Therefore, in the display device according to the embodiment of the present disclosure, damage of the light-emitting devices 300R, 300G, 300W and 300B in each sub-pixel R-SP, G-SP, W-SP and B-SP due to penetration of external moisture and external impact can be effectively reduced or prevented.

[0077] The sub-pixels R-SP, G-SP, W-SP, and B-SP of each pixel area PA can be arranged side by side along a first direction. For example, the red sub-pixel R-SP, green sub-pixel G-SP, white sub-pixel W-SP, and blue sub-pixel B-SP of each pixel area PA can be arranged side by side along the first direction X. The light-emitting devices 300R, 300G, 300W, and 300B of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be independently controlled. For example, the gate lines GL1 and GL2 can include a first gate line GL1 extending along the first direction X and a second gate line GL2 extending parallel to the first gate line GL1. The second gate line GL2 can be arranged between the first gate lines GL1. For example, the light-emitting areas R-EA, G-EA, W-EA, and B-EA of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be arranged between one of the first gate lines GL1 and one of the second gate lines GL2. The data lines DL1 and DL2 may include a first data line DL1 extending in a second direction Y and a second data line DL2 extending parallel to the first data line DL1. One of the first data lines DL1 and one of the second data lines DL2 may be disposed between the pixel areas PA. The power voltage supply line PL and the reference voltage supply line RL may extend in the second direction Y. For example, each of the data lines DL1 and DL2, the power voltage supply line PL, and the reference voltage supply line RL may cross the first gate line GL1 and the second gate line GL2.

[0078] Each of the sub-pixels R-SP, G-SP, W-SP, and B-SP in each pixel area PA can share data lines DL1 and DL2 with one of the sub-pixels R-SP, G-SP, W-SP, and B-SP in an adjacent pixel area PA. For example, one of the first data lines DL1 and one of the second data lines DL2 can pass between the pixel areas PA. The red drive circuit R-DC of the red sub-pixel R-SP in each pixel area PA can be electrically connected to the first data line DL1 disposed on one side of the corresponding pixel area PA, and the green drive circuit G-DC of the green sub-pixel G-SP in each pixel area PA can be electrically connected to the first data line DL1 disposed on the opposite side of the corresponding pixel area PA. The white drive circuit W-DC of the white sub-pixel W-SP in each pixel area PA can be electrically connected to the second data line DL2 disposed on one side of the corresponding pixel area PA, and the blue drive circuit B-DC of the blue sub-pixel B-SP in each pixel area PA can be electrically connected to the second data line DL2 disposed on the opposite side of the corresponding pixel area PA. That is, in a display device according to an embodiment of the present disclosure, the red subpixel R-SP of each pixel area PA can share one of the first data lines DL1 with the green subpixel G-SP of the adjacent pixel area PA, and the white subpixel W-SP of each pixel area PA can share one of the second data lines DL2 with the blue subpixel B-SP of the adjacent pixel area PA. Therefore, in a display device according to an embodiment of the present disclosure, the number of data lines DL1 and DL2 can be reduced. Therefore, in a display device according to an embodiment of the present disclosure, the area of ​​each subpixel R-SP, G-SP, W-SP, and B-SP can be increased. For example, in a display device according to an embodiment of the present disclosure, the size of the emission area R-EA, G-EA, W-EA, and B-EA defined in each subpixel R-SP, G-SP, W-SP, and B-SP can be increased.

[0079] Each of the sub-pixels R-SP, G-SP, W-SP, and B-SP can be electrically connected to different gate lines GL1 and GL2, along with the sub-pixels R-SP, G-SP, W-SP, and B-SP that share data lines DL1 and DL2 with the corresponding sub-pixels R-SP, G-SP, W-SP, and B-SP. For example, the red sub-pixel R-SP and the white sub-pixel W-SP of each pixel area PA can be electrically connected to one of the first gate lines GL1, and the green sub-pixel G-SP and the blue sub-pixel B-SP of each pixel area PA can be electrically connected to one of the second gate lines GL2. Therefore, in a display device according to an embodiment of the present disclosure, data signals can be simultaneously applied to the sub-pixels R-SP, G-SP, W-SP, and B-SP of each pixel area PA via the data lines DL1 and DL2. That is, in a display device according to an embodiment of the present disclosure, the sub-pixels R-SP, G-SP, W-SP, and B-SP of each pixel area PA can operate simultaneously. Therefore, in the display device according to the embodiment of the present disclosure, a reduction in driving speed due to an operation delay of each pixel area PA may be reduced or prevented.

[0080] The driving circuits R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP and the light-emitting areas R-EA, G-EA, W-EA, and B-EA may be arranged side by side along the second direction Y. The driving circuits R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be arranged close to the corresponding gate lines GL1 and GL2. For example, the red driving circuit R-DC and the white driving circuit W-DC of each pixel area PA may be arranged close to the corresponding first gate line GL1, and the green driving circuit G-DC and the blue driving circuit B-DC of each pixel area PA may be arranged close to the corresponding second gate line GL2. The red light emitting area R-EA defined in the red sub-pixel R-SP of each pixel area PA may be arranged between the red driving circuit R-DC of the corresponding pixel area PA and the corresponding second gate line GL2, and the white light emitting area W-EA defined in the white sub-pixel W-SP of each pixel area PA may be arranged between the white driving circuit W-DC of the corresponding pixel area PA and the corresponding second gate line GL2. The green light emitting area G-EA defined in the green sub-pixel G-SP of each pixel area PA may be arranged between the corresponding first gate line GL1 and the green driving circuit G-DC of the corresponding pixel area PA, and the blue light emitting area B-EA defined in the blue sub-pixel B-SP of each pixel area PA may be arranged between the corresponding first gate line GL1 and the blue driving circuit B-DC of the corresponding pixel area PA.

[0081] The sub-pixels R-SP, G-SP, W-SP, and B-SP electrically connected to the first gate line GL1 and the sub-pixels R-SP, G-SP, W-SP, and B-SP electrically connected to the second gate line GL2 can be alternately arranged in each pixel area PA. For example, the green sub-pixel G-SP of each pixel area PA can be arranged between the red sub-pixel R-SP and the white sub-pixel W-SP of the corresponding pixel area PA, and the white sub-pixel W-SP of each pixel area PA can be arranged between the green sub-pixel G-SP and the blue sub-pixel B-SP of the corresponding pixel area PA. Therefore, in the display device according to the embodiment of the present disclosure, the space for the driving circuit R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be sufficiently ensured. Therefore, in the display device according to the embodiment of the present disclosure, the reduction in the area of ​​the light-emitting areas R-EA, G-EA, W-EA and B-EA defined in each pixel area PA due to the driving circuits R-DC, G-DC, W-DC and B-DC of the corresponding pixel areas PA can be reduced or minimized.

[0082] The driving circuits R-DC, G-DC, W-DC, and B-DC of each pixel area PA can be arranged symmetrically with each other. For example, the green driving circuit G-DC of each pixel area PA can be arranged symmetrically with the red driving circuit R-DC of the corresponding pixel area PA with respect to a first direction X, and the white driving circuit W-DC of each pixel area PA can be arranged symmetrically with the blue driving circuit B-DC of the corresponding pixel area PA with respect to the first direction X. Therefore, in the display device according to an embodiment of the present disclosure, the coupling capacitance of the green subpixel G-SP in each pixel area PA can be substantially the same as the coupling capacitance of the red subpixel R-SP in the corresponding pixel area PA, and the coupling capacitance of the blue subpixel B-SP in each pixel area PA can be substantially the same as the coupling capacitance of the white subpixel W-SP in the corresponding pixel area PA. The white driving circuit W-DC of each pixel area PA can be arranged symmetrically with the red driving circuit R-DC of the corresponding pixel area PA with respect to a second direction Y, and the blue driving circuit B-DC of each pixel area PA can be arranged symmetrically with the green driving circuit G-DC of the corresponding pixel area PA with respect to the second direction Y. That is, in the display device according to the embodiment of the present disclosure, the coupling capacitance of the white sub-pixel W-SP in each pixel area PA can be substantially the same as the coupling capacitance of the red sub-pixel R-SP in the corresponding pixel area PA, and the coupling capacitance of the blue sub-pixel B-SP in each pixel area PA can be substantially the same as the coupling capacitance of the green sub-pixel G-SP in the corresponding pixel area PA. Therefore, in the display device according to the embodiment of the present disclosure, the luminance deviation of the light emitted by each sub-pixel R-SP, G-SP, W-SP, and B-SP due to the difference in coupling capacitance can be reduced or prevented.

[0083] The second thin-film transistor TR2 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be arranged away from the emission area R-EA, G-EA, W-EA, and B-EA of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the first gate line GL1 and the second gate line GL2 can be arranged between the emission area R-EA, G-EA, W-EA, and B-EA of each sub-pixel R-SP, G-SP, W-SP, and B-SP and the second thin-film transistor TR2. Therefore, in the display device according to an embodiment of the present disclosure, the coupling capacitance of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be reduced or minimized.

[0084] The first semiconductor pattern 211 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may have a shape extending in the second direction Y. For example, the first semiconductor pattern 211 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may intersect one of the first gate line GL1 and the second gate line GL2. The first gate line GL1 and the second gate line GL2 may be disposed on the same layer as the first gate electrode 213 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the first gate line GL1 and the second gate line GL2 may be disposed between the gate insulating layer 120 and the device passivation layer 130. The first gate line GL1 and the second gate line GL2 may include the same or substantially the same material as the first gate electrode 213 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. The first gate line GL1 and the second gate line GL2 may be formed using the same or substantially the same process as the first gate electrode 213 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the first gate line GL1 and the second gate line GL2 can be formed simultaneously with the first gate electrode 213 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. The first gate electrode 213 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be in direct contact with one of the first gate line GL1 and the second gate line GL2. For example, the first gate electrode 213 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be part of the corresponding gate lines GL1 and GL2. Therefore, in the display device according to the embodiment of the present disclosure, the process of forming the first gate electrode 213 in each sub-pixel R-SP, G-SP, W-SP, and B-SP can be simplified.

[0085] The second gate electrode 223 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be arranged parallel to the first gate line GL1 and the second gate line GL2. The second semiconductor pattern 221 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can have a shape extending in the second direction Y. For example, the second semiconductor pattern 221 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be arranged parallel to the data lines DL1 and DL2. The power connection line 250 extending along the first direction X can be electrically connected to at least one of the power supply voltage supply lines PL, and the second semiconductor pattern 221 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be electrically connected to one of the power connection lines 250. Therefore, in the display device according to the embodiment of the present disclosure, the configuration of the driving circuit R-DC, G-DC, W-DC, and B-DC in each sub-pixel R-SP, G-SP, W-SP, and B-SP can be simplified. That is, in the display device according to the embodiment of the present disclosure, the area occupied by the driving circuit R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be reduced or minimized. Therefore, in the display device according to the embodiment of the present disclosure, the size of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be reduced. Moreover, in the display device according to the embodiment of the present disclosure, the area of ​​the emission area R-EA, G-EA, W-EA, and B-EA defined in each sub-pixel R-SP, G-SP, W-SP, and B-SP can be increased or maximized.

[0086] The power connection line 250 may be provided on a different layer from the power supply voltage supply line PL. The power connection line 250 may be provided on the same layer as the source connection electrode 240 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the power connection line 250 may be provided between the gate insulating layer 120 and the device passivation layer 130. The power connection line 250 may include the same or substantially the same material as the source connection electrode 240 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. The power connection line 250 may be formed using the same or substantially the same process as the source connection electrode 240 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the power connection line 250 may be formed simultaneously with the source connection electrode 240 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. Therefore, in a display device according to an embodiment of the present disclosure, a reduction in process efficiency due to the formation of the power connection line 250 may be reduced or prevented.

[0087] The power supply voltage line PL can be arranged closer to the device substrate 100 than the power connection line 250. For example, the power supply voltage line PL can be arranged on the same layer as the light shielding pattern 105 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. The power supply voltage line PL can include the same or substantially the same material as the light shielding pattern 105 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. The power supply voltage line PL can be formed using the same or substantially the same process as the light shielding pattern 105 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the power supply voltage line PL can be formed simultaneously with the light shielding pattern 105 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. Therefore, in the display device according to the embodiment of the present disclosure, the process of forming the power supply voltage line PL can be simplified.

[0088] The data lines DL1 and DL2 can be provided on the same layer as the power supply line PL. For example, the data lines DL1 and DL2 can be provided between the device substrate 100 and the buffer insulating layer 110. The data lines DL1 and DL2 can include the same or substantially the same material as the power supply line PL. The data lines DL1 and DL2 can be formed using the same or substantially the same process as the power supply line PL. For example, the data lines DL1 and DL2 can be formed simultaneously with the power supply line PL. Therefore, in a display device according to an embodiment of the present disclosure, the process for forming the data lines DL1 and DL2 can be simplified.

[0089] The third thin film transistor TR3 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be spaced apart from the first thin film transistor TR1 and the second thin film transistor TR2 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The third semiconductor pattern 231 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may have a shape that extends in a different direction from the first semiconductor pattern 211 and the second semiconductor pattern 221 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the third semiconductor pattern 231 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may have a shape that extends in the first direction X. The third semiconductor pattern 231 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be arranged parallel to the first gate line GL1 and the second gate line GL2. The third gate electrode 233 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may extend in the second direction Y. The third gate electrode 233 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may extend in a direction perpendicular to the first gate line GL1 and the second gate line GL2. For example, the third gate electrode 233 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may have a shape that protrudes from one of the first gate line GL1 and the second gate line GL2. Therefore, in a display device according to an embodiment of the present disclosure, the width of each first gate line GL1 and the width of each second gate line GL2 can be increased. For example, in a display device according to an embodiment of the present disclosure, the resistance of each first gate line GL1 and the resistance of each second gate line GL2 can be reduced. Therefore, in a display device according to an embodiment of the present disclosure, the delay of a signal applied through the first gate line GL1 and the second gate line GL2 can be reduced or prevented.

[0090] The reference voltage supply line RL can be arranged parallel to the power voltage supply line PL. For example, the reference voltage supply line RL can extend in the second direction Y. Each reference voltage supply line RL can pass through one of the pixel areas PA. For example, the red sub-pixel R-SP and the green sub-pixel G-SP of each pixel area PA can be arranged between one of the second data lines DL2 and one of the reference voltage supply lines RL, and the white sub-pixel W-SP and the blue sub-pixel B-SP of each pixel area PA can be arranged between one of the reference voltage supply lines RL and one of the first data lines DL1. Therefore, in the display device according to the embodiment of the present disclosure, the process of connecting the third drain region of the third thin film transistor TR3 in each sub-pixel R-SP, G-SP, W-SP and B-SP to the corresponding reference voltage supply line RL can be simplified.

[0091] The reference voltage supply line RL can be provided on the same layer as the power voltage supply line PL. For example, the reference voltage supply line RL can be provided between the device substrate 100 and the buffer insulating layer 110. The reference voltage supply line RL can include the same or substantially the same material as the power voltage supply line PL. The reference voltage supply line RL can be formed using the same or substantially the same process as the power voltage supply line PL. For example, the reference voltage supply line RL can be formed simultaneously with the power voltage supply line PL. Therefore, in a display device according to an embodiment of the present disclosure, the process of forming the reference voltage supply line RL can be simplified.

[0092] The third drain region of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be electrically connected to a corresponding reference voltage supply line RL via a reference connection line 260 extending in the first direction X. For example, each reference connection line 260 can be electrically connected to one of the reference voltage supply lines RL. The reference connection line 260 can be provided on a different layer from the reference voltage supply line RL. The reference connection line 260 can be provided on the same layer as the power connection line 250. For example, the reference connection line 260 can be provided between the gate insulating layer 120 and the device passivation layer 130. The reference connection line 260 can include the same or substantially the same material as the power connection line 250. The reference connection line 260 can be formed using the same or substantially the same process as the power connection line 250. For example, the reference connection line 260 can be formed simultaneously with the power connection line 250. Therefore, in a display device according to an embodiment of the present disclosure, a decrease in process efficiency caused by forming the reference connection line 260 can be reduced or prevented.

[0093] Therefore, a display device according to an embodiment of the present disclosure may include a pixel area PA arranged between gate lines GL1 and GL2, data lines DL1 and DL2, and a power voltage supply line PL, wherein each pixel area PA may include sub-pixels R-SP, G-SP, W-SP, and B-SP arranged side by side along the gate lines GL1 and GL2, wherein the sub-pixels R-SP and W-SP of each pixel area PA electrically connected to the first gate line GL1 of the gate lines GL1 and GL2 may share data lines DL1 and DL2 with the sub-pixels G-SP and B-SP of the adjacent pixel area PA electrically connected to the second gate line GL2 of the gate lines GL1 and GL2, and wherein the driving circuits R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP may have a symmetrical arrangement with the driving circuits R-DC, G-DC, W-DC, and B-DC of the sub-pixels R-SP, G-SP, W-SP, and B-SP adjacent in the first direction X or the second direction Y. Therefore, in the display device according to the embodiment of the present disclosure, the sub-pixels R-SP, G-SP, W-SP, and B-SP of each pixel area PA can have substantially the same coupling capacitance. Therefore, in the display device according to the embodiment of the present disclosure, the degradation of image quality caused by the deviation of the brightness of the light emitted from each sub-pixel R-SP, G-SP, W-SP, and B-SP can be reduced or prevented.

[0094] Furthermore, in the display device according to the embodiment of the present disclosure, the coupling capacitance of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be substantially the same without reducing process efficiency. Therefore, in the display device according to the embodiment of the present disclosure, production energy can be reduced through process optimization.

[0095] The display device according to an embodiment of the present disclosure is described as the drive circuit R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be composed of a first thin film transistor TR1, a second thin film transistor TR2, a third thin film transistor TR3, and a storage capacitor Cst. However, in a display device according to another embodiment of the present disclosure, the drive circuit R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include a drive thin film transistor and at least one switching thin film transistor. For example, in a display device according to another embodiment of the present disclosure, the drive circuit R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be composed only of a first thin film transistor TR1 serving as a switching thin film transistor, a second thin film transistor TR2 serving as a drive thin film transistor, and a storage capacitor Cst. Therefore, in the display device according to another embodiment of the present disclosure, the degree of freedom in configuring the driving circuits R-DC, G-DC, W-DC and B-DC in each sub-pixel R-SP, G-SP, W-SP and B-SP can be improved.

[0096] In a display device according to an embodiment of the present disclosure, the positions and electrical connections of the first drain region, first source region, second drain region 221d, second source region 221s, third drain region, and third source region in each of the driving circuits R-DC, G-DC, W-DC, and B-DC can vary depending on the configuration of the corresponding driving circuit R-DC, G-DC, W-DC, and B-DC and / or the type of the corresponding thin-film transistors TR1, TR2, and TR3. For example, in a display device according to another embodiment of the present disclosure, the second gate electrode 223 of each of the driving circuits R-DC, G-DC, W-DC, and B-DC can be electrically connected to the first drain region of the corresponding driving circuit R-DC, G-DC, W-DC, and B-DC. Therefore, in a display device according to another embodiment of the present disclosure, the degree of freedom in the configuration of each of the driving circuits R-DC, G-DC, W-DC, and B-DC and the type of each of the thin-film transistors TR1, TR2, and TR3 can be increased.

[0097] The display device according to an embodiment of the present disclosure is described as being able to use the first drain region, first source region, second drain region 221d, second source region 221s, third drain region, and third source region of each pixel region PA as wiring. However, in a display device according to another embodiment of the present disclosure, the first thin-film transistor TR1, second thin-film transistor TR2, and third thin-film transistor TR3 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can have various structures. For example, in a display device according to an embodiment of the present disclosure, the driving circuit R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP can include a second drain electrode electrically connected to the second drain region 221d and a second source electrode electrically connected to the second source region 221s. The second drain electrode and the second source electrode of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be provided on a different layer from the second gate electrode 223 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the second drain electrode and the second source electrode of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be provided between the interlayer insulating layer covering the second gate electrode 223 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP and the device passivation layer 130. Therefore, in the display device according to another embodiment of the present disclosure, the degree of freedom of configuration of the driving circuit R-DC, G-DC, W-DC, and B-DC in each sub-pixel R-SP, G-SP, W-SP, and B-SP may be increased.

[0098] The display device according to the embodiment of the present disclosure is described as each reference voltage supply line RL being a signal wiring. However, in a display device according to another embodiment of the present disclosure, each reference voltage supply line RL may be formed of a plurality of wirings. For example, in a display device according to another embodiment of the present disclosure, each reference voltage supply line RL may include a main wiring R1, an auxiliary wiring R2, and a connection wiring Rc, such as Figure 7 and Figure 8As shown. The auxiliary wiring R2 may extend parallel to the main wiring R1. The auxiliary wiring R2 may be spaced apart from the main wiring R1. The connecting wiring Rc may be disposed between the main wiring R1 and the auxiliary wiring R2. The connecting wiring Rc may be in direct contact with a portion of the main wiring R1 and a portion of the auxiliary wiring R2. For example, the auxiliary wiring R2 may be in direct contact with the main wiring R1 through the connecting wiring Rc. The auxiliary wiring R2 and the connecting wiring Rc may comprise the same or substantially the same material as the main wiring R1. For example, the auxiliary wiring R2 and the connecting wiring Rc may be disposed on the same layer as the main wiring R1. The auxiliary wiring R2 and the connecting wiring Rc may be formed using the same or substantially the same process as the main wiring R1. For example, the auxiliary wiring R2 and the connecting wiring Rc may be formed simultaneously with the main wiring R1.

[0099] The third drain region of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be electrically connected to the main wiring R1 of the corresponding reference voltage supply line RL. The first electrode 310 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include a portion that overlaps with the auxiliary wiring R2 of the corresponding reference voltage supply line RL. For example, the auxiliary wiring R2 of each reference voltage supply line RL can be used in a repair process. The repair process may include disconnecting the auxiliary wiring R2 from some of the connection wiring Rc of the reference voltage supply line RL. For example, the red drive circuit R-DC of each pixel area PA can be electrically connected to the red light-emitting device 300R disposed in the red sub-pixel R-SP of an adjacent pixel area PA via the auxiliary wiring R2 of the corresponding reference voltage supply line RL, which is disconnected during the repair process. Therefore, in a display device according to another embodiment of the present disclosure, the repair process can be simplified. Consequently, in a display device according to another embodiment of the present disclosure, production energy can be effectively reduced through process optimization.

[0100] As a result, a display device according to an embodiment of the present disclosure can include a pixel region disposed between a first gate line and a second gate line, wherein each pixel region can include a first subpixel and a second subpixel, wherein a data line intersecting the first gate line and the second gate line can pass through the second subpixel in each pixel region and the first subpixel in an adjacent pixel region, and wherein a second driver circuit for the second subpixel disposed proximate to the second gate line can have a symmetrical arrangement with a first driver circuit for the first subpixel disposed proximate to the first gate line. Therefore, in the display device according to an embodiment of the present disclosure, the difference between the coupling capacitance of the first subpixel in each pixel region and the coupling capacitance of the second subpixel in each pixel region can be reduced. Thus, in the display device according to an embodiment of the present disclosure, light emitted from the second subpixel in each pixel region can have substantially the same brightness as light emitted from the first subpixel in each pixel region. That is, in the display device according to an embodiment of the present disclosure, a degradation in image quality caused by a brightness difference between the first subpixel and the second subpixel in each pixel region can be reduced or prevented. Furthermore, in the display device according to an embodiment of the present disclosure, production energy can be reduced through process optimization.

[0101] CROSS-REFERENCE TO RELATED APPLICATIONS

[0102] This application claims the benefit of Korean Patent Application No. 10-2024-0028797, filed in Korea on February 28, 2024, which is hereby incorporated by reference as if fully set forth herein.

Claims

1. A display device, comprising: a first gate line extending along a first direction; a first data line extending along a second direction transverse to the first direction, and crossing the first gate line; a second gate line, the second gate line extending parallel to the first gate line, and the second gate line crossing the first data line; a first sub-pixel, the first sub-pixel comprising a first driving circuit electrically connected to the first gate line and the first data line; as well as a second sub-pixel, the second sub-pixel comprising a second driving circuit electrically connected to the first data line and the second gate line, The first data line passes between the first sub-pixel and the second sub-pixel. wherein a second light emitting region of the second sub-pixel disposed between the first gate line and the second driving circuit displays a different color from a first light emitting region of the first sub-pixel disposed between the first driving circuit and the second gate line; and The second driving circuit and the first driving circuit have a symmetrical arrangement.

2. The display device according to claim 1, wherein The second light emitting area and the first light emitting area are arranged along the first direction.

3. The display device according to claim 1, wherein Each of the first driving circuit and the second driving circuit includes a driving thin film transistor, and Wherein, the gate electrode of the driving thin film transistor is arranged in parallel with the first gate line and the second gate line.

4. The display device according to claim 3, wherein The semiconductor pattern of the driving thin film transistor is arranged parallel to the first data line.

5. The display device according to claim 1, further comprising: a second data line, the second data line being arranged parallel to the first data line; a third sub-pixel, the third sub-pixel comprising a third driving circuit, the third driving circuit being electrically connected to the first gate line and the second data line; as well as a fourth sub-pixel, the fourth sub-pixel comprising a fourth driving circuit, the fourth driving circuit being electrically connected to the second data line and the second gate line, Wherein, the first sub-pixel is arranged between the second data line and the third sub-pixel, The fourth sub-pixel is disposed between the second sub-pixel and the first data line, and The fourth driving circuit and the second driving circuit are arranged along the first direction, the third driving circuit and the first driving circuit are arranged along the first direction, and the fourth driving circuit and the third driving circuit have a symmetrical arrangement. The display device according to claim 5 , wherein: The third drive circuit has a symmetrical arrangement with the first drive circuit, and the fourth drive circuit has a symmetrical arrangement with the second drive circuit.

7. The display device according to claim 5, wherein A third light emitting region of the third sub-pixel disposed between the third driving circuit and the second gate line displays a different color from the first light emitting region and the second light emitting region, and The fourth light-emitting region of the fourth sub-pixel, which is disposed between the first gate line and the fourth driving circuit, displays a different color from the first light-emitting region, the second light-emitting region, and the third light-emitting region.

8. The display device according to claim 7, further comprising a reference voltage supply line provided in parallel with the first data line and the second data line, in, The first sub-pixel is disposed between one of the reference voltage supply lines and the second data line, and The fourth sub-pixel is disposed between one of the reference voltage supply lines and the first data line.

9. A display device, comprising: a first data line, the first data line crossing the first gate line; a second data line, the second data line being disposed between the first data lines and crossing the first gate line; a second gate line, the second gate line extending parallel to the first gate line, and the second gate line crossing the first data line and the second data line; as well as pixel areas, the pixel areas being disposed between the first data line and the second data line, each of the pixel areas including a first sub-pixel and a second sub-pixel disposed along the first gate line and the second gate line, The first light emitting region of the first sub-pixel is arranged between the first driving circuit of the first sub-pixel and the second gate line. The second light emitting region of the second sub-pixel is arranged between the first gate line and the second driving circuit of the second sub-pixel, and The second driving circuit electrically connected to one of the second data lines and the second gate line is symmetrically arranged with the first driving circuit electrically connected to one of the first data lines and the first gate line.

10. The display device according to claim 9, wherein The second sub-pixel in each pixel area displays a different color from the first sub-pixel in the corresponding pixel area. The first sub-pixel in each pixel region displays the same color as the first sub-pixel in the adjacent pixel region, and The second sub-pixel in each pixel region displays the same color as the second sub-pixel in an adjacent pixel region.

11. The display device according to claim 9, wherein Each of the first sub-pixel and the second sub-pixel in each pixel region includes a first switching thin film transistor and a second switching thin film transistor, and The semiconductor pattern of the first switching thin film transistor crosses the first gate line or the second gate line.

12. The display device according to claim 11, wherein The first light emitting region and the second light emitting region of each pixel region are disposed between the first gate line and the second gate line.

13. The display device according to claim 11, wherein A gate electrode of the second switching thin film transistor has a shape protruding from the first gate line or the second gate line.

14. The display device according to claim 13, wherein The semiconductor pattern of the second switching thin film transistor is arranged parallel to the first gate line and the second gate line.

15. The display device according to claim 9, further comprising a reference voltage supply line disposed between the first data line and the second data line, the reference voltage supply line crossing the first gate line and the second gate line, in, Each of the reference voltage supply lines passes between the first sub-pixel and the second sub-pixel in one of the pixel areas.

16. The display device according to claim 15, wherein Each of the reference voltage supply lines includes a main wiring, an auxiliary wiring provided in parallel with the main wiring, and a connection wiring provided between the main wiring and the auxiliary wiring, wherein the auxiliary wiring is electrically connected to the main wiring through the connection wiring, wherein each of the first sub-pixel and the second sub-pixel includes a light emitting device overlapping with a corresponding light emitting area, and The first electrode of each light emitting device includes a portion overlapping with the auxiliary wiring.

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