Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a plurality of first pixel rows arranged in the second direction, each first pixel row comprises a plurality of first sub-pixels and a plurality of second sub-pixels which are alternately arranged in the first direction, each first sub-pixel comprises a first anode pattern, and each second sub-pixel comprises a second anode pattern; the sum of the areas of a plurality of first anode patterns and a plurality of second anode patterns in a (2k-1) th first pixel row is a first area, and the sum of the areas of a plurality of first anode patterns and a plurality of second anode patterns in a (2k) th first pixel row is a second area. The ratio of the absolute value of the difference value of the first area and the second area to the first area or the second area is smaller than or equal to 8%, the area difference of the first anode pattern and the second anode pattern in the odd-numbered lines and the even-numbered lines is reduced, and the difference of resistance and capacitance of anodes in different lines of sub-pixels is eliminated. The technical problem that cross grains appear when the display panel is used for displaying or holding breath is solved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) display technology is a new display technology that has gradually attracted people's attention with its unique advantages such as low power consumption, high saturation, fast response time and wide viewing angle, and occupies a certain position in the field of panel display technology.

[0003] In order to reduce the power consumption of the driver chip, current OLED display panels change the anode pattern so that each data line connects sub-pixels of the same color. However, this solution causes the pattern area of ​​the anodes in sub-pixels in different rows to be different, resulting in different resistance and capacitance of the anodes in sub-pixels in different rows, which causes the technical problem of horizontal stripes on the display panel. Summary of the Invention

[0004] The present application provides a display panel and a display device to improve the technical problem of horizontal stripes on existing display panels.

[0005] To solve the above problem, the technical solution provided by this application is as follows:

[0006] In a first aspect, the present application provides a display panel comprising:

[0007] a plurality of first sub-pixels and a plurality of second sub-pixels, and both are alternately arranged along a first direction and a second direction, wherein the plurality of first sub-pixels and the plurality of second sub-pixels arranged along the first direction constitute a first pixel row, and the plurality of first sub-pixels and the plurality of second sub-pixels arranged along the second direction constitute a first pixel column;

[0008] a plurality of data lines arranged along the first direction and extending along the second direction, the plurality of data lines including a first data line and a second data line, a first sub-pixel in two adjacent first pixel columns being electrically connected to a first data line, and a second sub-pixel in two adjacent first pixel columns being electrically connected to a second data line;

[0009] In which, the first sub-pixel includes a first anode pattern, the second sub-pixel includes a second anode pattern, in the 2k-1th row of the first pixel row, the sum of the areas of the multiple first anode patterns and the multiple second anode patterns is a first area, in the 2kth row of the first pixel row, the sum of the areas of the multiple first anode patterns and the multiple second anode patterns is a second area, and the ratio of the absolute value of the difference between the first area and the second area to the first area or the second area is less than or equal to 8%, and greater than or equal to 0.

[0010] In a second aspect, the present application also proposes a display device, which includes the above-mentioned display panel.

[0011] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0013] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same drawing numbers represent the same parts in the following description.

[0014] Figure 1 This is a first sub-pixel arrangement diagram of the display panel of this application;

[0015] Figure 2 This is a second sub-pixel arrangement diagram of the display panel of this application;

[0016] Figure 3 A simplified structural diagram of the display panel of this application;

[0017] Figure 4 This is an equivalent circuit diagram of a pixel circuit in the display panel of this application;

[0018] Figure 5 This is a schematic diagram of the film layer in the display panel of this application;

[0019] Figure 6 A stacking diagram of the first gate layer, the first active layer, the second active layer, the second gate layer, and the first source and drain layer in a repeating unit in the display panel of the present application;

[0020] Figure 7 for Figure 4 Structural diagram of the first gate layer;

[0021] Figure 8 for Figure 4 Structural diagram of the first active layer in FIG;

[0022] Figure 9 This is a structural diagram of the light-shielding layer in the repeating unit of the display panel of this application;

[0023] Figure 10 for Figure 4 Structural diagram of the second gate layer;

[0024] Figure 11 for Figure 4 Structural diagram of the second active layer;

[0025] Figure 12 for Figure 4 The structure diagram of the third gate layer;

[0026] Figure 13 for Figure 4 A structural diagram of the first source and drain layer;

[0027] Figure 14 This is a structural diagram of the second source and drain layer in the repeating unit of the display panel of the present application;

[0028] Figure 15 A stacking diagram of the first gate layer, the first active layer, the second active layer, the second gate layer, the first source-drain electrode layer, and the second source-drain electrode layer in a repeating unit in the display panel of the present application;

[0029] Figure 16 This is a first stacking diagram of the anode layer and multiple light-emitting units in the display panel of the present application;

[0030] Figure 17 A stacking diagram of the second source and drain layer, the anode layer, and multiple light-emitting units in this application;

[0031] Figure 18 A second stacking diagram of the anode layer and multiple light-emitting units in the display panel of this application;

[0032] Figure 19 This is a third stacking diagram of the anode layer and multiple light-emitting units in the display panel of this application;

[0033] Figure 20 This is a fourth stacking diagram of the anode layer and multiple light-emitting units in the display panel of this application. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0035] See also Figure 1 , Figure 1 This is a diagram of the first subpixel arrangement of the display panel of this application. The display panel includes multiple pixel columns. Odd-numbered pixel columns include alternating red subpixels R and blue subpixels B, with the subpixels in two adjacent odd-numbered pixel columns in the same row having different colors. Even-numbered pixel columns include multiple green subpixels G. Each pixel column is connected to a data line.

[0036] exist Figure 1 In the structure, the red sub-pixel R receives the Data-R signal, the green sub-pixel G receives the Data-G signal, and the blue sub-pixel B receives the Data-B signal. When the data lines connected to the odd-numbered pixel columns transmit data signals, since the Data-R signal and the Data-B signal need to be transmitted at the same time, the data lines are in alternating transmission of the Data-R signal and the Data-B signal during transmission. The data lines connected to the even-numbered pixel columns only need to transmit the Data-G signal. Therefore, the signals transmitted by the data lines connected to the even-numbered pixel columns are DC signals, and the signals transmitted by the data lines connected to the odd-numbered pixel columns are AC signals, which increases the power consumption of the driver chip.

[0037] In order to reduce the power consumption of the driver chip, please refer to Figure 2 , Figure 2 This is the second sub-pixel arrangement diagram of the display panel of this application. The sub-pixel connection method of the even-numbered rows in this embodiment is the same as Figure 1 Similarly, the sub-pixels in the nth column of the odd rows are electrically connected to the data lines in the n+2th column, so that each data line is connected to sub-pixels of the same luminous color, reducing the power consumption of the driver chip.

[0038] In order to connect each data line to sub-pixels of the same color, the present application can change the pattern of the anode so that one data line can independently control the red sub-pixel R, the green sub-pixel G or the blue sub-pixel B by means of an anode jumper, for example, by increasing the length of the anode lead to cross the adjacent pixel driving circuit; however, the change in the anode pattern causes the area of ​​the anode pattern in sub-pixels in different rows to be different, resulting in the resistance and capacitance of the anode in sub-pixels in different rows to be different, thereby causing a technical problem of horizontal stripes on the display panel.

[0039] See also Figures 3 to 20 The present application provides a display panel 100, which includes a plurality of first sub-pixels PXr and a plurality of second sub-pixels PXb, and the plurality of first sub-pixels PXr and the plurality of second sub-pixels PXb are alternately arranged along a first direction X and a second direction Y. The plurality of first sub-pixels PXr and the plurality of second sub-pixels PXb arranged along the first direction X constitute a first pixel row PH1, and the plurality of first sub-pixels PXr and the plurality of second sub-pixels PXb arranged along the second direction Y constitute a first pixel column PL1.

[0040] In this embodiment, the display panel 100 further includes a plurality of data lines Data, which are arranged along a first direction X and extend along a second direction Y. The plurality of data lines Data include a first data line D1 and a second data line D2. The first sub-pixels PXr in two adjacent first pixel columns PL1 are electrically connected to a first data line D1, and the second sub-pixels PXb in two adjacent first pixel columns PL1 are electrically connected to a second data line D2.

[0041] In this embodiment, the first sub-pixel PXr includes a first anode pattern 210, and the second sub-pixel PXb includes a second anode pattern 220. In the 2k-1th row of the first pixel row PH1, the sum of the areas of the multiple first anode patterns 210 and the multiple second anode patterns 220 is the first area. In the 2kth row of the first pixel row PH1, the sum of the areas of the multiple first anode patterns 210 and the multiple second anode patterns 220 is the second area. The ratio of the absolute value of the difference between the first area and the second area to the first area or the second area is less than or equal to 8%, and greater than or equal to 0.

[0042] The present application reduces the area difference between the first anode pattern 210 and the second anode pattern 220 in the odd and even rows, eliminates the difference in resistance and capacitance of the anodes in sub-pixels of different rows, and improves the technical problem of horizontal stripes appearing on the display panel 100 when displaying or holding the breath, by making the sum of the areas of the multiple first anode patterns 210 and the multiple second anode patterns 220 in the first pixel row PH1 of the 2k-1 row be the first area, and the sum of the areas of the multiple first anode patterns 210 and the multiple second anode patterns 220 in the first pixel row PH1 of the 2k row be the second area, and the ratio of the absolute value of the difference between the first area and the second area to the first area or the second area is less than or equal to 8%.

[0043] It should be noted that k in this application can be a positive integer greater than or equal to 1.

[0044] The technical solution of this application is now described in conjunction with specific embodiments.

[0045] See also Figure 3 The display panel 100 includes a display area AA and a non-display area NA adjacent to the display area AA. For example, the non-display area NA surrounds the display area AA, enclosing the display area AA. The display area AA is the area within the display panel 100 used for display functions, and contains a plurality of sub-pixels PX that implement these functions. The non-display area NA may be a border area of ​​the display panel 100, and may contain functional components that assist the sub-pixels PX within the display area AA in displaying.

[0046] See also Figure 3 The lower side of the display area AA is provided with a binding terminal 400. The binding terminal 400 can be connected to an external circuit and transmits the signal input from the external circuit to the data line, thereby driving the display panel 100 to display the image. For example, the binding terminal 400 can be bonded to a chip or a chip-on-film to provide power and driving signals to the display panel 100.

[0047] In this embodiment, the gate circuit 300 is arranged in the non-display area NA, and the gate circuit 300 can be arranged on both sides of the display area AA; the gate circuit 300 may include multiple cascaded gate driving units, and the structure of the gate driving unit is not specifically limited in this application.

[0048] In this embodiment, a plurality of light-emitting devices EL and a pixel circuit PC for driving the light-emitting devices EL may be arranged in an array in the display area AA. The pixel circuit PC may be a 7T1C, 7T2C, 8T1C, 8T2C, 8T3C, 8T4C or other pixel circuit PC. The following embodiment uses an 8T2C pixel circuit PC as an example for description.

[0049] See also Figure 4 The pixel circuit PC may include a switching transistor T2, a driving transistor T1, a compensation transistor T3, a first reset transistor T4, a second reset transistor T7, a first light-emitting transistor T5, a second light-emitting transistor T6, a third reset transistor T8, a storage capacitor Cst and a boost capacitor Cboost, and the storage capacitor Cst includes a first plate Cst1 and a second plate Cst2.

[0050] See also Figure 4, the drain of the switching transistor T2 is connected to the data line Data, the source of the switching transistor T2 is connected to the first node A, and the switching gate T2G of the switching transistor T2 is connected to the switching control line Pscan1; the drain of the driving transistor T1 is connected to the first node A, the source of the driving transistor T1 is connected to the second node B, and the driving gate T1G of the driving transistor T1 is connected to the third node Q; the drain of the compensation transistor T3 is connected to the third node Q, the source of the compensation transistor T3 is connected to the second node B, and the compensation gate T3G of the compensation transistor T3 is connected to the compensation control line Nscan1; the drain of the first reset transistor T4 is connected to the first reset signal line Vi1, the source of the first reset transistor T4 is connected to the third node Q, and the gate T4G of the first reset transistor T4 is connected to the first reset control line Nscan2; the drain of the second reset transistor T7 is connected to the second reset signal line Vi2, the source of the second reset transistor T7 is connected to the anode of the light emitting device EL, and the gate T7G of the second reset transistor T7 is connected to the second reset control line Pscan 2; a drain of the first light-emitting transistor T5 is connected to the high potential line VDD, a source of the first light-emitting transistor T5 is connected to the first node A, and a first light-emitting gate T5G of the first light-emitting transistor T5 is connected to the light-emitting control line EM; a drain of the second light-emitting transistor T6 is connected to the second node B, a source of the second light-emitting transistor T6 is connected to the anode of the light-emitting device EL, and a second light-emitting gate T6G of the second light-emitting transistor T6 is connected to the light-emitting control line EM; a drain of the third reset transistor T8 is connected to the third reset signal line Vi3, a source of the third reset transistor T8 is connected to the first node A, and a third reset gate T8G of the third reset transistor T8 is connected to the second reset control line Pscan2; a first plate Cst1 of the storage capacitor Cst is connected to the third node Q, and a second plate Cst2 of the storage capacitor Cst is connected to the high potential line VDD; one plate of the boost capacitor Cboost is connected to the switch control line Pscan1, and the other plate of the boost capacitor Cboost is connected to the third node Q; and a cathode of the light-emitting device EL is connected to the low potential line VSS.

[0051] It should be noted that the switch transistors T2 in different sub-pixels PX are connected to different data signal lines, and this application only takes one of them as an example for description.

[0052] It should be noted that the light-emitting device EL of the present application can be an organic light-emitting diode, Mini LED, MicroLED, a conventional-sized LED or other light-emitting source.

[0053] In this embodiment, the high potential line VDD is used to provide a constant high voltage level to the pixel circuit PC, and the low potential line VSS is used to provide a constant low voltage level to the pixel circuit PC.

[0054] In this embodiment, the switching transistor T2, the driving transistor T1, the second reset transistor T7, the third reset transistor T8, the first light-emitting transistor T5, the second light-emitting transistor T6, the compensation transistor T3 and the first reset transistor T4 can be P-type transistors or N-type transistors; this application is described by taking the switching transistor T2, the driving transistor T1, the second reset transistor T7, the third reset transistor T8, the first light-emitting transistor T5, and the second light-emitting transistor T6 as P-type transistors, and the compensation transistor T3 and the first reset transistor T4 as N-type transistors as an example.

[0055] In this embodiment, the source is only the output end of the present application, and the drain is only the input end of the present application, and the two are only distinguished in name.

[0056] In the following embodiments, the first direction is perpendicular to the extending direction of the data line, and the angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90°. For example, the first direction X is the horizontal direction, and the second direction Y is the vertical direction.

[0057] The following is for Figure 4 The structure of the pixel circuit PC of this application is described.

[0058] See also Figure 5 The display area AA and non-display area NA of the display panel 100 may include a base substrate 110 and an array drive layer 120 disposed on the base substrate 110. Within the display area AA, the display panel 100 may also include a pixel definition layer PDL disposed on the array drive layer 120, a light-emitting device layer disposed on the same layer as the pixel definition layer PDL, and an encapsulation layer TFE disposed on the pixel definition layer PDL. The following primarily describes the film layer structure within the display area AA.

[0059] In this embodiment, the base substrate 110 supports various layers provided on the base substrate 110. When the display panel 100 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent base substrate is used. When the display panel 100 is a top-emitting light-emitting display device, a semi-transparent or opaque base substrate as well as a transparent base substrate can be used.

[0060] In this embodiment, the base substrate 110 may be made of an insulating material such as glass, quartz, or polymer resin. The base substrate 110 may be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. Examples of flexible materials for the flexible substrate include, but are not limited to, polyimide (PI).

[0061] In this embodiment, the base substrate 110 may include a first flexible substrate 111, a first barrier layer 112, a second flexible substrate 113, and a second barrier layer 114 that are stacked. The first flexible substrate 111 and the second flexible substrate 113 may be formed of the same material, such as polyimide, and the first barrier layer 112 and the second barrier layer 114 may be formed of an inorganic material, for example, including at least one of SiOx and SiNx.

[0062] See also Figure 5 The array driving layer 120 may include a plurality of thin film transistors, which may be of an etch-stop type or a back-channel etch type, or may be classified into a bottom-gate thin film transistor, a top-gate thin film transistor, and other structures according to the position of the gate electrode and the active layer, or may be classified into an N-type thin film transistor or a P-type thin film transistor according to the performance of the thin film transistor; wherein, Figure 5 The thin film transistor does not represent Figure 4 The structural diagram of any transistor is merely a schematic diagram of the various film layers of the display panel 100 of the present application.

[0063] See also Figure 5 The array driving layer 120 may include a light shielding layer 121 disposed on the base substrate 110, a buffer layer 122 disposed on the light shielding layer 121, a first active layer 123 disposed on the buffer layer 122, a first insulating layer 124 disposed on the first active layer 123, a first gate layer 125 disposed on the first insulating layer 124, a second insulating layer 126 disposed on the first gate layer 125, a second gate layer 127 disposed on the second insulating layer 126, a third insulating layer 128 disposed on the second gate layer 127, a second active layer 129 disposed on the third insulating layer 128, and a first gate layer 129 disposed on the second gate layer 129. A fourth insulating layer 130 on the second active layer 129, a third gate layer 131 arranged on the fourth insulating layer 130, a fifth insulating layer 132 arranged on the third gate layer 131, a first source and drain layer 133 arranged on the fifth insulating layer 132, a first flat layer 134 arranged on the first source and drain layer 133, a second source and drain layer 135 arranged on the first flat layer 134, and a second flat layer 136 arranged on the second source and drain layer 135, a light-emitting device layer and a pixel definition layer PDL arranged on the second flat layer 136, and an encapsulation layer TFE arranged on the pixel definition layer PDL.

[0064] See also Figure 5 The light shielding layer 121 is provided on the second barrier layer 114 and is used to block external light from entering the thin film transistor from the bottom. The material of the light shielding layer 121 can be made of a black light shielding material, such as a black light shielding metal or a black organic material.

[0065] See also Figure 5The buffer layer 122 is arranged on the light-shielding layer 121. The buffer layer 122 is used to isolate the light-shielding layer 121 from the upper metal material. The material of the buffer layer 122 may include a compound composed of nitrogen, silicon and oxygen elements, such as a single-layer silicon oxide film layer, or a silicon oxide-silicon nitride stacked structure.

[0066] In this embodiment, the light shielding layer 121 may also be embedded in the buffer layer 122 .

[0067] See also Figure 5 The first active layer 123 is arranged on the buffer layer 122, and the second active layer 127 is arranged on the third insulating layer 128. In the present application, the material of the first active layer 123 can be a silicon semiconductor, such as low-temperature polycrystalline silicon, etc., and the material of the second active layer 129 can be an oxide semiconductor, such as metal oxide, etc.; and the pixel circuit PC has N-type transistors and P-type transistors, so the display area AA of the present application is provided with metal oxide semiconductors and low-temperature polycrystalline silicon semiconductors.

[0068] See also Figure 5 The first insulating layer 124, the second insulating layer 126, the third insulating layer 128, the fourth insulating layer 130, and the fifth insulating layer 132 are respectively arranged on the corresponding metal layer or semiconductor layer to separate the metal layers or semiconductor layers of different layers; the materials of the first insulating layer 124, the second insulating layer 126, the third insulating layer 128, the fourth insulating layer 130, and the fifth insulating layer 132 can be an inorganic substance composed of at least two elements in silicon oxynitride or an organic material with flatness, or can be a stack of single or multiple film layers.

[0069] See also Figure 5 The first gate layer 125 and the second gate layer 127 are respectively disposed on corresponding insulating layers. The materials of the first gate layer 125 and the second gate layer 127 can be copper, molybdenum, or molybdenum-titanium alloy.

[0070] See also Figure 5 The first source-drain electrode layer 133 is arranged on the fifth insulating layer 132, and the second source-drain electrode layer 135 is arranged on the first flat layer 134. The materials of the first source-drain electrode layer 133 and the second source-drain electrode layer 135 can be copper, molybdenum, titanium or molybdenum-titanium alloy, or a titanium-aluminum-titanium stacked structure.

[0071] See also Figure 5 The first flat layer 134 and the second flat layer 136 are laid as a whole layer to ensure the flatness of the film layer of the array driving layer 120. The material of the first flat layer 134 and the second flat layer 136 can be an inorganic material composed of nitride oxide silicon or an organic material with flatness.

[0072] See also Figure 5The light emitting device layer may include a plurality of light emitting devices, each of which has an anode AN, a light emitting unit EL, and a cathode CA connected to the pixel circuit.

[0073] See also Figure 6 The display panel 100 includes a plurality of repeating units RU arranged along a first direction X and a second direction Y, each repeating unit RU having two sub-pixels PX, and patterns of at least part of the film layers in two pixel circuits PC in one repeating unit RU are symmetrically arranged with a center line of the repeating unit RU as an axis, and the center line may be parallel to the second direction Y.

[0074] It should be noted that due to limitations such as process and equipment, there are slight differences in the film layer patterns in different pixel circuits PC of this application in actual products. Therefore, the symmetrical setting of this application is only a symmetrical setting within the error range; at the same time, in order to set the connection points with the upper structure, some structures widen the pattern in the area where the connection points are located, resulting in an asymmetric pattern setting, which is also within the error range.

[0075] It should be noted that the structure and film layer structure of the above-mentioned pixel circuit PC of the present application are applicable to all sub-pixels PX of the present application.

[0076] In the following embodiments, the structure of each film layer in two pixel circuits PC in a repeating unit RU is taken as an example to describe the technical solution of the present application.

[0077] See also Figure 7 The first gate layer 125 includes a first reset signal line Vi1, a switch control line Pscan1, a light emitting control line EM, and a second reset control line Pscan2 extending along the first direction X. The first reset signal line Vi1, the switch control line Pscan1, the light emitting control line EM, and the second reset control line Pscan2 are arranged in sequence along the second direction Y, and the first reset signal line Vi1, the switch control line Pscan1, the light emitting control line EM, and the second reset control line Pscan2 in a repeating unit RU are connected to each other.

[0078] See also Figure 7The first gate layer 125 also includes a first plate Cst1 of a storage capacitor Cst arranged between the switch control line Pscan1 and the light-emitting control line EM. The first plate Cst1 and the switch control line Pscan1 and the light-emitting control line EM are arranged at intervals. In order to ensure the compactness of the wiring space in the pixel circuit, a compensation transistor T3 is usually required between the first plate Cst1 and the switch control line Pscan1, and a transistor is not required between the first plate Cst1 and the light-emitting control line EM. Therefore, the distance between the first plate Cst1 and the switch control line Pscan1 of the present application is greater than the distance between the first plate Cst1 and the light-emitting control line EM; at the same time, the two first plates Cst1 in a repeating unit RU are arranged at intervals.

[0079] See also Figure 8 The first active layer 123 includes a switch active portion T2A of the switch transistor T2, a first light emitting active portion T5A of the first light emitting transistor T5, a driving active portion T1A of the driving transistor T1, a second light emitting active portion T6A of the second light emitting transistor T6, a second reset active portion T7A of the second reset transistor T7, a third reset active portion T8A of the third reset transistor T8, a first extension segment ET1, and a second extension segment ET2.

[0080] See also Figure 8 The switch active portion T2A, the first light-emitting active portion T5A, and the driving active portion T1A are connected to the first connection point N1, the driving active portion T1A and the second light-emitting active portion T6A are connected to the second connection point N2, the first extension segment ET1, the second light-emitting active portion T6A, and the second reset active portion T7A are connected to the third connection point N3, the first extension segment ET1 extends from the third connection point N3 to a side close to the first light-emitting active portion T5A, the third reset active portion T8A is spaced apart from the above active portions and is located between the first extension segment ET1 and the first light-emitting active portion T5A, the second extension segment ET2 is connected to the first connection point N1, and is located between the driving active portion T1A and the first light-emitting active portion T5A, and the two first light-emitting active portions T5A in a repeating unit RU are connected at the end away from the first node.

[0081] See also Figure 8 The switch active portion T2A, the first light emitting active portion T5A, the second light emitting active portion T6A, the second reset active portion T7A, and the third reset active portion T8A extend along the second direction Y and are strip-shaped, the first extension segment ET1 extends along the first direction X and is strip-shaped, and the driving active portion T1A can be U-shaped.

[0082] See also Figure 6The light emitting control line EM and the first light emitting active portion T5A have an overlapping portion. The light emitting control line EM in the overlapping portion is multiplexed as the first light emitting gate T5G. The first light emitting active portion T5A in the overlapping portion is the channel of the first light emitting transistor T5. The end of the first light emitting active portion T5A away from the first connection point N1 is multiplexed as the drain of the first light emitting transistor T5, and the end of the first light emitting active portion T5A close to the first connection point N1 is multiplexed as the source of the first light emitting transistor T5. That is, the structure in the area where the first connection point N1 is located is the first node A in the pixel circuit PC.

[0083] See also Figure 6 The light emitting control line EM and the second light emitting active portion T6A have an overlapping portion. The light emitting control line EM in the overlapping portion is multiplexed as the second light emitting gate T6G. The second light emitting active portion T6A in the overlapping portion is the channel of the second light emitting transistor T6. An end of the second light emitting active portion T6A away from the second connection point N2 is multiplexed as the source of the second light emitting transistor T6, and an end of the second light emitting active portion T6A close to the second connection point N2 is multiplexed as the drain of the second light emitting transistor T6. That is, the structure of the area where the second connection point N2 is located is the second node B in the pixel circuit PC, and the structure of the area where the third connection point N3 is located is the position connected to the anode AN in the pixel circuit PC.

[0084] See also Figure 6 The second reset control line Pscan2 and the second reset active portion T7A have an overlapping portion. The second reset control line Pscan2 in the overlapping portion is multiplexed as the second reset gate T7G. The second reset active portion T7A in the overlapping portion is the channel of the second reset transistor T7. An end of the second reset active portion T7A close to the third connection point N3 is multiplexed as the source of the second reset transistor T7, and an end of the second reset active portion T7A far from the third connection point N3 is multiplexed as the drain of the second reset transistor T7.

[0085] See also Figure 6 The second reset control line Pscan2 and the third reset active portion T8A have an overlapping portion. The second reset control line Pscan2 in the overlapping portion is multiplexed as the third reset gate T8G. The third reset active portion T8A in the overlapping portion is the channel of the third reset transistor T8. An end of the third reset active portion T8A close to the emission control line EM is multiplexed as the source of the third reset transistor T8, and an end of the third reset active portion T8A far from the emission control line EM is multiplexed as the drain of the third reset transistor T8.

[0086] See also Figure 6The switch control line Pscan1 and the switch active portion T2A have an overlapping portion. The switch control line Pscan1 in the overlapping portion is multiplexed as the switch gate T2G. The switch active portion T2A in the overlapping portion is the channel of the switch transistor T2. An end of the switch active portion T2A close to the first connection point N1 is multiplexed as the source of the switch transistor T2, and an end of the switch active portion T2A far from the first connection point N1 is multiplexed as the drain of the switch transistor T2.

[0087] See also Figure 9 The light-shielding layer 121 includes a driving light-shielding portion T1L and a first connecting segment CT1 and a second connecting segment CT2 connected to the driving light-shielding portion T1L. In the first direction X, two adjacent driving light-shielding portions T1L are connected by the first connecting segment CT1, and in the second direction Y, two adjacent driving light-shielding portions T1L are connected by the second connecting segment CT2, so that the multiple driving light-shielding portions T1L form a network structure. For example, high-potential signals can be transmitted on the driving light-shielding portions T1L to maintain the stability of the potential on the channel of the driving transistor T1. The horizontally and vertically staggered driving light-shielding portions T1L can reduce the impedance of the driving light-shielding portions T1L themselves, reduce the attenuation of the transmitted high-potential signals, and ensure the uniformity of the high-potential signals on the light-shielding layer 121.

[0088] In this embodiment, the driving light shielding portion T1L corresponds to the driving transistor T1 to shield the driving light shielding portion T1L; at the same time, the first connecting segment CT1 of the present application can also shield the compensation active portion T3A, and the second connecting segment CT2 can also shield the first reset active portion T4A.

[0089] exist Figure 10 In the structure, the second gate layer 127 includes the second electrode plate Cst2 of the storage capacitor Cst, and the second electrode plates Cst2 in a repeating unit RU are connected, and the second electrode plate Cst2 is arranged opposite to the first electrode plate Cst1.

[0090] In this embodiment, the first electrode plate Cst1 can be reused as the gate of the driving transistor. Since the area of ​​the first electrode plate Cst1 is fixed, the increase in the area of ​​the second electrode plate Cst2 can increase the relative area between the first electrode plate Cst1 and the second electrode plate Cst2, which is equivalent to increasing the capacitance of the storage capacitor. Therefore, the outer contour area of ​​the first electrode plate Cst1 of the present application is smaller than the outer contour area of ​​the second electrode plate Cst2.

[0091] exist Figure 10 In the structure, the second gate layer 127 further includes a first reset control line Nscan2a and a first compensation control line Nscan1a arranged at intervals along the second direction Y, and the first reset control line Nscan2a and the first compensation control line Nscan1a both extend along the first direction X.

[0092] exist Figure 11 In the structure, the second active layer 129 includes a first reset active portion T4A of the first reset transistor T4 and a compensation active portion T3A of the compensation transistor T3. The first reset active portion T4A and the compensation active portion T3A both extend along the second direction Y and are in a long strip shape. The first reset active portion T4A and the compensation active portion T3A are connected to a fourth connection point N4.

[0093] exist Figure 12 In the structure, the third gate layer 131 further includes a second first reset control line Nscan2b, a second compensation control line Nscan1b and a third reset signal line Vi3 arranged at intervals along the second direction Y, and the second first reset control line Nscan2b and the second compensation control line Nscan1b both extend along the first direction X.

[0094] exist Figure 6 In the structure, the first first reset control line Nscan2a and the second first reset control line Nscan2b have an overlapping portion with the first reset active portion T4A, and the first first reset control line Nscan2a and the second first reset control line Nscan2b in the overlapping portion are both multiplexed as the first reset gate T4G (i.e., the bottom gate and the top gate). The first reset active portion T4A in the overlapping portion is the channel of the first reset transistor T4, and an end of the first reset active portion T4A close to the fourth connection point N4 is multiplexed as the source of the first reset transistor T4, and an end of the first reset active portion T4A far from the fourth connection point N4 is multiplexed as the drain of the first reset transistor T4, that is, the structure in the area where the fourth connection point N4 is located is the third node Q in the pixel circuit PC, and the control signals transmitted by the first first reset control line Nscan2a and the second first reset control line Nscan2b are the same.

[0095] exist Figure 6 In the structure, the second compensation control line Nscan1b and the first compensation control line Nscan1a both have an overlapping portion with the compensation active portion T3A of the compensation transistor T3, and the first compensation control line Nscan1a and the second compensation control line Nscan1b in the overlapping portion are both multiplexed as the compensation gate T3G (i.e., the bottom gate and the fixed gate), the compensation active portion T3A in the overlapping portion is the channel of the compensation transistor T3, an end of the compensation active portion T3A close to the fourth connection point N4 is multiplexed as the drain of the compensation transistor T3, and an end of the compensation active portion T3A far from the fourth connection point N4 is multiplexed as the source of the compensation transistor T3, and the control signal transmitted by the second compensation control line Nscan1b and the first compensation control line Nscan1a is the same.

[0096] See also Figure 6 and Figure 13 The first source-drain layer 133 includes a lateral fan-out line FIAH and a second reset signal line Vi2. The lateral fan-out line FIAH is arranged on the side of the first reset signal line Vi1 away from the switch control line Pscan1. The second reset signal line Vi2 is arranged between the third reset signal line Vi3 and the second reset control line Pscan2.

[0097] See also Figure 6 and Figure 13 The first source-drain layer 133 further includes a third connection segment CT3, one end of the third connection segment CT3 is connected to the first reset signal line Vi1 through a via hole, and the other end of the third connection segment CT3 is connected to an end of the first reset active portion T4A away from the fourth connection point N4 through a via hole.

[0098] See also Figure 6 and Figure 13 The first source-drain layer 133 further includes a fourth connection segment CT4, one end of which is connected to the data line Data through a via hole, and the other end of which is connected to an end of the switch active portion T2A away from the first connection point N1 through a via hole.

[0099] See also Figure 6 and Figure 13 The first source-drain layer 133 further includes a fifth connection segment CT5, one end of which passes through the via hole and is connected to one end of the fourth connection point N4 of the compensation active portion T3A, and the other end of the fifth connection segment CT5 passes through the avoidance hole HL0 in the second electrode plate Cst2 and is connected to the first electrode plate Cst1.

[0100] See also Figure 6 and Figure 13 The first source-drain layer 133 further includes a sixth connection segment CT6, one end of the sixth connection segment CT6 is connected to an end of the compensation active portion T3A away from the fourth connection point N4 through a via hole, and the other end of the sixth connection segment CT6 is connected to an end of the second light-emitting active portion T6A away from the third connection point N3 through a via hole.

[0101] See also Figure 6 and Figure 13 The first source-drain layer 133 further includes a seventh connection segment CT7, one end of the seventh connection segment CT7 is connected to the end of the first extension segment ET1 away from the third connection point N3 through the via hole, and the other end of the seventh connection segment CT7 is connected to the upper metal layer through the via hole.

[0102] See also Figure 6 and Figure 13The first source-drain layer 133 further includes an eighth connection segment CT8, one end of the eighth connection segment CT8 is connected to the second extension segment ET2 through a via hole, and the other end of the eighth connection segment CT8 is connected to an end of the third reset active portion T8A close to the light emitting control line EM through a via hole.

[0103] In this embodiment, the third reset signal line Vi3 includes a reset transverse segment Vi3a and a reset extension segment Vi3b. The reset transverse segment Vi3a extends along the first direction X, and the reset extension segment Vi3b extends along the second direction Y. The reset extension segment Vi3b overlaps with the eighth connecting segment CT8, which is equivalent to the reset extension segment Vi3b overlapping with the area where the first node is located.

[0104] See also Figure 6 and Figure 13 The first source-drain electrode layer 133 further includes a ninth connection segment CT9, one end of which is connected to the reset extension segment Vi3b through a via hole, and the other end of the ninth connection segment CT9 is connected to an end of the third reset active portion T8A away from the light-emitting control line EM through a via hole, and the two ninth connection segments CT9 in a repeating unit RU are electrically connected at a position overlapping with the reset extension segment Vi3b.

[0105] See also Figure 6 and Figure 13 The first source-drain electrode layer 133 further includes a tenth connecting segment CT10. The tenth connecting segment CT10 includes a first transverse segment CT10a and a first longitudinal segment CT10b connected to each other. The first transverse segment CT10a is arranged along the first direction X, and the first longitudinal segment CT10b is arranged along the second direction Y.

[0106] In this embodiment, the first transverse segments CT10a in a repeating unit RU are connected to each other, and the first longitudinal segments CT10b in a repeating unit RU are shared; at the same time, the first longitudinal segment CT10b includes a first portion close to the first transverse segment CT10a and a second portion away from the first transverse segment CT10a, an end of the first portion close to the second portion is electrically connected to the second electrode Cst2 through a via hole, and an end of the second portion away from the first portion is connected to an end of the first light-emitting active portion T5A away from the first connection point N1 through a via hole.

[0107] In this embodiment, the line width of the first portion is greater than the line width of the second portion.

[0108] See also Figure 14 and Figure 15 The second source-drain layer 135 includes a high potential line VDD, a reset connection line Via, and a data line Data arranged along the first direction X. The high potential line VDD and the reset connection line Via both extend along the second direction Y.

[0109] Please note that Figure 14 In a repeating unit RU, the pixel circuit PC on the left may include a high potential line VDD, a reset connection line Via, and a data line Data arranged along the first direction X; the pixel circuit PC on the right may include a data line Data, a vertical fan-out line FIAZ, and a high potential line VDD arranged along the first direction X; each column of sub-pixels PX corresponds to a high potential line VDD and a data line Data, and each sub-pixel PX in each repeating unit RU is provided with a vertical fan-out line FIAZ, which may be electrically connected to the horizontal fan-out line FIAH.

[0110] It should be noted that the reset connection line Via can be a reset line connected to the first reset line Vi1, the second reset line Vi2, and the third reset line Vi3. For example, in three consecutive repeating units RU arranged in the first direction X, the reset connection line Via in the first repeating unit RU can be connected to the first reset line Vi1, the reset connection line Via in the second repeating unit RU can be connected to the second reset line Vi2, and the reset connection line Via in the third repeating unit RU can be connected to the third reset line Vi3, so that the reset lines transmitting the three reset signals form three different mesh structures, reducing the resistance and capacitance impedance of the metal lines of the reset signals.

[0111] It should be noted that Figure 14 The position of the reset connection line Via can also be set to the longitudinal fan-out line FIAZ, or Figure 14 The middle vertical fan-out line FIAZ can also be set with a reset connection line Via, which can be adaptively adjusted according to the setting density of the recurrence connection line Via and the vertical fan-out line FIAZ.

[0112] It should be noted that the second source and drain layer 135 of the present application may include multiple data lines Data, and the multiple data lines Data may include a first data line D1, a second data line D2, and a third data line D3. The sub-pixels connected to the first data line D1 have the same luminous color, the sub-pixels connected to the second data line D2 have the same luminous color, and the sub-pixels connected to the third data line D3 have the same luminous color. The sub-pixels connected to the first data line D1, the third data line D3, and the second data line D2 have different luminous colors. For example, the first data line D1 is electrically connected to the red sub-pixel, the second data line D2 is electrically connected to the blue sub-pixel, and the third data line D3 is electrically connected to the green sub-pixel.

[0113] See also Figure 16 and Figure 17The display panel 100 includes a plurality of first sub-pixels PXr, a plurality of second sub-pixels PXb, and a plurality of third sub-pixels PXg. The plurality of third sub-pixels PXg may be arranged along a first direction X and a second direction Y. The third sub-pixels PXg arranged along the first direction X may constitute a second pixel row PH2, and the third sub-pixels PXg arranged along the second direction Y may constitute a second pixel column PL2.

[0114] In this embodiment, the centers of two first sub-pixels PXr and two second sub-pixels PXb in two adjacent rows form a virtual quadrilateral QD, and a third sub-pixel PXg is located within the virtual quadrilateral QD.

[0115] In this embodiment, the anode layer AN includes a plurality of first anode patterns 210, a plurality of second anode patterns 220 and a plurality of third anode patterns 230, and the plurality of light-emitting units EL include a plurality of first light-emitting units ELr, a plurality of second light-emitting units ELb and a plurality of third light-emitting units ELg. The orthographic projection of the first light-emitting unit ELr on the base substrate 110 is located within the orthographic projection of the first anode pattern 210 on the base substrate 110, the orthographic projection of the second light-emitting unit ELb on the base substrate 110 is located within the orthographic projection of the second anode pattern 220 on the base substrate 110, and the orthographic projection of the third light-emitting unit ELg on the base substrate 110 is located within the orthographic projection of the third anode pattern 230 on the base substrate 110.

[0116] In this embodiment, the first anode pattern 210, the first light-emitting unit ELr and the pixel driving circuit PC connected to the first anode pattern 210 constitute a first sub-pixel PXr, the second anode pattern 220, the second light-emitting unit ELb and the pixel driving circuit PC connected to the second anode pattern 220 constitute a second sub-pixel PXb, and the third anode pattern 230, the third light-emitting unit ELg and the pixel driving circuit PC connected to the third anode pattern 230 constitute a third sub-pixel PXg.

[0117] For example, the light-emitting color of the first subpixel PXr is red, the light-emitting color of the second subpixel PXb is blue, and the light-emitting color of the third subpixel PXg is green, that is, the first light-emitting unit ELr is a red light-emitting unit, the second light-emitting unit ELb is a blue light-emitting unit, and the third light-emitting unit ELg is a green light-emitting unit.

[0118] In this embodiment, the area of ​​the first sub-pixel PXr is smaller than that of the second sub-pixel PXb, and the area of ​​the third sub-pixel PXg is smaller than or equal to that of the first sub-pixel PXr.

[0119] See also Figure 16 and Figure 17In the 2k-th row of the first pixel row PH1, the first anode pattern 210 includes a first anode body 211 and a first anode lead 212 connected to each other, the second anode pattern 220 includes a second anode body 221 and a second anode lead 222 connected to each other, the first anode lead 212 is electrically connected to the corresponding first data line D1, the second anode lead 222 is electrically connected to the corresponding second data line D2, and the first anode lead 212 and the second anode lead 222 extend along a third direction Z, which is opposite to the first direction X.

[0120] See also Figure 16 and Figure 17 In the 2k-1th row of the first pixel row PH1, the first anode pattern 210 includes a third anode body 213 and a third anode lead 214 connected to each other, the second anode pattern 220 includes a fourth anode body 223 and a fourth anode lead 224 connected to each other, the third anode lead 214 is electrically connected to the corresponding first data line D1, the fourth anode lead 224 is electrically connected to the corresponding second data line D2, and the third anode lead 214 and the fourth anode lead 224 extend along the first direction X.

[0121] See also Figure 16 and Figure 17 The third sub-pixel PXg includes a third anode pattern 230, the third anode pattern 230 includes a fifth anode body 231 and a fifth anode lead 232 connected to each other, the fifth anode lead 232 extends along the second direction Y, and a third data line D3 is electrically connected to multiple third sub-pixels PXg arranged along the second direction Y.

[0122] See also Figure 16 and Figure 17 The second source-drain layer 135 includes a plurality of high potential lines VDD and a plurality of data lines Data. Two data lines Data are provided between two adjacent high potential lines VDD. For example, Figure 17 The four data lines Data shown in the figure are respectively the first data line D1, the third data line D3, the second data line D2, and the third data line D3, that is, the first data line D1 and the third data line D3 are arranged between two adjacent high potential lines VDD, or the second data line D2 and the third data line D3 are arranged between two adjacent high potential lines VDD, that is, the multiple data lines Data of the present application are repeatedly arranged along the first direction X in the order of the first data line D1, the third data line D3, the second data line D2, and the third data line D3.

[0123] See also Figure 16 and Figure 17 A plurality of openings OP are formed on the high potential line VDD, and a first electrical connection segment 241 and a second electrical connection segment 242 arranged along the first direction X are provided in each opening OP. Figure 14The first electrical connection segment 241 and the second electrical connection segment 242 in the repeating unit RU are arranged at intervals, but the first electrical connection segment 241 and the second electrical connection segment 242 in two adjacent repeating units RU are arranged adjacent to each other.

[0124] In this embodiment, the first electrical connection segment 241 is electrically connected to the third sub-pixel PXg, and the second electrical connection segment 242 is electrically connected to the second sub-pixel PXb or the first sub-pixel PXr.

[0125] For example, Figure 17 In the structure, in the first pixel row PH1 of the 2k-1 row, the third anode lead 214 of the first sub-pixel PXr crosses over the adjacent first electrical connection segment 241 and is electrically connected to the second electrical connection segment 242 set at an interval, and the fourth anode lead 224 of the second sub-pixel PXb crosses over the adjacent first electrical connection segment 241 and is electrically connected to the second electrical connection segment 242 set at an interval; in the first pixel row PH1 of the 2k row, the first anode lead 212 of the first sub-pixel PXr is directly electrically connected to the adjacent first electrical connection segment 241, and the fourth anode lead 224 of the second sub-pixel PXb is directly electrically connected to the adjacent first electrical connection segment 241.

[0126] In this embodiment, since the anode lead of the odd-numbered first pixel row PH1 crosses the adjacent first electrical connection segment 241 and is electrically connected to the spaced second electrical connection segment 242, and the anode lead of the even-numbered first pixel row PH1 is directly electrically connected to the adjacent first electrical connection segment 241, the length of the anode lead of the odd-numbered first pixel row PH1 is greater than the length of the anode lead of the even-numbered first pixel row PH1, that is, the area of ​​the first anode lead 212 is smaller than the area of ​​the third anode lead 214, and the area of ​​the second anode lead 222 is smaller than the area of ​​the fourth anode lead 224.

[0127] Therefore, when the area of ​​the first anode body 211 is the same as the area of ​​the third anode body 213, and the area of ​​the second anode body 221 is the same as the area of ​​the fourth anode body 223, there is a difference in the anode area in the odd-numbered first pixel row PH1 and the even-numbered first pixel row PH1 of the present application, which leads to technical problems such as abnormal display such as horizontal stripes on the display panel 100 when displaying or holding the breath.

[0128] See also Figures 16 to 19 At least one of the first anode pattern 210 and the second anode pattern 220 further includes a compensation portion 30 connected to the corresponding anode body.

[0129] In this embodiment, the compensation portion 30 includes a first compensation unit 310 extending in a direction away from the first anode body 211, the first compensation unit 310 is in a long strip shape, and the angle between the first compensation unit 310 and the first anode lead 212 is in a range of 0 to 180 degrees; or / and, the compensation portion 30 includes a second compensation unit 320 extending in a direction away from the second anode body 221, the second compensation unit 320 is in a long strip shape, and the angle between the second compensation unit 320 and the second anode lead 222 is in a range of 0 to 180 degrees.

[0130] For example, in Figure 16 In the structure, the compensation part 30 includes a first compensation unit 310 and a second compensation unit 320. The first compensation unit 310 is located on the side of the first anode body 211 away from the first anode lead 212, and the first compensation unit 310 is spaced apart from the adjacent first anode lead 212; the second compensation unit 320 is located on the side of the second anode body 221 away from the second anode lead 222, and the second compensation unit 320 is spaced apart from the adjacent first anode lead 212.

[0131] exist Figure 16 In the structure, the present application increases the area of ​​the first anode pattern 210 and the second anode pattern 220 in the even first pixel row PH1 by setting the first compensation unit 310 in the first anode pattern 210 and the second compensation unit 320 in the second anode pattern 220, reduces the area difference between the first anode pattern 210 and the second anode pattern 220 in the odd rows and the even rows, eliminates the difference in resistance and capacitance between the anode and the underlying conductive structure in sub-pixels in different rows, and improves the technical problem of horizontal stripes appearing on the display panel 100 when displaying or holding the breath.

[0132] It should be noted that Figure 16 The compensation part 30 may only have the first compensation unit 310 or the second compensation unit 320, as long as the ratio of the absolute value of the difference between the first area and the second area to the first area or the second area is less than or equal to 8% and greater than or equal to 0.

[0133] It should be noted that the present application can make the sum of the areas of the first anode body 211, the first anode lead 212 and the first compensation unit 310 equal to the sum of the areas of the third anode body 213 and the third anode lead 214; and the sum of the areas of the second anode body 221, the second anode lead 222 and the second compensation unit 320 equal to the sum of the areas of the fourth anode body 223 and the fourth anode lead 224, that is, the areas of the anode patterns between different rows are the same, further eliminating the difference in resistance and capacitance between the anode patterns in sub-pixels in different rows and the underlying conductive structure, and improving the technical problem of horizontal stripes appearing on the display panel 100 when displaying or holding the breath.

[0134] It should be noted that the first compensation unit 310 and the second compensation unit 320 of the present application can be located at any position of the corresponding anode body, for example, Figure 18 In the structure, the first compensation unit 310 and the second compensation unit 320 can extend toward the location of the adjacent high potential line VDD so as to have an overlapping portion with the adjacent high potential line VDD, thereby increasing the overlapping area between the anode pattern and the high potential line VDD and improving the resistance and capacitance of the anode pattern in the even rows.

[0135] It should be noted that since the fifth anode lead 232 extends along the second direction Y, the first compensation unit 310 and the second compensation unit 320 of the present application need to avoid the corresponding fifth anode lead 232 to avoid the first compensation unit 310 and the second compensation unit 320 being electrically connected to the adjacent fifth anode lead 232.

[0136] In this embodiment, since the red sub-pixel is easier to light up than the sub-pixels of the other two colors among the red sub-pixels, the green sub-pixels and the blue sub-pixels, the potential stability of the red sub-pixel at the anode point of the present application needs to be better than the potential stability of the blue sub-pixel at the anode point; and since the first compensation unit 310 is connected to the first anode body 211 in the red sub-pixel, and the second compensation unit 320 is connected to the second anode body 221 in the green sub-pixel, the area of ​​the compensation unit is larger, then the area of ​​the anode in the corresponding sub-pixel is larger, the capacitance between the anode and the lower-layer wire is larger, and the potential stability of the anode point is better. Therefore, the present application can make the area of ​​the first compensation unit 310 greater than or equal to the area of ​​the second compensation unit 320, so as to increase the potential stability of the first anode pattern 210 of the red sub-pixels in the even rows, and ensure the luminous stability of the red sub-pixels.

[0137] In this embodiment, the compensation part 30 may include a third compensation unit 330, the first anode body 211 includes four first side edges L1 opposite to the first sub-pixel PXr of the adjacent row, and the third compensation unit 330 is connected to at least one of the four first side edges L1; or / and, the compensation part 30 may include a fourth compensation unit 340, the second anode body 221 includes four second side edges L2 opposite to the second sub-pixel PXb of the adjacent row, and the fourth compensation unit 340 is connected to at least one of the four second side edges L2.

[0138] For example, see Figure 19The first anode body 211 and the second anode body 221 are diamond-like in shape, the first anode body 211 has four first sides L1, the second anode body 221 has four second sides L2, the third compensation unit 330 is connected to a side of the first anode body 211 away from the fifth anode lead 232, and the fourth compensation unit 340 is connected to a side of the second anode body 221 away from the fifth anode lead 232.

[0139] For example, the third compensation unit 330 and the fourth compensation unit 340 may both be in the shape of a triangle, with one side of the triangle coinciding with a side of the corresponding anode body.

[0140] exist Figure 19 In the structure, two of the four first sides L1 away from the fifth anode lead 232 are each provided with a third compensation unit 330 , and two of the four second sides L2 away from the fifth anode lead 232 are each provided with a fourth compensation unit 340 .

[0141] It should be noted that the third compensation unit 330 and the fourth compensation unit 340 of the present application may also be in a polygonal shape, and the third compensation unit 330 and the fourth compensation unit 340 may also be arranged to overlap with the corresponding data line Data.

[0142] It should be noted that Figure 19 Only at least one of the two third compensation units 330 and the two fourth compensation parts 30 may be provided.

[0143] In this embodiment, the area of ​​the third compensation unit 330 can be greater than or equal to the area of ​​the fourth compensation unit 340. Since the increase in the area of ​​the third compensation unit 330 is equivalent to increasing the area of ​​the first anode pattern 210, the capacitance between the first anode pattern 210 and the underlying wire is larger, and the potential stability of the first anode pattern 210 is better. Therefore, the present application can make the area of ​​the third compensation unit 330 greater than or equal to the area of ​​the fourth compensation unit 340, so as to increase the potential stability of the first anode pattern 210 of the red sub-pixels in the even rows and ensure the luminous stability of the red sub-pixels.

[0144] It should be noted that Figure 19 and Figure 17 and Figure 18 The compensation units in the embodiment may be arbitrarily combined. For example, the first compensation unit 310 and the third compensation unit 330 may be present on the first anode pattern 210 at the same time, and the second compensation unit 320 and the fourth compensation unit 340 may be present on the second anode pattern 220 at the same time.

[0145] Since there is a coupling capacitor between the anode pattern and the data line Data, in order to avoid the influence of the signal on the data line Data on the potential on the anode pattern, the present application needs to reduce the overlapping area between the anode pattern and the data line Data. Therefore, the compensation part 30 of the present application is set to be non-overlapping with at least one of the first data line D1, the third data line D3, and the second data line D2.

[0146] For example Figures 17 to 19 In the structure of FIG, the first compensation unit 310, the second compensation unit 320, the third compensation unit 330 and the fourth compensation unit 340 are all arranged away from the data line Data.

[0147] It should be noted that although the red sub-pixel is easier to light up than the sub-pixels of the other two colors, the potential of the red sub-pixel at the anode point requires higher stability, but since the green sub-pixel accounts for a larger proportion of the luminous brightness in the display panel 100 than the red sub-pixel and the blue sub-pixel, the present application needs to reduce the coupling capacitance between the green sub-pixel and the lower conductive layer.

[0148] For example, Figures 17 to 19 In the figure, the overlapping area between the third sub-pixel PXg and the high potential line VDD is larger than the overlapping area between the second sub-pixel PXb and the high potential line VDD, and larger than the overlapping area between the first sub-pixel PXr and the high potential line VDD. Since the overlapping area between the third sub-pixel PXg and the high potential line VDD is the largest, and the high potential line VDD is used to transmit a constant high potential signal, a coupling capacitor is formed between the high potential line VDD and the third anode pattern 230, which can ensure the stability of the potential on the third anode pattern 230.

[0149] Since the areas of the anode patterns in the odd first pixel row PH1 and the even first pixel row PH1 are different, in addition to increasing the area of ​​the anode pattern in the even first pixel row PH1, the present application can also reduce the area of ​​the anode pattern in the odd first pixel row PH1.

[0150] In this embodiment, the area of ​​the first anode body 211 is greater than the area of ​​the third anode body 213 , or / and the area of ​​the second anode body 221 is greater than the area of ​​the fourth anode body 223 .

[0151] For example, see Figure 20 The area of ​​the first anode body 211 can be larger than the area of ​​the third anode body 213, and the area of ​​the second anode body 221 can be larger than the area of ​​the fourth anode body 223, which is equivalent to that the present application can reduce the areas of the third anode body 213 and the fourth anode body 223 so that the ratio of the absolute value of the difference between the first area and the second area to the first area or the second area is less than or equal to 8%, and greater than or equal to 0.

[0152] In this embodiment, since the third anode body 213 and the fourth anode body 223 both have side edges arranged adjacent to the fifth anode lead 232, the present application can reduce the area of ​​the third anode body 213 on the side close to the fifth anode lead 232, as well as the area of ​​the fourth anode body 223 on the side close to the fifth anode lead 232.

[0153] For example, in Figure 20 In the structure, the third anode body 213 includes a third side L3 close to the fifth anode lead 232 and a fourth side L4 away from the fifth anode lead 232. The minimum distance between the outer contour of the first light-emitting unit ELr in the odd-numbered first pixel row and the third side L3 is smaller than the minimum distance between the outer contour of the first light-emitting unit ELr in the even-numbered first pixel row and the fourth side L4. That is, the average distance between the outer contour of the first light-emitting unit ELr in the odd-numbered first pixel row and the outer contour of the third anode body 213 is smaller than the average distance between the outer contour of the first light-emitting unit ELr in the even-numbered first pixel row and the outer contour of the first anode body 211. ; and, the fourth anode body 223 includes a fifth side L5 close to the fifth anode lead 232 and a sixth side L6 away from the fifth anode lead 232, and the minimum distance between the outer contour of the second light-emitting unit ELb in the odd-numbered first pixel row and the fifth side L5 is smaller than the minimum distance between the outer contour of the second light-emitting unit ELb in the even-numbered first pixel row and the sixth side L6, that is, the average distance between the outer contour of the second light-emitting unit ELb in the odd-numbered first pixel row and the outer contour of the fourth anode body 223 is smaller than the average distance between the outer contour of the second light-emitting unit ELb in the even-numbered first pixel row and the outer contour of the second anode body 221.

[0154] Therefore, the present application can improve the technical problem of the difference in area of ​​the anode patterns between different rows by reducing the areas of the third anode body 213 and the fourth anode body 223 .

[0155] It should be noted that the Figure 20 The technical solutions in Figures 17 to 19 Combine the technical solutions in .

[0156] The present application also provides a display device, comprising the above-mentioned display panel. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0157] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0158] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0159] In the above embodiments, the structures shown in the drawings are only schematic diagrams, and the specific structure of the display panel of the present application is mainly based on the description.

[0160] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0161] The above are merely preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: include: a plurality of first sub-pixels and a plurality of second sub-pixels, and both are alternately arranged along a first direction and a second direction, wherein the plurality of first sub-pixels and the plurality of second sub-pixels arranged along the first direction constitute a first pixel row, and the plurality of first sub-pixels and the plurality of second sub-pixels arranged along the second direction constitute a first pixel column; a plurality of data lines arranged along the first direction and extending along the second direction, the plurality of data lines including a first data line and a second data line, a first sub-pixel in two adjacent first pixel columns being electrically connected to a first data line, and a second sub-pixel in two adjacent first pixel columns being electrically connected to a second data line; In which, the first sub-pixel includes a first anode pattern, the second sub-pixel includes a second anode pattern, in the 2k-1th row of the first pixel row, the sum of the areas of the multiple first anode patterns and the multiple second anode patterns is a first area, in the 2kth row of the first pixel row, the sum of the areas of the multiple first anode patterns and the multiple second anode patterns is a second area, and the ratio of the absolute value of the difference between the first area and the second area to the first area or the second area is less than or equal to 8%, and greater than or equal to 0.

2. The display panel according to claim 1, wherein: In the 2kth row of the first pixel row, the first anode pattern includes a first anode body and a first anode lead connected to each other, the second anode pattern includes a second anode body and a second anode lead connected to each other, the first anode lead is electrically connected to the corresponding first data line, and the second anode lead is electrically connected to the corresponding second data line; Wherein, at least one of the first anode pattern and the second anode pattern further includes a compensation portion connected to the corresponding anode body.

3. The display panel according to claim 2, wherein: The compensation portion includes a first compensation unit extending in a direction away from the first anode body, the first compensation unit is in a strip shape, and an angle between the first compensation unit and the first anode lead ranges from 0 to 180 degrees; or / and, The compensation portion includes a second compensation unit extending in a direction away from the second anode body, the second compensation unit is in a strip shape, and the angle between the second compensation unit and the second anode lead ranges from 0 to 180 degrees; The first anode lead and the second anode lead both extend along a third direction, and the third direction is opposite to the first direction.

4. The display panel according to claim 3, wherein: The first compensation unit is located on a side of the first anode body away from the first anode lead, and the first compensation unit is spaced apart from the adjacent second anode lead; The second compensation unit is located on a side of the second anode body away from the second anode lead, and the second compensation unit is spaced apart from the adjacent first anode lead.

5. The display panel according to claim 4, wherein: An area of ​​the first compensation unit is greater than or equal to an area of ​​the second compensation unit.

6. The display panel according to claim 2, wherein: The compensation portion includes a third compensation unit, the first anode body includes four first sides opposite to the first sub-pixels of adjacent rows, and the third compensation unit is connected to at least one of the four first sides; or / and, The compensation portion includes a fourth compensation unit, the second anode body includes four second sides opposite to the second sub-pixels of adjacent rows, and the fourth compensation unit is connected to at least one of the four second sides.

7. The display panel according to claim 6, wherein: An area of ​​the third compensation unit is greater than or equal to an area of ​​the fourth compensation unit.

8. The display panel according to claim 2, wherein: In the 2k-1th row of the first pixel row, the first anode pattern includes a third anode body and a third anode lead connected to each other, the second anode pattern includes a fourth anode body and a fourth anode lead connected to each other, the third anode lead is electrically connected to the corresponding first data line, and the fourth anode lead is electrically connected to the corresponding second data line; The area of ​​the first anode lead is smaller than that of the third anode lead, and the area of ​​the second anode lead is smaller than that of the fourth anode lead.

9. The display panel according to claim 8, wherein: The area of ​​the first anode body is the same as the area of ​​the third anode body, and the area of ​​the second anode body is the same as the area of ​​the fourth anode body.

10. The display panel according to any one of claims 2 to 9, characterized in that: The display panel further includes a plurality of third sub-pixels arranged along the first direction and the second direction, wherein centers of two first sub-pixels and two second sub-pixels in two adjacent rows form a virtual quadrilateral, and one third sub-pixel is located within the virtual quadrilateral; The third sub-pixel includes a fifth anode body and a fifth anode lead connected to each other, the fifth anode lead extends along the second direction, and the compensation portion is connected to a side of the corresponding anode body away from the fifth anode lead.

11. The display panel according to claim 10, wherein: The plurality of data lines further include a plurality of third data lines arranged along the first direction, and one of the third data lines is electrically connected to a plurality of third sub-pixels arranged along the second direction; The compensation portion is disposed in a non-overlapping manner with at least one of the first data line, the third data line, and the second data line.

12. The display panel according to claim 10, wherein: The display panel further includes a plurality of high-potential lines arranged along the first direction, and two data lines are arranged between two adjacent high-potential lines; The overlapping area between the third sub-pixel and the high potential line is larger than the overlapping area between the second sub-pixel and the high potential line, and larger than the overlapping area between the first sub-pixel and the high potential line.

13. The display panel according to claim 12, wherein: A plurality of openings are provided on the high-potential line, and a first electrical connection segment and a second electrical connection segment are provided in the openings and arranged along the first direction. The first electrical connection segment is electrically connected to the third sub-pixel, and the second electrical connection segment is electrically connected to the second sub-pixel or the first sub-pixel.

14. The display panel according to claim 10, wherein: The first sub-pixel emits red light, the second sub-pixel emits blue light, and the third sub-pixel emits green light.

15. The display panel according to claim 10, wherein: The area of ​​the first sub-pixel is smaller than that of the second sub-pixel, and the area of ​​the third sub-pixel is smaller than or equal to that of the first sub-pixel.

16. The display panel according to any one of claims 1 to 8, characterized in that: In the 2kth row of the first pixel row, the first anode pattern includes a first anode body and a first anode lead connected to each other, the second anode pattern includes a second anode body and a second anode lead connected to each other, the first anode lead is electrically connected to the corresponding first data line, and the second anode lead is electrically connected to the corresponding second data line; In the 2k-1th row of the first pixel row, the first anode pattern includes a third anode body and a third anode lead connected to each other, the second anode pattern includes a fourth anode body and a fourth anode lead connected to each other, the third anode lead is electrically connected to the corresponding first data line, and the fourth anode lead is electrically connected to the corresponding second data line; The area of ​​the first anode lead is smaller than that of the third anode lead, and the area of ​​the second anode lead is smaller than that of the fourth anode lead; Wherein, the area of ​​the first anode body is greater than the area of ​​the third anode body, or / and the area of ​​the second anode body is greater than the area of ​​the fourth anode body.

17. A display device, characterized in that: The display device includes the display panel described in any one of items 1 to 16 above.

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