Display device

Abstract

A display device is provided. The display device includes a first pixel and a second pixel disposed at a display panel, the first pixel and the second pixel respectively including a plurality of sub-pixels, and each of the plurality of sub-pixels of the second pixel includes a plurality of lenses that refract light from an emission diode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0029386 filed on February 29, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device, and in particular to a display device capable of selectively controlling a viewing angle. Background Art

[0004] An organic light emitting diode (OLED), which is a self-luminous diode, includes an anode electrode, a cathode electrode, and an organic compound layer formed between the anode electrode and the cathode electrode. The organic compound layer is composed of a hole transport layer (HTL), an emission layer (EML), and an electron transport layer (ETL). When a driving voltage is applied to the anode electrode and the cathode electrode, holes that have passed through the hole transport layer (HTL) and electrons that have passed through the electron transport layer (ETL) move to the emission layer (EML) to form excitons. As a result, the emission layer (EML) generates visible light. Active matrix light emitting display devices include organic light emitting diodes (OLEDs) that emit light themselves, and are widely used due to their advantages such as fast response speed, emission efficiency, brightness, and viewing angle.

[0005] In the display device, pixels each including an organic light emitting diode are arranged in a matrix form, and the brightness of the pixels is adjusted according to the grayscale of video data.

[0006] In addition, with the advancement of modern technology, display devices are used in various ways to provide information to users. Display devices are included in various electronic devices that require high technology, confirm user input, and provide information in response to the confirmed input, as well as electronic signboards that only transmit visual information in one direction.

[0007] As described above, the viewing angle of the display device is not limited, but when necessary, it needs to be selectively limited to protect privacy, information, etc. Summary of the Invention

[0008] An object of the present disclosure is to provide a display device that can selectively limit a viewing angle.

[0009] Another object of the present disclosure is to provide a display device that can ensure improvements in its lifespan and power consumption.

[0010] Another object of the present disclosure is to provide a display device that can further enhance brightness and cut-off performance of viewing angles compared to existing films for limiting viewing angles.

[0011] Yet another object of the present disclosure is to provide a display device that can selectively limit viewing angles in both row and column directions while resolving disadvantages caused by separate driving.

[0012] The objects of the present disclosure are not limited to the above objects, and those skilled in the art may clearly understand other objects not mentioned above from the following description.

[0013] To achieve the above-mentioned purpose, a display device of one embodiment includes a first pixel and a second pixel arranged at a display panel, the first pixel and the second pixel respectively include multiple sub-pixels, and each of the multiple sub-pixels of the second pixel includes multiple lenses for refracting light from an emitting diode.

[0014] Additional details of exemplary embodiments are included in the detailed description and accompanying drawings.

[0015] According to the present disclosure, in a case where a high wiring density makes it impossible to perform individual driving in a display device using an oxide thin film transistor, the display device can selectively limit a viewing angle.

[0016] According to the present disclosure, high resolution can be achieved, and lifespan and power consumption can be improved.

[0017] The effects according to the present disclosure are not limited to those exemplified above, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 is a functional block diagram of a display device according to an embodiment;

[0020] Figure 2 is a plan view of a pixel of a display device according to an embodiment;

[0021] Figure 3 It is along Figure 2 A-A' cross-sectional view;

[0022] Figure 4 It is along Figure 2 BB' cross-sectional view;

[0023] Figure 5 is a diagram of an exemplary sub-pixel circuit that can be used as a sub-pixel circuit of a display device according to one embodiment;

[0024] Figure 6is a timing chart for describing an example of driving a display device according to one embodiment;

[0025] Figure 7 is a plan view showing an example of driving of a display device according to an embodiment;

[0026] Figure 8A and 8B is a timing diagram of an example of driving a display device according to an embodiment;

[0027] Figure 9 is a plan view showing an example of driving of a display device according to another embodiment;

[0028] Figure 10A and 10B is used to describe Figure 9 A timing diagram showing an example of driving of a display device;

[0029] Figure 11 is a plan view showing an example of driving of a display device according to still another embodiment; and

[0030] Figure 12A and 12B is used to describe Figure 11 A timing diagram showing an example of driving of a display device. DETAILED DESCRIPTION

[0031] By referring to the exemplary embodiments described in detail below and the accompanying drawings, the advantages and features of the present disclosure and the methods for achieving these advantages and features will be clear. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only as examples so that those skilled in the art can fully understand the content disclosed by the present disclosure and the scope of the present disclosure.

[0032] The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally represent the same elements. In addition, in the following description of the present disclosure, detailed explanations of known related arts may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including," "having," and "consisting of" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only." Unless expressly stated otherwise, any reference to the singular may include the plural.

[0033] Even if not explicitly stated, the components are interpreted as including the ordinary error range.

[0034] When terms such as "on," "over," "below," and "adjacent" are used to describe a positional relationship between two parts, one or more parts may be located between the two parts unless these terms are used together with the terms "immediately next to" or "directly."

[0035] When an element or layer is referred to as being “on” another element or layer, the other layer or element may be directly on or interposed between the other element.

[0036] Although the terms "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component to be mentioned below may be the second component in the technical concept of the present disclosure.

[0037] Throughout the specification, like reference numerals generally refer to like elements.

[0038] For convenience of description, the size and thickness of each component shown in the drawings are illustrated, and the present disclosure is not limited to the size and thickness of the components shown.

[0039] The features of the various embodiments of the present disclosure may be partially or completely attached or combined with each other, may be technically interlocked and operate in various ways, and the embodiments may be performed independently or in association with each other.

[0040] Hereinafter, a display device according to exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0041] Figure 1 is a functional block diagram of a display device according to an embodiment.

[0042] As a display device in an embodiment, an electroluminescent display device may be applied, which may include an organic light emitting diode display device, a quantum dot light emitting diode display device, or an inorganic light emitting diode display device.

[0043] refer to Figure 1 , the display device 100 may include a display panel PN, a data driving circuit DD, a gate driving circuit GD, and a timing controller T-con.

[0044] In an embodiment, the display panel PN may generate an image to be provided to a user. For example, the display panel PN may generate and display an image to be provided to a user through a plurality of pixels PX provided with each pixel circuit.

[0045] The data driving circuit DD, the gate driving circuit GD, and the timing controller T-con may provide signals for the operation of each pixel PX through signal lines. The signal lines may include, for example, data lines DL and gate lines GL.

[0046] In some cases, the display device 100 may further include a power supply unit. In this case, signals for operating the pixels PX may be provided via a power line connecting the power supply unit and the display panel PN. In some embodiments, the power supply unit may supply power to the data drive circuit DD and the gate drive circuit GD. The data drive circuit DD and the gate drive circuit GD may be driven based on the power supplied by the power supply unit.

[0047] In an example, the data driving circuit DD may provide a data signal to each pixel PX through a data line DL, the gate driving circuit GD may provide a gate signal to each pixel PX through a gate line GL, and the power supply unit may provide a power voltage to each pixel PX through a power voltage supply line.

[0048] The timing controller T-con can control the data driving circuit DD and the gate driving circuit GD. For example, the timing controller T-con can realign the digital video data input from the outside according to the resolution of the display panel PN and provide the signal to the data driving circuit DD.

[0049] The data driving circuit DD may convert digital video data input from the timing controller T-con into analog data voltages based on a data control signal and provide the analog data voltages to a plurality of data lines.

[0050] The gate drive circuit GD can generate a scan signal and an emission signal (or emission control signal) based on the gate control signal. The gate drive circuit GD may include a scan driver and an emission signal driver. The scan driver may generate a scan signal in a row-continuous manner and provide the scan signal to the scan line to drive at least one or more scan lines connected to each pixel row. The emission signal driver may generate an emission signal in a row-continuous manner and provide the emission signal to the emission signal line to drive at least one or more emission signal lines connected to each pixel row.

[0051] In some embodiments, the gate driving circuit GD may be provided at the display panel PN based on a gate-in-panel (GIP) method. For example, the gate driving circuit GD may be divided into a plurality of gate driving circuits and respectively provided on at least two side surfaces of the display panel PN.

[0052] The display area of ​​the display panel PN may include a plurality of pixels PX. In a pixel PX, a plurality of data lines DL and a plurality of gate lines GL intersect each other, and may include sub-pixels arranged in each intersection area. Each sub-pixel included in a pixel PX may emit light of a different color. For example, a pixel PX may represent blue, red, and green by using three sub-pixels, but is not limited thereto. In some cases, a pixel PX may further include sub-pixels for further representing a specific color (e.g., white).

[0053] In the pixel PX, a region reflecting blue may be referred to as a blue sub-pixel, a region reflecting red may be referred to as a red sub-pixel, and a region reflecting green may be referred to as a green sub-pixel.

[0054] In an embodiment, the plurality of pixels PX may include a plurality of first pixels and a plurality of second pixels. The first pixels have a wide first viewing angle, and the second pixels have a limited second viewing angle. The first pixels and the second pixels each include a plurality of sub-pixels. The sub-pixels of the second pixel may include a lens that limits the viewing angle. In addition, the term lens in this disclosure may be used for ease of description and may also be defined as an optical component.

[0055] The non-display area may be provided along the periphery of the display area. Various components for driving the pixel circuit provided at the pixel PX may be provided in the non-display area. For example, at least a portion of the gate drive circuit GD may be provided in the non-display area. The non-display area may also be referred to as a frame area.

[0056] Figure 2 FIG. 1 is a plan view of a pixel of a display device according to an embodiment. Figure 3 It is along Figure 2 AA' cross-sectional view. Figure 4 It is along Figure 2 BB' cross-sectional view. Figure 2 A planar surface of a first pixel PX1 and a second pixel PX2 constituting a plurality of pixels PX of the display device 100 is shown. Figure 3 shows a cross section of the first sub-pixel SP1 of the first pixel PX1, and Figure 4 A cross section of the first subpixel SP1 of the second pixel PX2 is shown.

[0057] exist Figure 2 , only the first anode electrodes ANO1_1, ANO1_2, ANO1_3, the second electrodes ANO2_1, ANO2_2, ANO2_3, the light shielding pattern 180 and the lenses 161, 162, 163 of the first to third subpixels SP1, SP2, SP3 of each of the first pixel PX1 and the second pixel PX2 constituting the display device 100 are shown.

[0058] refer to Figure 2 , the first pixel PX1 and the second pixel PX2 can be arranged to be adjacent to each other in the row direction (X-axis direction), but are not limited thereto. The first pixel PX1 and the second pixel PX2 can also be arranged to be adjacent to each other in the column direction (Y-axis direction). The first pixel PX1 and the second pixel PX2 constitute a repeated pixel unit. The repeated pixel unit is arranged in a continuous manner in the row direction (X-axis direction) and the column direction (Y-axis direction). That is, the first pixel PX1 and the second pixel PX2 can be alternately arranged in the row direction (X-axis direction).

[0059] The first pixel PX1 and the second pixel PX2 provide different viewing angles. For example, the first pixel PX1 emits light without limiting the viewing angle, but the second pixel PX2 provides light within a specific range to limit the viewing angle. In this case, the first pixel PX1 and the second pixel PX2 can be operated independently. For example, only the first pixel PX1 can be driven to implement a wide field of view mode that provides a wide viewing angle, and only the second pixel PX2 can be driven to implement a narrow field of view mode that provides a limited viewing angle. The operation method of the first pixel PX1 and the second pixel PX2 is described below.

[0060] Each of the first and second pixels PX1 and PX2 may include first to third subpixels SP1, SP2, and SP3, and the first subpixel SP1 may be a green subpixel, the second subpixel SP2 may be a red subpixel, and the third subpixel SP3 may be a blue subpixel.

[0061] The first to third sub-pixels SP1, SP2, and SP3 may have polygonal shapes, respectively. At this time, the first to third sub-pixels SP1, SP2, and SP3 may have different shapes, but are not limited thereto in the present disclosure and may have various shapes.

[0062] The surface areas of the first to third sub-pixels SP1, SP2, and SP3 can be determined by considering the lifetime and emission efficiency of the emission diodes ED1 and ED2 provided in each sub-pixel SP1, SP2, and SP3. For example, if the red emission diode has the longest lifetime, the surface area of ​​the second sub-pixel SP2 can be smaller than the surface area of ​​each of the first and third sub-pixels SP1 and SP3 to ensure a consistent lifetime, but the present invention is not limited thereto. The ratio of the surface areas of the first to third sub-pixels SP1, SP2, and SP3 can be different.

[0063] In the following, refer to Figure 3 The structure of the first pixel PX1 is described.

[0064] Reference together Figure 2 and 3The display device 100 of the embodiment may include a substrate 111 , a first thin film transistor TFT1 , a second thin film transistor TFT2 , a first emission diode ED1 , an encapsulation portion 130 , a touch sensing portion 150 , and a lens protection layer 170 .

[0065] Figure 3 is a cross-sectional view showing two thin film transistors TFT1 and TFT2 and a capacitor CST. The two thin film transistors TFT1 and TFT2 include either a switching thin film transistor or a driving transistor made of a polycrystalline semiconductor material, or an oxide thin film transistor made of an oxide semiconductor material. In this case, the thin film transistor made of a polycrystalline semiconductor material is referred to as the polycrystalline thin film transistor TFT1, and the thin film transistor made of an oxide semiconductor material is referred to as the oxide thin film transistor TFT2.

[0066] exist Figure 3 In FIG, the polycrystalline thin film transistor TFT1 is an emission switching thin film transistor connected to the first emission diode ED1, and the oxide thin film transistor TFT2 is any one switching thin film transistor connected to the capacitor CST.

[0067] The first pixel PX1 includes a pixel driving circuit that provides a driving current to the first emitting diode ED1. The pixel driving circuit is provided on the substrate 111, and the first emitting diode ED1 is provided on the pixel driving circuit. In addition, an encapsulation portion 130 is provided on the first emitting diode ED1. The encapsulation portion 130 protects the first emitting diode ED1.

[0068] The pixel driving circuit may refer to a pixel array portion including a driving thin film transistor, a switching thin film transistor, and a capacitor. Furthermore, the first emission diode ED1 may refer to an array portion for emitting light, which includes a first anode electrode ANO1_1, a cathode electrode CAT, and a first emission layer EL1 disposed between the first anode electrode ANO1_1 and the cathode electrode CAT.

[0069] In one embodiment, the driver thin film transistor and at least one switch thin film transistor use oxide semiconductor materials as their active layers. Thin film transistors using oxide semiconductor materials as their active layers can better block leakage current and, compared to thin film transistors using polycrystalline semiconductor materials as their active layers, can incur lower manufacturing costs. Therefore, one embodiment of the pixel driver circuit includes a driver thin film transistor and at least one switch thin film transistor using oxide semiconductor materials, thereby reducing power consumption and manufacturing costs.

[0070] All thin film transistors constituting the pixel driving circuit may be implemented using an oxide semiconductor material, or part of the switching thin film transistors may be implemented using only an oxide semiconductor material.

[0071] However, thin film transistors using oxide semiconductor materials are very unreliable, and thin film transistors using polycrystalline semiconductor materials ensure fast operation speed and excellent reliability. Therefore, in one embodiment, both switching thin film transistors using oxide semiconductor materials and switching thin film transistors using polycrystalline semiconductor materials are included.

[0072] The substrate 111 may include an insulating material. The substrate 111 may include a transparent material. For example, the substrate 111 may include glass or plastic. In addition, the substrate 111 may have a multilayer structure in which organic films and inorganic films are alternately stacked. For example, the substrate 111 may be formed in a manner in which films of an organic material such as polyimide and films of an inorganic material such as silicon dioxide (SiO2) are alternately stacked.

[0073] A lower buffer layer 112a is formed on the substrate 111. The lower buffer layer 112a serves to block moisture that may penetrate from the outside, and the lower buffer layer 112a may be used by stacking a silicon dioxide (SiO2) layer in multiple layers, etc. An auxiliary buffer layer 112b may be further provided on the lower buffer layer 112a to protect the light emitting diode from moisture penetration.

[0074] A polycrystalline thin film transistor TFT1 is formed on a substrate 111. The polycrystalline thin film transistor TFT1 may use a polycrystalline semiconductor as an active layer. The polycrystalline thin film transistor TFT1 includes a first active layer ACT1, a first gate electrode GE1, a first source electrode SD1, and a first drain electrode SD2. The first active layer ACT1 includes a channel through which electrons or holes move.

[0075] The first active layer ACT1 includes a first channel region, a first source region disposed at one side of the first channel region, and a first drain region disposed at the other side of the first active layer ACT1, wherein the first channel region is between the first active layer ACT1 and the first source region.

[0076] The first source region and the first drain region are regions where a predetermined concentration of impurity ions classified as Group 5 or Group 3 (e.g., phosphorus (P) or boron (B)) is doped into a pure polycrystalline semiconductor material to make it conductive. The first channel region is used to maintain the pure state of the polycrystalline semiconductor material and provide a path for electrons or holes to move.

[0077] In addition, the polycrystalline thin film transistor TFT1 includes a first gate electrode GE1 overlapping with the first channel region of the first active layer ACT1. A first gate insulating layer 113 is provided between the first gate electrode GE1 and the first active layer ACT1. The first gate insulating layer 113 may be formed by stacking a silicon oxide (SiO2) film, a silicon nitride (SiN) film, and a plurality of other materials in a single layer or a multilayer. x) membrane or the like.

[0078] In one embodiment, the polycrystalline thin-film transistor TFT1 has a top-gate structure in which the first gate electrode GE1 is disposed on the first active layer ACT1. Therefore, the first electrode CST1 included in the capacitor CST and the light shielding layer LS included in the oxide thin-film transistor TFT2 can be formed of the same material as the first gate electrode GE1. The first gate electrode GE1, the first electrode CST1, and the light shielding layer LS are formed in a single mask process, resulting in a reduction in the number of mask processes.

[0079] The first gate electrode GE1 may be made of a metal material. For example, the first gate electrode GE1 may have a single-layer structure or a multi-layer structure, and may be composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited thereto.

[0080] The first interlayer insulating layer 114 is provided on the first gate electrode GE1. The first interlayer insulating layer 114 may be made of silicon oxide (SiO2), silicon nitride (SiN x ) etc. to implement.

[0081] The display device 100 may further include an upper buffer layer 115, a second gate insulating layer 116, and a second interlayer insulating layer 117 sequentially disposed on the first interlayer insulating layer 114, and the polycrystalline thin film transistor TFT1 includes a first source electrode SD1 and a first drain electrode SD2 formed on the second interlayer insulating layer 117 and connected to the first source region and the first drain region, respectively.

[0082] The first source electrode SD1 and the first drain electrode SD2 may have a single-layer structure or a multi-layer structure, which is composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof, but is not limited thereto.

[0083] The upper buffer layer 115 separates the second active layer ACT2 of the oxide thin film transistor TFT2 implemented using an oxide semiconductor material from the first active layer ACT1 implemented using a polycrystalline semiconductor material, and provides a base for forming the second active layer ACT2 .

[0084] The second gate insulating layer 116 covers the second active layer ACT2 of the oxide thin film transistor TFT2. The second gate insulating layer 116 is formed on the second active layer ACT2 implemented using an oxide semiconductor material and is implemented as an inorganic film. For example, the second gate insulating layer 116 may be silicon oxide (SiO2), silicon nitride (SiN x )wait.

[0085] The second gate electrode GE2 is made of a metal material. For example, the second gate electrode GE2 may have a single-layer structure or a multi-layer structure, and may be composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited thereto.

[0086] In addition, the oxide thin film transistor TFT2 includes a second active layer ACT2 formed on the upper buffer layer 115 and implemented using an oxide semiconductor material, a second gate electrode GE2 disposed on the second gate insulating layer 116 , and a second source electrode SD3 and a second drain electrode SD4 disposed on the second interlayer insulating layer 117 .

[0087] The second active layer ACT2 includes a pure second channel region that is implemented using an oxide semiconductor material and is not doped with impurities, and a second source region and a second drain region that are doped with impurities and become conductive.

[0088] The oxide thin film transistor TFT2 further includes a light shielding layer LS disposed below the upper buffer layer 115 and overlapping the second active layer ACT2. The light shielding layer LS can block light input to the active layer 401 and ensure the reliability of the oxide thin film transistor TFT2. The light shielding layer LS can be formed of the same material as the first gate electrode GE1 and formed on the upper surface of the first gate insulating layer 113. The light shielding layer LS can be electrically connected to the second gate electrode GE2 to form a dual gate.

[0089] The second source electrode SD3 and the second drain electrode SD4 are simultaneously formed of the same material on the second interlayer insulating layer 117 along with the first source electrode SD1 and the first drain electrode SD2 , resulting in a reduction in the number of mask processes.

[0090] In addition, a second electrode CST2 is provided on the first interlayer insulating layer 114 to overlap with the first electrode CST1 to implement a capacitor CST. For example, the second electrode CST2 may have a single-layer structure or a multi-layer structure, and may be composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0091] The capacitor CST stores a data voltage supplied via the data line DL for a certain period of time and then supplies the data voltage to the first emitting diode ED1. The capacitor CST includes two electrodes corresponding to each other and a dielectric material disposed between the two electrodes. A first interlayer insulating layer 114 is disposed between the first electrode CST1 and the second electrode CST2.

[0092] The first electrode CST1 or the second electrode CST2 of the capacitor CST may be electrically connected to the second source electrode SD3 or the second drain electrode SD4 of the oxide thin film transistor TFT2 , but is not limited thereto, and the connection relationship of the capacitor CST may vary depending on the pixel driving circuit.

[0093] In addition, the first planarization layer 118 and the second planarization layer 119 are continuously provided on the pixel driving circuit to planarize the upper end of the pixel driving circuit. The first planarization layer 118 and the second planarization layer 119 may be organic material films such as polyimide or acrylic resin.

[0094] The first emitting diode ED1 is formed on the second planarization layer 119 .

[0095] The first emission diode ED1 includes a first anode electrode ANO1_1, a cathode electrode CAT, and a first emission layer EL1 disposed between the first anode electrode ANO1_1 and the cathode electrode CAT. When the first emission diode ED1 is implemented as a pixel driving circuit that generally uses a low potential voltage connected to the cathode electrode CAT, the first anode electrode ANO1_1 is provided as a separate electrode for each sub-pixel. If the first emission diode ED1 is implemented as a pixel driving circuit that generally uses a high potential voltage, the cathode electrode CAT may be provided as a separate electrode for each sub-pixel.

[0096] The first emitting diode ED1 is electrically connected to the driving element through the intermediate electrode CNE provided on the first planarization layer 118. Specifically, the first anode electrode ANO1_1 of the first emitting diode ED1 and the first source electrode SD1 of the polycrystalline thin film transistor TFT1 constituting the pixel driving circuit may be connected to each other through the intermediate electrode CNE.

[0097] The first anode electrode ANO1_1 is connected to the intermediate electrode CNE exposed through a contact hole passing through the second planarization layer 119. In addition, the intermediate electrode CNE is connected to the first source electrode SD1 exposed through a contact hole passing through the first planarization layer 118.

[0098] The intermediate electrode CNE serves as a medium for connecting the first source electrode SD1 and the first anode electrode ANO1_1 . The intermediate electrode CNE may be formed of a conductive material such as copper (Cu), silver (Ag), molybdenum (Mo), and titanium (Ti).

[0099] The first anode electrode ANO1_1 may have a multilayer structure including a transparent conductive film and an opaque conductive film with high reflection efficiency. The transparent conductive film may be made of a material with a relatively high work function (e.g., indium tin oxide (ITO) or indium zinc oxide (IZO)), and the opaque conductive film may have a single-layer structure or a multilayer structure including aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or an alloy thereof. For example, the first anode electrode ANO1_1 may have a structure in which a transparent conductive film, an opaque conductive film, and a transparent conductive film are stacked continuously, or a structure in which a transparent conductive film and an opaque conductive film are stacked continuously.

[0100] The first emission layer EL1 is formed in such a manner that a hole-related layer, an organic emission layer, and an electron-related layer are stacked on the first anode electrode ANO1_1 in sequence or in reverse order.

[0101] The bank layer 120 may be a pixel-defining film that exposes the first anode electrode ANO1_1 of each sub-pixel and defines the emission area EA1. The bank layer 120 may be formed of an opaque material (e.g., a black material) to prevent light interference between adjacent sub-pixels. In this case, the bank layer 120 includes a light-shielding material made of at least one of a color pigment, organic black, and carbon. Spacers may be further provided on the bank layer 120.

[0102] The cathode electrode CAT is formed on the upper surface and side surfaces of the first emission layer EL1, facing the first anode electrode ANO1_1, wherein the first emission layer EL1 is between the cathode electrode CAT and the first anode electrode ANO1_1. The cathode electrode CAT can be integrally formed in the display area. When the cathode electrode CAT is applied to a top-emission organic light-emitting display device, the cathode electrode CAT can be composed of a transparent conductive material film such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0103] On the cathode electrode CAT, an encapsulation portion 130 is substantially formed on the front surface of the substrate 111. The encapsulation portion 130 prevents moisture or oxygen from penetrating into the light emitting diode from the outside.

[0104] The encapsulation part 130 may have a multi-layer structure. For example, the encapsulation part 130 may include a first encapsulation layer 131, a second encapsulation layer 132, and a third encapsulation layer 133 stacked in sequence, but is not limited thereto.

[0105] The first encapsulation layer 131 may be provided on the first emitting diode ED1 and inhibit the penetration of moisture or oxygen. The first encapsulation layer 131 may be made of an inorganic material, such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiN x Oy ) or aluminum oxide (Al y O z ), etc., but not limited to these.

[0106] The second encapsulation layer 132 is provided on the first encapsulation layer 131 and flattens its surface. In addition, the second encapsulation layer 132 can cover foreign matter or particles that may be generated during manufacturing. The second encapsulation layer 132 can be made of an organic material, such as silicon oxycarbide (SiO x C z ), acryl or epoxy resin, etc., but not limited thereto.

[0107] The third encapsulation layer 133 may be provided on the second encapsulation layer 132 and, similar to the first encapsulation layer 131, may suppress the penetration of moisture or oxygen. At this time, the third encapsulation layer 133 and the first encapsulation layer 131 may be formed to seal the second encapsulation layer 132. Therefore, the third encapsulation layer 133 may effectively reduce the penetration of moisture or oxygen into the emission diode ED1. The third encapsulation layer 133 may be made of an inorganic material, such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiN x O y ) or aluminum oxide (Al y O z ), etc., but not limited to these.

[0108] The touch buffer layer 140 may be provided on the encapsulation portion 130. The touch buffer layer 140 may include an inorganic insulating material, such as silicon oxide (SiO x ) and silicon nitride (SiN x ), and has a multi-layer structure.

[0109] The touch sensing portion 150 may be provided on the touch buffer layer 140. The touch sensing portion 150 may be provided in the display area including the first emitting diode ED1 and sense touch input. The touch sensing portion 150 may sense external touch information using a user's finger or a stylus. The touch sensing portion 150 includes a first inorganic insulating layer 151, a second inorganic insulating layer 155, an organic material layer 153, a bridge electrode 154, and a touch electrode 152.

[0110] The bridge electrode 154 may be provided on the touch buffer layer 140. The bridge electrode 154 may be an element for connecting the touch electrodes 152 that are disconnected at points where the touch electrodes 152 extending in the row direction and the touch electrodes 152 extending in the column direction cross each other.

[0111] The first inorganic insulating layer 151 may be provided on the bridge electrode 154. The first inorganic insulating layer 151 may cover the upper surface and the side surface of the bridge electrode 154. The first inorganic insulating layer 151 may be made of an inorganic material. For example, the inorganic insulating layer 151 may be made of a silicon nitride (SiN x ), silicon oxynitride (SiON) and other inorganic materials, but not limited thereto.

[0112] The organic material layer 153 may be disposed on the first inorganic insulating layer 151. The organic material layer 153 may ensure a gap between the first inorganic insulating layer 151 and the elements disposed thereon and may be made of an organic insulating material. For example, the organic material layer 153 may be made of photo acryl or benzocyclobutene (BCB), polyimide (PI), or polyamide (PA), but is not limited thereto.

[0113] The touch electrodes 152 may be provided on the organic material layer 153. The touch electrodes 152 may be provided in a planar shape along an upper surface of the organic material layer 153. The touch electrodes 152 may be provided in a row direction and a column direction.

[0114] The second inorganic insulating layer 155 may be provided on the touch electrode 152. The second inorganic insulating layer 155 may cover the upper surface and the side surface of the touch electrode 152. The second inorganic insulating layer 155 may be made of an inorganic material. For example, the second inorganic insulating layer 155 may be made of a silicon nitride (SiN x ), silicon oxynitride (SiON) and other inorganic materials, but not limited thereto.

[0115] Although not in Figure 2 and 3 , but in the non-display area, a wiring line connecting the touch electrode 152 provided at the outermost edge of the display area to the touch panel provided in the non-display area may be provided.

[0116] refer to Figure 3 The lens protection layer 170 is provided on the touch sensing portion 150. The lens protection layer 170 protects the lenses 161, 162, and 163 formed at the second pixel PX2 described below. The lens protection layer 170 may be made of an organic insulating material and have a flat upper surface. In addition, the refractive index of the lens protection layer 170 may be lower than the refractive index of the lens.

[0117] For example, the lens protection layer 170 may be made of photo acryl, benzocyclobutene (BCB), polyimide (PI), or polyamide (PA), but is not limited thereto.

[0118] In the following, refer to Figure 4 The structure of the second pixel PX2 is described.

[0119] Reference together Figure 2 and 4 The display device 100 of the embodiment may include a substrate 111, a first thin film transistor TFT1, a second thin film transistor TFT2, a second emitting diode ED2, an encapsulation portion 130, a touch sensing portion 150, a light shielding pattern 180, lenses 161, 162, 163, and a lens protection layer 170. The structure of the second pixel PX2 is the same as that of the first pixel PX2, except that the second pixel PX2 also includes the light shielding pattern 180 and the lenses 161, 162, 163. Figure 3 The structures of the first pixels PX1 shown are substantially the same, and therefore, descriptions of repeated elements are omitted.

[0120] refer to Figure 4 , a light-shielding pattern 180 is provided on the first inorganic insulating layer 151. The light-shielding pattern 180 may be formed to correspond to the first to third sub-pixels SP1, SP2, and SP3 adjacent to each other, or may be provided to overlap with the bridge electrode 154. In addition, the light-shielding pattern 180 may be provided in the emission area EA2 of the second emission diode ED2 to form a plurality of openings 185. Therefore, the lenses 161, 162, and 163 described below may be provided to correspond to the plurality of openings 185 formed by the light-shielding pattern 180.

[0121] The light shielding pattern 180 may be a black matrix and made of black resin, chromium oxide, or the like.

[0122] However, since the bridge electrode 154 and the touch electrode 152 perform a light shielding function in the second pixel PX2 , the light shielding pattern 180 may be omitted if necessary.

[0123] A plurality of lenses 161 , 162 , 163 may be placed on the touch sensing portion 150 .

[0124] Lenses 161, 162, 163 may be respectively disposed in the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 of the second pixel PX2. Specifically, lenses 161, 162, 163 may be disposed to correspond to the plurality of openings 185 formed by the light shielding pattern 180 at the second pixel PX2.

[0125] Light generated by the second emitting diode ED2 of the second pixel PX2 may be emitted through a plurality of corresponding lenses 161, 162, 163. The lenses 161, 162, 163 may limit the direction of light passing through the lenses 161, 162, 163 to the first direction and / or the second direction.

[0126] For example, lenses 161, 162, and 163, which are hemispherical lenses, may have a semicircular cross-section on a flat surface. In this case, the direction of light emitted from the emitting diode ED2 of the first subpixel SP1 of the second pixel PX2 can be limited to a first direction and a second direction. For example, the content provided by the lenses 161, 162, and 163 of the second pixel PX2 may not be shared with people around the user. That is, when an image is displayed at the second pixel PX2, a narrow field of view mode providing a limited viewing angle can be achieved.

[0127] refer to Figure 2 The multiple lenses 161, 162, and 163 include a first lens 161 corresponding to the first subpixel SP1 of the second pixel PX2, a second lens 162 disposed at the second subpixel SP2 of the second pixel PX2, and a third lens 163 disposed at the third subpixel SP3 of the second pixel PX2. The first lens 161, the second lens 162, and the third lens 163 may be disposed so as to overlap with the emission area EA2 of each of the first to third subpixels SP1, SP2, and SP3, respectively. In this case, the size of the lenses 161, 162, and 163 may be smaller than the size of the emission area EA2. Furthermore, the first lens 161, the second lens 162, and the third lens 163 may be disposed so as to correspond to the opening 185 formed by the light-shielding pattern 180 disposed at the first to third subpixels SP1, SP2, and SP3, respectively. In this case, the size of the lenses 161, 162, and 163 may be larger than the size of the opening 185. For example, the planar shape of the lenses 161, 162, and 163 and the planar shape of the opening 185 may be concentric circles. Therefore, the efficiency of light emitted from the opening 185 of the light shielding pattern 180 may be improved.

[0128] In addition, the sizes of the first lens 161, the second lens 162, and the third lens 163 may be the same. In the case where the sizes of the first lens 161, the second lens 162, and the third lens 163 are the same, the light emitted from each of the first to third sub-pixels SP1, SP2, and SP3 is refracted at the same angle and exhibits a consistent viewing angle. Figure 2 Since the surface areas of the emission regions of the first to third sub-pixels SP1, SP2, and SP3 in the second pixel PX2 are different, the number of first lenses 161, second lenses 162, and third lenses 163 provided in the first to third sub-pixels SP1, SP2, and SP3, respectively, may be different. For example, the number of third lenses 163 provided in the third sub-pixel SP3, which is a blue sub-pixel, may be greater than the number of first lenses 161 provided in the first sub-pixel SP1, which is a green sub-pixel, and the number of second lenses 162 provided in the second sub-pixel SP2, which is a red sub-pixel.

[0129] At the second pixel PX2, the distance between lenses 161, 162, and 163 can be 20 μm to 40 μm. When the distance between lenses 161, 162, and 163 falls within the above range, viewing angle cutoff performance can be improved. Specifically, when driving the second pixel PX2 in narrow field of view mode, light emitted from the second emitting diode ED2 can be significantly reduced to 3% or less relative to the front surface of the display device when exceeding a specific viewing angle. Furthermore, if the distance between lenses 161, 162, and 163 in sub-pixels emitting light of the same color is less than 20 μm, viewing angle cutoff performance may deteriorate. For example, if the luminance relative to the front surface of the display device is 3% or greater at a viewing angle of 30°, viewing angle cutoff performance may be insufficient. Furthermore, if the distance between lenses 161, 162, and 163 in two adjacent sub-pixels emitting light of different colors is less than 20 μm, color mixing may occur in the other adjacent sub-pixel, and performance of the display device may deteriorate. Furthermore, in the case where the distance between the lenses 161 , 162 , 163 is greater than 20 μm, it may be difficult to sufficiently secure the emission area of ​​the sub-pixel, and it may be difficult to achieve high resolution of the display device.

[0130] Figure 3 and 4 is a cross-sectional view of the first subpixel SP1, and the structures of the second and third subpixels SP2 and SP3 are the same as that of the first subpixel SP1 except for the size of the emission area and the anode electrodes being connected to the pixel circuits in the rows where the corresponding pixels are provided.

[0131] A display device according to one embodiment includes a first pixel that provides a wide viewing angle and a second pixel that provides a narrow viewing angle. Each of the first to third subpixels of the first pixel does not have a separate lens, but each of the first to third subpixels of the second pixel includes a lens that limits the viewing angle. Therefore, wide and narrow viewing angles can be achieved based on the selective driving of the first and second pixels. For example, when only the first pixel is driven, a wide field of view mode that provides a wide viewing angle can be achieved, and when only the second pixel is driven, a narrow field of view mode that provides a limited viewing angle can be achieved.

[0132] The display device of one embodiment can use oxide thin-film transistors and polysilicon thin-film transistors together. In this case, due to the high line density in the circuit, it is difficult to set additional lines. In the case of implementing the viewing angle limitation mode based on separate driving, the pixel aperture ratio is reduced. However, in the display device of one embodiment, based on selectively providing data voltages to a first pixel without a lens and a second pixel with a lens, a wide field of view mode and a narrow field of view mode can be selectively implemented without separate driving. Therefore, the aperture ratio and resolution of the pixel can be improved, thereby ensuring the improvement of the pixel life and power consumption.

[0133] Hereinafter, the configuration and driving method of the pixel circuit of a plurality of sub-pixels are described in detail.

[0134] The switching element constituting each sub-pixel may be implemented as a transistor of an n-type or p-type MOSFET structure. In the following embodiments, a p-type transistor is described as an example, but the invention is not limited thereto.

[0135] A transistor is a three-electrode device consisting of a gate electrode, a source electrode, and a drain electrode. The source electrode is the electrode that supplies carriers to the transistor. Carriers in a transistor begin to flow out of the source electrode. The drain electrode is the electrode from which carriers exit the transistor. That is, in a MOSFET, carriers flow from the source electrode to the drain electrode. In the case of an n-type MOSFET (NMOS), the carriers are electrons, and the voltage of the source electrode can be lower than the voltage of the drain electrode, allowing electrons to flow from the source electrode to the drain electrode. Since electrons flow from the source electrode to the drain electrode in an n-type MOSFET, current flows from the drain electrode to the source electrode. In a p-type MOSFET (PMOS), the carriers are holes, and the voltage of the source electrode can be higher than the voltage of the drain electrode, allowing holes to flow from the source electrode to the drain electrode. Since holes flow from the source electrode to the drain electrode in a p-type MOSFET, current flows from the source electrode to the drain electrode. It is worth noting that the source and drain electrodes of a MOSFET are not fixed. For example, the source electrode and the drain electrode of the MOSFET may be changed according to the supplied voltage.In the following embodiments, the subject matter of the present disclosure should not be limited by the source electrode and the drain electrode of the transistor.

[0136] Figure 5 is a diagram of an exemplary sub-pixel circuit that can be used as a sub-pixel circuit of a display device of one embodiment.

[0137] Figure 5 The pixel circuit is shown as an example for description, and the pixel circuit is not limited as long as the EM signal EM(n) is provided to control the emission of the emission diode ED. For example, the pixel circuit may include an additional scanning signal, a switching thin film transistor connected thereto, and a switching thin film transistor to which an additional initialization voltage is provided. In addition, in the pixel circuit, the connection relationship of the switching element or the connection position of the capacitor may be changed. In the following, for the convenience of description, the pixel circuit having Figure 5 A pixel circuit structure of a display device is described.

[0138] refer to Figure 5 , each of the plurality of sub-pixels may include a pixel circuit including a driving transistor DT and an emission diode ED connected to the pixel circuit.

[0139] The pixel circuit can control the driving current flowing in the emission diode ED to drive the emission diode ED. The pixel circuit may include a driving transistor DT, first to seventh transistors T1-T7, and a capacitor Cst. Each of the transistors DT, T1-T7 may include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other of the first electrode and the second electrode may be a drain electrode.

[0140] Each of the transistors DT, T1-T7 can be a P-type thin film transistor or an N-type thin film transistor. Figure 5 In the embodiment of the present invention, the first transistor T1 and the seventh transistor T7 are N-type thin film transistors, and the remaining transistors DT and T2-T6 are P-type thin film transistors, but the present invention is not limited thereto. In some embodiments, all or part of the transistors DT and T1-T7 may be P-type thin film transistors or N-type thin film transistors. In addition, the N-type thin film transistor may be an oxide thin film transistor, and the P-type thin film transistor may be a polysilicon thin film transistor.

[0141] In the following, it is assumed that the first transistor T1 and the seventh transistor T7 are N-type thin film transistors, and the remaining transistors DT, T2-T6 are P-type thin film transistors. The first transistor T1 and the seventh transistor T7 are turned on by a high-level voltage, and the remaining transistors DT, T2-T6 are turned on by a low-level voltage.

[0142] In one example of configuring a pixel circuit, the first transistor T1 may be used as a compensation transistor, the second transistor T2 may be used as a data supply transistor, the third transistor T3 and the fourth transistor T4 may be used as emission control transistors, the fifth transistor T5 may be used as a bias transistor, and the sixth transistor T6 and the seventh transistor T7 may be used as initialization transistors.

[0143] The emission diode ED may include an anode electrode and a cathode electrode. The anode electrode of the emission diode ED may be connected to the fifth node N5, and the cathode electrode may be connected to the low potential driving voltage EVSS.

[0144] The driving transistor DT may include a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a gate electrode connected to the first node N1. The driving transistor DT may provide a driving current Id to the emission diode ED based on the voltage of the first node N1 (or a data voltage stored in the capacitor Cst described below).

[0145] The first transistor T1 may include a first electrode connected to the first node N1, a second electrode connected to the third node N3, and a gate electrode that receives a first scan signal SC1(n). The first transistor T1 is turned on in response to the first scan signal SC1(n), and is diode-connected between the data voltage Vdata (the first node N1) and the third node N3 to sample a threshold voltage Vth of the drive transistor DT. The first transistor T1 may be a compensation transistor.

[0146] The capacitor Cst may be connected or formed between the first node N1 and the fourth node N4. The capacitor Cst may store or maintain the supplied high-potential driving voltage EVDD.

[0147] The second transistor T2 may include a first electrode connected to the data line DL (or receiving the data voltage Vdata), a second electrode connected to the second node N2, and a gate electrode receiving the second scan signal SC2(n). The second transistor T2 may be turned on in response to the second scan signal SC2(n) and deliver the data voltage Vdata to the second node N2. The second transistor T2 may be a data supply transistor.

[0148] The third transistor T3 and the fourth transistor T4 (or the first and second emission control transistors) may be connected between the high potential driving voltage EVDD and the emission diode ED and form a current flow path in which the driving current ID generated by the driving transistor DT flows.

[0149] The third transistor T3 may include a first electrode connected to the fourth node N4 and receiving the high potential driving voltage EVDD, a second electrode connected to the second node N2, and a gate electrode receiving the emission control signal EM(n).

[0150] The fourth transistor T4 may include a first electrode connected to the third node N3, a second electrode connected to the fifth node N5 (or the anode electrode of the emission diode ED), and a gate electrode receiving the emission control signal EM(n).

[0151] The third transistor T3 and the fourth transistor T4 may be turned on in response to the emission control signal EM(n), and at this time, the driving current Id may be supplied to the emission diode ED, and the emission diode ED may emit light having brightness corresponding to the driving current Id.

[0152] The fifth transistor T5 may include a first electrode receiving the bias voltage Vobs, a second electrode connected to the second node N2, and a gate electrode receiving the third scan signal SC3(n). The fifth transistor T5 may be a bias transistor.

[0153] The sixth transistor T6 may include a first electrode receiving the first initialization voltage Var, a second electrode connected to the fifth node N5, and a gate electrode receiving the third scan signal SC3(n).

[0154] The sixth transistor T6 may be turned on in response to the third scan signal SC3(n) before the emission diode ED emits light (or after the emission diode ED emits light) and initialize the anode electrode (or pixel electrode) of the emission diode ED using the first initialization voltage Var. The emission diode ED may have a parasitic capacitor formed between the anode electrode and the cathode electrode. The parasitic capacitor may be charged when the emission diode ED emits light, causing the anode electrode of the emission diode ED to have a specific voltage. Therefore, the first initialization voltage Var may be supplied to the anode electrode of the emission diode ED via the sixth transistor T6 to initialize the amount of charge accumulated in the emission diode ED.

[0155] In the present disclosure, the gate electrodes of the fifth transistor T5 and the sixth transistor T6 are configured to receive the third scan signal SC3(n) in common, but are not limited thereto. The gate electrodes of the fifth transistor T5 and the sixth transistor T6 may be configured to receive separate scan signals and be independently controlled.

[0156] The seventh transistor T7 may include a first electrode receiving the second initialization voltage Vini, a second electrode connected to the first node N1, and a gate electrode receiving the fourth scan signal SC4(n).

[0157] The seventh transistor T7 may be turned on in response to the fourth scan signal SC4(n) and initialize the gate electrode of the driving transistor DT using the second initialization voltage Vini. In the gate electrode of the driving transistor DT, unnecessary charge may remain due to the high potential driving voltage EVDD stored in the capacitor Cst. When the second initialization voltage Vini is supplied to the gate electrode of the driving transistor DT via the seventh transistor T7, the residual charge may be initialized.

[0158] Figure 6 is a timing chart for describing an example of driving of a display device according to one embodiment. Figure 6 It is a diagram for describing the driving of a sub-pixel circuit and an emission diode of a sub-pixel.

[0159] refer to Figure 6 , the sub-pixel circuit may include at least one bias segment Tobs1, Tobs2 to operate.

[0160] In at least one bias section Tobs1 or Tobs2, an on-bias stress operation OBS is performed to provide a bias voltage Vobs. The emission control signal EM(n) is at a high level, and the third transistor T3 and the fourth transistor T4 are turned off. The first scan signal SC1(n) and the fourth scan signal SC4(n) are at a low level, and the first transistor T1 and the seventh transistor T7 are turned off. The second scan signal SC2 is at a high level, and the second transistor T2 is turned off.

[0161] The third scan signal SC3 (n) of a low level is input, and the fifth transistor T5 and the sixth transistor T6 are turned on. When the fifth transistor T5 is turned on, the bias voltage Vobs is supplied to the first electrode of the driving transistor DT connected to the second node N2.

[0162] Herein, when the bias voltage Vobs is supplied to the third node N3 as the drain electrode of the driving transistor DT, the charging time, gate drive, or charging delay of the voltage of the fifth node N5 as the anode electrode of the emission diode ED can be reduced during the emission period while the driving transistor DT remains highly saturated.

[0163] For example, as the bias voltage Vobs increases, the voltage of the third node N3 as the drain electrode of the driving transistor DT may increase, and the gate-source voltage or drain-source voltage of the driving transistor DT may decrease. Therefore, the bias voltage Vobs is preferably at least greater than the data voltage Vdata.

[0164] At this time, the magnitude of the drain-source current Id through the driving transistor DT can be reduced, and in the case of positive bias stress, the stress of the driving transistor DT can be reduced to address the charging delay of the voltage of the third node N3. In other words, performing the on-bias stress (OBS) operation before sampling the threshold voltage Vth of the driving transistor DT can reduce the hysteresis of the driving transistor DT.

[0165] Therefore, in at least one bias section Tobs1 , Tobs2 , the on-bias stress operation may be defined as an operation of directly providing an appropriate bias voltage to the driving transistor DT during a non-emission period.

[0166] In addition, when the sixth transistor T6 is turned on in at least one bias section Tobs1 , Tobs2 , the anode electrode (or pixel electrode) of the emission diode ED connected to the fifth node N5 is initialized to the first initialization voltage Var.

[0167] However, the gate electrodes of the fifth transistor T5 and the sixth transistor T6 may be configured to receive separate scan signals and be independently controlled. That is, in the bias section, the bias voltage is not necessarily supplied to the first electrode of the driving transistor DT and the anode electrode of the emitting diode ED at the same time.

[0168] refer to Figure 6 , the pixel circuit may include an initialization section Ti to operate. The initialization section Ti is a section for initializing the voltage of the gate electrode of the driving transistor DT.

[0169] The first scan signal SC1(n) to the fourth scan signal SC4(n) and the emission control signal EM(n) are at a high level, and the first transistor T1 and the seventh transistor T7 are turned on. The second to sixth transistors T2, T3, T4, T5, and T6 are turned off. When the first transistor T1 and the seventh transistor T7 are turned on, the gate electrode and the second electrode of the driving transistor DT connected to the first node N1 are initialized with the second initialization voltage Vini or are initialized to the second initialization voltage Vini.

[0170] refer to Figure 6 The pixel circuit may include a sampling section Ts to operate. The sampling section is a section for sampling the threshold voltage Vth of the driving transistor DT.

[0171] The first scan signal SC1(n), the third scan signal SC3(n), and the emission control signal EM(n) are at a high level, and the second scan signal SC2(n) and the fourth scan signal SC4(n) are input at a low level. Therefore, the third to seventh transistors T3, T4, T5, T6, and T7 are turned off, the first transistor T1 remains on, and the second transistor T2 is turned on. That is, the second transistor T2 is turned on, providing the data voltage Vdata to the drive transistor DT, and the first transistor T1 is diode-connected between the first node N1 and the third node N3, so that the threshold voltage Vth of the drive transistor DT is sampled.

[0172] refer to Figure 6 , the pixel circuit may include an emission section Te to operate. The emission section Te is a section where the sampled threshold voltage Vth is offset and the emission diode ED emits light with a driving current corresponding to the sampled data voltage.

[0173] The emission control signal EM(n) is at a low level, and the third transistor T3 and the fourth transistor T4 are turned on.

[0174] When the third transistor T3 is turned on, the high potential driving voltage EVDD connected to the fourth node N4 is supplied to the first electrode of the driving transistor DT connected to the second node N2 through the third transistor T3. The driving current supplied from the driving transistor DT via the fourth transistor T4 to the emission diode ED compensates for the threshold voltage Vth of the driving transistor DT regardless of the value of the threshold voltage Vth of the driving transistor DT, and the driving transistor DT operates.

[0175] Hereinafter, a configuration and a driving method of a pixel circuit according to the arrangement structure of the first pixel PX1 and the second pixel PX2 are described in detail.

[0176] refer to Figure 7-8B An example of driving the display device according to one embodiment will be described in detail.

[0177] Figure 7 This is a plan view showing an example of driving of a display device according to an embodiment. Figure 8A and 8B is a timing diagram for describing an example of driving a display device according to an embodiment. Figure 7 , for convenience of description, only sub-pixels, data lines, and a multiplexer (MUX) of the first pixel PX1 and the second pixel PX2 are shown.

[0178] refer to Figure 7 , the first pixels and the second pixels are alternately arranged in the column direction (Y-axis direction), and are alternately arranged in the row direction (X-axis direction).

[0179] The first data line DL1 is connected to the first column (the nth column), and the second data line DL2 is connected to the second column (the n+1th column). The subpixels of the first pixel PX1_1 and the second pixel PX2_2 arranged in the first column are connected to the first data line DL1, and the subpixels of the second pixel PX2_1 and the first pixel PX1_2 arranged in the second column are connected to the second data line DL2.

[0180] Specifically, the first data line DL1 branches into a first left data line DLL1 and a first right data line DLR1. The first to third subpixels arranged in the first column are alternately connected to the first left data line DLL1 and the first right data line DLR1. Specifically, the first to third subpixels of the first pixel PX1_1 arranged in the first column are connected to the first left data line DLL1, and the first to third subpixels of the second pixel PX2_2 arranged in the first column are connected to the first right data line DLR1.

[0181] The second data line DL2 then branches into a second left data line DLL2 and a second right data line DLR2. The first to third subpixels arranged in the second column are alternately connected to the second left data line DLL2 and the second right data line DLR2. Specifically, the first to third subpixels of the second pixel PX2_1 arranged in the second column are connected to the second left data line DLL2, and the first to third subpixels of the first pixel PX1_2 arranged in the second column are connected to the second right data line DLR2.

[0182] refer to Figure 7 A display device according to the present disclosure includes a first multiplexer MUX1 and a second multiplexer MUX2. The first multiplexer MUX1 is connected to left data lines DLL1 and DLL2 branching from each data line, and the second multiplexer MUX2 is connected to right data lines DLR1 and DLR2 branching from each data line. The first multiplexer MUX1 continuously delivers a left data voltage to the left data line according to a first multiplexer MUX1 signal, and the second multiplexer MUX2 continuously delivers a right data voltage to the right data line according to a second multiplexer MUX2 signal.

[0183] Therefore, the first to third subpixels of the first pixel PX1_1 in the first column are supplied with the first data voltage from the first left data line DLL1 , and the first to third subpixels of the second pixel PX2_2 in the first column are supplied with the first data voltage from the first right data line DLR1 .

[0184] Similarly, the second data voltage is supplied from the second left data line DLL2 to the first to third subpixels of the second pixel PX2_1 disposed in the second column, and the second data voltage is supplied from the second right data line DLR2 to the first to third subpixels of the first pixel PX1_2 disposed in the second column.

[0185] at this time, Figure 8A and 8B 1 is a timing diagram in the sampling period Ts when the display device according to one embodiment drives only the second pixel and implements the narrow field of view mode. Figure 8A is a driving timing diagram of the first pixel PX1_1 and the second pixel PX2_2 arranged in the first column, and Figure 8B 2 is a driving timing diagram of the second pixel PX2_1 and the first pixel PX1_2 arranged in the second column.

[0186] Reference together Figure 6 and 8AIn the sampling period Ts, the emission control signal EM(n) is at a high level, and the second scan signal SC2(n) is input at a low level. At this time, the first data voltage Vdata1 is output at a high level, input at a low level to the first multiplexer MUX1, and input at a high level to the second multiplexer MUX2, thereby providing the high-level data voltage to the first pixel PX1_1. Then, the first data voltage Vdata1 is output at a low level, input at a high level to the first multiplexer MUX1, and input at a low level to the second multiplexer MUX2, thereby providing the low-level data voltage to the second pixel PX2_2. Therefore, the first pixel PX1_1 arranged in the first column is not driven, and the second pixel PX2_2 arranged in the first column is driven.

[0187] Similarly, refer to Figure 6 and 8B In the sampling period Ts, the emission control signal EM(n) is at a high level, and the second scan signal SC2(n) is input at a low level. At this time, the second data voltage Vdata2 is output at a low level, input at a low level to the first multiplexer MUX1, and input at a high level to the second multiplexer MUX2, thereby providing the low-level data voltage to the second pixel PX2_1. Then, the second data voltage Vdata2 is output at a high level, input at a high level to the first multiplexer MUX1, and input at a low level to the second multiplexer MUX2, thereby providing the high-level data voltage to the first pixel PX1_2. Therefore, the first pixel PX1_2 arranged in the second column is not driven, and the second pixel PX2_1 arranged in the second column is driven.

[0188] refer to Figure 6-8B , in such Figure 7 In the structure shown, the first pixels and the second pixels are alternately arranged in the column direction (Y-axis direction) and the row direction (X-axis direction). Since the data voltage provided to each sub-pixel is selectively input in the sampling segment Ts, only the second pixel is driven while the first pixel is not driven, thereby realizing a narrow field of view mode.

[0189] In addition, Figure 7 In the arrangement structure of the first pixel and the second pixel shown in FIG. 1 , when only the first pixel is driven to realize the wide field mode, the sampling period Ts may be provided with the same Figure 8A and 8B The data voltage shown is a data voltage of a level opposite to the input level.

[0190] Therefore, in Figure 7In the arrangement structure of the first pixel and the second pixel shown, the first data voltage Vdata1 supplied to the first data line DL1 and the second data voltage Vdata2 supplied to the second data line DL2 are output at opposite levels in the sampling section Ts, and the voltage levels of the first data voltage Vdata1 and the second data voltage Vdata2 are changed to selectively drive the first pixel and the second pixel in the sampling section Ts.

[0191] Next, refer to Figure 9-10B An example of driving the display device according to another embodiment will be described in detail.

[0192] Figure 9 It is a plan view showing an example of driving of a display device according to another embodiment. Figure 10A and 10B is a timing diagram for describing an example of driving a display device according to another embodiment. Figure 9 , for the convenience of description, only the sub-pixels of the first pixel and the second pixel, the data lines and the multiplexer MUX are shown.

[0193] refer to Figure 9 , the first pixels and the second pixels are alternately arranged in the row direction (X-axis direction), and are respectively arranged in a continuous manner in the column direction (Y-axis direction).

[0194] like Figure 9 As shown, the first data line DL1 is connected to the first column, and the second data line DL2 is connected to the second column. The subpixels of the two first pixels PX1_1 and PX1_2 arranged in the first column are connected to the first data line DL1, and the subpixels of the two second pixels PX2_1 and PX2_2 arranged in the second column are connected to the second data line DL2.

[0195] like Figure 9 As shown, the first data line DL1 branches into a first left data line DLL1 and a first right data line DLR1. The first to third subpixels arranged in the first column are alternately connected to the first left data line DLL1 and the first right data line DLR1. Specifically, the first to third subpixels of the first first pixel PX1_1 arranged in the first column are connected to the first left data line DLL1, and the first to third subpixels of the second first pixel PX1_2 arranged in the first column are connected to the first right data line DLR1.

[0196] The second data line DL2 then branches into a second left data line DLL2 and a second right data line DLR2. The first to third subpixels arranged in the second column are alternately connected to the second left data line DLL2 and the second right data line DLR2. Specifically, the first to third subpixels of the first second pixel PX2_1 arranged in the second column are connected to the second left data line DLL2, and the first to third subpixels of the second second pixel PX2_2 arranged in the second column are connected to the second right data line DLR2.

[0197] refer to Figure 9 The display device according to the present disclosure includes a plurality of first multiplexers MUX1 and second multiplexers MUX2. The first multiplexers MUX1 are connected to left data lines DLL1 and DLL2 branching from each data line DL1 and DL2, and the second multiplexers MUX2 are connected to right data lines DLR1 and DLR2 branching from each data line. The first multiplexer MUX1 continuously delivers a left data voltage to the left data lines DLL1 and DLL2 according to a first multiplexer MUX1 signal, and the second multiplexer MUX2 continuously delivers a right data voltage to the right data lines DLR1 and DLR2 according to a second multiplexer MUX2 signal.

[0198] Therefore, the first to third subpixels of the first first pixel PX1_1 in the first column are supplied with the first data voltage Vdata1 from the first left data line DLL1 , and the second first pixel PX1_2 in the first column is supplied with the first data voltage Vdata1 from the first right data line DLR1 .

[0199] Similarly, the first to third subpixels of the first second pixel PX2_1 in the second column are supplied with the second data voltage Vdata2 from the second left data line DLL2, and the second second pixel PX2_2 in the second column is supplied with the second data voltage Vdata2 from the second right data line DLR2.

[0200] at this time, Figure 10A and 10B 1 is a timing diagram in the sampling section Ts when the display device of another embodiment drives only the second pixel and implements the narrow field of view mode. Figure 10A is a driving timing diagram of the first pixels PX1_1 and PX1_2 arranged in the first column, and Figure 10B 2 is a driving timing diagram of the second pixels PX2_1 and PX2_2 arranged in the second column.

[0201] Reference together Figure 6 and 10ADuring the sampling period Ts, the emission control signal EM(n) is at a high level, and the second scan signal SC2(n) is input at a low level. At this time, the first data voltage Vdata1 is output at a high level, input at a low level into the first multiplexer MUX1, and input at a high level into the second multiplexer MUX2, thereby providing the high-level first data voltage Vdata1 to the first first pixel PX1_1. Then, the first data voltage Vdata1 remains at a high level, input at a high level into the first multiplexer MUX1, and input at a low level into the second multiplexer MUX2, thereby providing the high-level first data voltage Vdata1 to the second first pixel PX1_2. Therefore, the two first pixels PX1_1 and PX1_2 arranged in the first column are not driven.

[0202] Similarly, reference Figure 6 and 10B During the sampling period Ts, the emission control signal EM(n) is at a high level, and the second scan signal SC2(n) is input at a low level. At this time, the second data voltage Vdata2 is output at a low level, input to the first multiplexer MUX1 at a low level, and input to the second multiplexer MUX2 at a high level, thereby providing the low-level second data voltage Vdata2 to the first second pixel PX2_1. Then, the second data voltage Vdata2 remains at a low level, input to the first multiplexer MUX1 at a high level, and input to the second multiplexer MUX2 at a low level, thereby providing the low-level second data voltage Vdata2 to the second second pixel PX2_2. Thus, the two second pixels PX2_1 and PX2_2 arranged in the second column are driven.

[0203] In summary, in the case where the first pixel and the second pixel are alternately arranged in the row direction (X-axis direction) and are respectively arranged in a continuous manner in the column direction (Y-axis direction), as shown in FIG. Figure 9 As shown, the first data voltage Vdata1 and the second data voltage Vdata2 are input at opposite levels in the sampling section Ts and are kept constant, thereby driving only the second pixel to implement the narrow field mode without driving the first pixel.

[0204] In addition, through Figure 9 In the arrangement structure of the first pixel and the second pixel shown in FIG, when only the first pixel is driven to realize the wide field mode, the sampling period Ts may be provided with the same Figure 10A and 10B The data voltages shown are input at opposite levels to the data voltages shown in FIG.

[0205] Therefore, in Figure 9 In the arrangement structure of the first pixel and the second pixel shown, the first data voltage Vdata1 provided to the first data line DL1 and the second data voltage Vdata2 provided to the second data line DL2 are output at opposite levels in the sampling section Ts, and in the sampling section Ts, the voltage levels of the first data voltage Vdata1 and the second data voltage Vdata2 are maintained constant to selectively drive the first pixel and the second pixel.

[0206] Next, refer to Figures 11 to 12B An example of driving the display device according to still another embodiment will be described in detail.

[0207] Figure 11 It is a plan view showing an example of driving of a display device according to still another embodiment. Figure 12A and 12B is a timing diagram for describing an example of driving a display device according to another embodiment. Figure 11 In the figure, for the convenience of description, only the sub-pixels of the first pixel and the second pixel, the data lines and the multiplexer MUX are shown.

[0208] refer to Figure 11 , the first pixels and the second pixels are alternately arranged in the column direction (Y-axis direction), and are respectively arranged in a continuous manner in the row direction (X-axis direction).

[0209] like Figure 11 As shown, the first data line DL1 is connected to the first column, and the second data line DL2 is connected to the second column. The subpixels of the first pixel PX1_1 and the second pixel PX2_1 arranged in the first column are connected to the first data line DL1, and the subpixels of the first pixel PX1_2 and the second pixel PX2_2 arranged in the second column are connected to the second data line DL2.

[0210] like Figure 11 As shown, the first data line DL1 branches into a first left data line DLL1 and a first right data line DLR1. The first to third subpixels arranged in the first column are alternately connected to the first left data line DLL1 and the first right data line DLR1. Specifically, the first to third subpixels of the first pixel PX1_1 arranged in the first column are connected to the first left data line DLL1, and the first to third subpixels of the second pixel PX2_1 arranged in the first column are connected to the first right data line DLR1.

[0211] The second data line DL2 then branches into a second left data line DLL2 and a second right data line DLR2. The first to third subpixels arranged in the second column are alternately connected to the second left data line DLL2 and the second right data line DLR2. Specifically, the first to third subpixels of the first pixel PX1_2 arranged in the second column are connected to the second left data line DLL2, and the first to third subpixels of the second pixel PX2_2 arranged in the second column are connected to the second right data line DLR2.

[0212] refer to Figure 11 The display device according to the present disclosure includes a plurality of first multiplexers MUX1 and second multiplexers MUX2. The first multiplexers MUX1 are connected to left data lines DLL1 and DLL2 branched from each data line, and the second multiplexers MUX2 are connected to right data lines DLR1 and DLR2 branched from each data line. The first multiplexer MUX1 continuously delivers a left data voltage to the left data lines DLL1 and DLL2 according to a first multiplexer MUX1 signal, and the second multiplexer MUX2 continuously delivers a right data voltage to the right data lines DLR1 and DLR2 according to a second multiplexer MUX2 signal.

[0213] Therefore, the first data voltage Vdata1 is supplied from the first left data line DLL1 to the first to third subpixels of the first pixel PX1_1 disposed in the first column, and the first data voltage Vdata1 is supplied from the first right data line DLR1 to the first to third subpixels of the second pixel PX2_1 disposed in the first column.

[0214] Similarly, the second data voltage Vdata2 is supplied to the first to third subpixels of the first pixel PX1_2 in the second column from the second left data line DLL2, and the second data voltage Vdata2 is supplied to the first to third subpixels of the second pixel PX2_2 in the second column from the second right data line DLR2.

[0215] at this time, Figure 12A and 12B 4 is a timing diagram in the sampling section Ts when the display device according to still another embodiment drives only the second pixel and implements the narrow field of view mode. Figure 12A is a driving timing diagram of the first pixel PX1_1 and the second pixel PX2_1 arranged in the first column, and Figure 12B 2 is a driving timing diagram of the first pixel PX1_2 and the second pixel PX2_2 arranged in the second column.

[0216] refer to Figure 6 and 12AIn the sampling segment Ts, the emission control signal EM(n) is at a high level, and the second scan signal SC2(n) is input at a low level. At this time, the first data voltage Vdata1 is output at a high level, input at a low level to the first multiplexer MUX1, and input at a high level to the second multiplexer MUX2, thereby providing the high-level first data voltage Vdata1 to the first pixel PX1_1. Then, the first data voltage Vdata1 is output at a low level, input at a high level to the first multiplexer MUX1, and input at a low level to the second multiplexer MUX2, thereby providing the low-level first data voltage Vdata1 to the second pixel PX2_1. Therefore, the first pixel PX1_1 arranged in the first column is not driven, and the second pixel PX2_1 is driven.

[0217] Similarly, refer to Figure 6 and 12B In the sampling section Ts, the emission control signal EM(n) is at a high level, and the second scan signal SC2(n) is input at a low level. At this time, the second data voltage Vdata2 is output at a high level, input to the first multiplexer MUX1 at a low level, and input to the second multiplexer MUX2 at a high level, thereby providing the high-level second data voltage Vdata2 to the first pixel PX1_2. Then, the second data voltage Vdata2 is input at a low level, input to the first multiplexer MUX1 at a high level, and input to the second multiplexer MUX2 at a low level, thereby providing the low-level second data voltage Vdata2 to the second pixel PX2_2. Therefore, the first pixel PX1_2 arranged in the second column is not driven, and the second pixel PX2_2 is driven.

[0218] In summary, in the case where the first pixel and the second pixel are alternately arranged in the column direction (Y-axis direction) and are respectively arranged in a continuous manner in the row direction (X-axis direction), as shown in FIG. Figure 11 As shown, in the sampling section Ts, the first data voltage Vdata1 and the second data voltage Vdata2 are input at the same level, and the data voltage provided to each subpixel is selectively input, thereby driving only the second pixel to realize the narrow field mode without driving the first pixel.

[0219] In addition, through Figure 11 In the arrangement structure of the first pixel and the second pixel shown in FIG, when only the first pixel is driven to realize the wide field mode, the sampling period Ts may be provided with the same Figure 12A and 12BThat is, when a low level is input to the first multiplexer MUX1, the first data voltage Vdata1 and the second data voltage Vdata2 may be provided at a low level, and when a low level is input to the second multiplexer MUX2, the first data voltage Vdata1 and the second data voltage Vdata2 may be provided at a high level.

[0220] Therefore, in Figure 11 In the arrangement structure of the first pixel and the second pixel shown, the first data voltage Vdata1 supplied to the first data line DL1 and the second data voltage Vdata2 supplied to the second data line DL2 are output at the same level in the sampling section Ts, and in the sampling section Ts, the voltage levels of the first data voltage Vdata1 and the second data voltage Vdata2 are changed to selectively drive the first pixel and the second pixel.

[0221] Exemplary embodiments of the present disclosure may also be described as follows:

[0222] According to one aspect of the present disclosure, a display device is provided, including a first pixel and a second pixel disposed on a display panel, wherein the first pixel and the second pixel each include a plurality of sub-pixels, and each of the plurality of sub-pixels of the second pixel includes a plurality of lenses for refracting light from an emission diode.

[0223] The plurality of lenses may be hemispherical lenses.

[0224] The plurality of lenses may not be provided in the first pixel.

[0225] The distance between the multiple lenses may be 20-40 μm.

[0226] The plurality of sub-pixels may include a green sub-pixel, a red sub-pixel, and a blue sub-pixel. The plurality of lenses may include a plurality of first lenses disposed in the green sub-pixels of a second pixel, a plurality of second lenses disposed in the red sub-pixels of the second pixel, and a plurality of third lenses disposed in the blue sub-pixels of the second pixel. The number of the plurality of first lenses may be greater than the number of the plurality of second lenses, and the number of the plurality of third lenses may be greater than the number of the first lenses.

[0227] Each of the plurality of sub-pixels may include: a first thin film transistor and a second thin film transistor; an emission diode disposed on the first thin film transistor and the second thin film transistor; a bank layer exposing an anode electrode of the emission diode and defining an emission region; and an encapsulation portion disposed to cover the emission diode.

[0228] Each of the plurality of sub-pixels of the second pixel may further include a light shielding pattern disposed on the encapsulation portion and including a plurality of openings, and each of the plurality of lenses may be disposed on the light shielding pattern to correspond to each of the plurality of openings.

[0229] Each of the plurality of sub-pixels may further include a touch sensing portion disposed on the encapsulation portion. The touch sensing portion may include a first electrode, a second electrode on the first electrode, an organic material layer between the first and second electrodes, and an inorganic insulating layer on the second electrode. A light shielding pattern may be disposed below the organic material layer. Furthermore, a plurality of lenses may be disposed on the inorganic insulating layer.

[0230] Each of the plurality of lenses may have a lower surface that is smaller than a surface area of ​​the emission region and larger than a surface area of ​​the opening.

[0231] The first thin film transistor may include: a first active layer made of a polycrystalline silicon semiconductor material; a first gate electrode overlapping the first active layer, with a first gate insulating layer between the first gate electrode and the first active layer; and a first source electrode and a first drain electrode connected to the first active layer. Furthermore, the second thin film transistor may include: a second active layer made of an oxide semiconductor material; a second gate electrode overlapping the second active layer, with a second gate insulating layer between the second gate electrode and the second active layer; and a second source electrode and a second drain electrode connected to the second active layer.

[0232] The display device may further include: gate lines extending in a row direction; and data lines extending in a column direction and intersecting the gate lines. The data lines may branch into left and right data lines. A plurality of pixels may be arranged in the column and row directions. The plurality of pixels arranged in the row direction may be connected to the same gate line, and the plurality of pixels arranged in the column direction may be alternately connected to the left and right data lines.

[0233] The display device may further include a first multiplexer and a second multiplexer that sequentially deliver the data voltage from the data line to the left data line and the right data line.

[0234] The first pixels and the second pixels may be alternately arranged in a column direction and a row direction. The data line may include a first data line arranged in the nth column and a second data line arranged in the n+1th column. Each of the plurality of sub-pixels may be driven individually in an initial section, a sampling section, and an emission section. In the sampling section, a first data voltage supplied to the first data line may be output at a level opposite to a level of a second data voltage supplied to the second data line, and in the sampling section, voltage levels of the first data voltage and the second data voltage may be changed.

[0235] The first pixels and the second pixels may be arranged alternately in a row direction. The first pixels and the second pixels may be arranged in a continuous manner in a column direction. The data line may include a first data line arranged in the nth column and a second data line arranged in the n+1th column. Each of the plurality of sub-pixels may be driven individually in an initial section, a sampling section, and an emission section. In the sampling section, the first data voltage provided to the first data line may be output at a level opposite to a level of the second data voltage of the second data line. Moreover, in the sampling section, the voltage levels of the first data voltage and the second data voltage may be maintained constant.

[0236] The first pixel and the second pixel may be arranged in a continuous manner in the row direction. The first pixel and the second pixel may be arranged alternately in the column direction. The data line may include a first data line arranged in the nth column and a second data line arranged in the n+1th column. Each of the plurality of sub-pixels may be driven individually in the initial section, the sampling section, and the emission section. In the sampling section, the first data voltage provided to the first data line may be output at the same level as the second data voltage of the second data line. Moreover, in the sampling section, the voltage levels of the first data voltage and the second data voltage may vary.

[0237] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in a variety of different forms without departing from the technical concepts of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concepts of the present disclosure. The scope of the technical concepts of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device comprising: A first pixel and a second pixel are provided at the display panel, the first pixel and the second pixel respectively include a plurality of sub-pixels, and each of the plurality of sub-pixels of the second pixel includes a plurality of lenses that refract light from an emission diode.

2. The display device according to claim 1, wherein The plurality of lenses are hemispherical lenses.

3. The display device according to claim 1, wherein The plurality of lenses are not provided in the first pixel.

4. The display device according to claim 1, wherein The distance between the plurality of lenses is 20-40 μm.

5. The display device according to claim 1, wherein The plurality of sub-pixels include a green sub-pixel, a red sub-pixel, and a blue sub-pixel, The plurality of lenses include a plurality of first lenses disposed in the green sub-pixels of the second pixel, a plurality of second lenses disposed in the red sub-pixels of the second pixel, and a plurality of third lenses disposed in the blue sub-pixels of the second pixel, and The number of the plurality of first lenses is greater than the number of the plurality of second lenses, and the number of the plurality of third lenses is greater than the number of the plurality of first lenses.

6. The display device according to claim 1 , wherein each of the plurality of sub-pixels comprises: a first thin film transistor and a second thin film transistor; The emitting diode is provided on the first thin film transistor and the second thin film transistor; a bank layer exposing the anode electrode of the emitting diode and defining an emitting region; as well as The packaging portion is configured to cover the emitting diode.

7. The display device according to claim 6 , wherein each of the plurality of sub-pixels of the second pixel further comprises: a light shielding pattern provided on the packaging portion and including a plurality of openings, Each of the plurality of lenses is disposed on the light shielding pattern to correspond to each of the plurality of openings.

8. The display device according to claim 7, wherein: Each of the plurality of sub-pixels further includes a touch sensing portion disposed on the encapsulation portion, The touch sensing portion includes a first electrode, a second electrode on the first electrode, an organic material layer between the first electrode and the second electrode, and an inorganic insulating layer on the second electrode. The light shielding pattern is disposed below the organic material layer, and The plurality of lenses are disposed on the inorganic insulating layer.

9. The display device according to claim 7, wherein: Each of the plurality of lenses has a lower surface that is smaller than a surface area of ​​the emission region and larger than a surface area of ​​the opening.

10. The display device according to claim 6, wherein The first thin film transistor includes: a first active layer made of a polysilicon semiconductor material; a first gate electrode overlapping the first active layer, with a first gate insulating layer between the first gate electrode and the first active layer; and a first source electrode and a first drain electrode connected to the first active layer, and The second thin film transistor includes: a second active layer made of an oxide semiconductor material; a second gate electrode overlapping the second active layer, with a second gate insulating layer between the second gate electrode and the second active layer; and a second source electrode and a second drain electrode connected to the second active layer.

11. The display device according to claim 10, wherein: Each of the plurality of sub-pixels further includes a capacitor; and A first electrode included in the capacitor and a light shielding layer included in the second thin film transistor are formed of the same material as that of the first gate electrode.

12. The display device according to claim 1, further comprising: gate lines extending in a row direction; as well as data lines extending in a column direction and crossing the gate lines, The data line is branched into a left data line and a right data line. The plurality of sub-pixels are arranged in the column direction and the row direction, A plurality of sub-pixels arranged in the row direction are connected to the same gate line, and A plurality of sub-pixels arranged in a column direction are alternately connected to the left data line and the right data line.

13. The display device according to claim 12, wherein: The display device also includes a first multiplexer and a second multiplexer that sequentially deliver a data voltage from the data line to the left data line and the right data line.

14. The display device according to claim 13, wherein: The first pixels and the second pixels are alternately arranged in the column direction and the row direction, The data lines include a first data line arranged in the nth column and a second data line arranged in the n+1th column, driving each of the plurality of sub-pixels individually in an initial section, a sampling section, and an emission section, In the sampling section, the first data voltage supplied to the first data line is output at a level opposite to the level of the second data voltage supplied to the second data line, and In the sampling section, voltage levels of the first data voltage and the second data voltage are changed.

15. The display device according to claim 13, wherein The first pixels and the second pixels are alternately arranged in the row direction, The first pixels and the second pixels are respectively arranged in a continuous manner in the column direction, The data lines include a first data line arranged in the nth column and a second data line arranged in the n+1th column, driving each of the plurality of sub-pixels individually in an initial section, a sampling section, and an emission section, In the sampling section, the first data voltage supplied to the first data line is output at a level opposite to that of the second data voltage of the second data line, and In the sampling section, voltage levels of the first data voltage and the second data voltage are kept constant.

16. The display device according to claim 13, wherein The first pixels and the second pixels are respectively arranged in a continuous manner in the row direction, The first pixels and the second pixels are alternately arranged in the column direction, The data lines include a first data line arranged in the nth column and a second data line arranged in the n+1th column, driving each of the plurality of sub-pixels individually in an initial section, a sampling section, and an emission section, In the sampling section, the first data voltage supplied to the first data line is output at the same level as the second data voltage of the second data line, and In the sampling section, voltage levels of the first data voltage and the second data voltage are changed.

Images