Special-shaped display panel and display device

Abstract

Embodiments of the present disclosure provide a special-shaped display panel and a display device, which include a display area and a peripheral area arranged around the display area, and have a special-shaped boundary between the display area and the peripheral area; a color film substrate includes: a first substrate, the first substrate has a virtual display area arranged around the display area corresponding to the peripheral area, the virtual display area includes a plurality of virtual pixels arranged around an edge display pixel, the virtual pixel includes a plurality of virtual sub-pixels with different light-emitting colors; a black matrix layer is located on a side of the first substrate facing the array substrate, the black matrix layer covers the display area and the virtual display area, and the black matrix layer is provided with an opening corresponding to each display sub-pixel located in the display area; a plurality of light filtering structures are located on a side of the black matrix layer away from the first substrate, the light filtering structure is filled in the opening in the display area, and the light filtering structure is arranged on the side of the black matrix layer away from the first substrate corresponding to the position of the virtual sub-pixel in the virtual display area.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an irregularly shaped display panel and display device. Background Technology

[0002] With the development of science and technology, display devices are becoming more and more widely used, which makes people's requirements for display panels in display devices more and more diverse. In order to meet people's diverse needs for the shape of display panels, irregularly shaped display panels have emerged.

[0003] Irregularly shaped display panels break through the limitations of the single rectangular structure of display panels, making their applications more extensive, such as in automotive displays. The display area of ​​irregularly shaped display panels presents shapes other than rectangles, such as circles and ovals. Summary of the Invention

[0004] This disclosure provides an irregularly shaped display panel and display device, the specific solution of which is as follows:

[0005] This disclosure provides an irregularly shaped display panel, including a display area and a peripheral area surrounding the display area, with an irregularly shaped boundary between the display area and the peripheral area; the display area includes a plurality of display pixels arranged in an array along the row and column directions, and the display pixels include a plurality of display sub-pixels with different emission colors; the plurality of display pixels includes edge display pixels covered by the irregularly shaped boundary and regular display pixels not covered by the irregularly shaped boundary;

[0006] The irregularly shaped display panel includes an array substrate and a color filter substrate arranged opposite to and spaced apart, the color filter substrate comprising:

[0007] A first substrate, corresponding to the peripheral area, has a virtual display area disposed around the display area, the virtual display area including a plurality of virtual pixels disposed around the edge display pixels, the virtual pixels including a plurality of virtual sub-pixels with different emission colors;

[0008] A black matrix layer is located on the side of the first substrate facing the array substrate. The black matrix layer covers the display area and the virtual display area, and the black matrix layer has an opening corresponding to each display sub-pixel in the display area.

[0009] Multiple filter structures are located on the side of the black matrix layer away from the first substrate. The filter structures fill the opening in the display area. The filter structures are located on the side of the black matrix layer away from the first substrate in the virtual display area corresponding to the position of the virtual sub-pixel.

[0010] In one possible implementation, in the irregularly shaped display panel provided in the embodiments of this disclosure, at least one virtual pixel is provided on one side of the row direction and / or one side of the column direction of each edge display pixel.

[0011] In one possible implementation, in the irregularly shaped display panel provided in the embodiments of this disclosure, the array substrate includes a second substrate and a pixel electrode layer disposed on the side of the second substrate facing the color filter substrate. The pixel electrode layer includes display pixel electrodes disposed corresponding to each of the display sub-pixels and virtual pixel electrodes disposed corresponding to some of the virtual sub-pixels. The virtual pixel electrodes are disposed on one side of the edge of at least one row of display pixel electrodes.

[0012] In one possible implementation, in the irregularly shaped display panel provided in the embodiments of this disclosure, the array substrate corresponding to the peripheral area includes: a driver chip bonding area, and a fan-out area located between the driver chip bonding area and the display area and surrounding at least a portion of the display area; the fan-out area includes multiple fan-out traces; wherein...

[0013] At least a portion of the virtual sub-pixels have an overlapping region in the orthographic projection of the filter structure on the second substrate with at least a portion of the fan-out traces on the second substrate;

[0014] The orthographic projection of the virtual pixel electrode on the second substrate does not overlap with the orthographic projection of the fan-out trace on the second substrate.

[0015] In one possible implementation, in the irregularly shaped display panel provided in the embodiments of this disclosure, the array substrate corresponding to the display area includes: a plurality of scan lines extending along the row direction and arranged along the column direction, and a plurality of data lines extending along the column direction and arranged along the row direction; wherein the plurality of scan lines and the plurality of data lines are insulated from each other and cross to define the plurality of display pixels, and the driving chip bonding area is located on one side of the extension direction of the plurality of data lines;

[0016] The array substrate also includes a first gate driving circuit and a second gate driving circuit located on both sides of the extension direction of the plurality of scan lines corresponding to the peripheral area. The first gate driving circuit is electrically connected to one end of each scan line, and the second gate driving circuit is electrically connected to the other end of each scan line.

[0017] The first gate driving circuit is located on the side of a portion of the fan-out area away from the display area, and the second gate driving circuit is located on the side of another portion of the fan-out area away from the display area. Both the first gate driving circuit and the second gate driving circuit are arranged to conform to the display area.

[0018] In one possible implementation, in the irregularly shaped display panel provided in the embodiments of this disclosure, both the first gate driving circuit and the second gate driving circuit include a plurality of cascaded shift register units, each of which includes a charging transistor disposed near the edge of the peripheral region; wherein...

[0019] In at least two adjacent shift register units, the width of the charging transistor in one shift register unit is greater than the width of the charging transistor in the other shift register unit, the height of the charging transistor in one shift register unit is less than the height of the charging transistor in the other shift register unit, and the channel width-to-length ratio of the charging transistors in the two adjacent shift register units is the same.

[0020] In one possible implementation, in the irregularly shaped display panel provided in the embodiments of this disclosure, the array substrate further includes, corresponding to the peripheral area: a first common electrode ring disposed between the first gate driving circuit, the second gate driving circuit and the display area, and a second common electrode ring disposed on the side of the first gate driving circuit and the second gate driving circuit away from the display area; the first common electrode ring and the second common electrode ring are electrically connected.

[0021] In one possible implementation, in the irregularly shaped display panel provided in the embodiments of this disclosure, the array substrate corresponds to the peripheral area including a gap region located on the other side of the extension direction of the plurality of data lines and located between the first gate driving circuit and the second gate driving circuit, and the first common electrode ring and the second common electrode ring are electrically connected in the gap region.

[0022] In one possible implementation, in the irregularly shaped display panel provided in the embodiments of this disclosure, the first common electrode ring is disposed on the same layer as the data line;

[0023] The second common electrode ring is disposed in the same layer as the data line or the scan line;

[0024] Alternatively, the second common electrode ring may include a first sub-common electrode ring and a second sub-common electrode ring that are stacked and electrically connected to each other, wherein the first sub-common electrode ring is disposed on the same layer as the data line and the second sub-common electrode ring is disposed on the same layer as the scan line.

[0025] In one possible implementation, in the irregularly shaped display panel provided in the embodiments of this disclosure, the fan-out trace includes an inclined segment arranged around the display area and a vertical segment arranged along the extension direction of the data line, the vertical segment being located between the display area and the driver chip bonding area;

[0026] The inclined segment includes a first sub-inclined segment and a second sub-inclined segment. One end of the first sub-inclined segment is electrically connected to one end of the vertical segment, and the other end of the vertical segment is electrically connected to the driver chip in the driver chip bonding area. The other end of the first sub-inclined segment is connected to one end of the second sub-inclined segment through a corresponding via structure and a transparent conductive part. The other end of the second sub-inclined segment is electrically connected to one end of the data line.

[0027] In one possible implementation, in the irregularly shaped display panel provided in the embodiments of this disclosure, the array substrate includes a common electrode corresponding to the display area, and the common electrode is electrically connected to the first common electrode in the peripheral area through a via.

[0028] The gate line is located between the second substrate and the data line. The common electrode is located on the side of the data line away from the second substrate. The transparent conductive part is disposed in the same layer as the common electrode. The second sub-tilted segment is disposed in the same layer as the data line. The first sub-tilted segment and the vertical segment, which are electrically connected to each other, are located in the same film layer.

[0029] A portion of the first sub-tilted segment is disposed on the same layer as the scan line, and another portion of the first sub-tilted segment is disposed on the same layer as the data line. The first sub-tilted segments disposed on the same layer as the scan line and the first sub-tilted segments disposed on the same layer as the data line are alternately disposed along the row direction.

[0030] In one possible implementation, in the irregularly shaped display panel provided in the embodiments of this disclosure, the array substrate further includes: a gate insulating layer located between the gate line and the data line, and a passivation layer located between the data line and the common electrode;

[0031] The other end of the first sub-tilted segment, which is disposed on the same layer as the scan line, is electrically connected to the adapter through a via penetrating the gate insulating layer. The adapter is electrically connected to one end of the corresponding transparent conductive part through a via penetrating the passivation layer. The other end of the transparent conductive part is electrically connected to one end of the corresponding second sub-tilted segment through a via penetrating the passivation layer. The adapter is disposed on the same layer as the data line.

[0032] Alternatively, the other end of the first sub-tilted segment disposed on the same layer as the scan line is electrically connected to one end of the corresponding transparent conductive part through a via penetrating the gate insulating layer and the passivation layer, and the other end of the transparent conductive part is electrically connected to one end of the corresponding second sub-tilted segment through a via penetrating the passivation layer.

[0033] In one possible implementation, in the irregularly shaped display panel provided in the embodiments of this disclosure, the other end of the first sub-tilted segment disposed on the same layer as the data line is electrically connected to one end of the corresponding transparent conductive part through a through-hole penetrating the passivation layer, and the other end of the transparent conductive part is electrically connected to one end of the corresponding second sub-tilted segment through a through-hole penetrating the passivation layer.

[0034] In one possible implementation, in the irregularly shaped display panel provided in the embodiments of this disclosure, the via structure corresponding to the first sub-tilted segment disposed on the same layer as the scan line and the via structure corresponding to the first sub-tilted segment disposed on the same layer as the data line are located in different rows.

[0035] In one possible implementation, in the irregularly shaped display panel provided in the embodiments of this disclosure, a plurality of via structures between each first sub-tilted segment and each second sub-tilted segment are divided into a plurality of via regions along the direction from the edge of the driving chip to the center of the driving chip, and adjacent two via regions form a stepped structure along the direction from the edge of the driving chip to the center of the driving chip.

[0036] In one possible implementation, in the irregularly shaped display panel provided in the embodiments of this disclosure, multiple virtual traces are provided between the first sub-tilted segments that are electrically connected to the adjacent via structures of two adjacent via regions. The extension direction of the virtual traces is the same as the extension direction of the first sub-tilted segments, and the virtual traces include multiple segments of sub-virtual traces that are disconnected.

[0037] In one possible implementation, in the irregularly shaped display panel provided in the embodiments of this disclosure, the width of the inclined segment is smaller than the width of the vertical segment, and the gap width between adjacent inclined segments is smaller than the gap width between adjacent vertical segments.

[0038] In one possible implementation, in the irregularly shaped display panel provided in the embodiments of this disclosure, a protective layer is provided on the side of the vertical segment facing away from the second substrate, and the protective layer is disposed in the same layer as the common electrode.

[0039] In one possible implementation, in the irregularly shaped display panel provided in the embodiments of this disclosure, the width of the vertical segment along the row direction is less than or equal to the width of the protective layer along the row direction.

[0040] In one possible implementation, in the irregularly shaped display panel provided in the embodiments of this disclosure, the array substrate further includes an anti-static circuit disposed between the first common electrode ring and the display area and surrounding a portion of the display area, and the anti-static circuit is disposed opposite to the driver chip bonding area.

[0041] The anti-static circuit is electrically connected to the other end of the data line, and the anti-static circuit is used to release the static electricity accumulated on the data line through the static discharge terminal.

[0042] In one possible implementation, in the irregularly shaped display panel provided in this embodiment, the driver chip bonding area further includes ET test residual traces on both sides along the row direction, and the driver chip bonding area further includes an ET test circuit; wherein, the ET test residual trace includes a cut residual trace and a lead, the cut end of the cut residual trace is wrapped with an insulating layer, one end of the cut residual trace away from the cut end is electrically connected to one end of the lead, and the other end of the lead is electrically connected to the ET test circuit; wherein,

[0043] The pixel electrode layer is located between the data line and the second substrate. The ET test residual trace is disposed in the same layer as the pixel electrode layer, and the cut end of the ET test residual trace is wrapped with an insulating layer.

[0044] In one possible implementation, in the irregularly shaped display panel provided in the embodiments of this disclosure, a portion of the edge display pixels located in the display area is obscured by the black matrix layer. In each row of display pixels, the overlapping area between the display area and the edge display pixels points from small to large, and the area of ​​each edge display pixel obscured by the black matrix layer in each row of display pixels gradually decreases.

[0045] In one possible implementation, in the irregularly shaped display panel provided in the embodiments of this disclosure, the area of ​​each sub-pixel in the same edge display pixel that is covered by the black matrix layer is the same.

[0046] In one possible implementation, in the irregular display panel provided in the embodiments of this disclosure, the area of ​​each sub-pixel that is occluded by the black matrix layer is close to the irregular boundary.

[0047] In one possible implementation, the irregularly shaped display panel provided in the embodiments of this disclosure has a shape that includes a circle or an ellipse.

[0048] Accordingly, this disclosure also provides a display device, including the irregularly shaped display panel described in any of the above embodiments of this disclosure.

[0049] In one possible implementation, the display device provided in the embodiments of this disclosure is a vehicle-mounted display device. Attached Figure Description

[0050] Figure 1This is a plan view of an irregularly shaped display panel provided in an embodiment of the present disclosure;

[0051] Figure 2 for Figure 1 Enlarged structural diagram of dashed box E;

[0052] Figure 3 A planar schematic diagram of a row of sub-pixels in a color filter substrate corresponding to the display area AA and the peripheral area BB;

[0053] Figure 4 for Figure 3 A schematic diagram of the cross-section along the DD' direction;

[0054] Figure 5 This is a planar schematic diagram of the color filter substrate and the array substrate;

[0055] Figure 6 This is another planar schematic diagram of an irregularly shaped display panel;

[0056] Figure 7 This is an enlarged schematic diagram of the fan-out region;

[0057] Figure 8 for Figure 6 A schematic diagram of the specific structure of the first gate drive circuit GOA1;

[0058] Figure 9 for Figure 8 Enlarged schematic diagrams within dashed boxes M1 and M2;

[0059] Figure 10 This is an enlarged schematic diagram of the first common electrode ring COM1 and the second common electrode ring COM2;

[0060] Figure 11 for Figure 6 A magnified schematic diagram of the structure within the dashed box Q;

[0061] Figure 12 for Figure 6 A magnified schematic diagram of the structure within the dashed box R;

[0062] Figure 13 for Figure 6 A magnified schematic diagram of the structure within the dashed box K;

[0063] Figure 14 for Figure 13 A magnified schematic diagram of the structure within the dashed box Z;

[0064] Figure 15 for Figure 13 A magnified schematic diagram of the structure within the dashed box J;

[0065] Figure 16 for Figure 15A schematic cross-sectional view along the CC' direction;

[0066] Figure 17 for Figure 15 Another cross-sectional view along the CC' direction;

[0067] Figure 18 for Figure 15 Another cross-sectional schematic diagram along the EE' direction;

[0068] Figure 19 for Figure 15 A magnified view of a portion of the image;

[0069] Figure 20 for Figure 14 A schematic diagram of the cross section along the AA' direction;

[0070] Figure 21 for Figure 14 A schematic diagram of the cross-section along the BB' direction;

[0071] Figure 22 This is a structural diagram of the vertical section and the protective layer;

[0072] Figure 23 This is a schematic diagram of an anti-static circuit.

[0073] Figure 24 for Figure 13 Enlarged planar schematic diagram within the dashed box N;

[0074] Figure 25 for Figure 24 A schematic diagram of the cross-section along the FF' direction;

[0075] Figure 26 This is a schematic diagram of the grounding wire structure;

[0076] Figure 27 This is a schematic diagram of the structure where edge display pixels are blocked by a light-shielding layer. Detailed Implementation

[0077] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0078] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "comprising" or "including," and similar terms as used in this disclosure, mean that an element or object preceding the term encompasses the elements or objects listed following the term and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "inner," "outer," "upper," and "lower" are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0079] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0080] With the increasing integration of automotive displays with car bodies, the requirements for bezels in automotive displays are becoming more stringent, leading to a growing demand for irregularly shaped and circular automotive display designs. Furthermore, automotive displays require high reliability. The inventors of this case have discovered that existing irregularly shaped automotive displays suffer from poor image uniformity due to etching and exposure issues at the edges of irregularly shaped display areas, resulting in low display quality, reliability, and yield rates.

[0081] To address the issues of low display quality, reliability, and yield rate in existing automotive-grade irregularly shaped displays, this disclosure provides an irregularly shaped display panel, such as... Figure 1 As shown, Figure 1 This is a plan view of an irregularly shaped display panel, which includes a display area AA and a peripheral area BB surrounding the display area AA. An irregularly shaped boundary L separates the display area AA and the peripheral area BB. Figure 2 As shown, Figure 2 for Figure 1 The enlarged structural diagram of the dashed box E shows that the display area AA includes multiple display pixels P arranged in an array along the row direction X and the column direction Y. Each display pixel P includes multiple display sub-pixels sp with different emission colors. Among the multiple display pixels P are edge display pixels PA covered by the irregular boundary L and regular display pixels PB not covered by the irregular boundary L.

[0082] Irregularly shaped display panels include array substrates and color filter substrates arranged opposite to and spaced apart, such as Figure 3 and Figure 4 As shown, Figure 3 This is a planar schematic diagram showing a row of sub-pixels in a color filter substrate corresponding to the display area AA and the peripheral area BB. Figure 4 for Figure 3 A cross-sectional schematic diagram along the DD' direction shows that the color filter substrate includes:

[0083] The first substrate 1 has a virtual display area PD surrounding the display area AA in the peripheral area BB. The virtual display area PD includes a plurality of virtual pixels PN surrounding the edge display pixel PA. The virtual pixel PN includes a plurality of virtual sub-pixels np with different emitting colors.

[0084] The black matrix layer 2 is located on the side of the first substrate 1 facing the array substrate. The black matrix layer 2 covers the display area AA and the virtual display area PD, and the black matrix layer 2 has an opening for each display sub-pixel sp located in the display area AA.

[0085] Multiple filter structures 3 are located on the side of the black matrix layer 2 away from the first substrate 1. The filter structures 3 fill the opening in the display area AA. The filter structures 3 are set on the side of the black matrix layer 2 away from the first substrate 1 at the position corresponding to the virtual sub-pixel np in the virtual display area PD.

[0086] The irregularly shaped display panel provided in this embodiment can effectively improve the etching uniformity of the irregularly shaped display area by setting virtual pixels around the display area in the peripheral area, that is, the virtual pixels are located outside the irregular boundary. This effectively solves the problems of low display quality, reliability and yield of existing vehicle-mounted irregularly shaped displays.

[0087] It should be noted that, in the embodiments of this disclosure, the irregular boundary refers to the boundary between the display area AA and the surrounding area BB.

[0088] It should be noted that the edge display pixels covered by the irregular boundary, where "covered" means that the display pixels and the orthographic projection of the irregular boundary on the first substrate overlap.

[0089] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, such as Figure 2 As shown, a display pixel P may include three sub-pixels sp with different emission colors, such as R (red), G (green), and B (blue). Of course, in this embodiment of the present disclosure, a display pixel P is not limited to the case of including three sub-pixels as described above. For example, a display pixel P may also include four sub-pixels, such as R (red), G (green), B (blue), and white (W).

[0090] In some embodiments, the shape of the irregularly shaped display panel provided in this disclosure may include, but is not limited to, a circle or an ellipse with an irregularly shaped display area. This disclosure takes a circle as an example of an irregularly shaped display panel. Figure 1As shown, the irregular boundary L is circular. To ensure that the edge display pixels PA covered by the irregular boundary L have uniform etching with the regular display pixels PB, it is necessary to ensure that each edge display pixel PA has pixels on its top, bottom, left, and right sides. This ensures the uniform etching of the edge display pixels PA. Since some edge display pixels PA have a peripheral area BB on the row direction X side, some edge display pixels PA have a peripheral area BB on the column direction Y side, and some edge display pixels PA have peripheral areas BB on both the row direction X side and the column direction Y side, this disclosure sets at least one virtual pixel PN on the row direction X side of some edge display pixels PA, sets at least one virtual pixel PN on the column direction Y side of some edge display pixels PA, and sets at least one virtual pixel PN on both the row direction X side and the column direction Y side of some edge display pixels PA.

[0091] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, such as Figure 5 As shown, Figure 5 This is a planar schematic diagram of a color filter substrate and an array substrate. The array substrate includes a second substrate and a pixel electrode layer disposed on the side of the second substrate facing the color filter substrate. The pixel electrode layer includes display pixel electrodes 41 corresponding to each display sub-pixel sp and virtual pixel electrodes 42 corresponding to some virtual sub-pixels np. The virtual pixel electrodes 42 are disposed on one side of the edge of at least one row of display pixel electrodes 41. Thus, when fabricating the pixel electrode layer using an etching process, by placing the virtual pixel electrodes 42 on one side of the edge of at least one row of display pixel electrodes 41, the etching uniformity of the pixel electrode layer can be improved, thereby improving the display quality, reliability, and product yield of automotive-grade irregularly shaped displays.

[0092] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, such as Figures 5-7 As shown, Figure 6 This is another planar schematic diagram of an irregularly shaped display panel. Figure 5 for Figure 6 Enlarged structural diagram within the dashed box F. Figure 7 This is an enlarged schematic diagram of the fan-out area. The array substrate, corresponding to the peripheral area BB, includes: a driver chip bonding area (represented by IC), and a fan-out area BP located between the driver chip bonding area IC and the display area AA, and surrounding at least a portion of the display area AA. The fan-out area BP is conformally arranged around the display area AA. The fan-out area BP includes multiple fan-out traces 5.

[0093] At least some of the virtual sub-pixels np correspond to the filter structure 3 on the second substrate and the orthographic projection of at least some of the fan-out traces 5 on the second substrate have an overlapping area; this is because the color filter substrate does not set traces in the peripheral area BB, so the color filter substrate has no space limitation in the peripheral area BB, that is, a large number of virtual pixels PN can be set in the peripheral area BB of the color filter substrate to ensure that each edge display pixel PA is surrounded by pixels, so as to achieve the etching uniformity of the edge display pixel PA;

[0094] The orthographic projection of the virtual pixel electrode 42 on the second substrate and the orthographic projection of the fan-out trace 5 on the second substrate do not overlap. This is because the array substrate needs to set the fan-out trace 5 in the peripheral area BB, and the fan-out trace 5 is generally made of the material of the pixel electrode layer. In order to avoid short circuit between the virtual pixel electrode 42 and the fan-out trace 5, only a small part of the array substrate (the area close to the display area AA) is used to set the virtual pixel electrode 42 in the peripheral area BB, so as to ensure that the orthographic projection of the virtual pixel electrode 42 on the second substrate and the orthographic projection of the fan-out trace 5 on the second substrate do not overlap.

[0095] It should be noted that, as Figure 4 and Figure 5 As shown, the virtual pixel PN and the display pixel P corresponding to the color filter substrate have the same structural design. For example, each display pixel P corresponding to the color filter substrate includes R (red), G (green), and B (blue) display sub-pixels sp, and each display sub-pixel sp is provided with a filter structure 3. The virtual pixel PN also includes R (red), G (green), and B (blue) virtual sub-pixels np, and each virtual sub-pixel np is also provided with a filter structure 3. However, the difference between the display pixel P and the virtual pixel PN is that the filter structure 3 corresponding to each display sub-pixel sp is set in the opening of the black matrix layer 2, while the filter structure 3 corresponding to the virtual sub-pixel np is blocked by the black matrix layer 2.

[0096] It should be noted that, as Figure 5 As shown, since the color filter substrate does not have traces in the peripheral area BB, its peripheral area BB is not limited by space, and a large number of filter structures 3 can be set in the peripheral area BB of the color filter substrate. However, the array substrate needs to set fan-out traces 5 in the peripheral area BB. Therefore, the array substrate has only a small space to set virtual pixel electrodes 42 in the peripheral area B. Thus, the virtual pixel electrodes 42 set in the peripheral area BB of the array substrate only correspond to some of the filter structures 3 set in the peripheral area BB of the color filter substrate. That is, there are some filter structures 3 on the color filter substrate, but no virtual pixel electrodes 42 are set on the array substrate directly below them.

[0097] It should be noted that, as Figure 5As shown, the array substrate has the same pixel structure design corresponding to the positions of the display pixel electrode 41 and the virtual pixel electrode 42. For example, both the display pixel electrode 41 and the virtual pixel electrode 42 are electrically connected to the corresponding pixel driving circuit. The pixel driving circuits corresponding to the display pixel electrode 41 and the virtual pixel electrode 42 are electrically connected to the corresponding gate lines and data lines, respectively. That is, the display pixel electrode 41 and the virtual pixel electrode 42 can respectively input data signals to them through the data lines. However, the difference between the positions of the display pixel electrode 41 and the virtual pixel electrode 42 is that the virtual pixel electrode 42 is blocked by the black matrix layer 2 on the color filter substrate, while the display pixel electrode 41 is set to the opening of the black matrix layer 2 on the color filter substrate.

[0098] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, such as Figure 5 and Figure 6 As shown, the array substrate corresponding to the display area AA includes: multiple scan lines G extending along the row direction X and arranged along the column direction Y, and multiple data lines S extending along the column direction Y and arranged along the row direction X; wherein, the multiple scan lines G and the multiple data lines S are insulated and intersected to define multiple display pixels P, and the driver chip bonding area IC is located on one side of the extension direction of the multiple data lines S.

[0099] The array substrate also includes a first gate driving circuit GOA1 and a second gate driving circuit GOA2 located on both sides of the extension direction of multiple scan lines G. The first gate driving circuit GOA1 is electrically connected to one end of each scan line G, and the second gate driving circuit GOA2 is electrically connected to the other end of each scan line G.

[0100] In this design, the first gate driving circuit GOA1 is located on the side of one portion of the fan-out area BP that is furthest from the display area AA, and the second gate driving circuit GOA2 is located on the side of the other portion of the fan-out area BP that is furthest from the display area AA. Both the first gate driving circuit GOA1 and the second gate driving circuit GOA2 are arranged conformally around the display area AA. This conformal arrangement of the gate driving circuits around the display area AA allows the peripheral area BB to be nearly circular, thus meeting the current design requirements of customers for automotive displays.

[0101] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, such as Figure 6 and Figure 8 As shown, Figure 8 for Figure 6The schematic diagram of the specific structure of the first gate driving circuit GOA1 is shown. Both the first gate driving circuit GOA1 and the second gate driving circuit GOA2 include multiple shift register units 100 cascaded together. Each shift register unit 100 includes a charging transistor T disposed near the edge of the peripheral area BB. Since the irregular display panel provided in this embodiment is circular, and the bezel of a circular screen is generally small, GOA1 and GOA2 need to be placed along the periphery of the fan-out area BP to ensure that each shift register unit 100 is correctly cascaded. At the same time, since it is an automotive irregular screen, the transistor characteristics in the shift register unit 100 are required to be more uniform, and the transistors cannot be rotated. It is also necessary to ensure that the outer edge area of ​​GOA1 and GOA2 wrapped with the sealing glue is greater than 200μm.

[0102] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, such as Figures 6-9 As shown, Figure 9 The left image in the middle is Figure 8 Enlarged view within the dashed box M1 Figure 9 The right image in the middle is Figure 8 The enlarged schematic diagram within the dashed box M2 shows that since GOA1 and GOA2 are arranged along the periphery of the fan-out area BP, when the starting shift register unit 100, ending shift register unit 100, or any shift register unit 100 in the peripheral area BB of the irregularly shaped display panel cannot meet the cascading requirements due to the size limitations of the peripheral area BB, the dimensions of the shift register unit 100 along the row and column directions can be changed. However, the channel width-to-length ratio, direction, and angle of the transistors in the shift register unit 100 must remain unchanged. For example, in each gate drive circuit, at least two adjacent shift register units 100 (e.g.) Figure 8 The first and second shift register units 100 (from top to bottom) have the following configurations: the width W1 of the charging transistor T along the row direction X of one shift register unit 100 (e.g., the first one) is greater than the width W2 of the charging transistor T along the row direction X of the other shift register unit 100 (e.g., the second one); the height H1 of the charging transistor T along the column direction X of one shift register unit 100 (e.g., the first one) is less than the height H2 of the charging transistor T along the column direction X of the other shift register unit 100 (e.g., the second one); and the channel width-to-length ratio of the charging transistor T in adjacent shift register units 100 is the same. This design ensures the reliability of the vehicle-mounted irregularly shaped display screen while satisfying the customer's design requirements for the irregularly shaped display panel by making the gate drive circuit closer to a circle.

[0103] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, such as Figure 6As shown, the shift register unit 100 in the first gate driving circuit GOA1 and the second gate driving circuit GOA2 has the same specific structure. The first gate driving circuit GOA1 and the second gate driving circuit GOA2 are generally symmetrically arranged about the central area of ​​the irregular display panel. The specific working principle of the first gate driving circuit GOA1 and the second gate driving circuit GOA2 is the same as that in related technologies, and this disclosure will not describe it.

[0104] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, such as Figure 6 and Figure 10 As shown, Figure 10 This is an enlarged schematic diagram of the first common electrode ring COM1 and the second common electrode ring COM2. The array substrate, corresponding to the peripheral region BB, also includes: a first common electrode ring COM1 disposed between the first gate driving circuit GOA1, the second gate driving circuit GOA2, and the display area AA; and a second common electrode ring COM2 disposed on the side of the first gate driving circuit GOA1 and the second gate driving circuit GOA2 away from the display area AA. The first common electrode ring COM1 and the second common electrode ring COM2 are electrically connected. This disclosure employs a parallel design of the first common electrode ring COM1 and the second common electrode ring COM2, which can reduce the common electrode resistance and ensure a uniform film thickness in the peripheral region BB.

[0105] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, such as Figure 6 and Figure 10 As shown, the array substrate includes a spacer region BD on the other side of the extension direction (column direction Y) of the multiple data lines and located between the first gate drive circuit GOA1 and the second gate drive circuit GOA2. The first common electrode ring COM1 and the second common electrode ring COM2 are electrically connected in the spacer region BD, which facilitates the electrical connection of the first common electrode ring COM1 and the second common electrode ring COM2.

[0106] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, the first common electrode ring and the second common electrode ring can both be disposed on the same layer as the data line, so that the first common electrode ring and the second common electrode ring are directly connected in the interval BD.

[0107] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, the first common electrode ring can be disposed on the same layer as the data line, and the second common electrode ring can be disposed on the same layer as the scan line. In this way, the first common electrode ring and the second common electrode ring need to be connected through a via in the interval area BD.

[0108] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, the first common electrode ring can be disposed on the same layer as the data line, and the second common electrode ring can include a first sub-common electrode ring and a second sub-common electrode ring that are stacked and electrically connected to each other. The first sub-common electrode ring is disposed on the same layer as the data line, and the second sub-common electrode ring is disposed on the same layer as the scan line. In this way, the first sub-common electrode ring and the second common electrode ring are connected through vias, and the first common electrode ring and the first sub-common electrode ring are directly connected in the spacing region BD.

[0109] It should be noted that the above are only some examples of possible film locations for the first and second common electrode rings, and are not limited to these.

[0110] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, such as Figure 11 and Figure 12 As shown, Figure 11 for Figure 6 A magnified schematic diagram of the structure within the dashed box Q. Figure 12 for Figure 6 The enlarged structural diagram within the dashed box R shows the array substrate corresponding to the display area AA, including a common electrode 6. The common electrode 6 is electrically connected to the first common electrode ring COM1 in the peripheral area BB via a via V. When the irregularly shaped display panel is operating, the driver chip applies a common signal to the common electrode 6 through the first common electrode ring COM1.

[0111] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, such as Figure 13 and Figure 14 As shown, Figure 13 for Figure 6 A magnified schematic diagram of the structure within the dashed box K. Figure 14 for Figure 13 The enlarged structural diagram within the dashed box Z shows that the fan-out trace 5 includes an inclined segment 51 surrounding the display area AA and a vertical segment 52 extending along the data line in the direction of S (column direction Y). The vertical segment 52 is located between the display area AA and the driver chip bonding area IC.

[0112] like Figure 15 As shown, Figure 15 for Figure 13The enlarged structural diagram within the dashed box J shows that the inclined segment 51 includes a first sub-inclined segment 511 and a second sub-inclined segment 512. One end of the first sub-inclined segment 511 is electrically connected to one end of the vertical segment 52, and the other end of the vertical segment 52 is electrically connected to the driver chip of the driver chip bonding area IC. The other end of the first sub-inclined segment 511 is connected to one end of the second sub-inclined segment 512 through a corresponding via structure H and a transparent conductive part 7. The other end of the second inclined segment 512 is electrically connected to one end S1 of the data line S. In this embodiment, the fan-out trace 5 uses a via design. On the one hand, it can release static electricity through the via for ESD protection; on the other hand, the electrical connection between the transparent conductive part 7 and the metal trace through the via can reduce the resistance of the fan-out trace 5.

[0113] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, such as Figures 15-18 As shown, Figure 16 for Figure 15 A schematic cross-sectional view along the CC' direction. Figure 17 for Figure 15 Another cross-sectional schematic diagram along the CC' direction. Figure 18 for Figure 15 A cross-sectional schematic diagram along the EE' direction, the gate line G is located between the second substrate 8 (the second substrate of the array substrate) and the data line S, the common electrode 6 is located on the side of the data line S away from the second substrate 8, the transparent conductive part 7 is disposed in the same layer as the common electrode 6, the second sub-tilted segment 512 is disposed in the same layer as the data line S, and the first sub-tilted segment 511 and the vertical segment 52, which are electrically connected to each other, are located in the same film layer.

[0114] A portion of the first sub-tilt segment 511 (represented by 511') is set on the same layer as the scan line G, while another portion of the first sub-tilt segment 511 (represented by 511") is set on the same layer as the data line S. Furthermore, the first sub-tilt segment 511' set on the same layer as the scan line G and the first sub-tilt segment 511" set on the same layer as the data line S are alternately arranged along the row direction X. This layered routing of the first sub-tilt segment 511 within the fan-out area BP reduces the wiring space in the fan-out area BP, thus facilitating a narrow bezel design.

[0115] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, such as Figure 15 and Figure 16 As shown, the array substrate also includes: a gate insulating layer GI located between the gate line G and the data line S, and a passivation layer PVX located between the data line S and the common electrode 6;

[0116] The other end of the first sub-tilted segment 511', which is disposed on the same layer as the scan line G, is electrically connected to the adapter 9 through a via penetrating the gate insulating layer GI. The adapter 9 is electrically connected to one end of the corresponding transparent conductive part 7 through a via penetrating the passivation layer PVX. The other end of the transparent conductive part 7 is electrically connected to one end of the corresponding second sub-tilted segment 512 through a via penetrating the passivation layer PVX. The adapter 9 is disposed on the same layer as the data line S. In this way, the first sub-tilted segment 511' can be electrically connected to the second sub-tilted segment 512 through the via, the adapter 9, the via, the transparent conductive part 7, and the via, thereby achieving the purpose of ESD protection design and reducing the fan-out trace 5.

[0117] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, such as Figure 15 and Figure 17 As shown, the other end of the first sub-tilted segment 511', which is disposed on the same layer as the scan line G, is electrically connected to one end of the corresponding transparent conductive part 7 through a via penetrating the gate insulating layer GI and the passivation layer PVX. The other end of the transparent conductive part 7 is electrically connected to one end of the corresponding second sub-tilted segment 512 through a via penetrating the passivation layer PVX. In this way, the first sub-tilted segment 511' can be electrically connected to the second sub-tilted segment 512 through the via, the transparent conductive part 7, and the via, achieving the purpose of ESD protection design and reducing the fan-out trace 5.

[0118] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, such as Figure 15 and Figure 18 As shown, the other end of the first sub-tilted segment 511”, which is disposed on the same layer as the data line S, is electrically connected to one end of the corresponding transparent conductive part 7 through a via penetrating the passivation layer PVX. The other end of the transparent conductive part 7 is electrically connected to one end of the corresponding second sub-tilted segment 512 through a via penetrating the passivation layer PVX. In this way, the first sub-tilted segment 511” can be electrically connected to the second sub-tilted segment 512 through the via, the transparent conductive part 7, and the via, thereby achieving the purpose of ESD protection design and reducing the fan-out trace 5.

[0119] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, such as Figure 15 and Figure 19 As shown, Figure 19 for Figure 15 The enlarged schematic diagram shows that the via structure H corresponding to the first sub-tilted segment 511' set on the same layer as the scan line S and the via structure H corresponding to the first sub-tilted segment 511” set on the same layer as the data line S are located in different rows. This is beneficial for the layout of the fan-out traces 5 and enables a narrow bezel design.

[0120] In some embodiments, to improve electrostatic discharge capability, in the irregularly shaped display panel provided in the embodiments of this disclosure, such as... Figure 15 , Figure 16 and Figure 19 As shown, the number of vias penetrating the gate insulating layer GI between the first sub-tilted segment 511' and the transition portion 9, which are disposed on the same layer as the scan line G, can be multiple. In this embodiment, two are used as an example. These two vias can be arranged along the row direction. When there are four or more vias penetrating the gate insulating layer GI, the multiple vias can be distributed in an array. The number of vias penetrating the passivation layer PVX between the transition portion 9 and the transparent conductive portion 7 can be multiple. In this embodiment, two are used as an example. These two vias can be arranged along the row direction. When there are four or more vias penetrating the passivation layer PVX, the multiple vias can be distributed in an array. The number of vias penetrating the passivation layer PVX between the transparent conductive portion 7 and the second sub-tilted segment 512 can be multiple. In this embodiment, two are used as an example. These two vias can be arranged along the row direction. When there are four or more vias penetrating the passivation layer PVX, the multiple vias can be distributed in an array.

[0121] In some embodiments, to improve electrostatic discharge capability, in the irregularly shaped display panel provided in the embodiments of this disclosure, such as... Figure 15 , Figure 17 and Figure 19 As shown, the number of vias penetrating the gate insulating layer GI and the passivation layer PVX between the first sub-tilted segment 511' and the transparent conductive portion 7, which are disposed on the same layer as the scan line G, can be multiple. In this embodiment, two are used as an example, and these two vias can be arranged along the row direction. When there are four or more vias penetrating the gate insulating layer GI and the passivation layer PVX, the multiple vias can be distributed in an array. The number of vias penetrating the passivation layer PVX between the transparent conductive portion 7 and the second sub-tilted segment 512 can be multiple. In this embodiment, two are used as an example, and these two vias can be arranged along the row direction. When there are four or more vias penetrating the passivation layer PVX, the multiple vias can be distributed in an array.

[0122] In some embodiments, to improve electrostatic discharge capability, in the irregularly shaped display panel provided in the embodiments of this disclosure, such as... Figure 15 , Figure 18 and Figure 19 As shown, the number of vias penetrating the passivation layer PVX between the first sub-tilted segment 511' and the transparent conductive portion 7 of the data line S layer can be multiple. In this embodiment, two are used as an example, and these two vias can be arranged along the row direction. When there are four or more vias penetrating the passivation layer PVX, the multiple vias can be distributed in an array. The number of vias penetrating the passivation layer PVX between the transparent conductive portion 7 and the second sub-tilted segment 512 can also be multiple. In this embodiment, two are used as an example, and these two vias can be arranged along the row direction. When there are four or more vias penetrating the passivation layer PVX, the multiple vias can be distributed in an array.

[0123] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, such as Figure 15 As shown, the multiple via structures H between each first sub-tilted segment 511 and each second sub-tilted segment 512, along the direction from the edge of the driver chip to the center of the driver chip (i.e., the row direction X), are divided into multiple via regions (three dashed boxes represent three via regions, but not limited to three). Furthermore, along the direction from the edge of the driver chip to the center of the driver chip, adjacent via regions form a stepped structure. This staggered via design is beneficial for narrow bezel design.

[0124] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, such as Figure 15 As shown, multiple virtual traces 500 are provided between the first sub-tilted segments 511, which are electrically connected to adjacent via structures H in two adjacent via regions. The extension direction of the virtual traces 500 is the same as the extension direction of the first sub-tilted segments 511. The virtual traces 500 include multiple segments of discontinuous virtual traces. Specifically, a portion of the virtual traces 500 are disposed on the same layer as the scan line G, and another portion of the virtual traces 500 are disposed on the same layer as the data line S. The virtual traces 500 disposed on the same layer as the scan line G and the virtual traces 500 disposed on the same layer as the data line S are alternately disposed along the row direction X.

[0125] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, such as Figure 20 and Figure 21 As shown, Figure 20 for Figure 14 A schematic diagram of the cross-section along the AA' direction. Figure 21 for Figure 14 The cross-sectional diagram along the BB' direction shows that the width of the inclined segment 51 is smaller than the width of the vertical segment 52, and the gap width between adjacent inclined segments 51 is smaller than the gap width between adjacent vertical segments 52. This is because the width of the bottom border of the peripheral area BB is wider than the width of the left and right borders, so there is more space on the bottom border to arrange the vertical segments 52. Therefore, the width of the vertical segments 52 can be increased to reduce resistance, and the gap width between adjacent vertical segments 52 can be designed to be wider to prevent short circuits between adjacent traces.

[0126] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, such as Figure 20 and Figure 21 As shown, the width of the inclined segment 51 can be about 2.9 μm, the width of the vertical segment 52 can be 6 μm, the gap width between adjacent inclined segments 51 can be 4.35 μm, and the gap width between adjacent vertical segments 52 can be 5 μm. Of course, it is not limited to these, and the design is based on the specific space of the surrounding area B.

[0127] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, such as Figure 21 and Figure 22 As shown, a protective layer 20 is provided on the side of the vertical segment 52 facing away from the second substrate. The protective layer 20 is disposed in the same layer as the common electrode 6. Since the common electrode 6 is generally made of ITO, the protective layer 20 made of ITO can prevent the vertical segment 52 of the underlying metal material from being corroded by water and oxygen. In this way, only the original pattern needs to be changed when forming the common electrode 6, and the pattern of the protective layer 20 and the common electrode 6 can be formed in one patterning process without adding a separate process for preparing the protective layer 20. This simplifies the manufacturing process, saves production costs, and improves production efficiency.

[0128] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, such as Figure 22 As shown, the width of the vertical segment 52 along the X direction can be less than or equal to the width of the protective layer 20 along the X direction, which can further effectively prevent the vertical segment 52 of the metal material from being corroded by water and oxygen.

[0129] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, such as Figure 6 , Figure 12 and Figure 23 As shown, Figure 23 for Figure 6 An enlarged schematic diagram of the anti-static circuit shows that the array substrate, corresponding to the peripheral area BB, also includes an anti-static circuit 200 disposed between the first common electrode ring COM1 and the display area AA and surrounding part of the display area AA. The anti-static circuit 200 is disposed opposite to the driver chip bonding area IC, that is, the anti-static circuit 200 is disposed on the other end S2 side of the data line S.

[0130] The anti-static circuit 200 is electrically connected to the other end S2 of the data line S. The anti-static circuit 200 is used to release the static electricity accumulated on the data line S through the static discharge terminal. Specifically, the structure of the anti-static circuit 200 is as follows: Figure 12 As shown, the anti-static circuit 200 includes multiple sub-circuits connected in series. Each sub-circuit is composed of transistors. Each sub-circuit is electrically connected to the other end S2 of the data line S. The specific structure of the anti-static circuit 200 may be the same as that in related technologies, and will not be described in detail in this disclosure.

[0131] It should be noted that this disclosure adopts... Figure 15 The via structure H connected to one end S1 of the data line and the anti-static circuit 200 connected to the other end S2 of the data line S, as shown, simultaneously release static electricity from the data line S, which can improve the anti-static effect.

[0132] It should be noted that one end S1 of the data line S refers to the end closest to the IC bonding area of ​​the driver chip, and the other end S2 of the data line S refers to the end opposite to one end S1 of the data line S.

[0133] It should be noted that the surrounding area BB can be approximately divided into the top border, bottom border, left border, and right border. The driver chip bonding area IC is located on the bottom border, and the anti-static circuit 200 is located on the top border.

[0134] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, such as Figure 13 , Figure 24 and Figure 25 As shown, Figure 24 for Figure 13 An enlarged planar view within the dashed box N. Figure 25 for Figure 24 A cross-sectional diagram along the FF' direction shows that the driver chip bonding area IC also includes ET test residual traces 300 on both sides along the row direction, and the driver chip bonding area IC also includes an ET test circuit; wherein, the ET test residual traces 300 include a cut residual trace 301 and a lead 302, the cut end of the cut residual trace 301 is wrapped with an insulating layer 400, the end of the cut residual trace 301 away from the cut end is electrically connected to one end of the lead 302, and the other end of the lead 302 is electrically connected to the ET test circuit; wherein,

[0135] The pixel electrode layer is located between the data line S and the second substrate, and the ET test residual trace 300 can be set on the same layer as the pixel electrode layer. Specifically, due to the limited bezel size, it is not possible to design an ET test PAD in an irregularly shaped display panel. This disclosure adopts the method of designing ET test PADs on both sides of the driver chip bonding area IC, so that the display panel can be cut into a rectangular shape for ET testing first, and then cut into an irregularly shaped display panel of the specified size after the test is completed. In addition, this disclosure wraps an insulating layer 400 around the cutting end of the residual trace 301. That is, after cutting off the ET test PAD, it is necessary to apply an insulating layer 400 to the cutting edge for protection to prevent the residual trace 301 from being exposed at the cutting edge. This is because when the product is in a high temperature and high humidity environment, the cutting edge may attract moisture into the panel, causing circuit board corrosion, product abnormalities, and thus reliability issues.

[0136] In some embodiments, the ET test circuit provided in this disclosure may be the same as that in related technologies.

[0137] In some embodiments, in order to shield the internal circuitry of the display panel from interference from external signals, the irregularly shaped display panel provided in the embodiments of this disclosure, such as... Figure 6 and Figure 26As shown, the peripheral area BB also includes a grounding wire GND disposed on the side of the second common electrode ring COM2 away from the display area AA and surrounding the display area AA. The side of the driver chip bonding area IC away from the display area AA includes a flexible circuit board (FPC). The grounding wire GND can be electrically connected to the grounding terminal on the flexible circuit board FPC through silver paste.

[0138] Due to the shape limitations of irregularly shaped display panels, jagged edges are prone to appear at the edges of the display area. To reduce this jagged edge effect, the irregularly shaped display panel provided in this embodiment of the present disclosure, such as... Figures 2-5 and Figure 27 As shown, a portion of the edge display pixel PA located in the display area AA is obscured by the black matrix layer 2 to form an irregular boundary L. In each row of display pixels P, the overlapping area between the edge display pixel PA and the display area AA points towards the direction aa, from small to large. The area obscured by the black matrix layer 2 in each row of display pixels P gradually decreases. Thus, the sub-pixels sp in the edge display pixel PA closer to the irregular boundary L have lower transmittance, reducing the brightness around the irregular boundary L and minimizing jagged edges. Simultaneously, the sub-pixels sp in the edge display pixel PA farther from the irregular boundary L have higher transmittance, allowing for a gradual increase in brightness along the aa direction. This achieves a uniform brightness transition, reduces the brightness difference between adjacent edge display pixels PA, and ensures a smooth brightness transition among multiple sequentially arranged edge display pixels PA in the same row. This further weakens the jagged visual effect of the area where the irregular boundary L is located during display, improving the display effect of the irregular display panel.

[0139] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, such as Figure 13 , Figure 24 and Figure 25 As shown, the area of ​​each sub-pixel sp in the same edge display pixel PA that is blocked by the black matrix layer 2 is the same. This ensures that the light transmittance of each sub-pixel sp in the same edge display pixel PA is the same, thus avoiding the problem of excessive brightness of a single color in the same edge display pixel PA.

[0140] In some embodiments, in the irregularly shaped display panel provided in the present disclosure, such as Figure 13 , Figure 24 and Figure 25 As shown, the area in each sub-pixel sp that is occluded by the black matrix layer 2 is close to the irregular shape boundary. This makes the brightness uniform from the edge of the display area AA towards the center, allowing for a smooth transition in brightness from the edge of the display area AA to the center, further reducing the jaggedness at the irregular shape boundary L.

[0141] Based on the same inventive concept, embodiments of the present invention also provide a display device, including any of the irregularly shaped display panels provided in the embodiments of this disclosure. This display device can be: an in-vehicle display screen, a watch, etc. Implementation of this display device can refer to the embodiments of the irregularly shaped display panels described above; repeated details will not be repeated.

[0142] In some embodiments, the display device provided in the present disclosure may be a liquid crystal display device.

[0143] In some embodiments, the display device provided in the present disclosure can be an in-vehicle display device.

[0144] This disclosure provides an irregularly shaped display panel and display device. By setting virtual pixels around the display area in the peripheral area, i.e., the virtual pixels are located outside the irregular boundary, the etching uniformity of the irregularly shaped display area can be effectively improved, effectively solving the problems of low display quality, reliability and yield of existing automotive irregularly shaped displays.

[0145] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0146] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. An irregularly shaped display panel, wherein, It includes a display area and a peripheral area surrounding the display area, with an irregular boundary between the display area and the peripheral area; the display area includes a plurality of display pixels arranged in an array along the row and column directions, and the display pixels include a plurality of display sub-pixels with different emission colors; the plurality of display pixels include edge display pixels covered by the irregular boundary and regular display pixels not covered by the irregular boundary; The irregularly shaped display panel includes an array substrate and a color filter substrate arranged opposite to and spaced apart, the color filter substrate comprising: A first substrate, corresponding to the peripheral area, has a virtual display area disposed around the display area, the virtual display area including a plurality of virtual pixels disposed around the edge display pixels, the virtual pixels including a plurality of virtual sub-pixels with different emission colors; A black matrix layer is located on the side of the first substrate facing the array substrate. The black matrix layer covers the display area and the virtual display area, and the black matrix layer has an opening corresponding to each display sub-pixel in the display area. Multiple filter structures are located on the side of the black matrix layer away from the first substrate. The filter structures fill the opening in the display area. The filter structures are located on the side of the black matrix layer away from the first substrate in the virtual display area corresponding to the position of the virtual sub-pixel. The array substrate includes a second substrate and a pixel electrode layer disposed on the side of the second substrate facing the color filter substrate; the pixel electrode layer includes display pixel electrodes disposed corresponding to each of the display sub-pixels and virtual pixel electrodes disposed corresponding to some of the virtual sub-pixels, and the virtual pixel electrodes are disposed on one side of the edge of at least one row of display pixel electrodes; the virtual pixel electrodes are blocked by the black matrix layer, and the display pixel electrodes are disposed corresponding to the openings of the black matrix layer; The array substrate, corresponding to the peripheral area, includes: a driver chip bonding area, and a fan-out area located between the driver chip bonding area and the display area and surrounding at least a portion of the display area; the fan-out area includes multiple fan-out traces; wherein... At least a portion of the virtual sub-pixels have an overlapping region in the orthographic projection of the filter structure on the second substrate with at least a portion of the fan-out traces on the second substrate; The orthographic projection of the virtual pixel electrode on the second substrate does not overlap with the orthographic projection of the fan-out trace on the second substrate.

2. The irregularly shaped display panel as described in claim 1, wherein, At least one virtual pixel is provided on one side of the row direction and / or one side of the column direction of each of the edge display pixels.

3. The irregularly shaped display panel as described in claim 1, wherein, The array substrate corresponding to the display area includes: a plurality of scan lines extending along the row direction and arranged along the column direction, and a plurality of data lines extending along the column direction and arranged along the row direction; wherein the plurality of scan lines and the plurality of data lines are insulated from each other and cross to define the plurality of display pixels, and the driver chip bonding area is located on one side of the extension direction of the plurality of data lines; The array substrate also includes a first gate driving circuit and a second gate driving circuit located on both sides of the extension direction of the plurality of scan lines corresponding to the peripheral area. The first gate driving circuit is electrically connected to one end of each scan line, and the second gate driving circuit is electrically connected to the other end of each scan line. The first gate driving circuit is located on the side of a portion of the fan-out area away from the display area, and the second gate driving circuit is located on the side of another portion of the fan-out area away from the display area. Both the first gate driving circuit and the second gate driving circuit are arranged to conform to the display area.

4. The irregularly shaped display panel as described in claim 3, wherein, Both the first gate driving circuit and the second gate driving circuit include multiple shift register units arranged in cascade, and each shift register unit includes a charging transistor disposed near the edge of the peripheral region; wherein, In at least two adjacent shift register units, the width of the charging transistor in one shift register unit is greater than the width of the charging transistor in the other shift register unit, the height of the charging transistor in one shift register unit is less than the height of the charging transistor in the other shift register unit, and the channel width-to-length ratio of the charging transistors in the two adjacent shift register units is the same.

5. The irregularly shaped display panel as described in claim 4, wherein, The array substrate, corresponding to the peripheral area, further includes: a first common electrode ring disposed between the first gate driving circuit, the second gate driving circuit, and the display area; and a second common electrode ring disposed on the side of the first gate driving circuit and the second gate driving circuit away from the display area; the first common electrode ring and the second common electrode ring are electrically connected.

6. The irregularly shaped display panel as described in claim 5, wherein, The array substrate corresponds to the peripheral region including a gap region located on the other side of the extension direction of the plurality of data lines and between the first gate driving circuit and the second gate driving circuit, wherein the first common electrode ring and the second common electrode ring are electrically connected in the gap region.

7. The irregularly shaped display panel as described in claim 6, wherein, The first common electrode ring is disposed on the same layer as the data line; The second common electrode ring is disposed in the same layer as the data line or the scan line; Alternatively, the second common electrode ring may include a first sub-common electrode ring and a second sub-common electrode ring that are stacked and electrically connected to each other, wherein the first sub-common electrode ring is disposed on the same layer as the data line and the second sub-common electrode ring is disposed on the same layer as the scan line.

8. The irregularly shaped display panel as described in claim 7, wherein, The fan-out trace includes an inclined section arranged around the display area and a vertical section arranged along the extension direction of the data line, the vertical section being located between the display area and the driver chip bonding area; The inclined segment includes a first sub-inclined segment and a second sub-inclined segment. One end of the first sub-inclined segment is electrically connected to one end of the vertical segment, and the other end of the vertical segment is electrically connected to the driver chip in the driver chip bonding area. The other end of the first sub-inclined segment is connected to one end of the second sub-inclined segment through a corresponding via structure and a transparent conductive part. The other end of the second sub-inclined segment is electrically connected to one end of the data line.

9. The irregularly shaped display panel as described in claim 8, wherein, The array substrate includes a common electrode corresponding to the display area, and the common electrode is electrically connected to the first common electrode in the peripheral area through a via; The scan line is located between the second substrate and the data line. The common electrode is located on the side of the data line away from the second substrate. The transparent conductive part is disposed in the same layer as the common electrode. The second sub-tilted segment is disposed in the same layer as the data line. The first sub-tilted segment and the vertical segment, which are electrically connected to each other, are located in the same film layer. A portion of the first sub-tilted segment is disposed on the same layer as the scan line, and another portion of the first sub-tilted segment is disposed on the same layer as the data line. The first sub-tilted segments disposed on the same layer as the scan line and the first sub-tilted segments disposed on the same layer as the data line are alternately disposed along the row direction.

10. The irregularly shaped display panel as described in claim 9, wherein, The array substrate further includes: a gate insulating layer located between the scan line and the data line, and a passivation layer located between the data line and the common electrode; The other end of the first sub-tilted segment, which is disposed on the same layer as the scan line, is electrically connected to the adapter through a via penetrating the gate insulating layer. The adapter is electrically connected to one end of the corresponding transparent conductive part through a via penetrating the passivation layer. The other end of the transparent conductive part is electrically connected to one end of the corresponding second sub-tilted segment through a via penetrating the passivation layer. The adapter is disposed on the same layer as the data line. Alternatively, the other end of the first sub-tilted segment disposed on the same layer as the scan line is electrically connected to one end of the corresponding transparent conductive part through a via penetrating the gate insulating layer and the passivation layer, and the other end of the transparent conductive part is electrically connected to one end of the corresponding second sub-tilted segment through a via penetrating the passivation layer.

11. The irregularly shaped display panel as claimed in claim 10, wherein, The other end of the first sub-tilted segment, which is disposed on the same layer as the data line, is electrically connected to one end of the corresponding transparent conductive part through a via penetrating the passivation layer, and the other end of the transparent conductive part is electrically connected to one end of the corresponding second sub-tilted segment through a via penetrating the passivation layer.

12. The irregularly shaped display panel as described in claim 11, wherein, The via structure corresponding to the first sub-tilted segment disposed on the same layer as the scan line and the via structure corresponding to the first sub-tilted segment disposed on the same layer as the data line are located in different rows.

13. The irregularly shaped display panel as described in claim 12, wherein, The first sub-tilted segment and the second sub-tilted segment are divided into multiple via structures along the direction from the edge of the driver chip to the center of the driver chip, and adjacent two via regions form a stepped structure along the direction from the edge of the driver chip to the center of the driver chip.

14. The irregularly shaped display panel as described in claim 13, wherein, Multiple virtual traces are provided between the first sub-tilted segments that are electrically connected to the adjacent via structures of two adjacent via regions. The extension direction of the virtual traces is the same as the extension direction of the first sub-tilted segments. The virtual traces include multiple segments of virtual traces that are disconnected.

15. The irregularly shaped display panel as described in claim 14, wherein, The width of the inclined segment is smaller than the width of the vertical segment, and the gap width between adjacent inclined segments is smaller than the gap width between adjacent vertical segments.

16. The irregularly shaped display panel as claimed in claim 15, wherein, A protective layer is provided on the side of the vertical section away from the second substrate, and the protective layer is disposed in the same layer as the common electrode.

17. The irregularly shaped display panel as claimed in claim 16, wherein, The width of the vertical segment along the row direction is less than or equal to the width of the protective layer along the row direction.

18. The irregularly shaped display panel as claimed in claim 17, wherein, The array substrate also includes an anti-static circuit disposed between the first common electrode ring and the display area and surrounding a portion of the display area, and the anti-static circuit is disposed opposite to the driver chip bonding area. The anti-static circuit is electrically connected to the other end of the data line, and the anti-static circuit is used to release the static electricity accumulated on the data line through the static discharge terminal.

19. The irregularly shaped display panel as claimed in claim 18, wherein, The driver chip bonding area also includes ET test residual traces on both sides along the row direction, and the driver chip bonding area also includes an ET test circuit; wherein, the ET test residual trace includes a cut residual trace and a lead, the cut end of the cut residual trace is wrapped with an insulating layer, the end of the cut residual trace away from the cut end is electrically connected to one end of the lead, and the other end of the lead is electrically connected to the ET test circuit; wherein, The pixel electrode layer is located between the data line and the second substrate. The ET test residual trace is disposed in the same layer as the pixel electrode layer, and the cut end of the ET test residual trace is wrapped with an insulating layer.

20. The irregularly shaped display panel as claimed in claim 19, wherein, The edge display pixels are partially obscured by the black matrix layer in the display area. In each row of display pixels, the overlapping area between the display area and the edge display pixels is from small to large. The area of ​​each edge display pixel obscured by the black matrix layer in each row of display pixels gradually decreases.

21. The irregularly shaped display panel as claimed in claim 20, wherein, The area of ​​each sub-pixel in the same edge display pixel that is occluded by the black matrix layer is the same.

22. The irregularly shaped display panel as claimed in claim 21, wherein, The region of each sub-pixel that is occluded by the black matrix layer is close to the irregular boundary.

23. The irregularly shaped display panel as described in any one of claims 1-22, wherein, The irregularly shaped display panel can be circular or elliptical.

24. A display device, wherein, Including the irregularly shaped display panel as described in any one of claims 1-23.

25. The display device as claimed in claim 24, wherein, The display device is a vehicle-mounted display device.

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