Electronic control device and electronic control system

Abstract

An electronic control device (ECUm) is provided with a processor (204), a communication circuit (202), and a power supply IC (206), the communication circuit (202) sets an activation signal (INH-Vlevel) of the power supply IC (206) as a voltage level signal to an active level when receiving a wake-up command, and the processor (204) transmits a sleep command to the communication circuit (202) and transmits a power supply stop command to the power supply IC (206) when receiving a sleep command via the communication circuit (202). The power supply IC (206) has a priority wake-up processing unit (246) that continues generation of the power supply voltage when an active level of a start-up signal (INH-Vlevel) of the power supply IC (206) is maintained in a case where the power supply IC (206) is to stop the power supply in response to the power supply stop command.

Description

Technical Field

[0001] The present invention relates to an electronic control device and an electronic control system. Background Art

[0002] In recent years, the number of electronic devices installed in vehicles has increased, and with this, the power consumption of electronic control systems has tended to increase. In particular, there is a growing demand to reduce standby current (dark current) during vehicle stop, which is directly related to battery voltage drop.

[0003] As technologies for reducing power consumption of electronic control systems, there are known technologies such as the use of a selective wake-up function that only activates necessary units among multiple ECUs (Electronic Control Units), technologies that put processors such as CPUs (Central Processing Units) and MPUs (Micro Processing Units) into low-power consumption mode, and technologies that effectively use reduced-size sub-CPUs, sub-MPUs, and other sub-processors.

[0004] A technique utilizing the selective wakeup function is described in Patent Document 1, for example.

[0005] In addition, a technique utilizing a low power consumption mode of a processor is described in Patent Document 2, for example.

[0006] In addition, regarding the technology of using a sub-processor, for example, Patent Document 3 is described.

[0007] Prior art literature

[0008] Patent Literature

[0009] Patent Document 1: Japanese Patent Application Laid-Open No. 2022-132970

[0010] Patent Document 2: Japanese Patent Application Laid-Open No. 2016-76066

[0011] Patent Document 3: Japanese Patent Application Laid-Open No. 2017-144893 Summary of the Invention

[0012] Problems to be solved by the invention

[0013] However, the current situation requires further reductions in power consumption. Therefore, it is imperative to realize electronic control devices and electronic control systems that can further reduce power consumption while maintaining the necessary functions and reliability.

[0014] In addition, for example, when the power control ECU as the upper power control unit executes power control of multiple lower power control units, the power control ECU issues a sleep command to a certain ECU, but due to rapid changes in the vehicle condition, etc., a situation may arise in which a wake-up command needs to be issued to the same ECU immediately afterwards.

[0015] In this case, since it takes a certain amount of time to stop the power supply IC (integrated circuit) included in the ECU in response to the sleep command, a wake-up command may be received during the process of stopping the power supply IC, and the processing based on the sleep command and the processing based on the wake-up command received after the sleep command may conflict with each other.

[0016] In this case, it is preferable to prioritize processing based on the latest command, namely the wake-up command, and stop processing based on the currently executing sleep command to avoid unnecessary power outage. In order to perform such advanced processing, it is conceivable to utilize a structure that uses a sub-processor in addition to the main processor.

[0017] However, sub-processors are redundant, and their use increases power consumption. In recent years, electronic control systems have employed numerous electronic control units (ECUs). Increased power consumption in a single ECU leads to a dramatic increase in overall power consumption in the electronic control system, contradicting the aforementioned demand for low power consumption.

[0018] Patent Documents 1 to 3 mentioned above do not describe such a problem, nor do they mention a countermeasure therefor.

[0019] The present invention has been made in view of the above-mentioned problems, and one object of the present invention is to promote low power consumption of an electronic control device and to avoid an unexpected power shutdown when a communication circuit receives a wake-up command during power shutdown processing of a power IC.

[0020] Other objects of the present invention will become apparent to those skilled in the art by referring to the following exemplary embodiments and best mode and the accompanying drawings.

[0021] Means for solving problems

[0022] Hereinafter, in order to facilitate understanding of the outline of the present invention, embodiments according to the present invention are exemplified.

[0023] In a first aspect of the present invention, an electronic control device connected to a network includes: a processor that controls the operation of the electronic control device; a communication circuit that receives sleep commands and wakeup commands from other devices connected via the network and has a first interface for communicating with the processor; and a power supply IC that generates a power supply voltage and has a second interface for communicating with the processor. The communication circuit includes an activation signal generating unit that, upon receiving the wakeup command, sets an activation signal of the power supply IC, which is a voltage level signal, to an active level, and transmits the received sleep command to the processor via the first interface. Upon receiving the sleep command transmitted from the communication circuit, the processor transmits a sleep instruction to the communication circuit and a power stop instruction to the power supply IC. The power supply IC includes a priority wakeup processing unit that, when the power supply IC is to stop power in response to the power stop instruction transmitted from the processor, prioritizes the active level of the activation signal of the power supply IC over the power stop instruction, while the active level of the activation signal of the power supply IC transmitted from the communication circuit is maintained. The priority wakeup processing unit activates the power supply IC and continues generating the power supply voltage.

[0024] In the first aspect, the power supply IC includes a priority wakeup processing unit.

[0025] When a process based on a sleep command and a process based on a wakeup command received after the sleep command conflict with each other, the priority wakeup processing unit of the power supply IC performs a process (arbitration process) that prioritizes the latest wakeup command.

[0026] Therefore, a sub-processor is unnecessary, and since a sub-processor and a power supply for the sub-processor can be eliminated, power consumption can be reduced.

[0027] In addition, the communication circuit includes an activation signal generating unit.

[0028] If a wakeup command is received while the power supply IC is in the process of stopping, the communication circuit's activation signal generator sets the power supply IC's activation signal, which is a voltage-level signal, to an active level. This gives the wakeup command priority over the sleep command, and the power supply IC's priority wakeup processing unit continues generating the power supply voltage.

[0029] As the power IC startup signal, an edge-triggered startup signal is not used, but a voltage level signal is used. When a wake-up command is received, the communication circuit only needs to change the voltage level of the power IC startup signal to a valid level.

[0030] This simplifies the structure and eliminates the need for complex signal processing, contributing to smaller and lower-power electronic control units (ECUs).

[0031] In a second aspect dependent on the first aspect, the activation signal of the power supply IC may be transmitted from the communication circuit to the power supply IC via a signal path that does not pass through the sub-processor.

[0032] In the second embodiment, no sub-processor exists in the transmission path of the power IC's activation signal. Therefore, no sub-processor or sub-processor power supply is required, thus achieving reduced power consumption, simplified structure, and reduced software burden.

[0033] In a third aspect dependent on the first or second aspect, the first interface and the second interface may be communication interfaces that transmit and receive data in synchronization with a rising edge or a falling edge of a clock.

[0034] In the third embodiment, the first and second interfaces provided by the communication circuit for communicating data with the processor are synchronous communication interfaces that transfer data in synchronization with clock edges. For example, a highly reliable communication interface such as SPI (Serial Peripheral Interface) can be used.

[0035] As described in the first embodiment, data communication at a voltage level is performed between the communication circuit and the power supply IC.

[0036] That is, the communication circuit of this embodiment has a new structure that includes both a data communication interface for performing synchronous communication with a processor and a signal output terminal (in a broad sense, a data communication interface) for performing voltage-level data communication with a power supply IC.

[0037] Furthermore, if synchronous communication is used for communication with the power supply IC, if the power supply IC is in the power-off process at the time of data transmission, the data transmission at that time is invalid, and therefore the power supply IC cannot be notified of the receipt of the wake-up command.

[0038] If the signal is a voltage-level signal, the changed voltage level is maintained after the signal changes. This allows the power supply IC to determine the voltage level of the received signal with sufficient time. In other words, the power supply IC can determine the voltage level of the received startup signal at any timing. This allows the power supply IC to detect the receipt of a wake-up command.

[0039] In a fourth mode belonging to any one of the first to third modes, a monitoring circuit for the startup signal of the power supply IC that monitors the level of the startup signal of the power supply IC may be provided between a signal path that transmits the startup signal of the power supply IC output from the communication circuit to the power supply IC and the processor.

[0040] According to the fourth aspect, the processor can detect, via the monitoring circuit, whether the activation signal of the power supply IC is at an active level or an inactive level, for example.

[0041] For example, when the communication circuit receives a sleep command, the sleep command is sent to the processor, and the processor, having interpreted the sleep command, executes a process of sending a sleep instruction to the communication circuit.

[0042] When the communication circuit enters the sleep state, the activation signal of the power supply IC changes from active to inactive. The processor detects this voltage level change via the monitoring circuit and can determine whether the communication circuit is operating correctly according to the sleep command.

[0043] If the power supply IC's activation signal does not change in voltage level even after the processor issues a sleep command to the communication circuit, it can be assumed that there is an abnormality in the communication circuit, a fault in the communication path between the communication circuit and the processor, or a fault in the monitoring circuit, and prescribed countermeasures can be implemented. This helps prevent degradation of the electronic control device's reliability.

[0044] In a fifth mode belonging to any one of the first to fourth modes, the power supply IC may also have a reset unit that outputs a reset signal for resetting the processor. When the priority wake-up processing unit prioritizes starting the power supply IC based on the fact that the start signal of the power supply IC is valid so as to continue generating the power supply voltage, the power supply IC causes the reset unit to output the reset signal, thereby causing the processor to initially start up.

[0045] In the fifth aspect, the power supply IC includes a reset unit. When the power supply IC continues to generate the power supply voltage, the power supply voltage is also supplied to the processor, and the processor continues the operation state.

[0046] In this embodiment, at this time, the reset unit outputs a reset signal to the processor to reset the processor.

[0047] In other words, upon receipt of the wake-up command, the processor is reset and starts operating from an initialized state (initial startup).

[0048] When the processor is reset, for example, various counters, timers, input / output ports, etc. are initialized, and the internal state of the processor returns to an initial predetermined state.

[0049] Thus, even when a partial failure occurs inside the processor, for example, the processor can be reset to return to an initial predetermined state, and thus various programs can be normally activated.

[0050] This reduces the possibility of a future malfunction (failure) of the processor, thus helping to suppress a decrease in the reliability of the processor.

[0051] In a sixth aspect dependent on the fifth aspect, the power supply IC may cause the reset unit to output the reset signal by transitioning the power supply IC to an initial state.

[0052] In the sixth aspect, the power supply IC causes the reset unit to output the reset signal by transitioning its internal state to the initial state.

[0053] In other words, the reset signal can be outputted by utilizing the power-on reset function of the power IC, ie, the function of outputting a reset signal to the processor when the power is turned on and the processor starts from the initial state.

[0054] According to this aspect, the reset signal can be outputted by utilizing the existing functions of the power supply IC, and special processing for outputting the reset signal is unnecessary, thereby reducing the burden on the power supply IC.

[0055] In a seventh aspect of the present invention, in the electronic control system of the present invention, a plurality of electronic control devices according to any one of the first to sixth aspects are connected to the network.

[0056] According to the seventh aspect, an electronic control system is constructed by connecting a plurality of electronic control devices according to the present invention to a network.

[0057] As described above, the electronic control device of the present invention has a function of further reducing power consumption while maintaining necessary functions and reliability.

[0058] Therefore, it is possible to achieve an effect of significantly reducing power consumption of the entire electronic control system while maintaining reliability.

[0059] In recent years, the number of electronic devices installed in vehicles has increased, and with this, the power consumption of electronic control systems has tended to increase. In particular, there is a growing demand for reducing standby current (dark current) during vehicle stop, which is directly related to a drop in battery voltage.

[0060] According to this embodiment, the above-mentioned requirements can be met, which contributes to the realization of electric vehicles that can operate for a long time on a single battery charge, for example.

[0061] Effects of the Invention

[0062] According to the present invention, it is possible to promote low power consumption in electronic control devices and electronic control systems. In addition, when the communication circuit receives a wake-up command during the power supply IC power-off process, it is possible to avoid an unexpected power-off.

[0063] It is easily understood by those skilled in the art that the embodiments of the present invention described above can be further modified without departing from the spirit of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 This is a diagram showing an example of a configuration of an electronic control system using CAN (Controller Area Network).

[0065] Figure 2 The structure of the first comparative example with a sub-processor is compared with the structure without a sub-processor (in Figure 1 The figure is shown for comparison with the structure adopted in .

[0066] Figure 3 This figure shows the configuration and operation of an electronic control device in a second comparative example that does not use a sub-processor and uses an edge-triggered signal as a start-up signal for a power supply IC (Integrated Circuit).

[0067] Figure 4 This is a diagram showing an example of a specific configuration of an electronic control device in an embodiment of the present invention that does not use a sub-processor and uses a voltage level signal as an activation signal for a power supply IC.

[0068] Figure 5 1 is a diagram illustrating a wake-up operation during power outage in the electronic control device according to the embodiment of the present invention.

[0069] Figure 6 This is a diagram showing an example of the configuration of an electronic control device to which a monitoring circuit is added.

[0070] Figure 7 It shows Figure 6 Flowchart of an example of a sleep and wakeup process sequence in an electronic control device. DETAILED DESCRIPTION

[0071] The preferred embodiment described below is intended to facilitate understanding of the present invention. Therefore, those skilled in the art should note that the present invention is not unduly limited by the embodiment described below. Hereinafter, one embodiment of the present invention will be described with reference to the accompanying drawings.

[0072] Figure 1 is a diagram showing an example of the configuration of an electronic control system using CAN (Controller Area Network).

[0073] exist Figure 1 In the embodiment, the electronic control system 150 is mounted on the vehicle. However, this is just an example and the present invention is not limited to this example.

[0074] CAN bus (in Figure 1 The CAN-BUS is a two-wire communication bus consisting of a high-level CANH and a low-level CANL. Terminal resistors 30a and 30b are provided at the ends of CANH and CANL.

[0075] There are multiple ECUs (Electronic Control Units) connected to the CAN bus. Figure 1 In the system, ECU1 to ECUn (n is a natural number greater than or equal to 3) are provided as a plurality of ECUs.

[0076] ECU1 to ECUn are mounted on a vehicle and constitute an ECU group 200. The ECUs can realize one or more functions in cooperation with each other via an in-vehicle network (CAN bus), for example.

[0077] Furthermore, a power control ECU 102, a higher-level ECU capable of selectively controlling the sleep / wakeup of ECUs 1 through ECUn, is connected to the CAN bus. This power control ECU 102 is a higher-level unit responsible for power management of the lower-level ECUs 1 through ECUn and corresponds to "another device connected to the network (CAN bus)."

[0078] The power supply control ECU 102 includes a selective wakeup / sleep communication unit 104. Various commands are supplied to the power supply control ECU 102 from the higher-level device 10, and various sensor signals are supplied to the power supply control ECU 102 from the sensor 20.

[0079] The selective wakeup / sleep communication unit 104 can issue a selective sleep command PF1 and a selective wakeup command PF2 to an ECU m (m is a natural number satisfying 1<m<n).

[0080] The battery BATT supplies power to each of the ECUs 1 to ECUn via a power line 40 .

[0081] exist Figure 1 In the example shown in FIG. 1 , ECU1 to ECUn each have the same structure. In each ECU, the same reference numerals are used to denote the same parts. Below, the internal structure of ECUm is described as an example.

[0082] The ECU m includes: communication terminals D1 and D2 for connection to the CAN bus; a power supply terminal D3 connected to the power line 40; a CAN communication circuit (labeled "CAN" in the figure) 202; a CPU (Central Processing Unit; hereinafter referred to as "CPU") 204 as a processor; a power supply IC (Integrated Circuit) 206 that generates and outputs a power supply voltage VCC; a first SPI bus (labeled "SPI-BUS1" in the figure) for communication between the CAN communication circuit 202 and the CPU 204; a second SPI bus (labeled "SPI-BUS2" in the figure) for communication between the power supply IC 206 and the CPU 204; and a signal path (in other words, a signal path (signal line) L1) that supplies the power supply IC's activation signal INH-Vlevel, which is a voltage level signal output from the CAN communication circuit, to the power supply IC 206. The power supply IC may also be referred to as a power supply circuit.

[0083] In the following description, the CAN communication circuit may be simply referred to as a communication circuit or a communication unit. The CAN communication circuit 202 has an INH terminal that outputs an activation signal INH-Vlevel of the power supply IC as a voltage level signal.

[0084] In addition, the power supply IC 206 includes an ENA terminal for receiving a start-up signal INH-Vlevel of the power supply IC and a VC terminal for outputting a power supply voltage VCC.

[0085] The CAN communication circuit 202 has a selective reception function of detecting whether or not it has been selected upon receiving the selective sleep command PF1 and the selective wakeup command PF2 issued by the power supply control ECU 102 and executing prescribed processing for each command.

[0086] When receiving the sleep command PF1 , the CAN communication circuit 202 transmits the received sleep command PF1 to the CPU 204 .

[0087] The CPU 204 interprets the received sleep command PF1 to identify the content of the command, and sends a sleep command to the CAN communication circuit 202 via the first SPI bus (SPI-BUS1), and also sends a power stop command to the power IC 206 via the second SPI bus (SPI-BUS2).

[0088] The CAN communication circuit 202 transitions to a sleep mode (standby mode or low power consumption mode) upon receiving a sleep command from the CPU 204. Furthermore, the power supply IC 206, upon receiving a power stop command from the CPU 204, executes a process for stopping the generation of the power supply voltage VCC (which may be a power-off process or a transition to standby mode).

[0089] In addition, when the CAN communication circuit 202 receives the selective wake-up command PF2 , it detects whether the wake-up command PF2 is a wake-up command that specifies the CAN communication circuit 202 itself.

[0090] Since the CPU 204 is in the sleep state, the CAN communication circuit 202 does not notify the CPU 204 of receipt of the wake-up command. Instead, it changes the power supply IC activation signal INH-Vlevel, which is a voltage level signal, from the inactive level (L) to the active level (H).

[0091] When the power supply IC 206 detects that the power supply IC activation signal INH-Vlevel is at an active level, it starts generating and outputting the power supply voltage VCC.

[0092] In addition, at this time, the power supply IC 206 may output a reset signal RES to the CPU 204 to perform initial startup of the CPU 204. This will be described later.

[0093] Furthermore, there may be a case where the CAN communication circuit 202 receives the wakeup command PF2 right after receiving the sleep command PF1 .

[0094] In this case, the power supply IC 206 receives the wakeup command while the power supply IC 206 is executing the power supply stop process in response to the power supply stop instruction from the CPU 204 , and the activation signal INH-Vlevel of the power supply IC becomes active.

[0095] In other words, the process based on the sleep command and the process based on the wakeup command received after the sleep command conflict with each other.

[0096] The power IC 206 has a priority wake-up processing unit ( Figure 1 Not shown in the figure, Figure 4 The priority wake-up processing unit 246 prioritizes processing based on the latest command, namely the wake-up command, and stops the processing based on the sleep command in progress, thereby performing the following processing: avoiding unnecessary power outage. The details of this processing will be described later.

[0097] That is to say, in Figure 1In the ECU m of the present invention shown in , when processing based on a sleep command and processing based on a wakeup command received after the sleep command conflict with each other, the power supply IC 206 performs arbitration processing for eliminating the conflicting state.

[0098] A configuration in which the sub-CPU executes such mediation processing is also conceivable, but in this case, power consumption increases.

[0099] Therefore, in Figure 1 In the electronic control system, the conflict between the above-mentioned contradictory commands can be dealt with by a simple and inexpensive structure that does not use a sub-CPU.

[0100] Next, refer to Figure 2 . Figure 2 The structure of the first comparative example with a sub-processor and the structure without a sub-processor (in Figure 1 The structure used in the comparison is shown in the figure. Figure 2 In A-1 and A-2, Figure 1 The same reference numerals are used for the same parts, and this also applies to the other figures.

[0101] In addition, Figure 2 In A-1 and A-2, for ease of explanation, the battery BATT is depicted as being directly connected to the power supply terminal D3 of the ECUm. Figures 3 to 6 , the same is true in FIG8 .

[0102] Figure 2 The first comparative example A-1 is a configuration developed by the present inventors before the present invention and is not a publicly known example.

[0103] exist Figure 2 A-1 of FIG. 2 includes a sub-power supply 207 and a sub-CPU (sub-processor) 209. The signal output from the CAN communication circuit 202 is not a voltage level signal but an edge trigger signal INH-edge having a rising edge or a falling edge for data transmission.

[0104] When the CAN communication circuit 202 receives a wakeup command during the stop process of the power supply IC 206 , the CAN communication circuit 202 supplies an edge trigger signal INH-edge to the sub-CPU 209 to notify the sub-CPU 209 of the receipt of the wakeup command.

[0105] Sub-CPU 209 monitors the power supply voltage VCC generated by the power supply IC. Upon detecting that power supply voltage VCC has been stopped in power supply IC 206 in response to a sleep command from CPU 204, sub-CPU 209 supplies edge trigger signal SO-INH-edge to power supply IC 206, thereby restarting the power supply IC. This allows for conflict between a sleep command and a wakeup command.

[0106] However, the sub-power supply 207 and the sub-CPU (sub-processor) 209 can be said to be redundantly configured, and if the sub-power supply 207 and the sub-CPU 209 are used, power consumption increases.

[0107] In recent years, electronic control systems use a large number of electronic control devices (ECUs). When the power consumption of one electronic control device increases, the power consumption of the entire electronic control system increases dramatically, which runs counter to the aforementioned demand for low power consumption.

[0108] Therefore, if Figure 2 As shown in A-2 of FIG. 1 , when the sub power supply 207 and the sub CPU (sub processor) 209 are removed and the sleep command and the wakeup command conflict with each other, the power supply IC 206 performs arbitration processing.

[0109] In addition, Figure 2 In A-2, the CAN communication circuit 202 supplies the power supply IC activation signal INH-Vlevel, which is a voltage level signal, to the power supply IC 206. Furthermore, the power supply IC 206 supplies the reset signal RES to the CPU 204, and causes the CPU 204 to perform initial activation.

[0110] Compare Figure 2 From A-1 and A-2, we can see that Figure 2 The structure of the A-2 is simplified, thus achieving low power consumption, miniaturization and low cost.

[0111] On the other hand, in the present invention, the reliability of ECU is also fully considered. Figure 2 It is not described in A-1, but as described below Figure 6 As described above, a monitoring circuit 260 that monitors the power supply IC startup signal INH-V level may be provided to identify the level of the power supply IC startup signal and perform failure diagnosis of the related circuit.

[0112] Furthermore, as described above, by resetting the CPU 204 and performing initial startup, various programs can be started normally, which helps reduce the possibility of an abnormality (failure) occurring in the processor in the future.

[0113] As described above, in the electronic control unit (ECU) of the present invention, it is possible to significantly reduce power consumption while ensuring necessary reliability, and further achieve structural simplification, miniaturization, and cost reduction.

[0114] Next, we will explain why, in the present invention, a voltage-level signal is used instead of an edge-triggered signal as the power IC's startup signal. Based on this conclusion, using an edge-triggered signal can lead to arbitration failure and unnecessary power shutdown if a sleep command and a wake-up command conflict. This point will be explained in detail.

[0115] Reference Figure 3 . Figure 3 This figure shows the configuration and operation of an electronic control device in a second comparative example that does not use a sub-processor and uses an edge-triggered signal as a start-up signal for a power supply IC.

[0116] Figure 3 The second comparative example shown in A-1 is a structure developed by the present inventors before the present invention and is not a publicly known example.

[0117] exist Figure 3 In the second comparative example shown in A-1, Figure 2 The voltage level signal ENH-Vlevel in the configuration of the present invention described in A-2 is replaced by an edge trigger signal ENH-edge.

[0118] exist Figure 3 The left side of A-2 shows a timing chart showing operations in a normal wake-up / sleep process.

[0119] For example, when power is supplied from the battery BATT at time t1, the power IC 206 of the ECU m generates and outputs the power voltage VCC. Accordingly, the power IC activation signal INH-edge output from the CAN communication circuit 202 changes from L level (inactive level) to H level (active level).

[0120] Furthermore, upon receiving the sleep command, the CPU 204 transmits a sleep instruction to the CAN communication circuit 202 at time t2 and transmits a power stop instruction to the power IC 206 at time t3.

[0121] At time t4, in response to the sleep command, the activation signal INH of the power supply IC changes to L level (inactive level). Also, at time t4, in response to the power stop command, the generation of the power supply voltage VCC is stopped.

[0122] exist Figure 3 The right side of A-2 shows a timing chart showing an operation when a wake-up command is received while the power supply IC is executing the power stop process.

[0123] At time t5 , generation of the power supply voltage VCC starts, and the activation signal INH-edge of the power supply IC changes from the L level to the H level.

[0124] Upon receiving the sleep command, CPU 204 transmits a sleep instruction to CAN communication circuit 202 at time t6 and transmits a power stop instruction to power IC 206 at time t7. In response to the sleep instruction at time t6, activation signal INH-edge of the power IC changes to L level.

[0125] The period from time t7 to time t9 is a period during which the power supply IC 206 executes the power supply stop process.

[0126] At time t8 during this period, upon receiving the wakeup command, the power supply IC's enable signal INH-edge changes to an H level, generating a rising edge. In principle, the power supply IC 206 would detect the H level of the enable signal INH-edge in synchronization with this rising edge, and would recognize that the wakeup command had been received.

[0127] However, at time t8, the power supply IC 206 is in the process of stopping the power supply, and therefore, it cannot be detected that the activation signal INH-edge of the power supply IC is at the H level at time t8.

[0128] Therefore, at time t9, the generation of the power supply voltage VCC is stopped in accordance with the sleep command. In other words, an unnecessary power outage occurs. In other words, the wake-up during the power outage fails.

[0129] Therefore, in the present invention, the power supply IC's activation signal is changed from an edge-triggered signal (INH-edge) to a voltage-level signal (INH-Vlevel). A voltage-level signal maintains the changed voltage level after the activation signal changes, thus providing the power supply IC 206 with a time margin for determining the voltage level of the received activation signal.

[0130] That is, the power IC 206 can determine the voltage level of the received start signal at any timing. For example, the power IC 206 detects the voltage level of the start signal at the end of the sleep instruction period from the CPU 204. Therefore, the power IC 206 can know that the wake-up command has been received. For details on this, see Figure 5 Provide explanation.

[0131] Next, refer to Figure 4 . Figure 4This is a diagram showing an example of a specific structure of an electronic control device in an embodiment of the present invention that does not use a sub-processor and uses a voltage level signal as a start-up signal for a power supply IC. Figure 4 , the same reference numerals are given to the same parts as those in the above-mentioned figures.

[0132] The CAN communication circuit 202 includes a common mode filter 220 for removing noise, a transceiver 222 , a CAN controller 224 , a first SPI interface (I / F) 228 , and an activation signal generating unit 228 that generates and outputs an activation signal ENH-Vlevel for the power supply IC as a voltage level signal.

[0133] The power IC's activation signal ENH-Vlevel is sent to the power IC 206 via the signal path (signal line) L1 where no sub-CPU (sub-processor) exists. Eliminating the need for a sub-CPU and its power supply reduces power consumption, simplifies the structure, and reduces software load.

[0134] In addition, the power supply IC 206 includes: a start signal receiving unit 240, which receives the start signal INH-Vtlevel of the power supply IC; a determination unit 242, which has a comparator 244 that compares the received start signal INH-Vtlevel of the power supply IC with the reference voltage Vref, thereby determining whether the received start signal ENH-Vtlevel of the power supply IC is an invalid level (L) or a valid level (H); a priority wake-up processing unit 246; a power supply generating unit 248, which generates a power supply voltage VCC; a reset unit (RS) 250, which outputs a reset signal RES to the CPU 204; and a second SPI interface unit (I / F) 252.

[0135] The first SPI interface (I / F) 226 and the second SPI interface (I / F) 252 are sometimes referred to simply as the first interface and the second interface. The first SPI interface (I / F) 226 and the second SPI interface (I / F) 252 are synchronous data communication interfaces that transmit data in synchronization with clock edges. By including these interfaces, the CAN communication circuit 202 can utilize the SPI, a highly reliable communication interface.

[0136] The CAN communication circuit 202 has a new structure including both a data communication interface 226 for performing synchronous communication with the CPU 204 and a signal output terminal INH (in a broad sense, a data communication interface) for performing voltage-level data communication with the power supply IC 206 .

[0137] Furthermore, the first SPI bus SPI-BUS1 and the second SPI bus SPI-BUS2 include a communication line for a data transmission clock SCLK, a communication line for input data MOSI, a communication line for output data MISO, and a communication line for a chip select signal CS. The input data MOSI and the output data MISO are transmitted in synchronization with the rising or falling edge of the clock SCLK.

[0138] In addition, the CPU 204 includes SPI interface units 227 and 253 .

[0139] Upon receiving the wake-up command, the activation signal generating unit 228 in the CAN communication circuit 202 sets the activation signal INH-Vlevel of the power supply IC, which is a voltage level signal, to an active level (H level).

[0140] Furthermore, when receiving the sleep command, the CAN communication circuit 202 transmits the received sleep command to the CPU 204 via the first SPI bus SPI-BUS1.

[0141] Upon receiving the sleep command transmitted from the CAN communication circuit 202 , the CPU 204 interprets the command, transmits a sleep instruction to the CAN communication circuit 202 , and transmits a power stop instruction to the power IC 206 .

[0142] When the power supply IC 206 is about to stop the power supply in response to the power stop instruction sent from the CPU 204, the priority wake-up processing unit 246 determines whether the start signal INH-Vlevel of the power supply IC sent from the CAN communication circuit 202 is a valid level (H level), in other words, whether the valid level (H level) is maintained.

[0143] When the active level (H level) is maintained, the priority wakeup processing unit 246 prioritizes the active level of the power IC activation signal INH-Vtlevel over the power stop command and activates the power IC 206 to continue generating the power supply voltage VCC.

[0144] By using a voltage level signal instead of an edge-triggered start signal as the start signal for the power IC 206 , the voltage level is maintained even after receiving the sleep command, thereby providing a time margin for detecting the active level in the power IC 206 .

[0145] In other words, the priority wakeup processing unit 246 can determine whether the power supply IC's activation signal INH-Vlevel is at an active level, for example, when the power supply is about to be shut down. This determination allows the power supply IC 206 to detect receipt of the wakeup command. Consequently, generation of the power supply voltage VCC continues, preventing unnecessary power shutdown.

[0146] Figure 4 The ECUm has a simplified structure and does not require complex signal processing. This contributes to the miniaturization and low power consumption of the electronic control unit (ECU).

[0147] Furthermore, the power IC 206 includes a reset section (RS) 250. When the power IC 206 continues to generate the power voltage, the power voltage VCC is also supplied to the CPU 204, and the operation state of the CPU 204 continues.

[0148] In this embodiment, at this time, the reset unit (RS) 250 outputs a reset signal RES to the CPU 204 to reset the CPU 204 .

[0149] In other words, upon receipt of the wake-up command, the CPU 204 is reset and starts operating from an initialized state (initial startup).

[0150] When the CPU 204 is reset, for example, various counters, timers, input / output ports, etc. are initialized, and the internal state of the CPU 204 returns to an initial predetermined state.

[0151] Thus, even when a partial failure occurs inside the CPU 204, for example, the CPU 204 can be reset to return to an initial predetermined state, and thus various programs can be started normally.

[0152] This reduces the possibility of a future processor malfunction (failure), thus helping to suppress a decrease in processor reliability.

[0153] Furthermore, the power IC 206 can cause the reset portion (RS) 250 to output the reset signal RES by transitioning the state of the power IC 206 to the initial state.

[0154] In other words, the reset signal RES can be outputted by utilizing the power-on reset function of the power IC 206 , ie, the function of outputting the reset signal RES to the CPU 204 when the power is turned on and the CPU 204 starts up from the initial state.

[0155] In this case, the reset signal can be outputted by utilizing the existing function of the power supply IC 206 , and no special processing for outputting the reset signal is required, thereby reducing the burden on the power supply IC 206 .

[0156] Next, refer to Figure 5 . Figure 5 This is a diagram showing a wake-up operation during power outage in the electronic control device according to the embodiment of the present invention.

[0157] Figure 5 The A-1 is Figure 4 The structure of the figure is simplified and is the same as that shown before. Figure 2 A-2 is substantially the same structure. Figure 5 A-2 of FIG. 1 shows a timing chart showing a wake-up operation during power outage.

[0158] At time t10 , the power supply voltage VCC reaches 5 V, and accordingly, the activation signal INH-Vlevel of the power supply IC reaches an active level (H level).

[0159] Furthermore, the voltage of the ENA terminal of the power supply IC 206 changes in accordance with the voltage level of the activation signal INH-Vlevel of the power supply IC.

[0160] At time t11, the reset signal RES changes from L to H. At time t12, a sleep command is output from the CPU 204. In conjunction with this, at time t13, the activation signal INH-Vtlevel of the power supply IC becomes an inactive level (L level).

[0161] Furthermore, at time t13, a power stop command is output from the CPU 204. Time t13 to time t15 constitutes a power stop processing period T1.

[0162] At time t14, a wake-up command is received. Accordingly, at time t14, the activation signal INH-Vlevel of the power supply IC becomes active (H level). This active (H level) continues during the second half of the power-off processing period T1, period T2.

[0163] At time t15, the end of power down processing period T1, the power supply IC's activation signal INH-Vlevel remains active (H level). Therefore, priority wakeup processing unit 246 of power supply IC 206 prioritizes processing based on the wakeup command. Consequently, power supply voltage VCC remains at 5V even after time t15, preventing unnecessary power downtime.

[0164] At time t15, the reset signal RES changes from a low level to a high level, generating a rising edge. This resets and initializes the CPU 204. In other words, the initial startup of the CPU 204 is achieved.

[0165] Next, refer to Figure 6 . Figure 6This is a diagram showing an example of the configuration of an electronic control device to which a monitoring circuit is added.

[0166] exist Figure 6 In, right Figure 5 The configuration shown in A-1 is supplemented with a monitoring circuit 260 for the startup signal of the power supply IC (hereinafter simply referred to as a monitoring circuit).

[0167] The monitoring circuit 260 is provided between the CPU 204 and a signal path L1 that transmits the power supply IC activation signal INH-Vlevel output from the CAN communication circuit 202 to the power supply IC 206 .

[0168] The monitoring circuit 260 includes a voltage holding circuit including a resistor R1 and a capacitor C1 , a base resistor R2 , an NPN transistor TR1 , a load resistor R3 , and a bias resistor R4 for generating a bias voltage between the base and emitter of the NPN transistor TR1 .

[0169] When the activation signal INH-Vlevel of the power supply IC is at an inactive level (L level), the NPN transistor TR1 is turned off, and the monitoring terminal CH of the CPU 204 becomes at the level (H) of the power supply voltage VCC.

[0170] On the other hand, when the power supply IC's activation signal INH-Vlevel is active (H level), NPN transistor TR1 turns on, causing collector current to flow through load resistor R3, generating a voltage drop. Consequently, the CPU 204's monitoring terminal CH becomes a voltage (L) obtained by subtracting the voltage drop from the power supply voltage VCC.

[0171] That is, the CPU 204 can monitor the voltage level of the power supply IC's activation signal INH-Vlevel by detecting the voltage of the monitoring terminal CH. That is, the CPU 204 can detect, via the monitoring circuit 260, whether the power supply IC's activation signal INH-Vlevel is at an active level (H) or an inactive level (L).

[0172] For example, when the CAN communication circuit 202 receives a sleep command, the sleep command is sent to the CPU 204 as described above, and the CPU 204 interprets the sleep command and executes a process of sending a sleep instruction to the CAN communication circuit 202 .

[0173] When the CAN communication circuit 202 enters the sleep state, the activation signal INH-Vlevel of the power supply IC changes from the active level (H) to the inactive level (L).

[0174] The CPU 204 detects the occurrence of the change in voltage level via the monitoring circuit 260 , thereby being able to determine whether the CAN communication circuit 202 is operating correctly in accordance with the sleep command.

[0175] Assuming that the voltage level of the startup signal INH-Vlevel of the power supply IC does not change even after the CPU 204 issues a sleep command to the CAN communication circuit 202, it can be estimated that there is an abnormality in the CAN communication circuit 202, or an abnormality in the communication path (SPI-BUS1) between the CAN communication circuit 202 and the CPU 204, or an abnormality in the monitoring circuit 260, and the prescribed countermeasures can be executed.

[0176] The predetermined countermeasures include, for example, reporting the abnormality to the user and restarting the ECU.

[0177] If appropriate countermeasures can be promptly implemented, it will help to suppress the reduction in reliability of the electronic control unit (ECU).

[0178] Next, refer to Figure 7 . Figure 7 It shows Figure 6 Flowchart of an example of a sleep and wakeup process sequence in an electronic control device.

[0179] In step S1, the CPU that receives the sleep command sends a sleep instruction to the CAN communication circuit. In step S2, the CAN communication circuit determines whether there is a sleep instruction.

[0180] If the answer is “No” in step S2 , the CAN communication circuit maintains the active level of the activation signal of the power supply IC in step S3 .

[0181] If the answer is YES in step S2 , the CAN communication circuit sets the activation signal of the power supply IC to an inactive level in step S4 .

[0182] In step S5 , the CPU monitors the voltage level of the activation signal of the power supply IC via the monitoring circuit.

[0183] In step S6 , the CPU determines whether the activation signal of the power supply IC is at an inactive level.

[0184] If "No" in step S6, the level of the power supply IC's start signal has not reached the level corresponding to the sleep command sent in step S1. Therefore, in step S7, the CPU determines that the CAN communication circuit, SPI-BUS1, or monitoring circuit is abnormal.

[0185] If the answer is YES in step S6 , the CPU sends a power stop command to the power IC in step S8 .

[0186] In step S9 , the power IC determines whether a wakeup command is received while the power stop instruction is continuing, in other words, while the power stop process is continuing, that is, whether the start signal of the power IC is at an active level.

[0187] If the answer is "No" in step S9, in step S10, the CPU stops the power supply or shuts down the computer according to the sleep instruction.

[0188] When the answer is "YES" in step S9, in step S11, the power supply IC prioritizes making the power supply IC startup signal active to continue generating the power supply voltage. On the other hand, the CPU is reset by the reset signal from the power supply IC and starts executing operations from the initial state (initial startup).

[0189] As described above, according to the embodiments of the present invention, since a sub-processor (sub-CPU) is not used in the electronic control device, power consumption can be significantly reduced, and accordingly, low power consumption of the electronic control system can be promoted.

[0190] Furthermore, the electronic control device has a simplified structure in which the activation signal of the power supply IC is a voltage-level signal and a priority wakeup processing unit is provided in the power supply IC. This can achieve miniaturization and cost reduction of the electronic control device, and reduce the processing burden of the electronic control device.

[0191] Furthermore, when the communication circuit receives a wakeup command during the power supply IC's power supply stop process, an unexpected power supply stop can be avoided.

[0192] Furthermore, by resetting the CPU or providing a monitoring circuit to monitor the voltage level of the activation signal of the power supply IC, it is possible to suppress a decrease in the reliability of the electronic control device.

[0193] Furthermore, even when the electronic control device receives a sleep command immediately after startup, the electronic control device can be shifted to the sleep state in accordance with the sleep command.

[0194] Thus, as described above, the electronic control device of the present invention has a function of further reducing power consumption while maintaining necessary functions and reliability.

[0195] Therefore, reliability can be maintained and the overall electronic control system can achieve a significant power consumption reduction effect.

[0196] In recent years, the number of electronic devices installed in vehicles has increased, and with this, the power consumption of electronic control systems has tended to increase. In particular, there is a growing demand for reducing standby current (dark current) during vehicle stop, which is directly related to a drop in battery voltage.

[0197] According to the present invention, the above-mentioned requirements can be met, which contributes to the realization of electric vehicles, electric motorcycles, etc. that can operate for a long time on a single battery charge.

[0198] As mentioned above, although embodiment of this invention was described, this invention is not limited to the said embodiment, Various deformation|transformation and application are possible.

[0199] For example, the electronic control device and the electronic control system of the present invention can be mounted on electric vehicles and so-called hybrid vehicles and can also be used for ships and general industrial applications.

[0200] Industrial Application Possibilities

[0201] The present invention is suitable as an electronic control device and an electronic control system mounted on a vehicle, for example.

[0202] Description of Reference Numerals

[0203] 10: Host device, 20: Sensor, 30a, 30b: Terminal resistor, 40: Power line, 102: Other devices connected to the network (power control ECU, etc.), 104: Selective wakeup / sleep communication unit, 150: Electronic control system, 200: ECU group, 202: CAN communication circuit (communication circuit), 204: CPU (Central Processing Unit, Processor), 206: Power supply IC (power supply circuit, power supply integrated circuit), 220: Common mode filter, 222: Transceiver (CAN transceiver), 224: CAN controller, 226: First interface unit (first SPI interface unit), 227: SPI interface unit, 228: Start signal generation unit (start signal generation unit of power supply IC) : component), 240: start signal receiving unit (start signal receiving unit of power supply IC), 242: determination unit, 244: comparator (comparison unit), 246: priority wake-up processing unit, 250: reset unit (reset circuit), 252: second interface unit (second SPI interface unit), 253: SPI interface unit, 260: monitoring circuit, BATT: battery, ECU (ECU1~ECUm): electronic control unit as an electronic control unit, INH-Vlevel: start signal of power supply IC (voltage level signal, start signal of power supply IC as voltage level signal), RES: reset signal, SPI-BUS1: first SPI bus, SPI-BUS2: second SPI bus.

Claims

1. An electronic control device connected to a network, comprising: a processor that controls the operation of the electronic control device; a communication circuit that receives a sleep command and a wakeup command from other devices connected via the network and has a first interface for communicating with the processor; and a power supply IC that generates a power supply voltage and has a second interface for communicating with the processor, The communication circuit includes an activation signal generating unit that sets an activation signal of the power supply IC, which is a voltage level signal, to an active level when receiving the wake-up command, and transmits the received sleep command to the processor via the first interface. When the processor receives the sleep command sent from the communication circuit, it sends a sleep instruction to the communication circuit and sends a power stop instruction to the power IC. The power supply IC includes a priority wake-up processing unit. When the power supply IC is about to stop the power supply in response to a power stop instruction sent from the processor, while the valid level of the start signal of the power supply IC sent from the communication circuit is maintained, the power supply IC is started up based on the fact that the start signal of the power supply IC is valid, rather than the power stop instruction, so that the power supply voltage continues to be generated.

2. The electronic control device according to claim 1, wherein: The activation signal of the power supply IC is transmitted from the communication circuit to the power supply IC via a signal path that does not pass through the sub-processor.

3. The electronic control device according to claim 1, wherein: The first interface and the second interface are communication interfaces that transmit and receive data in synchronization with a rising edge or a falling edge of a clock.

4. The electronic control device according to claim 1, wherein: A power supply IC activation signal monitoring circuit for monitoring the level of the power supply IC activation signal is provided between the processor and a signal path for transmitting the power supply IC activation signal output from the communication circuit to the power supply IC.

5. The electronic control device according to claim 1, wherein: The power supply IC includes a reset unit that outputs a reset signal for resetting the processor. When the priority wakeup processing unit activates the power supply IC based on the activation signal of the power supply IC being active to continue generating the power supply voltage, the power supply IC causes the reset unit to output the reset signal, thereby initially activating the processor.

6. The electronic control device according to claim 5, wherein: The power supply IC causes the reset unit to output the reset signal by transitioning the state of the power supply IC to the initial state.

7. An electronic control system, wherein: A plurality of electronic control devices according to any one of claims 1 to 6 are connected to the network.

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