Semiconductor refrigerator

Abstract

The invention relates to a semiconductor cooler which comprises a heat dissipation block, an electrode, a first insulating heat-conducting adhesive layer, a first conducting layer, a P-type semiconductor particle layer, an N-type semiconductor particle layer, a second insulating heat-conducting adhesive layer, a second conducting layer and a cooling block, and the second insulating heat-conducting adhesive layer is arranged and attached to the upper surface of the heat dissipation block; second conductive layers which are arranged at intervals are adhered to one surface, far away from the heat dissipation block, of the second insulating heat-conducting glue layer; a first insulating heat-conducting glue layer is arranged and attached to the lower surface of the refrigeration block; first conductive layers which are arranged at intervals are adhered to one surface, far away from the refrigeration block, of the first insulating heat-conducting glue layer; two ends of the P-type semiconductor particle layer and the N-type semiconductor particle layer are respectively contacted with the first conductive layer and the second conductive layer; and the extension parts of the first conductive layer and the second conductive layer on the outermost layer form an electrode comprising a positive electrode and a negative electrode. The refrigerating / heating efficiency of the semiconductor refrigerator can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of thermoelectric refrigeration, and in particular to a semiconductor refrigerator. Background Art

[0002] A thermal electric cooler (TEC) is a device that utilizes the Peltier effect of semiconductor materials to achieve both cooling and heating. The Peltier effect refers to the process whereby when a direct current passes through a galvanic couple composed of two semiconductor materials, one end of the couple absorbs heat while the other releases it, transferring heat from one location to another. This creates a large temperature difference between the two ends, forming a hot end and a cold end, thereby achieving both cooling and heating. In related technologies, TECs generally utilize a double-sided ceramic substrate structure made of aluminum oxide or aluminum nitride. From bottom to top, the structure consists of a heat sink (hot end), a lower ceramic substrate, a layer of semiconductor particles, copper particles, an upper ceramic substrate, a thermally conductive medium, and a cooling block (cold end). The copper particles are affixed to the lower ceramic substrate through a high-temperature sintering process. However, TECs with this structure require heat conduction from both the cold and hot ends through the ceramic substrate, and since the thermal conductivity of the ceramic substrate is significantly lower than that of the thermally conductive medium and the high-temperature sintered copper particles, this creates multiple layers of thermal resistance, increasing the power consumption of the TEC and resulting in lower cooling / heating efficiency. Summary of the Invention

[0003] In view of this, the present invention provides a semiconductor refrigerator.

[0004] Specifically, the present invention is achieved through the following technical solutions: According to a first aspect of the present invention, a semiconductor refrigerator is provided, comprising: a heat sink (18), an electrode (13), a first insulating thermally conductive adhesive layer (19), a first conductive layer (12), a P-type semiconductor particle layer (14), an N-type semiconductor particle layer (15), a second insulating thermally conductive adhesive layer (21), a second conductive layer (22), and a cooling block (17), wherein: A second insulating heat-conducting adhesive layer (21) is provided and applied on the upper surface of the heat dissipation block (18); On the side of the second insulating thermally conductive adhesive layer (21) away from the heat dissipation block (18), a second conductive layer (22) arranged alternately is applied; A first insulating heat-conducting adhesive layer (19) is provided and applied to the lower surface of the refrigeration block (17); On the side of the first insulating heat-conductive adhesive layer (19) away from the refrigeration block (17), a first conductive layer (12) arranged alternately is applied; Two ends of the P-type semiconductor particle layer (14) and the N-type semiconductor particle layer (15) are in contact with the first conductive layer (12) and the second conductive layer (22), respectively; The outermost first conductive layer (12) and the extension of the second conductive layer (22) form an electrode (13) including a positive electrode and a negative electrode.

[0005] Optionally, the first conductive layer (12) includes a copper particle layer.

[0006] Optionally, the first conductive layer (12) and the second conductive layer (22) are arranged alternately in the same direction.

[0007] Optionally, adjacent first conductive layers (12) and second conductive layers (22) have overlapping portions in spatial projection.

[0008] Optionally, the alternately arranged first conductive layer (12) includes: a first copper particle first sublayer (121), a first copper particle second sublayer (122), a first copper particle third sublayer (123) and a first copper particle fourth sublayer (124); the alternately arranged second copper particle layer includes: a second copper particle first sublayer (221), a second copper particle second sublayer (222) and a second copper particle third sublayer (223); the P-type semiconductor particle layer (14) includes: a first P-type semiconductor particle layer (141), a second P-type semiconductor particle layer (142) and a third P-type semiconductor particle layer (143); the N-type semiconductor particle layer (15) includes: a first N-type semiconductor particle layer (151), a second N-type semiconductor particle layer (152) and a third N-type semiconductor particle layer (153); wherein, The first copper particle first sublayer (121) is the outermost layer of the semiconductor cooler in the horizontal direction to the right, the first copper particle fourth sublayer (124) is the outermost layer of the semiconductor cooler in the horizontal direction to the left, the first copper particle first sublayer (121) is extended to form the positive electrode or negative electrode in the electrode (13), and the first copper particle fourth sublayer (124) is extended to form the negative electrode or positive electrode corresponding to the positive electrode or negative electrode formed by the first copper particle first sublayer (121); The first P-type semiconductor particle layer (141) is in contact with the first copper particle first sublayer (121) and the second copper particle first sublayer (221) respectively; The first N-type semiconductor particle layer (151) is in contact with the second copper particle first sublayer (221) and the first copper particle second sublayer (122) respectively; The second P-type semiconductor particle layer (142) is in contact with the first copper particle second sublayer (122) and the second copper particle second sublayer (222) respectively; The second N-type semiconductor particle layer (152) is in contact with the second copper particle second sublayer (222) and the first copper particle third sublayer (123) respectively; The third P-type semiconductor particle layer (143) is in contact with the first copper particle third sublayer (123) and the second copper particle third sublayer (223) respectively; The third N-type semiconductor particle layer (153) is in contact with the second copper particle third sublayer (223) and the first copper particle fourth sublayer (124) respectively.

[0009] Optionally, the alternately arranged first conductive layer (12) includes: a first copper particle first sublayer (121), a first copper particle second sublayer (122), a first copper particle third sublayer (123), and a first copper particle fourth sublayer (124); the alternately arranged second copper particle layer includes: a second copper particle first sublayer (221), a second copper particle second sublayer (222), a second copper particle third sublayer (223), and a second copper particle fourth sublayer; the P-type semiconductor particle layer (14) includes: a first P-type semiconductor particle layer (141) and a second P-type semiconductor particle layer (142); and the N-type semiconductor particle layer (15) includes: a first N-type semiconductor particle layer (151) and a second N-type semiconductor particle layer (152), wherein: The first copper particle first sublayer (121) is the outermost layer of the semiconductor cooler in the horizontal direction to the right, the second copper particle fourth sublayer is the outermost layer of the semiconductor cooler in the horizontal direction to the left, the first copper particle first sublayer (121) is extended to form the positive electrode or negative electrode in the electrode (13), and the second copper particle fourth sublayer is extended to form the negative electrode or positive electrode corresponding to the positive electrode or negative electrode formed by the first copper particle first sublayer (121); The first P-type semiconductor particle layer (141) is in contact with the first copper particle first sublayer (121) and the second copper particle first sublayer (221) respectively; The first N-type semiconductor particle layer (151) is in contact with the first copper particle second sublayer (122) and the second copper particle second sublayer (222) respectively; The second P-type semiconductor particle layer (142) is in contact with the first copper particle third sublayer (123) and the second copper particle third sublayer (223) respectively; The second N-type semiconductor particle layer (152) is in contact with the first copper particle fourth sublayer (124) and the second copper particle fourth sublayer respectively; The first copper particle first sublayer (121) and the first copper particle third sublayer (123) are connected in parallel to form a first parallel layer, and the second copper particle second sublayer (222) and the second copper particle fourth sublayer are connected in parallel to form a second parallel layer, connecting the first parallel layer and the second parallel layer.

[0010] Optionally, the applying comprises spreading evenly.

[0011] Optionally, the interlaced arrangement includes an array arrangement.

[0012] Optionally, the P-type semiconductor particle layer (14) is welded between the first conductive layer (12) and the second conductive layer (22), and the N-type semiconductor particle layer (15) is welded between the first conductive layer (12) and the second conductive layer (22).

[0013] Optionally, it also includes: The insulating and heat-insulating adhesive is used to fill the space formed between the P-type semiconductor particle layer (14) and the N-type semiconductor particle layer (15).

[0014] A semiconductor refrigerator in the present technical solution includes: a heat sink, an electrode, a first insulating thermally conductive adhesive layer, a first conductive layer, a P-type semiconductor particle layer, an N-type semiconductor particle layer, a second insulating thermally conductive adhesive layer, a second conductive layer, and a cooling block, wherein the upper surface of the heat sink is provided with and applied with the second insulating thermally conductive adhesive layer; the second conductive layer arranged alternately is applied on the side of the second insulating thermally conductive adhesive layer away from the heat sink; the lower surface of the cooling block is provided with and applied with the first insulating thermally conductive adhesive layer; the first conductive layer arranged alternately is applied on the side of the first insulating thermally conductive adhesive layer away from the cooling block; the two ends of the P-type semiconductor particle layer and the N-type semiconductor particle layer are in contact with the first conductive layer and the second conductive layer respectively; the extension of the outermost first conductive layer and the second conductive layer forms an electrode including a positive electrode and a negative electrode. In this way, by providing a high thermally conductive insulating adhesive layer on the hot and cold surfaces and bonding a copper particle layer array on the high thermally conductive insulating adhesive layer, the arrangement space of the semiconductor cooling particles can be effectively increased, the power density can be enhanced, and the cooling / heating efficiency of the semiconductor refrigerator can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0017] Figure 1 A schematic diagram of the structure of a semiconductor refrigerator in related technology; Figure 2 A schematic structural diagram of a semiconductor refrigerator provided by an embodiment of the present invention; Figure 3 This is another structural schematic diagram of a semiconductor refrigerator provided by an embodiment of the present invention.

[0018] The following are the descriptions of the reference numerals: 11-upper ceramic substrate, 12-first conductive layer, 13-electrode, 14-P-type semiconductor particle layer, 15-N-type semiconductor particle layer, 16-lower ceramic substrate, 17-refrigeration block, 18-heat sink, 19-first insulating thermally conductive adhesive layer, 20-thermal conductive medium, 21-second insulating thermally conductive adhesive layer, 22-second conductive layer, 121-first sublayer of first copper particles, 122-second sublayer of first copper particles, 123-third sublayer of first copper particles, 124-fourth sublayer of first copper particles, 221-first sublayer of second copper particles, 222-second sublayer of second copper particles, 223-third sublayer of second copper particles, 141-first P-type semiconductor particle layer, 142-second P-type semiconductor particle layer, 143-third P-type semiconductor particle layer, 151-first N-type semiconductor particle layer, 152-second N-type semiconductor particle layer, 153-third N-type semiconductor particle layer. DETAILED DESCRIPTION

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0020] Figure 1 This is a schematic diagram of the structure of a semiconductor refrigerator in the related art. In the related art, the semiconductor refrigerator is formed from bottom to top by a heat sink 18, a lower ceramic substrate 16, a P-type semiconductor particle layer 14, an N-type semiconductor particle layer 15, a first conductive layer 12, an upper ceramic substrate 11, a heat conducting medium 20 and a cooling block 17. The first conductive layer 12 is fixed on the lower ceramic substrate 16 through a high-temperature sintering process. Figure 1As shown, the lower ceramic substrate 16 is arranged on the heat dissipation block 18, and a plurality of first conductive layers 12 arranged alternately are formed on the lower ceramic substrate 16 by a high-temperature sintering process, a P-type semiconductor particle layer 14 and an N-type semiconductor particle layer 15 are arranged on the first conductive layer 12, and an electrode 13 including a positive pole and a negative pole is formed based on the P-type semiconductor particle layer 14 and the N-type semiconductor particle layer 15; a heat-conducting medium 20 is applied to the bottom of the cooling block 17, and an upper ceramic substrate 11 is applied to the other side of the heat-conducting medium 20, and a plurality of first conductive layers 12 arranged alternately are formed on the other side of the upper ceramic substrate 11 by a high-temperature sintering process. Among them, the P-type semiconductor particle layer 14 and the N-type semiconductor particle layer 15 are in contact with the first conductive layer 12 sintered at high temperature on the upper ceramic substrate 11 and the first conductive layer 12 sintered at high temperature on the lower ceramic substrate 16, respectively. Because the thermal conductivity of the ceramic substrate is significantly lower than that of the heat-conducting medium and the high-temperature sintered copper particles, a multi-layer thermal resistance is formed, which increases the power consumption of the semiconductor refrigerator and makes the cooling / heating efficiency of the semiconductor refrigerator low. Specifically, it has the following disadvantages: 1. Multi-layer thermal resistance superposition: The upper ceramic substrate is used to cool or heat the refrigeration block, and heat is conducted by a heat-conducting medium installed between the upper ceramic substrate and the refrigeration block. The lower ceramic substrate is used to dissipate heat from the heat dissipation block, and heat is conducted by a heat-conducting medium installed between the lower ceramic substrate and the heat dissipation block. Since both the cold end and the hot end need to conduct heat through the ceramic substrate, the heat transfer route is as follows: Heat is conducted from the PN junction surface formed by the P-type semiconductor particle layer and the N-type semiconductor particle layer through the upper ceramic substrate to the heat-conducting medium, and then to the refrigeration block through the heat-conducting medium. The thermal conductivity of the ceramic substrate is significantly lower than that of the heat-conducting medium and the high-temperature sintered copper particles, forming a multi-layer thermal resistance superposition, which increases the power consumption of the semiconductor refrigerator and makes the cooling / heating efficiency of the semiconductor refrigerator low.

[0021] 2. Low space utilization: The ceramic substrate needs to retain a thickness of 1-2mm to ensure the structural strength of the semiconductor cooler, and the high-temperature sintering and re-etching process requires a certain amount of space. For example, short circuits need to be avoided between the array-distributed copper particle layers, and the spacing between the copper particle layers needs to be maintained at a certain interval. In the process of high-temperature sintering and re-etching, the spacing between the copper particle layers is related to the thickness of the copper particle layers. Therefore, the array arrangement of the copper particle layers through high-temperature sintering and re-etching has a large spacing between the copper particle layers, which makes the arrangement density on the surface of the upper ceramic substrate small, thereby limiting the arrangement density of the semiconductor particles on the ceramic substrate, thereby reducing the power of the semiconductor cooler and failing to meet the cooling / heating requirements; 3. Thermal stress damage: The difference in thermal expansion coefficient between the ceramic substrate and the thermal conductive medium, copper particles, and semiconductor particles causes interfacial stress during temperature cycling, leading to delamination failure.

[0022] In an embodiment of the present application, a semiconductor refrigerator with a new structure is provided, which uses insulating thermal conductive glue as an insulating thermal conductive medium between the cooling block and the heat dissipation block, thereby reducing the superposition of multiple layers of thermal resistance between cooling or heating, effectively reducing the thermal resistance of the hot and cold surfaces, and thereby reducing the power consumption of the semiconductor refrigerator and improving the cooling / heating efficiency of the semiconductor refrigerator.

[0023] Figure 2 A schematic diagram of the structure of a semiconductor cooler provided by an embodiment of the present invention. Figure 2 The embodiment of the present invention provides a semiconductor refrigerator, which includes: a heat sink 18, an electrode 13, a first insulating thermal conductive adhesive layer 19, a first conductive layer 12, a P-type semiconductor particle layer 14, an N-type semiconductor particle layer 15, a second insulating thermal conductive adhesive layer 21, a second conductive layer 22 and a cooling block 17, wherein: A second insulating thermal conductive adhesive layer 21 is provided and applied on the upper surface of the heat dissipation block 18; On the side of the second insulating thermal conductive adhesive layer 21 away from the heat dissipation block 18, a second conductive layer 22 arranged alternately is applied; A first insulating and heat-conductive adhesive layer 19 is provided and applied to the lower surface of the refrigeration block 17; On the side of the first insulating thermal conductive adhesive layer 19 away from the refrigeration block 17, there are applied the first conductive layers 12 arranged alternately; Both ends of the P-type semiconductor particle layer 14 and the N-type semiconductor particle layer 15 are in contact with the first conductive layer 12 and the second conductive layer 22 respectively; The outermost first conductive layer 12 and the extension portion of the second conductive layer 22 form the electrode 13 including the positive electrode and the negative electrode.

[0024] In this embodiment, as an optional embodiment, the P-type semiconductor particle layer and the N-type semiconductor particle layer are respectively in contact with the first copper particle layer on the first insulating thermal conductive adhesive layer applied to the lower surface of the refrigeration block and the second copper particle layer on the second insulating thermal conductive adhesive layer applied to the upper surface of the heat dissipation block.

[0025] In this embodiment, as an optional embodiment, the first conductive layer and the second conductive layer have the same structure, including but not limited to copper particle layers, that is, the first conductive layer is a first copper particle layer, and the second conductive layer is a second copper particle layer.

[0026] In this embodiment, as an optional embodiment, the insulating thermally conductive adhesive layer includes but is not limited to: a thermally conductive silicone sheet layer, a thermally conductive silicone grease layer, and the insulating thermally conductive adhesive layer is used to form a hot and cold surface thermal resistance interface between the refrigeration block and the insulating thermally conductive adhesive layer, and the insulating thermally conductive adhesive layer and the copper particle layer form another hot and cold surface thermal resistance interface. Compared with using a ceramic substrate, a hot and cold surface thermal resistance interface is formed between the refrigeration block and the heat-conducting medium surface, another hot and cold surface thermal resistance interface is formed between the heat-conducting medium and the ceramic substrate surface, and another hot and cold surface thermal resistance interface is formed between the ceramic substrate and the copper particle layer. This can effectively reduce the number of hot and cold surface thermal resistance interfaces, thereby reducing thermal resistance loss and reducing power consumption of the semiconductor refrigerator, thereby improving the cooling or heating efficiency of the semiconductor refrigerator; further, by pasting the insulating thermally conductive adhesive layer and the conductive layer, the arrangement density of the conductive layer on the surface of the insulating thermally conductive adhesive layer can be increased compared to the method of high-temperature sintering and corrosion that requires a certain space, thereby improving the power of the semiconductor refrigerator.

[0027] In this embodiment, as an optional embodiment, the first copper particle layer and the second copper particle layer in the same direction are arranged alternately. For example, Figure 2 In the diagram, the left-right direction is the horizontal direction, the up-down direction is the vertical direction, and the front-back direction is the depth direction. Taking the horizontal direction as an example, a second copper grain layer is arranged below adjacent first copper grain layers, that is, the first copper grain layers and the second copper grain layers are arranged alternately in the horizontal direction. As an optional embodiment, adjacent first copper grain layers and second copper grain layers have an overlapping portion in spatial projection. For example, in this embodiment, the horizontal projection has an overlapping portion, that is, the first copper grain layer and the second copper grain layer below another first copper grain layer adjacent to the first copper grain layer have an overlapping portion in the horizontal spatial projection.

[0028] Figure 3 This is another structural diagram of a semiconductor refrigerator provided by an embodiment of the present invention. Figure 3 In this embodiment, as an optional embodiment, the alternately arranged first copper particle layer includes: a first copper particle first sublayer 121, a first copper particle second sublayer 122, a first copper particle third sublayer 123, and a first copper particle fourth sublayer 124; the alternately arranged second copper particle layer includes: a second copper particle first sublayer 221, a second copper particle second sublayer 222, and a second copper particle third sublayer 223; the P-type semiconductor particle layer 14 includes: a first P-type semiconductor particle layer 141, a second P-type semiconductor particle layer 142, and a third P-type semiconductor particle layer 143; the N-type semiconductor particle layer 15 includes: a first N-type semiconductor particle layer 151, a second N-type semiconductor particle layer 152, and a third N-type semiconductor particle layer 153, wherein, The first copper grain first sublayer 121 is the outermost layer in the horizontal direction to the right of the semiconductor cooler, and the first copper grain fourth sublayer 124 is the outermost layer in the horizontal direction to the left of the semiconductor cooler. The first copper grain first sublayer 121 is extended to form the positive electrode or the negative electrode in the electrode 13, and the first copper grain fourth sublayer 124 is extended to form the negative electrode or the positive electrode corresponding to the positive electrode or the negative electrode formed by the first copper grain first sublayer 121. The first P-type semiconductor particle layer 141 is in contact with the first copper particle first sub-layer 121 and the second copper particle first sub-layer 221 respectively; The first N-type semiconductor particle layer 151 is in contact with the second copper particle first sub-layer 221 and the first copper particle second sub-layer 122 respectively; The second P-type semiconductor particle layer 142 is in contact with the first copper particle second sub-layer 122 and the second copper particle second sub-layer 222 respectively; The second N-type semiconductor particle layer 152 is in contact with the second copper particle second sub-layer 222 and the first copper particle third sub-layer 123 respectively; The third P-type semiconductor particle layer 143 is in contact with the first copper particle third sub-layer 123 and the second copper particle third sub-layer 223 respectively; The third N-type semiconductor particle layer 153 is in contact with the second copper particle third sub-layer 223 and the first copper particle fourth sub-layer 124 respectively.

[0029] In this embodiment, a P-type semiconductor particle layer and an N-type semiconductor particle layer are arranged on the copper particle layer. The P-type semiconductor particle layer arranged on the first copper particle layer and the N-type semiconductor particle layer arranged on the adjacent second copper particle layer are connected in series to form a copper conductive circuit. The two ends of the copper conductive circuit form electrodes including a positive electrode and a negative electrode. In this way, the P-type semiconductor particle layer and the N-type semiconductor particle layer are used to sequentially connect the first copper particle layer and the second copper particle layer adjacent to the first copper particle layer, so that the P-type semiconductor particle layer and the N-type semiconductor particle layer are sequentially connected in series.

[0030] In this embodiment, as another optional embodiment, the alternately arranged first copper particle layer includes: a first copper particle first sublayer 121, a first copper particle second sublayer 122, a first copper particle third sublayer 123, and a first copper particle fourth sublayer 124; the alternately arranged second copper particle layer includes: a second copper particle first sublayer 221, a second copper particle second sublayer 222, a second copper particle third sublayer 223, and a second copper particle fourth sublayer (not shown in the figure); the P-type semiconductor particle layer 14 includes: a first P-type semiconductor particle layer 141 and a second P-type semiconductor particle layer 142; the N-type semiconductor particle layer 15 includes: a first N-type semiconductor particle layer 151 and a second N-type semiconductor particle layer 152, wherein, The first sublayer 121 of the first copper grain is the outermost layer in the horizontal direction to the right of the semiconductor cooler, and the fourth sublayer of the second copper grain is the outermost layer in the horizontal direction to the left of the semiconductor cooler. The first sublayer 121 of the first copper grain is extended to form the positive electrode or the negative electrode in the electrode 13, and the fourth sublayer of the second copper grain is extended to form the negative electrode or the positive electrode corresponding to the positive electrode or the negative electrode formed by the first sublayer 121 of the first copper grain. The first P-type semiconductor particle layer 141 is in contact with the first copper particle first sub-layer 121 and the second copper particle first sub-layer 221 respectively; The first N-type semiconductor particle layer 151 is in contact with the first copper particle second sub-layer 122 and the second copper particle second sub-layer 222 respectively; The second P-type semiconductor particle layer 142 is in contact with the first copper particle third sub-layer 123 and the second copper particle third sub-layer 223 respectively; The second N-type semiconductor particle layer 152 is in contact with the first copper particle fourth sub-layer 124 and the second copper particle fourth sub-layer respectively; The first copper grain first sublayer 121 and the first copper grain third sublayer 123 are connected in parallel to form a first parallel layer, and the second copper grain second sublayer 222 and the second copper grain fourth sublayer are connected in parallel to form a second parallel layer, connecting the first parallel layer and the second parallel layer.

[0031] In this embodiment, the P-type semiconductor particle layers are connected in parallel and then connected to the N-type semiconductor particle layers connected in parallel to form a parallel connection.

[0032] In this embodiment, copper particles are used to connect the P-type semiconductor particle layer and the N-type semiconductor particle layer, which can ensure that current flows evenly through the thermocouple pair.

[0033] In this embodiment, as an optional embodiment, the application includes but is not limited to uniform coating. The first insulating thermal conductive adhesive layer applied to the lower surface of the refrigeration block is formed by uniform coating, and is arranged in an array, that is, on the surface of the first insulating thermal conductive adhesive layer away from the refrigeration block, the first copper particle layer is arranged in an array.

[0034] In this embodiment, similar to the first insulating thermally conductive adhesive layer applied on the refrigeration block, a layer of insulating thermally conductive adhesive is formed on the upper surface of the heat dissipation block by evenly applying the layer, and the insulating thermally conductive adhesive layer evenly applied on the upper surface of the heat dissipation block is away from the surface of the heat dissipation block, and a copper particle layer is arranged in an array.

[0035] In this embodiment, to improve the reliability of the semiconductor refrigerator during hot and cold cycle operation, as an optional embodiment, a P-type semiconductor particle layer is welded between the first copper particle layer and the second copper particle layer, and an N-type semiconductor particle layer is welded between the first copper particle layer and the second copper particle layer, so that the ends of the semiconductor particle layer are in contact with the first copper particle layer and the second copper particle layer, respectively. As an optional embodiment, SnBi solder is used as the welding material.

[0036] In this embodiment, there is a certain space between the P-type semiconductor particle layer and the N-type semiconductor particle layer. In order to prevent the liquid on the cold end surface of the semiconductor refrigerator from penetrating into the space formed between the P-type semiconductor particle layer and the N-type semiconductor particle layer, thereby affecting the performance of the semiconductor refrigerator, as an optional embodiment, the semiconductor refrigerator further includes: The insulating and heat-insulating adhesive (not shown in the figure) is used to fill the space formed between the P-type semiconductor particle layer and the N-type semiconductor particle layer.

[0037] In this embodiment, the insulating adhesive is used to isolate the P-type semiconductor particle layer from the N-type semiconductor particle layer within the semiconductor cooler, achieving a sealed insulation effect. Furthermore, the insulating adhesive is required to have excellent heat insulation, thermal insulation, moisture resistance, and durability. It can maintain a good seal between the P-type semiconductor particle layer and the N-type semiconductor particle layer within the semiconductor cooler and reduce the impact of environmental changes. As an optional embodiment, the insulating adhesive includes but is not limited to aerogel.

[0038] In the embodiment of the present application, insulating thermally conductive adhesive is respectively applied on the surface of the refrigeration block and the heat dissipation block. Since the insulating thermally conductive adhesive has the function of insulating and heat conducting, there is no need to set a ceramic substrate as an insulating layer. In this way, by removing the upper and lower ceramic substrates, the thermal resistance of the hot and cold surfaces can be effectively reduced. For example, in the related art, a hot and cold surface thermal resistance interface is formed between the refrigeration block and the surface of the heat-conducting medium, another hot and cold surface thermal resistance interface is formed between the heat-conducting medium and the surface of the ceramic substrate, and another hot and cold surface thermal resistance interface is formed between the ceramic substrate and the copper particle layer, thereby forming multiple hot and cold surface thermal resistance interfaces and increasing the interface impedance. The semiconductor refrigerator of this embodiment only forms a hot and cold surface thermal resistance interface between the refrigeration block and the surface of the insulating thermally conductive adhesive, and another hot and cold surface thermal resistance interface is formed between the insulating thermally conductive adhesive and the copper particle layer, thereby reducing the heat transfer temperature difference by more than 0.5°C, reducing power consumption by more than 5%, and effectively improving the cooling / heating efficiency of the semiconductor refrigerator. At the same time, there is no need to fix the copper particle layer through high-temperature sintering and then etching, thereby increasing the arrangement space of the insulating thermal conductive adhesive layer. The insulating thermal conductive adhesive layer is conducive to stress buffering and stress release. On the insulating thermal conductive adhesive layer, the copper particle layer can be arranged in an array with smaller spacing and margins, effectively increasing the arrangement density and thus improving temperature uniformity. As an optional embodiment, the copper particle layer is fixed to the surface of the insulating thermal conductive adhesive by mounting, thereby effectively increasing the power density of the TEC, and can increase the power density inside the TEC by more than 10%. Furthermore, because the electrode can be freely mounted and is not restricted by the size of the lower ceramic substrate, the size of the electrode can be made longer and larger, thereby effectively increasing the welding space. Moreover, using double-sided adhesive to fix the copper particle layer can effectively reduce the warping stress of the ceramic tile and can increase the service life of the TEC by more than 10%. It can be used in electronic equipment heat dissipation, for example, to dissipate heat for central processing units (CPUs) and graphics processing units (GPUs), as well as for dissipating heat for radio frequency modules in 5G communication base stations. It has the following beneficial technical effects: (1) By removing the ceramic substrate, the thermal resistance of the hot and cold surfaces is effectively reduced, the power consumption of the product is reduced, and the power is increased.

[0039] (2) Through the ceramic-free design, the arrangement space of semiconductor refrigeration particles is increased, and the power density inside TEC is improved.

[0040] (3) Double-sided adhesive fixes and distributes copper particles to reduce tile warping stress and enhance the life of the TEC itself.

[0041] Although this specification contains many specific implementation details, these should not be interpreted as limiting the scope of any invention or the scope of protection claimed, but are mainly used to describe the features of specific embodiments of specific inventions. Certain features described in multiple embodiments within this specification can also be implemented in combination in a single embodiment. On the other hand, the various features described in a single embodiment can also be implemented separately in multiple embodiments or in any suitable sub-combination. In addition, although the features can work in certain combinations as above and even initially claim protection, one or more features from the claimed combination can be removed from the combination in some cases, and the claimed combination can point to a sub-combination or a variation of the sub-combination.

[0042] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that these operations be performed in the particular order shown or performed sequentially, or that all illustrated operations be performed to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product, or packaged into multiple software products.

[0043] Thus, specific embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the particular order shown or sequential sequence to achieve the desired results. In some implementations, multitasking and parallel processing may be advantageous.

[0044] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device that includes the element.

[0045] The foregoing is merely a detailed description of the present invention, intended to enable those skilled in the art to understand and implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein, but is to be construed in the widest manner consistent with the principles and novel features claimed herein.

Claims

1. A semiconductor refrigerator, characterized in that: include: A heat dissipation block (18), an electrode (13), a first insulating thermal conductive adhesive layer (19), a first conductive layer (12), a P-type semiconductor particle layer (14), an N-type semiconductor particle layer (15), a second insulating thermal conductive adhesive layer (21), a second conductive layer (22) and a cooling block (17), wherein: A second insulating heat-conducting adhesive layer (21) is provided and applied on the upper surface of the heat dissipation block (18); On the side of the second insulating thermally conductive adhesive layer (21) away from the heat dissipation block (18), a second conductive layer (22) arranged alternately is applied; A first insulating heat-conducting adhesive layer (19) is provided and applied to the lower surface of the refrigeration block (17); On the side of the first insulating heat-conductive adhesive layer (19) away from the refrigeration block (17), a first conductive layer (12) arranged alternately is applied; Two ends of the P-type semiconductor particle layer (14) and the N-type semiconductor particle layer (15) are in contact with the first conductive layer (12) and the second conductive layer (22), respectively; The outermost first conductive layer (12) and the extension of the second conductive layer (22) form an electrode (13) including a positive electrode and a negative electrode.

2. The semiconductor refrigerator according to claim 1, characterized in that: The first conductive layer (12) comprises a copper particle layer.

3. The semiconductor refrigerator according to claim 1, characterized in that The first conductive layer (12) and the second conductive layer (22) are arranged alternately in the same direction.

4. The semiconductor refrigerator according to claim 3, characterized in that: The adjacent first conductive layer (12) and second conductive layer (22) have overlapping parts in spatial projection.

5. The semiconductor cooler according to any one of claims 1 to 4, characterized in that: The alternately arranged first conductive layer (12) includes: a first copper particle first sublayer (121), a first copper particle second sublayer (122), a first copper particle third sublayer (123), and a first copper particle fourth sublayer (124); the alternately arranged second copper particle layer includes: a second copper particle first sublayer (221), a second copper particle second sublayer (222), and a second copper particle third sublayer (223); the P-type semiconductor particle layer (14) includes: a first P-type semiconductor particle layer (141), a second P-type semiconductor particle layer (142), and a third P-type semiconductor particle layer (143); the N-type semiconductor particle layer (15) includes: a first N-type semiconductor particle layer (151), a second N-type semiconductor particle layer (152), and a third N-type semiconductor particle layer (153); wherein, The first copper particle first sublayer (121) is the outermost layer of the semiconductor cooler in the horizontal direction to the right, the first copper particle fourth sublayer (124) is the outermost layer of the semiconductor cooler in the horizontal direction to the left, the first copper particle first sublayer (121) is extended to form the positive electrode or negative electrode in the electrode (13), and the first copper particle fourth sublayer (124) is extended to form the negative electrode or positive electrode corresponding to the positive electrode or negative electrode formed by the first copper particle first sublayer (121); The first P-type semiconductor particle layer (141) is in contact with the first copper particle first sublayer (121) and the second copper particle first sublayer (221) respectively; The first N-type semiconductor particle layer (151) is in contact with the second copper particle first sublayer (221) and the first copper particle second sublayer (122) respectively; The second P-type semiconductor particle layer (142) is in contact with the first copper particle second sublayer (122) and the second copper particle second sublayer (222) respectively; The second N-type semiconductor particle layer (152) is in contact with the second copper particle second sublayer (222) and the first copper particle third sublayer (123) respectively; The third P-type semiconductor particle layer (143) is in contact with the first copper particle third sublayer (123) and the second copper particle third sublayer (223) respectively; The third N-type semiconductor particle layer (153) is in contact with the second copper particle third sublayer (223) and the first copper particle fourth sublayer (124) respectively.

6. The semiconductor cooler according to any one of claims 1 to 4, characterized in that: The alternately arranged first conductive layer (12) includes: a first copper particle first sublayer (121), a first copper particle second sublayer (122), a first copper particle third sublayer (123), and a first copper particle fourth sublayer (124); the alternately arranged second copper particle layer includes: a second copper particle first sublayer (221), a second copper particle second sublayer (222), a second copper particle third sublayer (223), and a second copper particle fourth sublayer; the P-type semiconductor particle layer (14) includes: a first P-type semiconductor particle layer (141) and a second P-type semiconductor particle layer (142); the N-type semiconductor particle layer (15) includes: a first N-type semiconductor particle (151) layer and a second N-type semiconductor particle layer (152); wherein, The first copper particle first sublayer (121) is the outermost layer of the semiconductor cooler in the horizontal direction to the right, the second copper particle fourth sublayer is the outermost layer of the semiconductor cooler in the horizontal direction to the left, the first copper particle first sublayer (121) is extended to form the positive electrode or negative electrode in the electrode (13), and the second copper particle fourth sublayer is extended to form the negative electrode or positive electrode corresponding to the positive electrode or negative electrode formed by the first copper particle first sublayer (121); The first P-type semiconductor particle layer (141) is in contact with the first copper particle first sublayer (121) and the second copper particle first sublayer (221) respectively; The first N-type semiconductor particle layer (151) is in contact with the first copper particle second sublayer (122) and the second copper particle second sublayer (222) respectively; The second P-type semiconductor particle layer (142) is in contact with the first copper particle third sublayer (123) and the second copper particle third sublayer (223) respectively; The second N-type semiconductor particle layer (152) is in contact with the first copper particle fourth sublayer (124) and the second copper particle fourth sublayer respectively; The first copper particle first sublayer (121) and the first copper particle third sublayer (123) are connected in parallel to form a first parallel layer, and the second copper particle second sublayer (222) and the second copper particle fourth sublayer are connected in parallel to form a second parallel layer, connecting the first parallel layer and the second parallel layer.

7. The semiconductor cooler according to any one of claims 1 to 4, characterized in that: The applying includes evenly spreading.

8. The semiconductor cooler according to any one of claims 1 to 4, characterized in that: The interlaced arrangement includes an array arrangement.

9. The semiconductor cooler according to any one of claims 1 to 4, characterized in that: By welding, the P-type semiconductor particle layer (14) is welded between the first conductive layer (12) and the second conductive layer (22), and the N-type semiconductor particle layer (15) is welded between the first conductive layer (12) and the second conductive layer (22).

10. The semiconductor cooler according to any one of claims 1 to 4, characterized in that: Also includes: The insulating and heat-insulating adhesive is used to fill the space formed between the P-type semiconductor particle layer (14) and the N-type semiconductor particle layer (15).

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