A BMS function load aging test system and method

Abstract

The present invention relates to the field of battery management system detection technology, and in particular to a BMS function load aging test system and method. The method comprises the following steps: in the process of continuous load current flowing through the battery management system, periodically and synchronously collecting the bus current value, bus voltage value and the return status code of the battery management system to generate a real-time triplet; subtracting the real-time triplet from the preset historical triplet to determine the current drift amount, and marking the current drift amount as the amplitude instruction of the reverse current pulse. The present invention uses current calibration and pseudo-random detection technology to complete the drift-zero drift-insulation triple inspection without interrupting the load current throughout the whole process, thereby improving the accuracy and reliability of the battery management system aging detection and effectively ensuring the safe operation of the battery system.

Description

Technical Field

[0001] The present invention relates to the technical field of battery management system detection, and in particular to a BMS function load aging test system and method. Background Art

[0002] The Battery Management System (BMS) is a crucial component of a battery pack. Its functions include battery status monitoring, balancing control, and protection to ensure safe, reliable, and efficient battery operation. In practical applications, the aging state of the BMS directly impacts the performance and safety of the battery system. Therefore, conducting load aging tests on the BMS is an important means of evaluating its performance and reliability. However, existing technologies use static calibration, which is unable to compensate for the accumulated errors of the Hall effect sensor under load conditions in real time, resulting in reduced current monitoring accuracy. Furthermore, the use of fixed-frequency or simple pulse signals to apply disturbances makes it difficult to cope with current fluctuations under complex operating conditions, resulting in insufficient detection accuracy. Furthermore, when abnormal aging is detected, existing technologies are unable to promptly cut off the load current and record the anomaly, which can lead to safety hazards in the battery management system due to aging. Summary of the Invention

[0003] Based on this, it is necessary to provide a BMS function load aging test system and method to solve at least one of the above technical problems.

[0004] To achieve the above object, a BMS function load aging test method is provided, the method comprising the following steps:

[0005] Step S1: While the load current is continuously flowing through the battery management system, the bus current value, bus voltage value and the status code returned by the battery management system are periodically and synchronously collected to generate a real-time triplet;

[0006] Step S2: subtracting the real-time triplet from the preset historical triplet to determine the current drift, and marking the current drift as the amplitude instruction of the reverse current pulse;

[0007] Step S3: Instantaneously inject a reverse current pulse into the bus according to the amplitude instruction, and synchronously read the Hall output value during the pulse duration, and determine the Hall zero drift value by the difference between the Hall output value and the current value in the real-time triplet;

[0008] Step S4: Mapping the Hall zero drift to an insulation impedance disturbance value, applying it to the positive and negative terminals of the busbar in sequence at a preset pseudo-random beat, and reading the insulation response bit value of the battery management system in real time;

[0009] Step S5: If the difference between the insulation response bit value and the insulation impedance disturbance value is within the preset range, the battery management system is determined to be in a normal aging state and the loaded operating condition is maintained until the end of the detection cycle; if it is not within the preset range, the battery management system is determined to be in an abnormal aging state, the loaded current is immediately cut off and the abnormality is recorded.

[0010] This specification also provides a BMS function load aging test system for performing the BMS function load aging test method described above. The BMS function load aging test system includes:

[0011] The three-tuple real-time monitoring module is used to periodically and synchronously collect the bus current value, bus voltage value and the return status code of the battery management system during the process of continuous load current flowing through the battery management system, and generate real-time three-tuples;

[0012] A current pulse amplitude mapping module is used to subtract the real-time triplet from the preset historical triplet to determine the current drift and mark the current drift as the amplitude instruction of the reverse current pulse;

[0013] The Hall zero drift calculation module is used to instantaneously inject a reverse current pulse into the bus according to the amplitude instruction, and synchronously read the Hall output value during the pulse duration, and determine the Hall zero drift value by the difference between the Hall output value and the current value in the real-time triplet;

[0014] The busbar positive and negative terminal application module is used to map the Hall zero drift into an insulation impedance disturbance value, apply it to the positive and negative terminals of the busbar in sequence at a preset pseudo-random beat, and read the insulation response bit value of the battery management system in real time;

[0015] The on-load aging detection module is used to determine that the battery management system is in a normal aging state if the difference between the insulation response bit value and the insulation impedance disturbance value is within a preset range, and maintain the on-load operating condition until the end of the detection cycle; if it is not within the preset range, the battery management system is determined to be in an abnormal aging state, immediately cut off the on-load current and record the abnormality.

[0016] The beneficial effects of the present invention are:

[0017] On the one hand, by periodically collecting the bus current value, bus voltage value and BMS return status code to generate a real-time triplet, and calculating the current drift, the reverse current pulse is dynamically injected to calibrate the Hall zero drift. This process is based on the dynamic characteristics of current monitoring and can compensate for the cumulative error of the Hall sensor under load conditions in real time; further, by dynamically injecting reverse current pulses, the zero drift error of the Hall sensor can be calibrated in real time to ensure high precision and stability of current monitoring, avoid the lag of traditional methods, and can effectively cope with current fluctuations under complex working conditions, significantly improving the reliability of current monitoring.

[0018] Furthermore, a pseudo-random pulse is used to apply insulation impedance disturbances and monitor the insulation response values ​​in real time. The introduction of the pseudo-random pulse, due to its good autocorrelation and cross-correlation, effectively distinguishes signals from noise in complex electromagnetic environments. Furthermore, applying a disturbance signal with a pseudo-random pulse not only effectively avoids electromagnetic interference but also accurately captures subtle changes in insulation performance, significantly improving the accuracy of insulation performance testing.

[0019] On the other hand, the aging status of the BMS is monitored in real time under load conditions, and normal and abnormal aging are determined by the difference within a preset range, which can truly reflect the aging degree of the BMS. The present invention captures the dynamic changes of the BMS in actual work by performing detection under load conditions, thereby more accurately determining the aging status. In addition, when an abnormal aging status is detected, the load current can be immediately cut off and the abnormality can be recorded, effectively protecting the battery system and avoiding safety hazards caused by aging. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A flow chart showing the steps of a BMS function load aging test method;

[0021] Figure 2 This is a schematic diagram of the timing of applying pseudo-random beat sequence pulses;

[0022] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0023] The following is a clear and complete description of the technical method of the present invention in conjunction with the accompanying drawings. It is obvious that the embodiments described are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts are within the scope of protection of the present invention.

[0024] In addition, the accompanying drawings are merely schematic illustrations of the present invention and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor and / or microcontroller approaches.

[0025] It should be understood that although the terms "first," "second," and the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the exemplary embodiments. The term "and / or" as used herein includes any and all combinations of one or more of the listed associated items.

[0026] To achieve this, please refer to Figures 1 to 2 A BMS function load aging test method, the method comprising the following steps:

[0027] Step S1: While the load current is continuously flowing through the battery management system, the bus current value, bus voltage value and the status code returned by the battery management system are periodically and synchronously collected to generate a real-time triplet;

[0028] In an embodiment of the present invention, while the battery management system is continuously operating under load, bus current values, bus voltage values, and a status code returned by the battery management system are periodically and synchronously collected; the data collection cycle can be set to once per second. The collected bus current value, bus voltage value, and returned status code form a real-time triplet, denoted as (I real-time, U real-time, S real-time), where I real-time represents the real-time collected bus current value, U real-time represents the real-time collected bus voltage value, and S real-time represents the real-time returned status code of the battery management system.

[0029] In one implementation of the embodiment of the present invention, assuming that the bus current value collected at a certain moment is 10A, the bus voltage value is 12V, and the returned status code is 0x01, the real-time triplet is (10A, 12V, 0x01).

[0030] Step S2: subtracting the real-time triplet from the preset historical triplet to determine the current drift, and marking the current drift as the amplitude instruction of the reverse current pulse;

[0031] In this embodiment of the present invention, the current drift is obtained by subtracting the real-time triplet (I real-time, U real-time, S real-time) from the preset historical triplet (I history, U history, S history). The preset historical triplet is based on the historical data of the battery management system under normal aging conditions and is used as a reference benchmark. The calculation formula is as follows:

[0032]

[0033]

[0034]

[0035] in, Indicates the current drift, Indicates the voltage drift, Indicates the state code drift. The amplitude instruction marked as the reverse current pulse is used to inject the reverse current pulse into the bus in the subsequent steps.

[0036] In one implementation of the embodiment of the present invention, assuming that the preset historical triplet is (8A, 12V, 0x01) and the real-time triplet is (10A, 12V, 0x01), the calculated current drift amount is: ； Therefore, the amplitude instruction is 2A.

[0037] Step S3: Instantaneously inject a reverse current pulse into the bus according to the amplitude instruction, and synchronously read the Hall output value during the pulse duration, and determine the Hall zero drift value by the difference between the Hall output value and the current value in the real-time triplet;

[0038] In the embodiment of the present invention, according to the amplitude instruction , a reverse current pulse is injected into the busbar instantaneously. During the pulse duration, the output value of the Hall sensor is read synchronously and recorded as Hall. Calculate Hall output value Current values ​​in Hall and real-time triplet The real-time difference is used to determine the Hall zero drift.

[0039] In one implementation of the embodiment of the present invention, assuming that during the pulse duration, the Hall sensor output value is 8A and the current value in the real-time triplet is 10A, the Hall zero drift for:

[0040] ;

[0041] Step S4: Mapping the Hall zero drift to an insulation impedance disturbance value, applying it to the positive and negative terminals of the busbar in sequence at a preset pseudo-random beat, and reading the insulation response bit value of the battery management system in real time;

[0042] In the embodiment of the present invention, the Hall zero drift Mapped into insulation impedance disturbance values; specifically, a mapping relationship table can be established to determine the corresponding insulation impedance disturbance values ​​according to the size of the Hall zero drift; the insulation impedance disturbance values ​​are applied to the positive and negative ends of the busbar in sequence with a preset pseudo-random beat, and while applying the insulation impedance disturbance values, the insulation response bit value of the battery management system is read in real time, which is recorded as Sinsulation.

[0043] In one implementation of the present invention, it is assumed that the Hall zero drift The current is -2A. According to the mapping table, the corresponding insulation impedance disturbance value is 100Ω. The 100Ω insulation impedance disturbance value is applied to the positive and negative terminals of the busbar in sequence at a preset pseudo-random beat (for example, once every 5 seconds), and the insulation response bit value of the battery management system is read in real time.

[0044] Step S5: If the difference between the insulation response bit value and the insulation impedance disturbance value is within the preset range, the battery management system is determined to be in a normal aging state and the loaded operating condition is maintained until the end of the detection cycle; if it is not within the preset range, the battery management system is determined to be in an abnormal aging state, the loaded current is immediately cut off and the abnormality is recorded.

[0045] In this embodiment of the present invention, the difference between the insulation response bit value Sinsulation and the insulation impedance disturbance value is compared. If the difference is within a preset range, for example, ±10%, the battery management system is determined to be in a normal aging state and the loaded operating condition is maintained until the end of the detection period. If it is not within the preset range, the battery management system is determined to be in an abnormal aging state, the loaded current is immediately cut off, and the abnormality is recorded.

[0046] In one implementation of the embodiment of the present invention, assuming that the preset range is ±10%, the insulation resistance disturbance value is 100 The insulation response value read is 110 , then the difference is:

[0047]

[0048] As mentioned above, due to 10 Within the preset range (±10 ), so the battery management system is determined to be in a normal aging state and maintains the loaded working condition until the end of the detection cycle.

[0049] Preferably, step S1 includes the following steps:

[0050] Step S11: selecting the starting section, the middle section, and the end section along the busbar in sequence, and capturing the current value and voltage value in each section simultaneously, which are recorded as the starting double value, the middle double value, and the end double value respectively;

[0051] Step S12: while capturing the dual value, independently read the status code sent back by the battery management system and record them as the starting single code, the middle single code, and the end single code respectively;

[0052] Step S13: Based on the initial double value, the capture of the middle double value and the end double value is triggered in sequence at intervals that increase geometrically over time, and instantaneous cooling is applied to the busbar immediately after each capture;

[0053] Step S14: Combine the starting double value and the starting single code, the middle double value and the middle single code, and the end double value and the end single code in the order of the segments to generate a real-time triplet.

[0054] In one implementation of the present invention, assuming the current value captured in the starting segment is 10A and the voltage value is 12V, the starting double value is (10A, 12V). If the current value captured in the middle segment is 11A and the voltage value is 11.8V, the middle double value is (11A, 11.8V). If the current value captured in the ending segment is 9A and the voltage value is 11.5V, the ending double value is (9A, 11.5V).

[0055] In another implementation of an embodiment of the present invention, assuming that the status code read in the starting segment is 0x01, the status code read in the middle segment is 0x02, and the status code read in the end segment is 0x03, then the starting single code is 0x01, the middle single code is 0x02, and the end single code is 0x03.

[0056] In another implementation of this embodiment, assuming Δt is 0.1 seconds, the starting segment captures the starting dual value (10A, 12V) at t = 0. At t = 0.1 seconds, the middle segment captures the dual value (11A, 11.8V), and at t = 0.2 seconds, the end segment captures the dual value (9A, 11.5V). After each capture, instantaneous cooling is applied to the busbar.

[0057] In another implementation of the present invention, assuming the starting double value is (10A, 12V) and the starting single code is 0x01, the starting triplet is (10A, 12V, 0x01). If the middle double value is (11A, 11.8V) and the middle single code is 0x02, the middle triplet is (11A, 11.8V, 0x02). If the ending double value is (9A, 11.5V) and the ending single code is 0x03, the ending triplet is (9A, 11.5V, 0x03).

[0058] Preferably, step S2 includes the following steps:

[0059] Step S21: At the beginning of the current detection cycle, first read the bus current value, bus voltage value, and returned status code in the real-time triplet; then read the corresponding three items in the preset historical triplet saved in the previous detection cycle, subtract the three items in the two groups one by one, and combine the three differences to form the drift value;

[0060] Step S22: inputting the bus current difference, bus voltage difference and status code difference in the drift value into the current comparison interval, voltage comparison interval and status code comparison interval respectively, and outputting the comparison result;

[0061] Step S23: Corresponding the comparison result to the output current correction coefficient, voltage correction coefficient and status code correction coefficient;

[0062] Step S24: multiplying the drift amount by the output correction coefficient item by item, and recording the sum of the products as the drift amplitude;

[0063] Step S25: perform an XOR operation on the lower eight bits of the drift amplitude and the lower eight bits of the detection cycle sequence number, and use the decimal value of the operation result as an index to locate the reverse current pulse level in the preset pulse amplitude table to write into the amplitude instruction register.

[0064] In one implementation of the embodiment of the present invention, assuming that the real-time triplet is (10A, 12V, 0x01) and the preset historical triplet is (8A, 12V, 0x01), the calculated drift amount is (2A, 0V, 0).

[0065] In another implementation of the embodiment of the present invention, if the current comparison interval is [-1A, 1A], the voltage comparison interval is [-0.5V, 0.5V], and the status code comparison interval is [0, 0]; assuming that the current comparison result exceeds the interval, the output current correction coefficient is 0.8; the voltage comparison result is within the interval, the output voltage correction coefficient is 1.0; the status code comparison result is within the interval, the output status code correction coefficient is 1.0.

[0066] In another implementation of the present invention, the drift amount is multiplied by the output correction coefficients item by item, and the sum of the products is recorded as the drift amplitude. For example, assuming the drift amount is (2A, 0V, 0), and the correction coefficients are 0.8, 1.0, and 1.0 respectively, the drift amplitude is:

[0067] Bus current part: 2A×0.8=1.6;

[0068] Bus voltage part: 0V×1.0=0;

[0069] Status code part: 0×1.0=0;

[0070] The total drift amplitude is: 1.6+0+0=1.6.

[0071] In one implementation of the present invention, assume the drift amplitude is 1.6, with its lower eight bits being 0x01, and the detection cycle number is 10, with its lower eight bits being 0x0A. An exclusive-OR operation is performed to obtain 0x0B. 0x0B is converted to the decimal value 11, which is used as an index to locate the reverse current pulse level in a preset pulse amplitude table. Assuming that index 11 in the pulse amplitude table corresponds to a reverse current pulse level of 2A, the system writes 2A to the amplitude command register.

[0072] Preferably, step S3 includes the following steps:

[0073] Step S31: In the first detection cycle after the amplitude instruction takes effect, a reverse current pulse is injected into the starting section of the busbar; wherein the pulse width is limited to one detection cycle, and the pulse leading edge is aligned with the starting edge of the detection cycle;

[0074] Step S32: During the pulse duration, synchronously read the Hall output value within the same detection cycle, and write the Hall output value and the current value in the real-time triplet into the difference register;

[0075] Step S33: performing bit-by-bit subtraction on the Hall output value and the real-time current value based on the difference register, discarding the resulting overflow bit, and latching the resulting remaining bit as the Hall zero drift value.

[0076] In one implementation of the present invention, upon detecting that the amplitude command has taken effect, the pulse generator is immediately activated. The pulse generator generates a reverse current pulse based on the amplitude command value, with the pulse width matching the duration of the detection period. The pulse generator aligns the leading edge of the pulse with the start edge of the detection period. If the detection period is 10 milliseconds and the amplitude command is 2A, the pulse generator generates a reverse current pulse with a width of 10 milliseconds and an amplitude of 2A, and begins injecting the pulse at the start of the detection period.

[0077] In another implementation of the present invention, a data acquisition module is activated simultaneously with pulse injection to synchronously read the Hall sensor output value. The data acquisition module acquires the Hall sensor output value with high precision and frequency. The current value is extracted from the real-time triplet and compared with the Hall sensor output value. The difference between the Hall sensor output value and the real-time current value is calculated and written to a difference register. Assuming the Hall sensor output value is 8A and the current value in the real-time triplet is 10A, the value written to the difference register is -2A.

[0078] In another implementation of this embodiment, the difference data is read from a difference register and a bit-by-bit subtraction operation is performed on the difference data to ensure computational accuracy and reliability. During the computation, if an overflow bit is detected, it is discarded to avoid data errors. The remaining valid bits are latched as the Hall effect zero drift value and stored in a designated register. Assuming the value in the difference register is -2A, the system discards the overflow bit after bit-by-bit subtraction, resulting in a latched Hall effect zero drift value of -2A.

[0079] See also Figure 2, showing the application process of the pseudo-random sequence correction pulse. The red line in the figure indicates that the positive bus positive pulse maintains a constant amplitude of approximately 3.3, and the cyan line indicates that the mirror pulse on the negative bus presents a periodic waveform. The light blue and orange dots represent two independent beat interval sequences, where beat interval sequence 1 cycles in the order of 1ms→2ms→3ms→2ms→1ms, and beat interval sequence 2 cycles in the order of 3ms→2ms→1ms→2ms→3ms. The starting points of the two sequences differ by approximately 5ms, half a cycle. When beat interval sequence 1 is triggered, the system reads the current value from the Hall zero drift register to generate a positive pulse. The pulse width is synchronously scaled with the beat interval and applied to the positive bus. When beat interval sequence 2 is triggered, the system generates a mirror pulse. The pulse width is inversely scaled with the beat interval and applied to the negative bus. The entire process achieves dynamic compensation for the Hall sensor zero drift through this pseudo-random beat interval change and phase difference control. At the same time, after each pulse is applied, the system will record the corresponding beat sequence number and direction identification into the traceability queue for subsequent analysis.

[0080] Preferably, applying the preset pseudo-random beats to the positive and negative ends of the busbar in sequence in step S4 includes:

[0081] A first pseudo-random beat sequence is independently generated for the positive-end bus, and the beat interval is set to be an increasing-decreasing cycle;

[0082] A second pseudo-random beat sequence is independently generated for the negative bus, and the beat interval is set to be a decreasing-increasing cycle;

[0083] The starting points of the first pseudo-random beat sequence and the second pseudo-random beat sequence differ by half a period;

[0084] Each time the first sequence is triggered, the Hall zero drift is applied to the positive bus in the form of a positive pulse, and the pulse width is scaled synchronously with the beat interval;

[0085] Each time the second sequence is triggered, the Hall zero drift is applied to the negative bus in the form of a mirror pulse, and the pulse width and the beat interval are scaled inversely.

[0086] In an embodiment of the present invention, a pseudo-random sequence generator is started to generate independent beat sequences for the positive bus and the negative bus, respectively. The beat interval of the first pseudo-random beat sequence is set to an increasing-decreasing cycle. For example, the beat interval can be set to cycle in the order of 1ms, 2ms, 3ms, 2ms, and 1ms. The beat interval of the second pseudo-random beat sequence is set to a decreasing-increasing cycle.

[0087] It should be noted that the beat interval can be cycled in the order of 3ms, 2ms, 1ms, 2ms, and 3ms. When two beat sequences are started, the starting point of the first sequence is set to differ from the starting point of the second sequence by half a cycle.

[0088] It should be noted that if a complete cycle is 10ms, the difference between the starting point of the first sequence and the starting point of the second sequence is 5ms. When the trigger signal of the first sequence is detected, the current Hall zero drift value is read from the Hall zero drift register. Based on the current beat interval, the width of the positive pulse is adjusted to synchronize with the beat interval.

[0089] It should be noted that if the current tick interval is 2ms and the Hall effect zero drift is -2A, a positive pulse with a width of 2ms and an amplitude of 2A is generated and applied to the positive bus. When the second sequence of trigger signals is detected, the current Hall effect zero drift value is read from the Hall effect zero drift register. Based on the current tick interval, the width of the mirror pulse is adjusted so that it scales inversely with the tick interval.

[0090] It should be noted that if the current beat interval is 2ms and the Hall zero drift is -2A, a mirror pulse with a width of 1ms (assuming the reverse scaling ratio is 0.5) and an amplitude of 2A is generated and applied to the negative bus.

[0091] Preferably, the step S4 further includes applying the preset pseudo-random beats to the positive and negative ends of the busbar in sequence:

[0092] The absolute values ​​of the amplitudes of the positive pulse and the mirror pulse are taken from the same register, but with opposite signs;

[0093] After each pulse is applied, the corresponding beat number and direction identifier are immediately written into the traceback queue, where the queue depth is equal to the number of triggers.

[0094] In one implementation of the present invention, when the first pseudo-random beat sequence is triggered, the system reads the current Hall zero drift value from the Hall zero drift register. Based on this value, the system generates a positive pulse with the same absolute amplitude as the Hall zero drift value, but with a positive sign.

[0095] The specific operation is as follows: When the system detects the first sequence of trigger signals, it reads the current Hall zero drift value from the Hall zero drift register, assuming it is -2A. The system then generates a positive pulse with an amplitude of 2A. The system then adjusts the width of the positive pulse based on the current beat interval, scaling it in sync with the beat interval. For example, if the current beat interval is 2ms, a positive pulse with a width of 2ms and an amplitude of 2A is generated and applied to the positive bus.

[0096] In another implementation of the embodiment of the present invention, when the second pseudo-random beat sequence is triggered, the system reads the current Hall zero drift value from the Hall zero drift register; and generates a mirror pulse based on the value, the absolute value of whose amplitude is the same as the absolute value of the Hall zero drift, but the sign is negative.

[0097] The specific operation is as follows: When the system detects the second sequence of trigger signals, it reads the current Hall zero drift value from the Hall zero drift register, assuming it is -2A. The system generates a mirror pulse with an amplitude of -2A. Based on the current tick interval, the system adjusts the width of the mirror pulse, inversely scaling it with the tick interval. For example, if the current tick interval is 2ms, a mirror pulse with a width of 1ms (assuming an inverse scaling factor of 0.5) and an amplitude of -2A is generated and applied to the negative bus.

[0098] In another implementation of the embodiment of the present invention, after each pulse is applied, the system immediately writes the corresponding beat sequence number and direction identifier into a tracing queue, and the depth of the tracing queue is equal to the number of triggers.

[0099] The specific operation is as follows: after applying a forward pulse or a mirror pulse, the system records the current beat number and pulse direction (forward or mirror); the system writes this information into the retrospective queue; the depth of the retrospective queue is equal to the number of triggers, that is, the queue can store information about all trigger events; for example, if the current trigger is the 5th pulse and the direction is forward, the system will write (5, forward) into the retrospective queue.

[0100] Preferably, in step S4, reading the insulation response bit value of the battery management system in real time includes:

[0101] When the first sequence is triggered, the positive terminal observation window is started, a positive pulse is applied to the positive terminal bus, and the insulation response bit of the battery management system is latched at the moment the pulse width ends, which is recorded as the first response code;

[0102] When the second sequence is triggered, the negative terminal observation window is started, the mirror pulse is applied to the negative terminal bus, and the insulation response bit of the battery management system is latched again at the moment the pulse width ends, which is recorded as the second response code;

[0103] The first response code and the second response code are written into the isolation response queue in a triggering order to form an isolation response bit value.

[0104] In one implementation of the present invention, when the first pseudo-random beat sequence is triggered, the system initiates the positive terminal observation window and applies a positive pulse to the positive terminal bus. At the moment the pulse width ends, the system latches the battery management system's insulation response bit, which is recorded as the first response code.

[0105] The specific operation is as follows: When the first sequence of trigger signals is detected, the positive terminal observation window is activated; the current Hall zero drift value, assumed to be 2A, is read from the Hall zero drift register. A positive pulse with an amplitude of 2A is generated and applied to the positive bus. At the moment the pulse width ends, the insulation monitoring module latches the insulation response bit of the battery management system, which is recorded as the first response code. For example, if the pulse width is 2ms, the system latches the insulation response bit 2ms later, resulting in a first response code of 0x01.

[0106] In another implementation of the present invention, when the second pseudo-random beat sequence is triggered, the system starts the negative terminal observation window and applies a mirror pulse to the negative terminal bus. At the moment the pulse width ends, the system again latches the insulation response bit of the battery management system, which is recorded as the second response code.

[0107] The specific operation is as follows: When the second sequence trigger signal is detected, the negative terminal observation window is activated; the current Hall zero drift value is read from the Hall zero drift register, assuming it is -2A; a mirror pulse with an amplitude of -2A is generated and applied to the negative bus. At the moment the pulse width ends, the insulation monitoring module latches the insulation response bit of the battery management system, which is recorded as the second response code. For example, if the pulse width is 1ms, the system latches the insulation response bit 1ms later, resulting in a second response code of 0x02.

[0108] In another implementation of the present invention, after each pulse application, the system writes the latched first and second response codes into the isolation response queue in the order in which they were triggered. The isolation response queue is used to store the isolation response bit values ​​after each pulse application. For example, if the first response code of the first trigger is 0x01 and the second response code is 0x02, the system writes (0x01, 0x02) into the isolation response queue. If the first response code of the second trigger is 0x03 and the second response code is 0x04, the system writes (0x03, 0x04) into the isolation response queue, forming an isolation response bit value sequence.

[0109] Preferably, in step S5, if the difference between the insulation response bit value and the insulation impedance disturbance value is within a preset range, it includes:

[0110] In each detection cycle, the insulation response value is subtracted from the insulation impedance disturbance value, and the absolute value is taken and recorded as the difference;

[0111] When the difference is within the preset range, the battery management system status is marked as the detection continuation state within the detection cycle;

[0112] The current load current and voltage waveforms are locked and remain unchanged until the end of the detection cycle. During this period, no external interrupt signals are received.

[0113] In one implementation of the embodiment of the present invention, in each detection cycle, the system subtracts the insulation response bit value from the insulation impedance disturbance value, takes the absolute value, and records it as the difference.

[0114] The specific operations are as follows: the system reads the current insulation response bit value from the insulation response queue, and the system reads the current insulation impedance disturbance value from the preset insulation impedance disturbance value table. The system calculates the difference between the two and takes the absolute value; for example, assuming that the current insulation response bit value is 100Ω and the insulation impedance disturbance value is 95Ω, the difference is |100Ω-95Ω|=5Ω.

[0115] In another implementation of the present invention, when the difference is within a preset range, the battery management system is marked as in the "Continue Testing" state for the duration of the testing cycle. Simultaneously, the current load current and voltage waveforms are locked and remain unchanged until the end of the testing cycle, during which no external interrupt signals are accepted.

[0116] The system operates as follows: the calculated difference is compared with a preset range, assuming the range is 0Ω to 10Ω. If the difference is within the preset range (for example, 5Ω is within the range of 0Ω to 10Ω), the system marks the battery management system's status as "continue testing." The system locks the current load current and voltage waveforms to ensure they remain unchanged during the current test cycle. The system also sets a flag to indicate that no external interrupt signals will be accepted during the current test cycle to avoid disrupting the test process. For example, if the current load current is 10A and the voltage is 12V, the system locks these values ​​and maintains them unchanged during the test cycle, ignoring any external interrupt signals.

[0117] Preferably, if the condition is not within the preset range in step S5, the following steps are performed:

[0118] When the difference exceeds the preset range, an abnormal flag is generated and synchronously written to the trailing edge of the current detection cycle;

[0119] After the abnormal flag takes effect, an instantaneous shutdown action is triggered immediately, so that the load current drops to zero before the next clock edge;

[0120] After the shutdown action is completed, the exception mark and the current cycle sequence number are encapsulated into an exception frame and pushed into the traceability queue in sequence;

[0121] When the tracing queue is full, the subsequent beats are automatically locked and the load current is cut off.

[0122] In one implementation of an embodiment of the present invention, when the difference exceeds a preset range, the system generates an exception flag and writes the exception flag synchronously with the trailing edge of the current detection cycle. The calculated difference is compared with a preset range. Assume the preset range is 0Ω to 10Ω. If the difference exceeds the preset range (for example, a difference of 15Ω exceeds the range of 0Ω to 10Ω), the system generates an exception flag. The system writes the exception flag to the status register at the trailing edge of the current detection cycle, ensuring that the exception flag is synchronized with the current detection cycle.

[0123] In another implementation of the present invention, upon detecting that the abnormality flag has taken effect, the system immediately issues a shutdown command. The system controls the current controller to perform an instantaneous shutdown action, ensuring that the load current drops to zero before the next clock edge. For example, assuming the current clock frequency is 100 kHz, the system ensures that the load current drops to zero within 10 microseconds after detecting the abnormality flag.

[0124] In another implementation of this embodiment of the present invention, after the shutdown action is completed, the system reads the exception flag from the status register. The system obtains the sequence number of the current detection cycle and encapsulates the exception flag and the current cycle sequence number into an exception frame. The system pushes the exception frames into the traceback queue in order. For example, if the current cycle sequence number is 10 and the exception flag is 0x01, the system encapsulates (10, 0x01) into an exception frame and pushes it into the traceback queue.

[0125] In another implementation of this embodiment, the system continuously monitors the fill status of the traceback queue. When the traceback queue is full, the system issues a lock command, locking subsequent ticks. The system then shuts off the load current, ensuring a safe state. For example, assuming the traceback queue depth is 10, when the tenth abnormal frame is pushed into the queue, the system locks subsequent ticks and shuts off the load current.

[0126] The present invention is therefore intended to be illustrative and non-restrictive in all respects, with the scope of the invention being defined by the appended claims rather than the foregoing description, and all changes that come within the meaning and range of equivalents of the application documents are intended to be embraced therein.

[0127] The foregoing description is intended only to provide specific embodiments of the present invention, which will enable those skilled in the art to understand and implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not intended to be limited to the embodiments shown herein, but is to be construed in the widest possible manner consistent with the principles and novel features disclosed herein.

Claims

1. A BMS function load aging test method, characterized in that: Applied to a battery management system, the battery management system includes a busbar, and the BMS function load aging test method includes the following steps: Step S1: While the load current is continuously flowing through the battery management system, the bus current value, bus voltage value and the status code returned by the battery management system are periodically and synchronously collected to generate a real-time triplet; Step S2: subtracting the real-time triplet from the preset historical triplet to determine the current drift, and marking the current drift as the amplitude instruction of the reverse current pulse; Step S3: Instantaneously inject a reverse current pulse into the bus according to the amplitude instruction, and synchronously read the Hall output value during the pulse duration, and determine the Hall zero drift value by the difference between the Hall output value and the current value in the real-time triplet; Step S4: Mapping the Hall zero drift to an insulation impedance disturbance value, applying it to the positive and negative terminals of the busbar in sequence at a preset pseudo-random beat, and reading the insulation response bit value of the battery management system in real time; Step S5: If the difference between the insulation response bit value and the insulation impedance disturbance value is within the preset range, the battery management system is determined to be in a normal aging state and the loaded operating condition is maintained until the end of the detection cycle; if it is not within the preset range, the battery management system is determined to be in an abnormal aging state, the loaded current is immediately cut off and the abnormality is recorded.

2. The BMS function load aging test method according to claim 1, characterized in that: Step S1 includes the following steps: Step S11: selecting the starting section, the middle section, and the end section along the busbar in sequence, and capturing the current value and voltage value in each section simultaneously, which are recorded as the starting double value, the middle double value, and the end double value respectively; Step S12: while capturing the dual value, independently read the status code sent back by the battery management system and record them as the starting single code, the middle single code, and the end single code respectively; Step S13: Based on the initial double value, the capture of the middle double value and the end double value is triggered in sequence at intervals that increase geometrically over time, and instantaneous cooling is applied to the busbar immediately after each capture; Step S14: Combine the starting double value and the starting single code, the middle double value and the middle single code, and the end double value and the end single code in the order of the segments to generate a real-time triplet.

3. The BMS function load aging test method according to claim 1, characterized in that: Step S2 includes the following steps: Step S21: At the beginning of the current detection cycle, first read the bus current value, bus voltage value, and returned status code in the real-time triplet; then read the corresponding three items in the preset historical triplet saved in the previous detection cycle, subtract the three items in the two groups one by one, and combine the three differences to form the drift value; Step S22: inputting the bus current difference, bus voltage difference and status code difference in the drift value into the current comparison interval, voltage comparison interval and status code comparison interval respectively, and outputting the comparison result; Step S23: Corresponding the comparison result to the output current correction coefficient, voltage correction coefficient and status code correction coefficient; Step S24: multiplying the drift amount by the output correction coefficient item by item, and recording the sum of the products as the drift amplitude; Step S25: perform an XOR operation on the lower eight bits of the drift amplitude and the lower eight bits of the detection cycle sequence number, and use the decimal value of the operation result as an index to locate the reverse current pulse level in the preset pulse amplitude table to write into the amplitude instruction register.

4. The BMS function load aging test method according to claim 1, characterized in that: Step S3 includes the following steps: Step S31: In the first detection cycle after the amplitude instruction takes effect, a reverse current pulse is injected into the starting section of the busbar; wherein the pulse width is limited to one detection cycle, and the pulse leading edge is aligned with the starting edge of the detection cycle; Step S32: During the pulse duration, synchronously read the Hall output value within the same detection cycle, and write the Hall output value and the current value in the real-time triplet into the difference register; Step S33: performing bit-by-bit subtraction on the Hall output value and the real-time current value based on the difference register, discarding the resulting overflow bit, and latching the resulting remaining bit as the Hall zero drift value.

5. The BMS function load aging test method according to claim 1, characterized in that: In step S4, applying the preset pseudo-random beat to the positive and negative ends of the busbar in sequence includes: A first pseudo-random beat sequence is independently generated for the positive-end bus, and the beat interval is set to be an increasing-decreasing cycle; A second pseudo-random beat sequence is independently generated for the negative bus, and the beat interval is set to be a decreasing-increasing cycle; The starting points of the first pseudo-random beat sequence and the second pseudo-random beat sequence differ by half a period; Each time the first sequence is triggered, the Hall zero drift is applied to the positive bus in the form of a positive pulse, and the pulse width is scaled synchronously with the beat interval; Each time the second sequence is triggered, the Hall zero drift is applied to the negative bus in the form of a mirror pulse, and the pulse width and the beat interval are scaled inversely.

6. The BMS function load aging test method according to claim 5, characterized in that: The step S4 of sequentially applying the preset pseudo-random beats to the positive and negative ends of the bus also includes: The absolute values ​​of the amplitudes of the positive pulse and the mirror pulse are taken from the same register, but with opposite signs; After each pulse is applied, the corresponding beat number and direction identifier are immediately written into the traceback queue, where the queue depth is equal to the number of triggers.

7. The BMS function load aging test method according to claim 5, characterized in that: Reading the insulation response bit value of the battery management system in real time in step S4 includes: When the first sequence is triggered, the positive terminal observation window is started, a positive pulse is applied to the positive terminal bus, and the insulation response bit of the battery management system is latched at the moment the pulse width ends, which is recorded as the first response code; When the second sequence is triggered, the negative terminal observation window is started, the mirror pulse is applied to the negative terminal bus, and the insulation response bit of the battery management system is latched again at the moment the pulse width ends, which is recorded as the second response code; The first response code and the second response code are written into the isolation response queue in a triggering order to form an isolation response bit value.

8. The BMS function load aging test method according to claim 1, characterized in that: In step S5, if the difference between the insulation response bit value and the insulation impedance disturbance value is within a preset range, it includes: In each detection cycle, the insulation response value is subtracted from the insulation impedance disturbance value, and the absolute value is taken and recorded as the difference; When the difference is within the preset range, the battery management system status is marked as the detection continuation state within the detection cycle; The current load current and voltage waveforms are locked and remain unchanged until the end of the detection cycle. During this period, no external interrupt signals are received.

9. The BMS function load aging test method according to claim 8, characterized in that: If the condition in step S5 is not within the preset range, it includes: When the difference exceeds the preset range, an abnormal flag is generated and synchronously written to the trailing edge of the current detection cycle; After the abnormal flag takes effect, an instantaneous shutdown action is triggered immediately, so that the load current drops to zero before the next clock edge; After the shutdown action is completed, the exception mark and the current cycle sequence number are encapsulated into an exception frame and pushed into the traceability queue in sequence; When the tracing queue is full, the subsequent beats are automatically locked and the load current is cut off.

10. A BMS function load aging test system, characterized in that: For executing the BMS function load aging test method according to claim 1, the BMS function load aging test system comprises: The three-tuple real-time monitoring module is used to periodically and synchronously collect the bus current value, bus voltage value and the return status code of the battery management system during the process of continuous load current flowing through the battery management system, and generate real-time three-tuples; A current pulse amplitude mapping module is used to subtract the real-time triplet from the preset historical triplet to determine the current drift and mark the current drift as the amplitude instruction of the reverse current pulse; The Hall zero drift calculation module is used to instantaneously inject a reverse current pulse into the bus according to the amplitude instruction, and synchronously read the Hall output value during the pulse duration, and determine the Hall zero drift value by the difference between the Hall output value and the current value in the real-time triplet; The busbar positive and negative terminal application module is used to map the Hall zero drift into an insulation impedance disturbance value, apply it to the positive and negative terminals of the busbar in sequence at a preset pseudo-random beat, and read the insulation response bit value of the battery management system in real time; The on-load aging detection module is used to determine that the battery management system is in a normal aging state if the difference between the insulation response bit value and the insulation impedance disturbance value is within a preset range, and maintain the on-load operating condition until the end of the detection cycle; if it is not within the preset range, the battery management system is determined to be in an abnormal aging state, immediately cut off the on-load current and record the abnormality.

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