Electronic device, data processing method, device, medium and program product

Abstract

The invention discloses electronic equipment, a data processing method, equipment, a medium and a program product in the technical field of computers. In each board card, a first memory is used for storing processor identification information corresponding to the board card; the first memory is used for storing the mark information of the slot position of each board card, the second memory is used for storing the mark information of the slot position of each board card, the first memory and the second memory gate the second link at the gate, and any processor can access the first memory and the second memory through the second connector in each board card and the second link; therefore, according to the data stored in the first memory and the second memory, the silk-screen information of the slot position of each board card is confirmed, and the slot position of each board card and the equipment connected with the slot position are positioned. According to the scheme, the lamps of the slots do not need to be triggered one by one to flicker, and the positioning efficiency of the physical slots can be improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an electronic device, a data processing method, a device, a medium, and a program product. Background Art

[0002] Typically, you can set an indicator light at the physical slot to flash the light in a specific slot to locate the physical location of the device connected to that slot. However, in high-density servers, there are many physical slots, and triggering the light in each slot to flash one by one reduces the efficiency of physical slot location.

[0003] Therefore, how to improve the positioning efficiency of physical slots is a problem that those skilled in the art need to solve. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide an electronic device, a data processing method, a device, a medium and a program product to improve the positioning efficiency of physical slots.

[0005] In a first aspect, the present application provides an electronic device comprising: at least one processor and at least one board; wherein any target board in the at least one board comprises: a first connector, a second connector, a selector, a first memory and a second memory; the first connector is connected to the selector via a first link; the second connector is connected to the selector and the second memory via a second link; the selector is also connected to the first memory; the selector is used to select the first link or the second link; the first memory is used to store processor identification information corresponding to the target board; the second memory is used to store label information of the slots included in each board; accordingly, the first connector and the second connector in each board are connected to any processor.

[0006] In a second aspect, the present application provides a data processing method, which is applied to an electronic device, the electronic device comprising: at least one processor and at least one board card; wherein any target board card in the at least one board card comprises: a first connector, a second connector, a selector, a first memory, and a second memory; the first connector is connected to the selector through a first link; the second connector is connected to the selector and the second memory through a second link; the selector is also connected to the first memory; the selector is used to select the first link or the second link; the first memory is used to store the processor identification information corresponding to the target board card; the second memory is used to store the marking information of the slots included in each board card; the first connector and the second connector in each board card are connected to any one processor; accordingly, the data processing method comprises: after any processor is connected to the second link in the target board card, controlling the basic input and output system to read the processor identification information from the first memory, and reading the marking information of the slots included in the target board card from the second memory; determining the silkscreen information of the slots included in the target board card based on the processor identification information and the marking information of the slots included in the target board card.

[0007] In a third aspect, the present application provides an electronic device, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the aforementioned disclosed data processing method.

[0008] In a fourth aspect, the present application provides a non-volatile storage medium for storing a computer program, wherein the computer program implements the aforementioned disclosed data processing method when executed by a processor.

[0009] In a fifth aspect, the present application provides a computer program product, comprising a computer program / instruction, which implements the steps of the aforementioned disclosed data processing method when executed by a processor.

[0010] It can be seen from the above scheme that the present application provides an electronic device, including: at least one processor and at least one board card; wherein, any target board card in the at least one board card includes: a first connector, a second connector, a selector, a first memory and a second memory; the first connector is connected to the selector through a first link; the second connector is connected to the selector and the second memory through a second link; the selector is also connected to the first memory; the selector is used to: select the first link or the second link; the first memory is used to: store the processor identification information corresponding to the target board card; the second memory is used to: store the label information of the slots included in each board card; accordingly, the first connector and the second connector in each board card are connected to any processor.

[0011] It can be seen that the beneficial effects of this application are as follows: in each board, the first memory is used to store the processor identification information corresponding to the board; the second memory is used to store the marking information of the slot included in each board, and the first memory and the second memory are selected by the selector to select the second link. Any processor can access the first memory and the second memory through the second connector in each board and the second link, thereby confirming the silkscreen information of the slot of each board based on the data stored in the first memory and the second memory, thus completing the positioning of the slot of each board and the device connected to it. This solution does not need to trigger the lights of each slot to flash one by one, which can improve the efficiency of physical slot positioning.

[0012] Correspondingly, the data processing device, medium and program product provided by this application also have the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0014] Figure 1 A schematic diagram of an electronic device disclosed in this application; Figure 2 Schematic diagram of another electronic device disclosed in this application; Figure 3 A flow chart of a data processing method disclosed in this application; Figure 4 A schematic diagram of another electronic device disclosed in this application; Figure 5 A server structure diagram provided for this application; Figure 6 This is a terminal structure diagram provided for this application. DETAILED DESCRIPTION

[0015] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0016] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0017] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0018] Typically, an indicator light can be set at a physical slot to trigger the light in a specific slot to flash, thereby locating the physical location of the device connected to that slot. In high-density servers, there are many physical slots, and the need to trigger the light in each slot to flash individually results in low physical slot location efficiency. Therefore, this application provides a solution that can improve the efficiency of physical slot location.

[0019] See also Figure 1 As shown, an embodiment of the present application discloses an electronic device comprising: at least one processor and at least one board; wherein any target board in the at least one board comprises: a first connector, a second connector, a selector, a first memory, and a second memory; the first connector is connected to the selector via a first link; the second connector is connected to the selector and the second memory via a second link; and the selector is further connected to the first memory. The at least one processor may be provided on a motherboard. The board may be specifically a server expansion card or a riser card.

[0020] Among them, the selector is used to select the first link or the second link; the first memory is used to store the processor identification information corresponding to the target board; the second memory is used to store the label information of the slots included in each board, such as the label information of slot 0 is SLOT0; accordingly, the first connector and the second connector in each board are connected to any processor.

[0021] In one example, the first connector is an MCIO connector, and the second connector is an I2C (Inter-Integrated Circuit Bus) connector. Accordingly, the I2C connector on each board is connected to the processor via the motherboard-side I2C connector (i.e., the motherboard-side second connector). To extend the I2C link, an I2C switch (i.e., an expander) can be provided between the processor and the motherboard-side I2C connector. For example, a processor is connected to an I2C switch, and the I2C switch's eight outputs are connected to eight motherboard-side I2C connectors. These eight motherboard-side I2C connectors are then connected to the I2C connectors on eight boards. Accordingly, the MCIO connector on each board is connected to a port on a processor via the motherboard-side MCIO connector (i.e., the motherboard-side first connector). For example, a processor has four ports, each of which is connected to a motherboard-side MCIO connector, and each motherboard-side MCIO connector is connected to the first connector on each board. In one embodiment, the processor is connected to multiple connectors (e.g., multiple motherboard-side I2C connectors) via an expander (e.g., an I2C switch), and each connector is connected to the second connector on a different board. That is: any processor is connected to multiple motherboard-side second connectors through an expander, and each motherboard-side second connector is respectively connected to the second connector in a different board; any processor is connected to multiple motherboard-side first connectors, and each motherboard-side first connector is respectively connected to the first connector in a different board.

[0022] In one embodiment, the gate includes: a selector (such as Figure 2 MUX in the ) and the signaler connected to the selector (such as Figure 2 IO EXPANDER in the signal device is used to: output for connecting the first link (such as Figure 2 or outputs a first signal for connecting a second link (such as MCIO I2C in Figure 2 The selector is used to: connect the first link and disconnect the second link according to the first signal; or connect the second link and disconnect the first link according to the second signal.

[0023] When the electronic device is turned on, the signal transmitter is set to output a high-order signal by default so that the first link can reach the first memory. Specifically, the signal transmitter is used to output a first signal when the electronic device is turned on. In one embodiment, any processor is used to control the basic input and output system to write a second signal in the signal transmitter after the second link in the target board is connected, so that the signal transmitter outputs the second signal. Any processor is used to control the basic input and output system to write a first signal in the signal transmitter after the first link in the target board is connected, so that the signal transmitter outputs the first signal. In one embodiment, the signal transmitter is used to output a high-order signal as the first signal; and output a low-order signal as the second signal.

[0024] To enable the first memory to store the processor identification information corresponding to the target board, this embodiment causes the processor connected to the target board to control the basic input / output system to write the processor identification information corresponding to the target board into the first memory after the first link in the target board is connected. In one embodiment, the processor connected to the target board is configured to control the basic input / output system to write the processor serial number and port number of the target board into the first memory as the processor identification information after the first link in the target board is connected. For example, if the processor serial number is 000 and the port number is 0001, the processor identification information can be 0000001.

[0025] In one embodiment, the second memory is further used to store the board information of the target board, such as the board manufacturer, serial number, etc.

[0026] In one embodiment, the second memory is used to: construct a physical location table based on the tag information of the slots included in each board, and store the physical location table. The physical location table can be found in Table 1, and the contents of Table 1 can be compared with Figure 2 The physical location table is burned into the second memory.

[0027] Table 1

[0028] In one embodiment, any processor is used to: when the second link in the target board is connected, control the basic input and output system to read the processor identification information from the first memory, and read the tag information of the slot included in the target board from the second memory; determine the silk screen information of the slot included in the target board based on the processor identification information and the tag information of the slot included in the target board. For example: the processor number 000 is spliced ​​with the port number 0001 of the processor to obtain the processor identification information 0000001, where 000 represents CPU0 and the port number 0001 represents port PE0. Then, when the tag information of the slot is SLOT0, the silk screen information of the slot can be recorded as: CPU0_PE0_SLOT0. Accordingly, the processor can record the silk screen information, generate a target log based on the recorded content, and display the target log. The processor can splice the processor identification information corresponding to the target board and the tag information of the slot included in the target board into silk screen information.

[0029] After any processor determines the silkscreen information of the slots included in the target board with the help of the basic input and output system, the basic input and output system can send it to a management controller connected to the processor, such as a BMC (Baseboard Management Controller). The management controller records all the silkscreen information, generates a target log based on the silkscreen information, and displays the target log.

[0030] In one embodiment, any processor is used to: when the electronic device is powered on, record the processor identification information corresponding to each board and generate a logical location table. The physical location table can be found in Table 2, and the contents of Table 2 can be compared with Figure 2 In Table 2, CPU ADDR2, CPU ADDR1, and CPU ADDR0 constitute the number 000, and VPP ADDR3, VPP ADDR2, VPP ADDR1, and VPPADDR0 constitute the port number 0001. Therefore, the first row of Table 2 indicates that port PE0 of CPU0 is connected to MCIO connector 0, and the processor identification information corresponding to this path is 0000001.

[0031] Table 2

[0032] It should be noted that the first connector in any of the boards is connected to a slot included in the board, and the slot is used to connect to a network card, a disk array or an accelerator card. A slot can have one or more ports for connecting to PCIE devices.

[0033] As can be seen, in this embodiment, the first memory on each board stores the processor identification information corresponding to the board; the second memory stores the marking information of the slot included in each board. The first and second memories are connected to each other via the second link selected by the selector. The processor can access the first and second memories through the second connector on each board and the second link. Based on the data stored in the first and second memories, the silkscreen information of each board's slot is confirmed, thus completing the location of each board's slot and its connected device. This solution eliminates the need to trigger the lights of each slot to flash one by one, which can improve the efficiency of physical slot location.

[0034] See Figure 2 , there is a BMC and two CPUs on the motherboard. The four ports of each CPU are connected to four MCIO connectors, and each MCIO connector is connected to the MCIO connector of an expansion card (i.e., board); the BIOS (Basic Input Output System) expands 8 I2C channels through the I2C Switch and connects to the eight I2C connectors on the motherboard, and each I2C connector is connected to the I2C connector of an expansion card; in this design, 8 expansion cards can be connected, and the internal structure of each expansion card is the same.

[0035] Specifically, each expansion card includes an I2C connector, an MCIO connector, a PCIE slot, a multiplexer (MUX), an IO expander (IO expander), a secondary memory (board EEPROM), and a primary memory (silicon-printed EEPROM). The MUX selects one of two I2C signals (MCIO I2C and Header I2C) and connects it to the silkscreen EEPROM. The silkscreen EEPROM stores the logical source of the expansion card's upstream PCIE signals, namely the CPU and CPU port number connected upstream to the expansion card. The IO expander outputs the MUX_SEL signal to control the MUX select function. The board EEPROM stores the physical information of all the expansion card's PCIE slots, which forms a physical location table.

[0036] Connect the I2C connectors on the motherboard according to Table 1. For example, I2C connector 0 connects to the expansion card in slot 0, I2C connector 1 connects to the expansion card in slot 1, I2C connector 2 connects to the expansion card in slot 2, and so on. This forms a physical location table, which defines the correspondence between I2C connectors and the physical locations of slots on the motherboard. For example, I2C connector 0 corresponds to location ID 0 and physical location SLOT 0.

[0037] The MCIO connector on the motherboard is connected according to Table 2, which defines the CPU port information corresponding to the MCIO connector on the motherboard. For example, the CPU ADDR (CPU number) 000 and VPP ADDR (CPU port number) 0001 corresponding to MCIO connector 0 indicate that the upstream PCIE of MCIO connector 0 comes from CPU0_PE0.

[0038] The motherboard's CPU outputs PCIE signals and I2C signals (this I2C path is called MCIO I2C) to the motherboard's MCIO connector, which is then connected to the MCIO connector on the expansion card via a cable. The MCIO connector on the expansion card connects the PCIE to the PCIE slot. The MCIO I2C is then selected by the MUX and connected to the silkscreen EEPROM on the expansion card.

[0039] The CPU also provides another I2C channel (called the Header I2C). This channel, after passing through the I2C switch on the motherboard, expands into multiple I2C channels, each connected to multiple I2C connectors on the motherboard. These channels are then connected to the I2C connectors on the expansion card via cables. The Header I2C is then selected by the MUX on the expansion card and connected to the silkscreen EEPROM. The IOEXPANDER and Board EEPROM on the expansion card are also connected to the Header I2C. The MUX selection function is controlled by writing the MUX_SEL signal to the IOEXPANDER register output from the Header I2C. When the MUX_SEL signal is high, the MCIO I2C is connected to the silkscreen EEPROM. When the MUX_SEL signal is low, the Header I2C is connected to the silkscreen EEPROM.

[0040] Specifically, when the motherboard is powered on, the MUX_SEL signal on the expansion card defaults to high, and the MUX connects the MCIO I2C to the silkscreen EEPROM by default.

[0041] The BIOS writes the CPU ADDD and VPP ADDR values ​​corresponding to each MCIO connector on the motherboard to the silk-screen EEPROM on the expansion card through the MCIO I2C according to the contents defined in the logical location table. For example, 0000001 is written to the EEPROM on the expansion card connected to MCIO connector 0, 0000010 is written to the EEPROM on the expansion card connected to MCIO connector 1, and so on.

[0042] The BIOS writes the IO EXPANDER register through the Header I2C to pull the MUX_SEL signal low, controlling the MUX to connect the Header I2C to the silkscreen EEPROM.

[0043] The BIOS switches the I2C switch to channel 0 and reads the information in the silkscreen EEPROM on the expansion card connected to the I2C connector 0 and the physical location table in the board EEPROM through the header I2C. The BIOS switches the I2C switch to channel 1 and reads the information in the silkscreen EEPROM on the expansion card connected to the I2C connector 1 and the physical location table in the board EEPROM through the header I2C. The BIOS switches the I2C switch to channel 2 and reads the information in the silkscreen EEPROM on the expansion card connected to the I2C connector 2 and the physical location table in the board EEPROM through the header I2C. The same applies to other channels.

[0044] If a network card is connected to the expansion card's slot, the BIOS generates a complete silkscreen of the logical and physical locations of the PCIE network card based on the information it reads. For example, the BIOS reads 0000001 from the silkscreen EEPROM on the expansion card connected to I2C connector 0. According to the logical location table recorded in the BIOS, 0000001 represents CPU0_PE0. According to the physical location table in the expansion card's BOARD EEPROM, I2C connector 0 corresponds to Location ID 0 and a fixed physical location of SLOT 0. Therefore, the complete silkscreen of this PCIE network card is CPU0_PE0_SLOT0. The BIOS reads 0010001 from the silkscreen EEPROM on the expansion card connected to I2C connector 2. According to the logical location table recorded in the BIOS, 0010001 represents CPU1_PE0. According to the physical location table in the BOARD EEPROM on the expansion card, the location ID corresponding to I2C connector 2 is 2 and the fixed physical location is SLOT2. Therefore, the complete silkscreen of this PCIE network card is CPU1_PE0_SLOT2.

[0045] The BIOS can also transmit silkscreen information to the BMC for logging and display. The BIOS can run on any processor. For example, a dedicated processor can be set up on the motherboard to run the BIOS, or the BIOS can be run on other processors or graphics processors.

[0046] This embodiment adaptively binds the logical and physical locations of PCIE network cards, automatically obtaining the PCIE source and current physical location of a particular network card, effectively improving the efficiency of locating faulty network cards. In hyperscale data centers, the physical locations of all network cards can be accurately and timely located simultaneously. Because the logical and physical locations are adaptively bound, the technical solution of this embodiment can be used on different models, even with different configurations.

[0047] The following introduces a data processing method provided in an embodiment of the present application. The data processing method described below can be referenced with other embodiments described in this document.

[0048] The present application discloses a data processing method, which is applied to an electronic device. The electronic device includes: at least one processor and at least one board; wherein any target board in the at least one board includes: a first connector, a second connector, a gate, a first memory, and a second memory; the first connector is connected to the gate via a first link; the second connector is connected to the gate and the second memory via a second link; the gate is also connected to the first memory; the gate is used to gate the first link or the second link; the first memory is used to store processor identification information corresponding to the target board; the second memory is used to store label information of slots included in each board; the second connector in each board is connected to the processor; the first connector and the second connector in each board are connected to any one of the processors;

[0049] See also Figure 3 As shown, the data processing method disclosed in the embodiment of the present application includes: S301: After the second link in the target board is connected, the processor controls the basic input and output system to read the processor identification information corresponding to the target board from the first memory in the target board, and read the label information of the slot included in the target board from the second memory.

[0050] S302: The processor determines the silkscreen information of the slots included in the target board according to the processor identification information corresponding to the target board and the marking information of the slots included in the target board.

[0051] The method of this embodiment can be specifically executed by BIOS, that is, the BIOS relies on any processor to run to execute S301 and S302.

[0052] In one embodiment, the selector includes: a selector and a signaler connected to the selector; the signaler is used to: output a first signal for connecting a first link; or output a second signal for connecting a second link; the selector is used to: connect the first link and disconnect the second link according to the first signal; or connect the second link and disconnect the first link according to the second signal.

[0053] In one embodiment, the signaler is configured to output a first signal when the electronic device is powered on.

[0054] In one embodiment, the arbitrary processor is configured to: when the second link in the target board is connected, control the basic input and output system to write the second signal into the annunciator, so that the annunciator outputs the second signal.

[0055] In one embodiment, any processor is configured to: when the first link in the target board is connected, control the basic input / output system to write the first signal into the annunciator, so that the annunciator outputs the first signal.

[0056] In one embodiment, the signaler is configured to: output a high-bit signal as the first signal; and output a low-bit signal as the second signal.

[0057] In one embodiment, the processor is connected to a plurality of mainboard-side second connectors via an expander, and each mainboard-side second connector is connected to a second connector in a different board.

[0058] In one embodiment, the processor connected to the target board is configured to: when the first link in the target board is connected, control the basic input and output system to write the processor identification information corresponding to the target board into the first memory.

[0059] In one embodiment, the processor connected to the target board is configured to: when the first link in the target board is connected, control the basic input and output system to write the serial number and port number of the processor connected to the target board into the first memory as processor identification information.

[0060] In one embodiment, the second memory is further configured to store the board information of the target board.

[0061] In one embodiment, the second memory is used to: construct a physical location table based on the marking information of the slots included in each board, and store the physical location table.

[0062] In one embodiment, any processor is used to: when the second link in the target board is connected, control the basic input and output system to read the processor identification information from the first memory, and read the marking information of the slot included in the target board from the second memory; determine the silk screen information of the slot included in the target board based on the processor identification information and the marking information.

[0063] In one embodiment, any processor is configured to record silk screen information, generate a target log based on the recorded content, and display the target log.

[0064] In one embodiment, any processor is configured to: combine the processor identification information and the marking information into silk-screen information.

[0065] In one embodiment, any processor is configured to: when the electronic device is powered on, record the processor identification information corresponding to each board and generate a logic position table.

[0066] In one embodiment, the first connector in any board is connected to a slot included in the board, and the slot is used to connect to a network card, a disk array, or an accelerator card.

[0067] Among them, for more specific working processes of each module and unit in this embodiment, reference can be made to the corresponding contents disclosed in the aforementioned embodiments, which will not be repeated here.

[0068] It can be seen that this embodiment provides a data processing device that can adaptively bind the logical location and physical location of a PCIE network card, and can automatically obtain the PCIE source and current physical location of a certain network card device, effectively improving the efficiency of locating faulty network cards.

[0069] The following describes an electronic device provided in an embodiment of the present application. The electronic device described below can be cross-referenced with other embodiments described herein. The electronic device in this embodiment can include various functional modules such as a processor, a board, a gate, a first memory, and a second memory.

[0070] See also Figure 4 As shown, an embodiment of the present application discloses an electronic device, including: a memory 401 for storing a computer program; a processor 402 for executing the computer program to implement the method disclosed in any of the above embodiments.

[0071] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: selecting the first link or the second link.

[0072] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: storing processor identification information corresponding to the target board.

[0073] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: storing the marking information of the slots included in each board.

[0074] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: after the second link in the target board is connected, the basic input and output system is controlled to read the processor identification information from the first memory, and the marking information of the slot included in the target board is read from the second memory.

[0075] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: determining the silkscreen information of the slot included in the target board according to the processor identification information and the marking information.

[0076] In this embodiment, when the processor executes the computer program stored in the memory, the processor may specifically implement the following steps: outputting a first signal for connecting the first link; or outputting a second signal for connecting the second link.

[0077] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: connecting the first link and disconnecting the second link according to the first signal; or connecting the second link and disconnecting the first link according to the second signal.

[0078] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: if the electronic device is powered on, a first signal is output.

[0079] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: when the second link in the target board is connected, the basic input and output system is controlled to write the second signal in the annunciator so that the annunciator outputs the second signal.

[0080] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: when the first link in the target board is connected, the basic input and output system is controlled to write the first signal in the annunciator so that the annunciator outputs the first signal.

[0081] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: outputting a high-bit signal as the first signal; and outputting a low-bit signal as the second signal.

[0082] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: when the first link in the target board is connected, the basic input and output system is controlled to write the processor identification information corresponding to the target board into the first memory.

[0083] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: when the first link in the target board is connected, the basic input and output system is controlled to write the number and port number of the processor connected to the target board into the first memory as processor identification information.

[0084] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: storing the board information of the target board.

[0085] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: constructing a physical location table based on the marking information of the slots included in each board, and storing the physical location table.

[0086] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: when the second link in the target board is connected, the basic input and output system is controlled to read the processor identification information from the first memory, and read the marking information of the slot included in the target board from the second memory; and the silk screen information of the slot included in the target board is determined based on the processor identification information and the marking information.

[0087] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: recording silk screen information, generating a target log based on the recorded content, and displaying the target log.

[0088] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: splicing the processor identification information and the marking information into silk-screen information.

[0089] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: when the electronic device is powered on, the processor identification information corresponding to each board is recorded to generate a logic position table.

[0090] Furthermore, the embodiment of the present application also provides an electronic device. The electronic device can be Figure 5 The server shown can also be Figure 6 Terminal shown. Figure 5 and Figure 6 Each of the diagrams is a structural diagram of an electronic device according to an exemplary embodiment, and the contents in the diagrams cannot be considered as any limitation on the scope of use of the present application.

[0091] Figure 5This is a schematic diagram of the structure of a server provided in an embodiment of the present application. The server may specifically include: at least one processor, at least one memory, a power supply, a communication interface, an input / output interface, and a communication bus. The memory is used to store a computer program, which is loaded and executed by the processor to implement the relevant steps of the data processing disclosed in any of the aforementioned embodiments.

[0092] In this embodiment, the power supply is used to provide operating voltage for each hardware device on the server; the communication interface can create a data transmission channel between the server and external devices. The communication protocol it follows is any communication protocol that can be applied to the technical solution of this application and is not specifically limited here; the input and output interface is used to obtain external input data or output data to the outside world. The specific interface type can be selected according to specific application needs and is not specifically limited here.

[0093] In addition, the memory as a carrier for resource storage can be a read-only memory, random access memory, disk or CD, etc. The resources stored thereon include operating system, computer programs and data, etc. The storage method can be temporary storage or permanent storage.

[0094] The operating system is used to manage and control the hardware devices and computer programs on the server, enabling the processor to operate and process data in the memory. It can be Windows Server, NetWare, Unix, Linux, etc. In addition to computer programs capable of performing the data processing methods disclosed in any of the aforementioned embodiments, computer programs can also include computer programs capable of performing other specific tasks. Data can include data such as application update information and other data such as application developer information.

[0095] Figure 6 This is a schematic diagram of the structure of a terminal provided in an embodiment of the present application. The terminal may specifically include but is not limited to a smartphone, tablet computer, laptop computer or desktop computer.

[0096] Generally, the terminal in this embodiment includes: a processor and a memory.

[0097] The processor may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor may be implemented in at least one of the following hardware forms: a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), or a PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is used to process data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing content required to be displayed on the display. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0098] The memory may include one or more computer non-volatile storage media, which may be non-transitory. The memory may also include high-speed random access memory, and non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory is used to store at least the following computer program, wherein, after the computer program is loaded and executed by the processor, it can implement the relevant steps in the data processing method performed by the terminal side disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory may also include an operating system and data, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system may include Windows, Unix, Linux, etc. The data may include but is not limited to update information of the application.

[0099] In some embodiments, the terminal may further include a display screen, an input and output interface, a communication interface, a sensor, a power supply, and a communication bus.

[0100] Those skilled in the art will understand that Figure 6 The structure shown in the figure does not constitute a limitation to the terminal, and may include more or fewer components than shown in the figure.

[0101] A non-volatile storage medium provided in an embodiment of the present application is introduced below. The non-volatile storage medium described below can be referenced with other embodiments described herein.

[0102] A non-volatile storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the data processing method disclosed in the aforementioned embodiment. The non-volatile storage medium is a computer-readable non-volatile storage medium that, as a carrier for resource storage, may be a read-only memory, random access memory, a magnetic disk, or an optical disk. The resources stored thereon include an operating system, a computer program, and data, and the storage method may be either temporary or permanent.

[0103] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: selecting the first link or the second link.

[0104] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: storing processor identification information corresponding to the target board.

[0105] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: storing the marking information of the slots included in each board.

[0106] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: after the second link in the target board is connected, the basic input and output system is controlled to read the processor identification information from the first memory, and the marking information of the slot included in the target board is read from the second memory.

[0107] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: determining the silkscreen information of the slots included in the target board according to the processor identification information and the marking information.

[0108] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: outputting a first signal for connecting the first link; or outputting a second signal for connecting the second link.

[0109] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: connecting the first link and disconnecting the second link according to the first signal; or connecting the second link and disconnecting the first link according to the second signal.

[0110] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: if the electronic device is powered on, a first signal is output.

[0111] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: when the second link in the target board is connected, the basic input and output system is controlled to write the second signal in the annunciator so that the annunciator outputs the second signal.

[0112] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: when the first link in the target board is connected, the basic input and output system is controlled to write the first signal in the annunciator so that the annunciator outputs the first signal.

[0113] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: outputting a high-bit signal as the first signal; and outputting a low-bit signal as the second signal.

[0114] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: when the first link in the target board is connected, the basic input and output system is controlled to write the processor identification information corresponding to the target board in the first memory.

[0115] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: when the first link in the target board is connected, the basic input and output system is controlled to write the number and port number of the processor connected to the target board into the first memory as processor identification information.

[0116] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: storing the board information of the target board.

[0117] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: constructing a physical location table based on the marking information of the slots included in each board, and storing the physical location table.

[0118] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: when the second link in the target board is connected, the basic input and output system is controlled to read the processor identification information from the first memory, and read the marking information of the slot included in the target board from the second memory; and the silk screen information of the slot included in the target board is determined based on the processor identification information and the marking information.

[0119] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: recording silk screen information, generating a target log based on the recorded content, and displaying the target log.

[0120] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: splicing the processor identification information and the marking information into silk-screen information.

[0121] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: when the electronic device is powered on, the processor identification information corresponding to each board is recorded and a logical location table is generated.

[0122] A computer program product provided in an embodiment of the present application is introduced below. The computer program product described below can be referenced with other embodiments described herein.

[0123] A computer program product comprises a computer program / instruction, which implements the steps of the aforementioned data processing method when executed by a processor.

[0124] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium is used to store a computer program, and when the computer program is executed by a processor, the steps in any of the above embodiments are implemented.

[0125] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: selecting the first link or the second link.

[0126] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: storing processor identification information corresponding to the target board.

[0127] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: storing the marking information of the slots included in each board.

[0128] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: after the second link in the target board is connected, the basic input and output system is controlled to read the processor identification information from the first memory, and the marking information of the slot included in the target board is read from the second memory.

[0129] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: determining the silkscreen information of the slots included in the target board according to the processor identification information and the marking information.

[0130] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: outputting a first signal for connecting the first link; or outputting a second signal for connecting the second link.

[0131] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: connecting the first link and disconnecting the second link according to the first signal; or connecting the second link and disconnecting the first link according to the second signal.

[0132] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: if the electronic device is powered on, a first signal is output.

[0133] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: when the second link in the target board is connected, the basic input and output system is controlled to write the second signal in the annunciator so that the annunciator outputs the second signal.

[0134] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: when the first link in the target board is connected, the basic input and output system is controlled to write the first signal in the annunciator so that the annunciator outputs the first signal.

[0135] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: outputting a high-bit signal as the first signal; and outputting a low-bit signal as the second signal.

[0136] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: when the first link in the target board is connected, the basic input and output system is controlled to write the processor identification information corresponding to the target board in the first memory.

[0137] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: when the first link in the target board is connected, the basic input and output system is controlled to write the number and port number of the processor connected to the target board into the first memory as processor identification information.

[0138] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: storing the board information of the target board.

[0139] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: constructing a physical location table based on the marking information of the slots included in each board, and storing the physical location table.

[0140] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: when the second link in the target board is connected, the basic input and output system is controlled to read the processor identification information from the first memory, and read the marking information of the slot included in the target board from the second memory; and the silk screen information of the slot included in the target board is determined based on the processor identification information and the marking information.

[0141] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: recording silk screen information, generating a target log based on the recorded content, and displaying the target log.

[0142] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: splicing the processor identification information and the marking information into silk-screen information.

[0143] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: when the electronic device is powered on, the processor identification information corresponding to each board is recorded and a logical location table is generated.

[0144] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0145] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of non-volatile storage medium known in the art.

[0146] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. An electronic device, characterized in that: include: at least one processor and at least one board; Wherein, any target board in the at least one board includes: a first connector, a second connector, a gate, a first memory, and a second memory; the first connector is connected to the gate via a first link; the second connector is connected to the gate and the second memory via a second link; the gate is also connected to the first memory; The gate is used to: gate the first link or the second link; The first memory is used to: store processor identification information corresponding to the target board; The second memory is used to: store the marking information of the slots included in each board; Correspondingly, the first connector and the second connector in each board are connected to any processor.

2. The electronic device according to claim 1, wherein The gate device includes: a selector and a signal device connected to the selector; The signaler is used to: output a first signal for connecting the first link; or output a second signal for connecting the second link; The selector is configured to: connect the first link and disconnect the second link according to the first signal; or connect the second link and disconnect the first link according to the second signal.

3. The electronic device according to claim 2, wherein: The annunciator is configured to output the first signal when the electronic device is powered on.

4. The electronic device according to claim 2, wherein: Any processor is configured to: when the second link in the target board is connected, control the basic input and output system to write the second signal into the annunciator, so that the annunciator outputs the second signal.

5. The electronic device according to claim 2, wherein: Any processor is configured to: when the first link in the target board is connected, control a basic input / output system to write the first signal into the annunciator, so that the annunciator outputs the first signal.

6. The electronic device according to claim 2, wherein: The signal device is used to: output a high-bit signal as the first signal; and output a low-bit signal as the second signal.

7. The electronic device according to claim 1, wherein: Any processor is connected to multiple mainboard-side second connectors through an expander, and each mainboard-side second connector is connected to a second connector in a different board. Any processor is connected to a plurality of mainboard-side first connectors, and each mainboard-side first connector is respectively connected to a first connector in a different board.

8. The electronic device according to claim 1, wherein: The processor connected to the target board is used for controlling the basic input and output system to write the processor identification information corresponding to the target board into the first memory when the first link in the target board is connected.

9. The electronic device according to claim 8, wherein: The processor connected to the target board is used to: when the first link in the target board is connected, control the basic input and output system to write the number and port number of the processor connected to the target board into the first memory as the processor identification information.

10. The electronic device according to claim 1, wherein The second memory is further used to store the board information of the target board.

11. The electronic device according to claim 1, wherein The second memory is used to construct a physical location table based on the marking information of the slots included in each board, and store the physical location table.

12. The electronic device according to claim 1, wherein Any processor is used to: when the second link in the target board is connected, control the basic input and output system to read the processor identification information from the first memory and read the marking information of the slot included in the target board from the second memory; determine the silk screen information of the slot included in the target board according to the processor identification information and the marking information of the slot included in the target board.

13. The electronic device according to claim 12, wherein: Any processor is used to: record the silk screen information, generate a target log based on the recorded content, and display the target log.

14. The electronic device according to claim 12, wherein: Any processor is used to: splice the processor identification information and the marking information of the slot included in the target board into the silk screen information.

15. The electronic device according to any one of claims 1 to 14, characterized in that: Any processor is used to: when the electronic device is powered on, record the identification information of the processors corresponding to each board and generate a logic position table.

16. The electronic device according to any one of claims 1 to 14, characterized in that: The first connector in any board is connected to a slot included in the board, and the slot is used to connect to a network card, a disk array or an acceleration card.

17. A data processing method, characterized in that: Applied to an electronic device, the electronic device comprising: at least one processor and at least one board; wherein any target board in the at least one board comprises: a first connector, a second connector, a gate, a first memory, and a second memory; the first connector is connected to the gate via a first link; the second connector is connected to the gate and the second memory via a second link; the gate is also connected to the first memory; The gate is used to: gate the first link or the second link; The first memory is used to: store processor identification information corresponding to the target board; The second memory is used to: store the marking information of the slots included in each board; The first connector and the second connector in each board are connected to any processor; Accordingly, the data processing method includes: After the second link in the target board is connected, any processor controls the basic input and output system to read the processor identification information from the first memory and read the marking information of the slot included in the target board from the second memory; and determines the silkscreen information of the slot included in the target board according to the processor identification information and the marking information of the slot included in the target board.

18. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to execute the computer program to implement the method according to claim 17.

19. A non-volatile storage medium, characterized in that: Used to store a computer program, wherein when the computer program is executed by a processor, the method according to claim 17 is implemented.

20. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the method of claim 17 is implemented.

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