Time sequence control circuit, data driving circuit, display panel and data output method

Abstract

The invention provides a time sequence control circuit, a data driving circuit, a display panel and a data output method. Wherein the time sequence control circuit is used for receiving an image signal and correspondingly outputting a data signal and a data latch signal, and the time sequence control circuit at least comprises a detection unit and a signal generation unit. The detection unit determines a corresponding refresh rate according to the data signal and outputs a corresponding detection signal. The signal generation unit outputs a data latch signal according to the detection signal, and adjusts the duty ratio of the data latch signal or the switching speed of the two potentials when the refresh rate is increased. The data driving circuit outputs a gray scale voltage corresponding to the data signal to a pixel unit in the display panel according to the data latch signal.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a timing control circuit, a data driving circuit, a display panel, and a data output method. Background Art

[0002] Display panels convert electronic signals into visible images for display purposes and are widely used in a variety of display devices, including televisions, monitors, mobile phones, tablets, and in-car displays. As user demands for enhanced image quality increase, the image refresh rate has become a key factor in optimizing display quality.

[0003] The image refresh rate changes during the display panel's image display process. This means that users may require different refresh rates to adjust their usage scenarios, such as switching from 2K to 4K, or from 4K to 8K. During this refresh rate switching process, display anomalies often occur, resulting in poor display quality. Summary of the Invention

[0004] Based on the aforementioned technical problems, the present application provides a timing control circuit, a data driving circuit, a display panel, and a data output method applied to the display panel for ensuring better image display.

[0005] In a first aspect, a timing control circuit is provided for receiving an image signal and correspondingly outputting a data signal and a data latch signal, comprising: a storage unit, configured to receive the data signal and store the data signal corresponding to the image signal; a detection unit, which determines a corresponding refresh rate according to the data signal and outputs a corresponding detection signal; a signal generating unit connected to the detection unit and outputting the data latch signal according to the detection signal, wherein the first data latch signal is output when the refresh rate is a first refresh rate, and the second data latch signal is output within an adjustment period starting from when the first refresh rate is increased to the second refresh rate, the duty cycle of the second data latch signal is smaller than the duty cycle of the first data latch signal, or the speed at which two potentials in the second data latch signal are switched is faster than the speed at which two potentials in the first data latch signal are switched; and A data sending unit is connected to the storage unit and is used to output the data signal.

[0006] In one embodiment of the present application, the first data latch signal has a first duty cycle or a first speed when switching between two potentials; the second data latch signal has a second duty cycle or a second speed when switching between two potentials, wherein the second duty cycle is smaller than the first duty cycle, or the second speed is greater than the first speed; After the adjustment time period, the detection unit outputs the first data latch signal.

[0007] In one embodiment of the present application, when the data signal corresponds to a first refresh rate, the duty cycle of the detection signal is a first duty cycle; when the refresh rate corresponding to the data signal increases to a second refresh rate, the duty cycle of the detection signal is the second duty cycle within the adjustment period; after the adjustment period, the duty cycle of the detection signal returns to the first duty cycle, and the waveform of the data latch signal is the same as the waveform of the detection signal.

[0008] In one embodiment of the present application, the data latch signal is a periodically changing pulse signal, and the signal generating unit includes an output control circuit, a first potential output circuit, and a second potential output circuit. The output control circuit receives a latch enable signal and determines whether to output the data latch signal based on the latch enable signal. The first potential output circuit is connected to the output control circuit and is used to provide a first potential to the output control circuit under the control of the detection signal. The second potential output circuit is connected to the output control circuit and is used to provide a second potential to the output control circuit under the control of the detection signal. The first potential and the second potential switch with each other to form the first data latch signal or the second data latch signal within a cycle.

[0009] In one embodiment of the present application, the signal generating unit further includes a corner cancellation circuit, which is connected between the first potential output circuit and the output control circuit, and is used to perform corner cancellation processing when the first potential changes to the second potential within the adjustment time length, so as to improve the speed of switching between the two potentials in the second data latch signal.

[0010] In one embodiment of the present application, the first potential is a high potential, and the second potential is a low potential.

[0011] In a second aspect, an embodiment of the present application provides a data driving circuit for receiving the data signal and the data latch signal from the aforementioned timing control circuit, wherein the data driving circuit includes a data latch unit, and the data latch unit includes a first data latch and a second data latch. The first data latch receives and latches the data signal according to the first data latch signal or the second data latch signal. The second data latch is connected to the first data latch and is configured to receive the data signal from the first data latch according to the edge of the first data latch signal or the second data latch signal during potential switching, and output the data signal at the edge of the adjacent potential switching.

[0012] In one embodiment of the present application, the data signal corresponding to each row of pixel units includes blank data, calibration data, polarity data, valid data, and stop data in sequence, and the pixel units are used to perform image display according to the data signals. In the first data latch signal, the first data latch receives the data signal at the rising edge of the first data latch signal. When the refresh rate increases, within the adjustment time, the first data latch outputs the valid data corresponding to the M-th row of pixel units to the second data latch at the rising edge of the second data latch signal. The first data latch receives the blank data in the data signal corresponding to the M+1-th row of pixel units at the falling edge of the second data latch signal. At the same time, the second data latch outputs the valid data in the data signal corresponding to the M-th row of pixel units at the falling edge of the second data latch signal, where M is a positive integer greater than or equal to 1.

[0013] In one embodiment of the present application, the data signal corresponding to each row of pixel units includes blank data, calibration data, polarity data, valid data, and stop data in sequence, and the pixel units are used to perform image display according to the data signals. In the first data latch signal, the first data latch receives the data signal at the rising edge of the first data latch signal. When the refresh rate increases, within the adjustment time, the first data latch outputs the valid data corresponding to the M-th row of pixel units to the second data latch at the rising edge of the second data latch signal. The first data latch receives the data "1" in the polarity data of the data signal corresponding to the M+1-th row of pixel units at the falling edge of the second data latch signal. At the same time, the second data latch outputs the valid data in the data signal corresponding to the M-th row of pixel units at the falling edge of the second data latch signal, where M is a positive integer greater than or equal to 1.

[0014] In a third aspect, an embodiment of the present application provides a display panel, which includes n scan lines extending along a first direction, m data lines extending along a second direction, and a plurality of pixel units arranged in an array, a scan driving circuit, the aforementioned timing control circuit, and the aforementioned data driving circuit. The data driving circuit and the scan driving circuit are connected to the pixel units through the data lines and the scan lines, respectively. The pixel units are used to receive scan signals from the scan lines, and receive data signals from the data lines under the control of the scan signals to perform image display. The timing control circuit is used to provide the first data latch signal and the second data latch signal to the data driving circuit. The data driving circuit outputs the grayscale voltage corresponding to the data signal to the pixel units based on the first data latch signal and the second data latch signal.

[0015] In a fourth aspect, a data output method is provided, which is applied to the aforementioned display panel, comprising: The timing control circuit identifies a refresh rate of an image to be displayed, outputs the first data latch signal corresponding to a display image of a first refresh rate, and the first data latch and the second data latch output the data signal according to the first data latch signal; During the adjustment period when the refresh rate corresponding to the data signal increases to the second refresh rate, the timing control circuit outputs the second data latch signal, and the first data latch and the second data latch output the data signal according to the second data latch signal; After the adjustment time, the timing control circuit outputs the first data latch signal, and the first data latch and the second data latch output the data signal according to the first data latch signal; The data signal is converted into a grayscale voltage and output to the pixel unit.

[0016] Compared with the prior art, in an embodiment of the present application, within the adjustment period after the data signal refresh rate is increased, the waveform of the data latch signal is adjusted so that the time for the first data latch to receive valid data and the time for the second data latch to output data are staggered, so that the loads on the first data latch and the second data latch are smaller, thereby reducing the impact of the increase in the ground voltage as a reference voltage due to the large load on the accuracy of the data signal, ensuring the accuracy of the first data latch receiving data, thereby improving the accuracy of the pixel unit receiving data and improving the image display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0018] Figure 1 A schematic structural diagram of a display device provided in one embodiment of the present application; Figure 2 for Figure 1 A schematic diagram of the planar layout structure of the display panel is shown; Figure 3 for Figure 2 A schematic diagram of the functional modules of the display device shown; Figure 4 For example Figure 2 Functional module diagram of the data driving circuit shown; Figure 5 for Figure 4The schematic diagram of the circuit structure of the data driving circuit shown; Figure 6 Schematic diagram of the waveform of the data latch signal; Figures 7 to 9 is a working state diagram of the first data latch and the second data latch; Figure 10 For example Figure 3 A schematic diagram of a voltage waveform of the data driving circuit corresponding to the ground voltage; Figure 11 for Figure 2 Schematic diagram of image display effect of some pixel units shown; Figure 12 In the first embodiment of this application, Figure 2 Functional module diagram of the timing control circuit shown; Figure 13 For example Figure 12 Schematic diagram of the specific circuit structure of the signal generating unit shown; Figure 14 like Figure 13 Schematic diagram of waveforms of various signals when the timing control circuit outputs a data latch signal; Figure 15 A schematic diagram of the working process of outputting data latch signals for the timing control circuit; Figure 16-17 This is a schematic diagram of the working state of the signal generating unit; Figure 18 A circuit block diagram of a signal generating unit in the second embodiment of the present application; Figure 19 like Figure 18 Schematic diagram of the second data latch signal output by the signal generating unit; Figure 20 For application Figures 12-19 The figure shows a flow chart of a method for outputting data from a display panel in a display device.

[0019] Description of Figure Numbers: Display device 100, display panel 10, supporting frame Fr, display area 10a, non-display area 10b, pixel unit P, data lines D1-Dn, scan lines G1-Gm, first direction X, second direction Y, timing control circuit 20, data drive circuit 30, scan drive circuit 40, power supply circuit 50, data drive control signal DDC, data signal Data, horizontal synchronization control signal Hsync, vertical synchronization signal Vsync, main clock signal CLK, source shift clock signal SSC, source start pulse signal SSP, data latch signal TP, first data latch signal TP1, second data latch signal TP2, power supply voltage -VCC, ground voltage -GND, first circuit board -X-Board, second circuit board -C-Board, low voltage differential signal -LV, receiving data clock signal -LVCLK, data receiving unit -30A, data receiving interface -DR, bidirectional shift register -BSR, shift clock -PCLK, parallel component data signal -RGB, enable signal -EIO, shift direction control signal -DIR, data buffer unit -30B, data register unit -31, data latch unit -32, sampling signal -SS, first data latch -LA1, second data latch -LA2, data amplifying and converting unit -30C, digital-to-analog conversion unit -33, output buffer unit -34, digital-to-analog converter -AD, output Buffer-BUF, data receiving time-Tre1, first period-ta1, second period-ta2, third period-ta3, fourth period-ta4, fifth period-ta5, data transmission time-Tre2, data output time-Tre3, adjustment time-Tx, detection unit-21, signal generating unit-22, output control circuit-220, first switch tube-M1, first control terminal-CC1, first conductive terminal-EC1, second conductive terminal-EC2, second switch tube-M2, second control terminal-CC2, third conductive terminal-EC3, fourth conductive terminal-EC4, output control terminal-CA, first power supply terminal-Pt1, second power supply terminal-Pt2, latch signal output terminal-TPout, A potential output circuit 221, a third switch tube M3, a third control terminal CC3, a fifth conductive terminal EC5, a sixth conductive terminal EC6, a fourth switch tube M4, a fourth control terminal CC4, a seventh conductive terminal EC7, an eighth conductive terminal EC8, a second potential output circuit 222, a fifth switch tube M5, a fifth control terminal CC5, a ninth conductive terminal EC9, a tenth conductive terminal EC10, a sixth switch tube M6, a sixth control terminal CC6, an eleventh conductive terminal EC11, a twelfth conductive terminal EC12, a storage unit 23, a data transmission unit 24, a video signal and / or an image signal VD, a detection signal Sdt, a latch enable signal TPen, an angle elimination circuit 223,Sampling latches - R10~R31, R component data - R

[20] , G component data - G

[10] , G component data - G

[20] , B component data - B

[10] , B component data - B

[20] , grayscale voltage - Dout. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0021] See also Figure 1 , Figure 1 This is a schematic diagram of the structure of a display device provided in one embodiment of the present application. The display device 100 includes a display panel 10 and a support frame Fr, to which the display panel 10 is fixed. The support frame Fr provides a secure and protective function for the display panel 10. In other embodiments of the present application, the display device 100 may not require a support frame Fr, such as a portable electronic device such as a mobile phone or tablet computer.

[0022] See Figure 2 , Figure 2 for Figure 1 FIG. 1 is a schematic diagram of the planar layout structure of the display panel 10. Figure 2 As shown, the display area 10 a of the display panel 10 includes a plurality of m×n pixel units P arranged in a matrix, n data lines D1 -Dn, and m scan lines G1 -Gm, where m and n are natural numbers greater than 1.

[0023] The m scan lines G1 -Gm extend along a first direction X and are insulated from each other and arranged in parallel along a second direction Y for outputting scan signals to the pixel units P.

[0024] The n data lines D1 -Dn extend along the second direction Y and are insulated from each other and arranged in parallel along the first direction X. The first direction X and the second direction Y are perpendicular to each other.

[0025] The non-display area 10 b of the display panel 10 may be provided with functional circuits and signal lines for driving the pixel units P to display images.

[0026] The display device 100 further includes a timing control circuit 20, a data driving circuit 30, a scan driving circuit 40, and a power supply circuit 50 for driving the pixel units P to display images. The scan driving circuit 40 can be disposed in the non-display area 10b of the display panel 10, while the timing control circuit 20 and the data driving circuit 30 can be disposed on a circuit board and electrically connected to the display area 10a via signal traces for signal transmission.

[0027] The timing control circuit 20 is electrically connected to the data driving circuit 30 and the scan driving circuit 40 and is used to control the operating timing of the data driving circuit 30 and the scan driving circuit 40. That is, it outputs corresponding timing control signals to the data driving circuit 30 and the scan driving circuit 40 to control when the scan driving circuit 40 outputs the corresponding scan signal and when the data driving circuit 30 outputs the corresponding data signal Data.

[0028] Specifically, in this embodiment, the timing control circuit 20 responds to externally input control signals, such as the horizontal synchronization control signal Hsync, the vertical synchronization signal Vsync, and the main clock signal CLK, and generates a data drive control signal DDC and a data signal Data based on the externally input video signal and / or image signal VD and outputs them to the data drive circuit 30.

[0029] It can be understood that the data driving control signal DDC includes a source shift clock signal SSC, a source start pulse signal SSP, a data latch signal TP, and the like.

[0030] The data driving circuit 30 is electrically connected to the n data lines D1-Dn and is configured to transmit a data signal Data to be displayed in the form of a grayscale voltage to the plurality of pixel units P via the n data lines D1-Dn. Specifically, the data driving circuit 30 converts the data signal Data into a corresponding grayscale voltage under the control of the data latch signal TP and transmits the converted grayscale voltage to the pixel units P. In this embodiment, the data driving circuit 30 transmits the grayscale voltage to the plurality of pixel units P in the display area 10a via the n data lines D1-Dn.

[0031] In this embodiment, the data latch signal TP is a pulse signal that periodically has a preset duty cycle, for example, a pulse signal that includes a plurality of consecutive cycles, and the pulse signal in each cycle has a preset duty cycle.

[0032] The data driver circuit 30 receives the data signal Data in response to the rising edge of the data latch signal TP. Under the control of the source shift clock signal SSC and the source start pulse signal SSP, the data driver circuit 30 samples and identifies the received data signal Data to obtain the multiple data signals Data corresponding to the multiple pixel units P in the same row and the polarity of the data signal Data. In response to the falling edge of the data latch signal TP, the data driver circuit 30 outputs the latched data signal Data for conversion into a grayscale voltage. It will be understood that in this embodiment, the data signal Data is a digital signal, and the grayscale voltage is an analog signal.

[0033] The scan driving circuit 40 is electrically connected to the m scan lines G1-Gm and is configured to output scan signals to the pixel units P via the m scan lines G1-Gm to control when the pixel units P receive the data signals Data. The scan driving circuit 40 sequentially outputs scan signals from the m scan lines G1-Gm according to their positional arrangement and in accordance with a scan cycle.

[0034] The power supply circuit 50 is configured to provide a power supply voltage to the data driving circuit 30 so that the data driving circuit can convert the data signal Data into a corresponding grayscale voltage. The power supply circuit 50 can also generate a plurality of driving voltages to be provided to the scan driving circuit 40 and each pixel unit P in the display area 10a of the display panel 10. In this embodiment, the power supply circuit 50 is configured to provide a first power supply voltage and a second power supply voltage. For example, the first power supply voltage can be a high voltage power supply voltage VCC, and the second power supply voltage can be a low voltage ground voltage GND. Of course, the power supply voltage also includes other power supply voltages.

[0035] See also Figure 3 , Figure 3 for Figure 2 Schematic diagram of the functional modules of the display device 100. Figure 3 As shown, the display device 100 further includes a first circuit board X-Board and a second circuit board C-Board. The first circuit board X-Board is connected to the display panel 10 and the second circuit board C-Board. The first circuit board X-Board and the display panel 10 can be connected via flexible conductive wires or flexible conductive films, thereby enabling the first circuit board X-Board to rotate or pivot relative to the display panel 10 and be fixed to the display panel 10. Correspondingly, the first circuit board X-Board and the second circuit board C-Board are also connected via flexible wires, thereby enabling the second circuit board C-Board to rotate relative to the first circuit board X-Board and be fixed to the display panel 10.

[0036] In this embodiment, the first circuit board X-Board and the second circuit board C-Board can be provided separately, or the first circuit board X-Board and the second circuit board C-Board can be integrated into the same circuit board.

[0037] The power supply circuit 50 and the timing control circuit 20 are disposed on the second circuit board C-Board, and are mainly used to receive display signals for image display provided externally, and output data signals, control signals and power supply voltage accordingly.

[0038] The first circuit board X-Board, serving as a driver circuit board, primarily receives data and control signals from the second circuit board C-Board and transmits them to multiple data driver circuits 30. In this embodiment, the first circuit board X-Board includes a memory (not shown) and is connected to the display panel 10 via a chip-on-flex (COF) film, which houses a data driver chip. The data driver chip is connected to the pixel units P via data lines to transmit data signals to the pixel units P for image display.

[0039] In this embodiment, the first circuit board X-Board further includes power traces (not labeled) for connecting the data driving circuit 30 and the power circuit 50 to output a power voltage VCC and a ground voltage GND.

[0040] Please also refer to Figure 4 and Figure 5 , Figure 4 For example Figure 2 The functional module diagram of the data driving circuit 30 is shown in FIG. Figure 5 for Figure 4 FIG. 1 is a schematic diagram of a partial circuit structure of the data driving circuit 30 .

[0041] like Figure 4-Figure 5 As shown, the data driver circuit 30 receives the data driver control signal DDC and the data signal Data from the timing control circuit 20. It will be understood that the multiple signals included in the data driver control signal DDC are combined and encoded with the data signal Data by the timing control circuit 20 and then transmitted to the data driver circuit 30. The data driver circuit 30 receives the combined and encoded signals and decodes them to obtain the corresponding individual signals. In this embodiment, the data signal Data is transmitted to the data driver circuit 30 as a low voltage differential signal (LV).

[0042] like Figure 4 As shown, the data driving circuit 30 includes a data receiving section 30A, a data buffer section 30B, and a data amplifying and converting section 30C.

[0043] Specifically, if Figure 4-Figure 5 As shown, the data receiving unit (Data Receiver) 30A is used to receive the data signal Data in the form of a low voltage differential signal LV from the timing control circuit 20. In this embodiment, the data receiving unit 30A includes a data receiving interface DR and a bidirectional shift register BSR.

[0044] The data receiving interface DR is an interface portion connected to the timing control circuit 20, and receives the data clock signal LVCLK and the low-voltage differential signal LV in the form of a serial data signal corresponding to the data signal Data. The data receiving interface DR generates a shift clock PCLK and a parallel component data signal RGB based on the received data clock signal and the low-voltage differential signal LV in the form of a serial data signal. The parallel component data signal RGB can be R component data R

[20] , G component data G

[10] , G

[20] , B component data B

[10] , B

[20] , etc., wherein the parallel component data signal RGB represents 8-bit data corresponding to the brightness of each color of a pixel unit P.

[0045] The bidirectional shift register BSR is connected to the data receiving interface DR and receives the shift clock PCLK and the parallel component data signal RGB. Under the control of the shift clock PCLK, the enable signal EIO and the shift direction control signal DIR, the bidirectional shift register BSR transmits the parallel component data signal RGB to the data buffer section 30B.

[0046] The data buffer 30B includes a data register unit 31 and a data latch unit 32. The data register unit 31 samples the data signal Data and outputs a sampling signal SS. The data latch unit 32 samples, identifies, and latches the data signal Data based on the sampling signal SS and a data latch signal TP. In this embodiment, the data latch signal TP can be referred to as an internal strobe signal.

[0047] The data amplifying and converting section 30C includes a digital-to-analog converting unit 33 and an output buffer unit 34. The digital-to-analog converting unit 33 is used to convert the data signal Data into an analog data voltage, and the output buffer unit 34 is used to amplify and buffer the data voltage.

[0048] In this embodiment, the data register unit 31 is used to receive the sampling clock signal SCLK and generate a sampling signal accordingly. The data register unit 31 is implemented by a shift register SR (Shift Register).

[0049] Specifically, the data register unit 31 receives the source shift clock signal SSC and the source start pulse signal SSP from the timing control circuit 20. During each cycle of the source shift clock signal SSC, the data register unit 31 sequentially generates n sampling signals while controlling the shifting of the source start pulse signal SSP. To generate n sampling signals SS, the data register unit 31 includes n bidirectional shift registers.

[0050] The data latch unit 32 includes a first data latch LA1 and a second data latch LA2. Both the first data latch LA1 and the second data latch LA2 can be latches. In this embodiment, the first data latch LA1 and the second data latch LA2 receive a data latch signal TP and parallel component data signals RGB corresponding to the data signal Data. They cooperate with each other to sample, identify, and latch the parallel component data signals RGB under the control of the data latch signal TP and the sampling signal SS.

[0051] Among them, the first data latch LA1 receives the parallel component data signal RGB corresponding to the data signal Data according to the data latch signal TP, and samples and identifies the parallel component data signal RGB corresponding to the data signal Data according to the sampling signal to obtain multiple data signals corresponding to multiple pixel units P located in the same row and the polarities of these data voltages, and transmits the data signal Data to the second data latch LA2 according to the data latch signal TP.

[0052] The second data latch LA2 receives and latches the data signal Data from the first data latch LA1 according to the data latch signal TP, and transmits the data to the data amplifying and converting unit 30C under the control of the data latch signal TP after being latched for a preset time.

[0053] In this embodiment, the first data latch LA1 acts as a sampling latch, sequentially storing data in response to sampling signals sequentially supplied from the data register unit 31. Here, the first data latch LA1 is provided with k sampling latches for storing k digital data. Furthermore, each sampling latch has a size corresponding to the number of bits in the data. For example, when the data is structured to have k bits, the number of sampling latches is set to have a size of k bits. In this embodiment, k is 32, and the k sampling latches can represent R10 to R31.

[0054] The second data latch LA2 is equivalent to a holding latch. The first data latch LA1 receives and stores data from the first data latch LA1 under the control of the data latch signal TP, and the second data latch LA2 provides the data stored therein to the data amplification and conversion unit 30C under the control of the data latch signal TP. Here, the second data latch LA2 is provided with k holding latches for storing k data. In addition, each holding latch has a size corresponding to the number of bits of data. For example, each holding latch is set to have a size of k bits for storing k bits of data. In this embodiment, k is 32. Of course, in other embodiments of the present application, k can be other integers and is not limited to this example.

[0055] The data amplifying and converting section 30C includes a digital-to-analog converter AD and an output buffer BUF.

[0056] The digital-to-analog converter AD can convert the parallel component data signal RGB corresponding to the data signal Data into an analog voltage based on the gamma reference voltage, and the output buffer BUF can amplify the analog data voltage to obtain a grayscale voltage loaded to multiple pixel units P in a corresponding row.

[0057] In this embodiment, the digital-to-analog converter AD includes a plurality of digital-to-analog converters, and the output buffer BUF includes a voltage follower formed by a plurality of operational amplifiers (OPA).

[0058] See also Figure 6 , which is a waveform diagram of the data latch signal TP.

[0059] like Figure 6 The data latch signal TP is a pulse signal having a plurality of temporally continuous square waves, wherein the data latch signal TP has a first duty cycle, that is, a high potential from a rising edge to a falling edge in each cycle has a first duration.

[0060] Now combined Figure 6 、 Figures 7 to 9 The working process of the first data latch LA1 and the second data latch LA2 is specifically described. In particular, the specific process of the first data latch LA1 and the second data latch LA2 receiving and outputting the Mth to M+1th data signals Data is described by taking the Nth to N+2th cycles of any cycle of the data latch signal TP as an example. Figures 7 to 9 : is a working state diagram of the first data latch LA1 and the second data latch LA2, where N and M are integers greater than or equal to 1.

[0061] It should be noted that the M-th row data signal Data and the M+1-th row data signal Data refer to the data signal corresponding to the M-th row pixel unit P and the data signal Data corresponding to the M+1-th row pixel unit P, respectively.

[0062] In addition, it should be noted that the data signal Data corresponding to each row of pixel units P is referred to as a row data signal Data in this embodiment. For example, the M-th row data signal Data is the data signal Data corresponding to the M-th row of pixel units P. Each row data signal Data is packaged when transmitted to the data latch unit 32. Each packaged row data signal Data sequentially includes blank data, calibration data, polarity data, valid data, and stop data. The blank data, calibration data, polarity data, valid data, and stop data are all composed of binary data "0" and data "1".

[0063] like Figure 6 and Figure 7 As shown, at the data receiving time Tre1 corresponding to the rising edge of the Nth cycle of the data latch signal TP, the first data latch LA1 starts to prepare to receive the data signal Data of the Mth row.

[0064] In this embodiment, the first data latch LA1 includes 5 consecutive time periods from the first time period ta1 to the fifth time period ta5 during operation, wherein the first time period ta1 corresponds to the rising edge of the Nth cycle of the data latch signal TP, or in other words, the data receiving moment Tre1 corresponding to the rising edge of the Nth cycle of the data latch signal TP is located at a time point in the middle of the first time period ta1.

[0065] In the first period ta1, the first data latch LA1 begins to receive blank data in the M-th row data signal Data, or in other words, the first data latch LA1 receives blank data in the M-th row data signal Data during the rising edge of the N-th cycle of the data latch signal TP.

[0066] In the second period ta2 , the data latch signal TP switches to a high level through a rising edge change, the first data latch LA1 receives the calibration data in the M-th row data signal Data, and calibrates the calibration data to determine the accuracy of the data signal Data.

[0067] During the third period ta3, the data latch signal TP switches to a low level after a falling edge transition. The first data latch LA1 receives the polarity data in the M-th row data signal Data and identifies the polarity data accordingly to determine whether the data signal Data is positive or negative, facilitating transmission of the data signal Data to different channels. The falling edge of the data latch signal TP occurs in the middle of the third period ta3.

[0068] In the fourth period ta4 , the data latch signal TP is at a low level, and the first data latch LA1 receives the valid data in the M-th row data signal Data and latches the valid data.

[0069] In the fifth period ta5 , the data latch signal TP maintains a low level, the first data latch LA1 receives the stop data in the M-th row data signal Data, and confirms that the data reception of the M-th row data signal Data is completed according to the stop data.

[0070] like Figure 6 and Figure 8 As shown, at the data transfer moment Tre2 corresponding to the rising edge of the N+1th cycle of the data latch signal TP, in the first time period ta1, the first data latch LA1 transfers the valid data in the M-th row data signal Data to the second data latch LA2. In other words, corresponding to the second data latch LA2, at the rising edge of the N+1th cycle of the data latch signal TP, the valid data of the M-th row data signal Data is received and latched. At the same time, the second data latch LA2 enters a high-impedance state and stops data output from the data transfer moment Tre2 corresponding to the rising edge of the N+1th cycle of the data latch signal TP, so as to accurately latch the valid data in the M-th row data signal Data.

[0071] It can be understood that after the first data latch LA1 transfers the valid data in the M-th row data signal Data to the second data latch LA2 at the rising edge of the N+1th cycle, the first data latch LA1 is ready to receive the M+1th row data signal Data. At this time, the data transfer moment Tre2 corresponding to the rising edge of the data latch signal TP in the N+1th cycle is also the data reception moment Tre1 of the M+1th row data signal Data. Corresponding to the N+1th cycle, in the second time period ta2, the data latch signal TP changes to a high level after a rising edge. The first data latch LA1 receives the calibration data in the M+1th row data signal Data and calibrates the calibration data accordingly to determine the accuracy of the data signal Data.

[0072] During the third period ta3, the data latch signal TP changes to a low level after a falling edge. That is, at the data output time Tre3 corresponding to the falling edge of the data latch signal TP, the first data latch LA1 receives the polarity data in the data signal Data of the M+1th row and identifies the polarity data accordingly to determine whether the data signal Data is positive or negative, facilitating the transmission of the data signal Data to different channels. The falling edge of the data latch signal TP occurs in the middle of the third period ta3.

[0073] At the same time, if Figure 6 and Figure 9 As shown, at the data output time Tre3 corresponding to the falling edge of the data latch signal TP, the second data latch LA2 releases the high-impedance state and outputs the valid data corresponding to the latched data signal Data of the Mth row to the digital-to-analog converter AD and the output buffer BUF of the data amplification and conversion section 30C, so as to convert the data signal Data into grayscale voltages and output them to the pixel units P of the Mth row. It can be understood that after the second data latch LA2 outputs the latched data signal Data of the Mth row to the data amplification and conversion section 30C, it receives and outputs the valid data in the data signal Data of the M+1th row during the N+2th cycle of the data latch signal TP.

[0074] In the fourth period ta4 , the data latch signal TP is at a low level, and the first data latch LA1 receives the valid data in the M+1th row data signal Data and latches the valid data.

[0075] In the fifth period ta5 , the data latch signal TP maintains a low level, the first data latch LA1 receives the stop data in the M+1th row data signal Data, and confirms that the data reception of the M+1th row data signal Data is completed according to the stop data.

[0076] In this embodiment, the first data latch LA1 cooperates with the second data latch LA2 to receive the M-th row data signal Data in two adjacent cycles of the data latch signal TP, that is, in the N-th cycle and the N+1-th cycle, and identifies, processes, and latches the M-th row data signal Data and outputs it to the data amplification and conversion unit 30C to perform grayscale voltage conversion output.

[0077] See also Figure 10 , which is as follows Figure 3 FIG. 1 is a schematic diagram of a voltage waveform of the data driving circuit 30 corresponding to the ground voltage.

[0078] Please also refer to Figure 9 、 Figure 10When the second data latch LA2 outputs the valid data of the M-th row data signal Data to the data amplifying and converting unit 30C at the data output time Tre3 corresponding to the falling edge of the N+1-th cycle, the first data latch LA1 is simultaneously receiving the polarity data in the M+1-th row data signal Data. That is, the first data latch LA1 and the second data latch LA2 are simultaneously performing the data receiving and data output operations. If the refresh rate of the display device 100 suddenly increases at this time, for example, from the first refresh rate corresponding to 4K to the second refresh rate corresponding to 8K, the loads of the first data latch LA1 and the second data latch LA2 will suddenly increase or even be overloaded, which will synchronously cause the data amplifying and converting unit 30C to be overloaded and the output grayscale voltage Dout to have an error. At the same time, the current corresponding to the power supply line connected to the transmission ground voltage GND in the data driving circuit 30 is bound to flow suddenly, causing the voltage of the power supply line connected to the transmission ground voltage GND to increase, resulting in a ground bounce. The existence of GND bounce causes the voltage of the power supply line connected to the transmission ground voltage GND to increase. Since the ground voltage GND is used as the voltage of the signal reference ground, if the voltage of the signal reference ground is unstable, it will cause the data signal potential to shift or distort, or the data signal to be interfered with during the transmission process, resulting in abnormal valid data of the data signal Data received by the data amplification and conversion unit 30C, and then causing the grayscale voltage transmitted by the data driving circuit 30 to the pixel unit P to fail to reach the target voltage, resulting in the following problems: Figure 11 The image shown is distorted or has abnormal colors, and the charging and discharging speed of the pixel unit P slows down, resulting in smearing or blurring. Figure 11 for Figure 2 Schematic diagram of image display effect of some pixel units P shown.

[0079] See also Figure 12 As shown, it is the first embodiment of the present application. Figure 2 The functional module diagram of the timing control circuit 20 is shown.

[0080] The timing control circuit 20 includes a detection unit 21 , a signal generation unit 22 , a storage unit 23 and a data sending unit 24 .

[0081] The storage unit 23 receives a video signal and / or an image signal VD corresponding to an image to be displayed provided from the outside through a data receiving interface.

[0082] The detection unit 21 identifies the corresponding refresh rate based on the video signal and / or image signal VD received by the storage unit 23 to confirm the first refresh rate of the image displayed by the current frame of the pixel unit P and the second refresh rate of the image of the next frame to be displayed, outputs the corresponding detection signal Sdt, and confirms the change of the refresh rate.

[0083] For example, if the first refresh rate of the current frame displayed is 4K and the second refresh rate of the next frame to be displayed is 8K, it means that the refresh rate of the display panel 10 increases during the subsequent image display process. It can be understood that when the refresh rate increases, the amount of data received by the timing control circuit 20 will inevitably increase accordingly.

[0084] According to the change in the refresh rate of the data signal Data, the detection unit 21 outputs the corresponding detection signal Sdt to the signal generating unit 22. The duty cycle of the detection signal Sdt will change within the preset time period when the refresh rate begins to change. In this embodiment, when the refresh rate increases, the duty cycle of the detection signal decreases within the preset time period and restores the original duty cycle after the preset time period. For example, the first refresh rate of the current frame display image is 4K, the detection signal Sdt has a first duty cycle, and the second refresh rate of the next frame image to be displayed is 8K. Within the preset adjustment time period Tx, the duty cycle of the detection signal is adjusted to the second duty cycle, and the second duty cycle is smaller than the first duty cycle. After the adjustment time period Tx, the duty cycle of the detection signal Sdt returns to the first duty cycle.

[0085] The signal generating unit 22 outputs the data latch signal TP based on the detection signal Sdt and the latch enable signal TPen. In this embodiment, the signal generating unit 22 adjusts the duty cycle and waveform of the data latch signal TP based on the detection signal Sdt. The latch enable signal TPen can be a signal triggered by the timing control circuit 20 upon receiving the video signal and / or image signal VD.

[0086] It is understandable that the signal generating unit 22 can also generate other signals, such as a source shift clock signal SSC, a source start pulse signal SSP, etc., to form the data driving control signal DDC together with the data latch signal TP.

[0087] The data sending unit 24 is configured to output a data signal Data to the data driving circuit 30 in response to the data latch signal TP.

[0088] See also Figure 13 , which is as follows Figure 12 Schematic diagram of the specific circuit structure of the signal generating unit 22 is shown.

[0089] The signal generating unit 22 includes an output control circuit 220 , a first potential output circuit 221 , and a second potential output circuit 222 .

[0090] The output control circuit 220 receives the latch enable signal TPen and determines whether to output the data latch signal TP according to the latch enable signal TPen.

[0091] The first potential output circuit 221 is connected to the output control circuit 220 and is configured to provide a first potential to the output control circuit 220 under the control of the detection signal Sdt.

[0092] The second potential output circuit 222 is connected to the output control circuit 220 and is configured to provide a second potential to the output control circuit 220 under the control of the detection signal Sdt.

[0093] In this embodiment, the first potential is a high potential, and the second potential is a low potential.

[0094] More specifically, the output control circuit 220 includes a first switch M1 and a second switch M2. The first switch M1 is connected to the output control terminal CA and the first power terminal Pt1, and the second switch M2 is connected to the first switch M1, the latch signal output terminal TPout, the first potential output circuit 221, and the second potential output circuit 222.

[0095] The output control terminal CA is connected to the detection unit 21 for receiving the latch enable signal TPen. The first switch tube M1 and the second switch tube M2 cooperate with each other to output the voltage signals provided by the first potential output circuit 221 and the second potential output circuit 222 under the control of the latch enable signal TPen.

[0096] More specifically, the first switch tube M1 includes a first control terminal CC1, a first conductive terminal EC1 and a second conductive terminal EC2. The first control terminal CC1 is connected to the output control terminal CA for receiving the latch enable signal TPen. The first conductive terminal EC1 is connected to the first power terminal Pt1. The second conductive terminal EC2 is connected to the second switch tube M2.

[0097] The first switch transistor M1 is configured to selectively provide a first power supply voltage provided by the first power supply terminal Pt1 to the second switch transistor M2 under the control of a latch enable signal TPen. The first power supply voltage is used to control the second switch transistor M2 to transmit the voltage signals provided by the first potential output circuit 221 and the second potential output circuit 222 to the latch signal output terminal TPout to form a data latch signal TP. For example, when the first switch transistor M1 is turned on under the control of the latch enable signal TPen, the first power supply voltage is provided to the second switch transistor M2. When the first switch transistor M1 is turned off under the control of the latch enable signal TPen, the first power supply voltage ceases to be provided to the second switch transistor M2.

[0098] The second switch tube M2 includes a second control terminal CC2, a third conductive terminal EC3 and a fourth conductive terminal EC4. The second control terminal CC2 receives the second conductive terminal EC2 connected to the first switch tube M1, the third conductive terminal EC3 is connected to the latch signal output terminal TPout, and the fourth conductive terminal EC4 is connected to the first potential output circuit 221 and the second potential output circuit 222.

[0099] When the second switch M2 receives the first power supply voltage, it is in the on state, thereby electrically connecting the first potential output circuit 221, the second potential output circuit 222, and the latch signal output terminal TPout. This allows the voltage signals provided by the first potential output circuit 221 and the second potential output circuit 222 to be transmitted to the latch signal output terminal TPout to form the data latch signal TP. Correspondingly, when the second switch M2 does not receive the first power supply voltage, it is in the off state. The first potential output circuit 221 and the second potential output circuit 222 are electrically disconnected from the latch signal output terminal TPout. The voltage signals provided by the first potential output circuit 221 and the second potential output circuit 222 cannot be transmitted to the latch signal output terminal TPout, causing the latch signal output terminal TPout to stop outputting the data latch signal TP.

[0100] In this embodiment, the first power supply voltage is a high-potential power supply voltage, and the first switch tube M1 and the second switch tube M2 are N-type metal-oxide-semiconductor field-effect-transistors (MOSFETs) or N-type thin-film transistors (TFTs). Of course, in other embodiments of the present application, the first switch tube M1 and the second switch tube M2 may also be N-type transistors or triodes of other types that can be used as switches.

[0101] Alternatively, if the first power supply voltage is a low potential, the first switch tube M1 and the second switch tube M2 may also be P-type MOS tubes or TFTs.

[0102] In this embodiment, when the first switch transistor M1 and the second switch transistor M2 are MOS transistors or TFTs, the first control terminal CC1 and the second control terminal CC2 are gates of the MOS transistors or TFTs, and the first conductive terminal EC1 to the fourth conductive terminal EC4 can be sources / drains of the MOS transistors or TFTs, respectively.

[0103] The first potential output circuit 221 includes a third switch M3 and a fourth switch M4. The third switch M3 is connected to the first power terminal Pt1, the fourth switch M4, and the detection unit 21. The fourth switch M4 is connected to the third switch M3, the first power terminal Pt1, and the output control circuit 220. The third switch M3 and the fourth switch M4 cooperate to provide the first potential to the output control circuit 220 based on the detection signal Sdt provided by the detection unit 21.

[0104] Specifically, the third switch tube M3 includes a third control terminal CC3, a fifth conductive terminal EC5 and a sixth conductive terminal EC6. The third control terminal CC3 receives the detection signal Sdt. The fifth conductive terminal EC5 is connected to the first power terminal Pt1. The sixth conductive terminal EC6 is connected to the fourth switch tube M4.

[0105] The fourth switch tube includes a fourth control terminal CC4, a seventh conductive terminal EC7 and an eighth conductive terminal EC8, wherein the fourth control terminal CC4 is connected to the sixth conductive terminal EC6, the seventh conductive terminal EC7 is connected to the first power terminal Pt1, and the eighth conductive terminal EC8 is connected to the output control circuit 220.

[0106] In this embodiment, when the third switch M3 is turned on under the control of the detection signal Sdt, the first power supply voltage at the first power supply terminal Pt1 is transmitted to the fourth switch M4, and the fourth switch M4 is simultaneously turned on, thereby transmitting the power supply voltage VCC, which serves as the first power supply voltage, to the output control circuit 220, thereby transmitting the first power supply voltage as a first potential voltage signal to the output control circuit 220. Correspondingly, when the third switch M3 is turned off under the control of the detection signal Sdt, the first power supply voltage at the first power supply terminal Pt1 cannot be transmitted to the fourth switch M4. The fourth switch M4 is turned off, and the first power supply voltage stops being transmitted to the output control circuit 220.

[0107] In this embodiment, the third switch tube M3 and the fourth switch tube M4 may also be N-type MOS tubes or N-type TFTs. Of course, in other embodiments of the present application, the third switch tube M3 and the fourth switch tube M4 may also be N-type MOS tubes or other N-type transistors or triodes that can be used as switches.

[0108] Alternatively, if the first power supply voltage is a low potential, the third switch tube M3 and the fourth switch tube M4 may also be N-type MOS tubes, P-type MOS tubes, or TFTs.

[0109] In this embodiment, the third switch transistor M3 and the fourth switch transistor M4 may also be N-type MOS transistors. When the MOS transistors or TFTs are used, the third control terminal CC3 and the fourth control terminal CC4 may be gates of the MOS transistors or TFTs, and the fifth conductive terminal EC5 to the eighth conductive terminal EC8 may be sources and drains of the MOS transistors or TFTs, respectively.

[0110] The second potential output circuit 222 includes a fifth switch M5 and a sixth switch M6. The fifth switch M5 is connected to the first power terminal Pt1, the sixth switch M6, and the detection unit 21. The sixth switch M6 is connected to the fifth switch M5, the second power terminal Pt2, and the output control circuit 220. The fifth switch M5 and the sixth switch M6 cooperate to provide the second potential to the output control circuit 220 based on the detection signal Sdt provided by the detection unit 21.

[0111] Specifically, the fifth switch tube M5 includes a fifth control terminal CC5, a ninth conductive terminal EC9 and a tenth conductive terminal EC10. The fifth control terminal CC5 is connected to the detection unit 21 to receive the detection signal Sdt. The ninth conductive terminal EC9 is connected to the first power terminal Pt1. The tenth conductive terminal EC10 is connected to the sixth switch tube M6.

[0112] The sixth switch transistor M6 includes a sixth control terminal CC6, an eleventh conductive terminal EC11, and a twelfth conductive terminal EC12. The sixth control terminal CC6 is connected to the tenth conductive terminal EC10, the eleventh conductive terminal EC11 is connected to the second power terminal Pt2, and the twelfth conductive terminal EC12 is connected to the output control circuit 220. The second power terminal Pt2 is used to provide a second power supply voltage.

[0113] In this embodiment, the first power supply voltage corresponds to the high potential power supply voltage VCC, and the second power supply voltage corresponds to the low potential ground voltage GND.

[0114] In this embodiment, when the sixth switch M6 is turned on under the control of the detection signal Sdt, the first power supply voltage at the first power terminal Pt1 is transmitted to the sixth switch M6, and the sixth switch M6 is simultaneously turned on, thereby transmitting the second power supply voltage at the second power terminal Pt2 to the output control circuit 220, thereby transmitting the second power supply voltage as a second potential voltage signal to the output control circuit 220. Correspondingly, when the fifth switch M5 is turned off under the control of the detection signal Sdt, the first power terminal Pt1 cannot transmit power to the sixth switch M6. The sixth switch M6 is turned off, and the second power supply voltage provided by the second power terminal Pt2 stops being transmitted to the output control circuit 220.

[0115] In this embodiment, the fifth switch transistor M5 may be a P-type MOS transistor or a P-type TFT, and the sixth switch transistor M6 may be an N-type MOS transistor or an N-type TFT. Of course, in other embodiments of the present application, the fifth switch transistor M5 may be a P-type transistor or triode of other types that can be used as a switch, and the sixth switch transistor M6 may be an N-type MOS transistor or a N-type transistor or triode of other types that can be used as a switch.

[0116] Alternatively, if the second power supply voltage is a high potential, the fifth switch tube M5 may also be an N-type MOS tube or a TFT, and the fourth switch tube M4 may also be a P-type MOS tube.

[0117] In this embodiment, when the fifth switching transistor M5 and the sixth switching transistor M6 are MOS transistors or TFTs, the fifth control terminal CC5 and the sixth control terminal CC6 are gates of the MOS transistors or TFTs, and the ninth conductive terminal EC9 to the twelfth conductive terminal EC12 can be sources and drains of the MOS transistors or TFTs, respectively.

[0118] Please also refer to Figure 14-17 , Figure 14 For example Figure 13 Schematic diagram of the waveforms of various signals when the timing control circuit 20 outputs the data latch signal TP, wherein TPen represents the waveform of the latch enable signal, TP1 / TP2 represent the waveforms of the first data latch signal and the second data latch signal, Sdt represents the waveform of the detection signal, LA1 represents a schematic diagram of the data received by the first data latch, and LA2 represents a schematic diagram of the data received by the second data latch. Figure 15 FIG. 1 is a schematic diagram of the working process of the timing control circuit 20 outputting the data latch signal TP. Figure 16-17 Schematic diagram of the working state of the signal generating unit 22.

[0119] like Figure 15 As shown, in step 1000 , the timing control circuit 20 identifies the refresh rate of the data signal to be displayed, and outputs a detection signal according to the change of the refresh rate of the data signal to be displayed.

[0120] Specifically, the detection unit 21 identifies the corresponding refresh rate based on the data signal received by the storage unit 23 to confirm the refresh rate of the current frame displayed image of the pixel unit P and the refresh rate of the next frame image to be displayed and outputs the corresponding detection signal to confirm the change of the refresh rate.

[0121] Based on the change in refresh rate, the detection unit 21 outputs a corresponding detection signal Sdt to the signal generation unit 22. The duty cycle of the detection signal Sdt changes during the preset adjustment time Tx at which the refresh rate begins to change. In this embodiment, when the refresh rate increases, the duty cycle of the detection signal Sdt decreases during the adjustment time Tx and then returns to its original duty cycle after the adjustment time Tx.

[0122] For example, the first refresh rate of the current frame displayed is 4K, the detection signal Sdt has a first duty cycle, and the second refresh rate of the next frame to be displayed is 8K. During a preset adjustment time period Tx, the duty cycle of the detection signal is adjusted to a second duty cycle that is smaller than the first duty cycle. After the adjustment time period Tx, the duty cycle of the detection signal Sdt returns to the first duty cycle.

[0123] In step 2000 , a detection signal Sdt having a first duty cycle is outputted corresponding to image data of a first refresh rate.

[0124] The output control circuit 220 receives the latch enable signal TPen, and the detection unit 21 provides the detection signal Sdt to the first potential output circuit 221 and the second potential output circuit 222 .

[0125] like Figure 14 and Figure 16As shown, the high potential in the latch enable signal TPen controls the first switch tube M1 and the second switch tube M2 in the output control circuit 220 to be turned on, thereby electrically connecting the latch signal output terminal TPout to the first potential output circuit 221 and the second potential output circuit 222.

[0126] The high potential in the detection signal Sdt controls the third switch tube M3 and the fourth switch tube M4 of the first potential output circuit 221 to be turned on, so that the first potential provided by the first power supply terminal Pt1 is output to the latch signal output terminal TPout. At the same time, the high potential in the detection signal Sdt controls the fifth switch tube M5 and the sixth switch tube M6 of the second potential output circuit 222 to be turned off, preventing the second potential provided by the second power supply terminal Pt2 from being transmitted to the latch signal output terminal TPout.

[0127] Further, if Figure 14 and Figure 17 As shown, the low potential of the detection signal Sdt controls the third switch tube M3 and the fourth switch tube M4 of the first potential output circuit 221 to be turned off, so that the first potential provided by the first power supply terminal Pt1 stops being output to the latch signal output terminal TPout. At the same time, the low potential of the detection signal Sdt controls the fifth switch tube M5 and the sixth switch tube M6 of the second potential output circuit 222 to be turned on, so that the second potential provided by the second power supply terminal Pt2 is transmitted to the latch signal output terminal TPout.

[0128] Thus, the first and second voltage signals output from the latch signal output terminal TPout alternately form the first data latch signal TP1. Alternatively, the first and second voltage signals alternately form the data latch signal TP within one cycle. It can be understood that the data latch signal TP includes the first data latch signal TP1 and the second data latch signal TP2. In this embodiment, the first data latch signal TP1 and the second data latch signal TP2 have the same duty cycle as the detection signal Sdt.

[0129] In step 3000 , a detection signal having a second duty cycle is outputted within an adjustment time period Tx in response to the data signal being changed to the second refresh rate.

[0130] like Figure 14 As shown, within the adjustment time Tx starting from the second refresh rate, the detection signal Sdt has a second duty cycle, wherein the second duty cycle is smaller than the first duty cycle, that is, the high voltage time of the detection signal Sdt in each cycle within the preset time Tx is reduced.

[0131] In this embodiment, the first data latch signal TP1 and the second data latch signal TP2 output by the signal generating unit 22 are generated as follows: Figure 17-18As shown, when the duty cycle of the detection signal Sdt is reduced, resulting in a decrease in the high voltage time in each cycle, the data output timing Tre3 corresponding to the falling edge of each cycle of the second data latch signal TP2 within the preset time length Tx is earlier than the falling edge timing of the first data latch signal TP1.

[0132] like Figure 14 As shown, in the second data latch signal TP2, for the Mth row data signal Data, at the falling edge, the first data latch LA1 receives the blank data corresponding to the M+1th row data signal Data. Before the first data latch LA1 receives the polarity data, the second data latch LA2 receives the Mth row data signal Data at the falling edge. Therefore, at the falling edge of the second data latch signal TP2, the first data latch LA1 receives the blank data of the M+1th row data signal Data, while the second data latch LA2 receives the valid data of the Mth row data signal Data. The Mth row data signal Data is the data signal corresponding to the Mth row pixel unit P, and the M+1th row data signal Data is the data signal corresponding to the M+1th row pixel unit P.

[0133] Since blank data is invalid data, the amount of data received by the first data latch LA1 and the second data latch LA2 is smaller than when the first data latch LA1 and the second data latch LA2 simultaneously receive valid polarity data. Consequently, at the falling edge within the adjustment time Tx, the load on the first data latch LA1 and the second data latch LA2 is smaller, and the overall load on the data driver circuit 30 is smaller. This, in turn, has a smaller impact on the ground voltage transmitted in the power supply line, thereby reducing the probability of a GND bounce. In other words, even if the ground voltage is GND-bounced due to the load on the first data latch LA1 and the second data latch LA2, the first data latch LA1 receives blank data, which does not affect the accuracy of the data received by the first data latch LA1. This ensures the accuracy of the data received by the pixel unit P and improves the image display effect.

[0134] In this embodiment, the first data latch signal TP1 and the second data latch signal TP2 are continuous in time and together constitute the data latch signal TP.

[0135] In this embodiment, the number of cycles included in the second data latch signal TP2 within the adjustment time period Tx can be set based on the actual refresh rate and refresh rate requirements, and can be one or more. Furthermore, the adjustment time period Tx represents the buffering time for switching to a high refresh rate and can also be set based on actual conditions so as not to affect the normal display of the high refresh rate image.

[0136] When adjusting the duration Tx, the duration of the high voltage level of the second data latch signal TP2 can also be adjusted based on actual needs to avoid valid polarity data. In this embodiment, in addition to adjusting the duration Tx, the falling edge of the first data latch signal TP1 corresponds to the third byte of the polarity data. When each type of data is 8 bytes, the high voltage level of the second data latch signal TP2 is reduced by more than 11 bytes, which corresponds to the period of blank data. At the same time, in order to provide sufficient temporary storage time for the second data latch LA2 from receiving data to outputting valid data, the duration of the high voltage level cannot be too short. In this embodiment, the second data latch LA2 provides sufficient temporary storage time of four bytes from receiving data to outputting valid data. Therefore, the high voltage level of the second data latch signal TP2 is reduced to less than 15 bytes.

[0137] In step 4000 , after adjusting the time duration Tx, the detection signal having the first duty cycle and the first data latch signal TP1 are restored to be output.

[0138] like Figure 14 As shown, after adjusting the time length Tx, corresponding to the second refresh rate, the detection signal Sdt is restored to the first duty cycle corresponding to the first refresh rate. Correspondingly, the first data latch signal TP1 output by the signal generating unit 22 is processed as shown in FIG. Figure 16-17 shown.

[0139] See also Figure 18-19 , Figure 18 This is a circuit block diagram of a signal generating unit in the second embodiment of the present application. Figure 19 For example Figure 18 FIG. 1 is a schematic diagram of a second data latch signal TP2 output by the signal generating unit 22 .

[0140] In this embodiment, Figure 19 The first data latch signal TP1 and the second data latch signal TP2 are shown Figure 14 The figures are basically the same as shown, except for the shape of the falling edge of the second data latch signal TP2 corresponding to the preset time length Tx.

[0141] like Figure 19As shown, the falling edge of the second data latch signal TP2 is de-angled, and the potential after de-angle is greater than the voltage that controls the output data of the second data latch LA2. The falling edge corresponds to the moment when the pixel units in a row receive the data "1" of the polarity data in the data signal. For example, the falling edge corresponds to the moment when the pixel units in the M+1th row receive the data "1" of the polarity data in the data signal, thereby effectively reducing the error probability of binary data "0" in the data signal and improving data accuracy. In this embodiment, the duty cycle of the second data latch signal TP2 and the first data latch signal TP1 can be the same or different, and there is no limitation. It is only necessary to ensure that the falling edge of the second data latch signal TP2 corresponds to the moment when the polarity data in the data signal receives the data "1".

[0142] See also Figure 18 , and Figure 13 The circuit diagram of the signal generating unit 22 shown is basically the same, the difference is that it also includes a corner elimination circuit 223, which is connected between the first potential output circuit 221 and the output control circuit 220, and is used to output the voltage change of the control circuit 220 in the process of changing from high potential to low potential, that is, to adjust the waveform and speed of the falling edge of the second data latch signal TP2, so that the falling edge of the second data latch signal TP2 corresponds to the moment of receiving the data "1" in the polarity data.

[0143] In this embodiment, the angle elimination circuit 223 can be implemented by using a capacitor in conjunction with a switch tube to increase the falling edge speed of the data latch signal TP and adjust the falling edge position.

[0144] More specifically, if Figure 19 As shown, within the adjusted duration Tx, at the rising edge of the second data latch signal TP2, the first data latch LA1 transmits the data signal Data corresponding to the Mth row to the second data latch LA2; the voltage value of the falling edge of the second data latch signal TP2 after the angle is eliminated corresponds to the position of the "1" in the polarity data of the data signal Data of the M+1th row. For example, if the polarity data of the data signal of the M+1th row is "011001111", the timing of the falling edge of the second data latch signal TP2 corresponds to the time corresponding to the high voltage data "1" in the corresponding polarity data. In this embodiment, at the time of the falling edge of the second data latch signal TP, the second data latch LA2 outputs the data signal Data corresponding to the Mth row. At the same time, the timing of the falling edge of the second data latch signal TP corresponds to the time when any data "1" corresponds in the last four bits of the polarity data "011001111" in the data signal Data of the M+1th row.

[0145] In this embodiment, since the voltage value of the falling edge of the second data latch signal TP2 corresponds to the data "1" in the polarity data, when the ground voltage GND increases as the signal reference voltage, the first data latch LA1 can still accurately receive the data "1" in the data signal Data, and will not misjudge the data "0" due to the increase of the ground voltage GND as the signal reference voltage, thereby effectively ensuring the accuracy of the first data latch LA1 receiving the data signal Data.

[0146] Optionally, the voltage value of the falling edge of the second data latch signal TP2 after the angle is eliminated corresponds to two adjacent bits of data in the polarity data being “1”, thereby further effectively ensuring that the first data latch LA1 can still accurately receive data “1”.

[0147] See also Figure 20 , which is applied to Figures 12-19 The figure shows a flow chart of a method for outputting data from a display panel in a display device.

[0148] It can be understood that the above data output method is mainly used for Figures 12 to 19 The timing control circuit 20 and the data driving circuit 30 are shown.

[0149] In step 1001, the timing control circuit 20 identifies the refresh rate of the data signal to be displayed, and outputs the first data latch signal TP1 corresponding to the display image of the first refresh rate. The first data latch LA1 and the second data latch LA2 output the data signal Data according to the first data latch signal TP1.

[0150] In step 2001, within the adjustment time Tx when the refresh rate corresponding to the data signal Data increases to the second refresh rate, the timing control circuit 20 outputs the second data latch signal TP2, and the first data latch LA1 and the second data latch LA2 output the data signal Data according to the second data latch signal.

[0151] Step 3001: After the time length Tx is adjusted, the timing control circuit 20 outputs the first data latch signal TP1, and the first data latch LA1 and the second data latch LA2 output the data signal according to the first data latch signal TP1; Step 4001: Convert the data signal into a grayscale voltage and output it to the pixel unit P.

[0152] It can be understood that this step is performed by the data amplifying and converting section 30C in the data driving circuit 30 .

[0153] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above implementation methods is only used to help understand the core idea of ​​this application. At the same time, for those skilled in the art, based on the idea of ​​this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on this application.

Claims

1. A timing control circuit, characterized in that: Used to receive image signals and output data signals and data latch signals accordingly, including: a storage unit, configured to receive the data signal and store the data signal corresponding to the image signal; a detection unit, which determines a corresponding refresh rate according to the data signal and outputs a corresponding detection signal; a signal generating unit connected to the detection unit and outputting the data latch signal according to the detection signal, wherein the first data latch signal is output when the refresh rate is a first refresh rate, and the second data latch signal is output within an adjustment period starting from when the first refresh rate is increased to the second refresh rate, the duty cycle of the second data latch signal is smaller than the duty cycle of the first data latch signal, or the speed at which two potentials in the second data latch signal are switched is faster than the speed at which two potentials in the first data latch signal are switched; and A data sending unit is connected to the storage unit and is used to output the data signal.

2. The timing control circuit according to claim 1, wherein: The first data latch signal has a first duty cycle or a first speed when switching between two potentials; the second data latch signal has a second duty cycle or a second speed when switching between two potentials, wherein the second duty cycle is smaller than the first duty cycle and the second speed is greater than the first speed; After the adjustment time period, the detection unit outputs the first data latch signal.

3. The timing control circuit according to claim 2, wherein: When the data signal corresponds to the first refresh rate, the duty cycle of the detection signal is the first duty cycle. When the refresh rate corresponding to the data signal increases to the second refresh rate, the duty cycle of the detection signal is the second duty cycle within the adjustment period. After the adjustment period, the duty cycle of the detection signal returns to the first duty cycle, and the waveform of the data latch signal is the same as the waveform of the detection signal.

4. The timing control circuit according to claim 3, wherein: The data latch signal is a pulse signal that changes periodically. The signal generating unit includes an output control circuit, a first potential output circuit and a second potential output circuit, wherein: The output control circuit receives a latch enable signal and determines whether to output the data latch signal according to the latch enable signal; The first potential output circuit is connected to the output control circuit, and is used to provide a first potential to the output control circuit under the control of the detection signal; The second potential output circuit is connected to the output control circuit and is used to provide a second potential to the output control circuit under the control of the detection signal. The first potential and the second potential switch with each other to form the first data latch signal or the second data latch signal within one cycle.

5. The timing control circuit according to claim 4, wherein: The signal generating unit also includes a corner elimination circuit, which is connected between the first potential output circuit and the output control circuit, and is used to perform corner elimination processing on the second data latch signal when the first potential changes to the second potential within the adjustment time, so as to improve the speed of switching between the two potentials in the second data latch signal.

6. The timing control circuit according to any one of claims 4 to 5, characterized in that: The first potential is a high potential, and the second potential is a low potential.

7. A data driving circuit, characterized in that: The timing control circuit according to any one of claims 1 to 6 is configured to receive the data signal and the data latch signal, wherein the data driving circuit includes a data latch unit, and the data latch unit includes a first data latch and a second data latch, wherein: the first data latch receiving and latching the data signal according to the first data latch signal or the second data latch signal; The second data latch is connected to the first data latch, and is used to receive the data signal from the first data latch according to the edge of the first data latch signal or the second data latch signal when the potential switches, and output the data signal at the edge of the adjacent potential switch.

8. The data driving circuit according to claim 7, wherein: The data signal corresponding to each row of pixel units includes blank data, calibration data, polarity data, valid data and stop data in sequence, and the pixel units are used to perform image display according to the data signals; In the first data latch signal, the first data latch receives the data signal on the rising edge of the first data latch signal. When the refresh rate increases, within the adjustment period, the first data latch outputs the valid data corresponding to the M-th row of pixel units to the second data latch on the rising edge of the second data latch signal. The first data latch receives the blank data in the data signal corresponding to the M+1-th row of pixel units on the falling edge of the second data latch signal. At the same time, the second data latch outputs the valid data in the data signal corresponding to the M-th row of pixel units on the falling edge of the second data latch signal, where M is a positive integer greater than or equal to 1.

9. The data driving circuit according to claim 7, wherein: The data signal corresponding to each row of pixel units includes blank data, calibration data, polarity data, valid data and stop data in sequence, and the pixel units are used to perform image display according to the data signals; In the first data latch signal, the first data latch receives the data signal on the rising edge of the first data latch signal. When the refresh rate increases, within the adjustment period, the first data latch outputs the valid data corresponding to the M-th row of pixel units to the second data latch on the rising edge of the second data latch signal. The first data latch receives the data "1" in the polarity data in the data signal corresponding to the M+1-th row of pixel units on the falling edge of the second data latch signal. At the same time, the second data latch outputs the valid data in the data signal corresponding to the M-th row of pixel units on the falling edge of the second data latch signal, where M is a positive integer greater than or equal to 1.

10. A display panel, characterized in that: The display panel includes n scan lines extending along a first direction, m data lines extending along a second direction, and a plurality of pixel units arranged in an array, a scan driving circuit, a timing control circuit according to any one of claims 1 to 6, and a data driving circuit according to any one of claims 7 to 9. The data driving circuit and the scan driving circuit are connected to the pixel units through the data lines and the scan lines, respectively. The pixel units are used to receive scan signals from the scan lines, and receive the data signals from the data lines under the control of the scan signals to perform image display. The timing control circuit is used to provide the first data latch signal and the second data latch signal to the data driving circuit. The data driving circuit outputs the grayscale voltage corresponding to the data signal to the pixel units based on the first data latch signal and the second data latch signal.

11. A data output method, applied to the display panel according to claim 10, characterized in that: include: The timing control circuit identifies the refresh rate of the data signal to be displayed, outputs the first data latch signal corresponding to the display image of the first refresh rate, and the first data latch and the second data latch output the data signal according to the first data latch signal; During the adjustment period when the refresh rate corresponding to the data signal increases to the second refresh rate, the timing control circuit outputs the second data latch signal, and the first data latch and the second data latch output the data signal according to the second data latch signal; After the adjustment time, the timing control circuit outputs the first data latch signal, and the first data latch and the second data latch output the data signal according to the first data latch signal; The data signal is converted into a grayscale voltage and output to the pixel unit.

Images