SRAM chip, SRAM chip control method and electronic device

Abstract

This invention relates to the field of SRAM technology, providing an SRAM chip, an SRAM chip control method, and an electronic device. The SRAM chip includes an SRAM array, a row decoder, and a column decoder. The row decoder has word lines corresponding to each row of 6T-SRAM cells. The ground terminal of each column of 6T-SRAM cells is grounded through a discharge NMOS transistor. The column decoder has a write enable signal terminal, a read enable signal terminal, and an OR gate, corresponding to the read select signal terminal, write select signal terminal, and NAND gate for each column of 6T-SRAM cells. The write enable signal terminal and read enable signal terminal are connected to the input terminals of the OR gates, and the output terminals of the OR gates are connected to the input terminals of the NAND gates in each column. The input terminals of each column of NAND gates are connected to the read select signal terminal and write select signal terminal of the corresponding column, and the output terminals of each column of NAND gates are connected to the gates of the discharge NMOS transistors in the corresponding column. This addresses the problem that SRAM arrays struggle to simultaneously achieve low power consumption, low area overhead, and simple control timing.

Description

Technical Field

[0001] This invention relates to the field of static random access memory technology, and in particular to an SRAM chip, an SRAM chip control method, and an electronic device. Background Technology

[0002] Static Random Access Memory (SRAM) is often used in the form of arrays. In an SRAM array, when an SRAM cell in a row or column is activated, the cells in that row or column that are not fully selected, i.e., half-selected cells, will generate additional leakage current paths due to the conduction of some of their transistors, resulting in redundant power consumption.

[0003] To address this, related technologies have added two NMOS transistors and read control signals to the 6T-SRAM cell, designing a read-write separated 8T-SRAM cell. The 8T-SRAM array uses the same control logic as the 6T-SRAM array during the write phase, and it can reduce the power consumption of the half-select cells during the read phase. However, the 8T-SRAM array can only reduce the power consumption of the half-select cells partially, and it significantly increases the memory area overhead and the complexity of the control timing.

[0004] There is currently no effective solution to the problem that SRAM arrays of related technologies cannot simultaneously achieve low power consumption, low area overhead, and simple control timing. Summary of the Invention

[0005] The present invention provides an SRAM chip, an SRAM chip control method, and an electronic device, which at least solves the problem that SRAM arrays in related technologies are difficult to achieve in a balance of low power consumption, low area overhead, and simple control timing.

[0006] This invention provides an SRAM chip comprising a static random access memory (SRAM) array, a row decoder, and a column decoder. The row decoder provides word lines for each row of 6T-SRAM cells in the SRAM array, and the column decoder provides bit lines and complementary bit lines for each column of 6T-SRAM cells in the SRAM array. The ground terminal of each column of 6T-SRAM cells is grounded through a discharge NMOS transistor. The column decoder includes a write enable signal terminal, a read enable signal terminal, and an OR gate. Each column of 6T-SRAM cells also includes a read select signal terminal, a write select signal terminal, and a NAND gate. The write enable signal terminal and the read enable signal terminal are connected to the input terminals of the OR gates, and the output terminals of the OR gates are connected to the input terminals of the NAND gates in each column. The input terminals of each column of NAND gates are also connected to the read select signal terminal and the write select signal terminal of the corresponding column, and the output terminals of each column of NAND gates are connected to the gates of the discharge NMOS transistors in the corresponding column.

[0007] The SRAM chip provided in the embodiments of the present invention has a common grounding NMOS transistor for the grounding terminal of each column of 6T-SRAM cells, or each 6T-SRAM cell is equipped with a grounding NMOS transistor.

[0008] The SRAM chip provided in this invention includes a NAND gate comprising a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor. The first, second, and third PMOS transistors are connected in parallel via a common source and a common drain. The common source is connected to a power supply, and the common drain is connected to the gate of the corresponding discharge NMOS transistor and the drain of the first NMOS transistor. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the source of the second NMOS transistor is connected to the drain of the third NMOS transistor, and the source of the third NMOS transistor is grounded. The gates of the first PMOS transistor and the first NMOS transistor are connected to the corresponding write select signal terminals, the gates of the second PMOS transistor and the second NMOS transistor are connected to the output terminal of an OR gate, and the gates of the third PMOS transistor and the third NMOS transistor are connected to the corresponding read select signal terminals.

[0009] The SRAM chip provided in the embodiment of the present invention has an SRAM array configured with 2n 6T-SRAM cells, where n is an integer greater than or equal to 2.

[0010] The SRAM chip provided in the embodiments of the present invention has 6T-SRAM cells whose MOS transistors and discharge NMOS transistors are fin field-effect transistors, and the fin field-effect transistors have a process precision of 12 nanometers.

[0011] The SRAM chip provided in the embodiments of the present invention has multiple column decoders, and the multiple column decoders share a write enable signal terminal, a read enable signal terminal, a write select signal terminal, and a read select signal terminal.

[0012] The SRAM chip provided in the embodiments of the present invention has a column decoder equipped with a multiplexer. The multiplexer is used to select the write select signal terminal and the read select signal terminal corresponding to the target column 6T-SRAM cell.

[0013] This invention provides an SRAM chip control method, wherein the SRAM chip is any of the aforementioned SRAM chips. During the data writing phase, the write enable signal is set to a high level, the write select signal corresponding to the column where the 6T-SRAM select unit is located is set to a low level, and the word line corresponding to the row where the select unit is located is set to a high level, controlling the bit line and complementary bit line corresponding to the column where the select unit is located to write the target data into the select unit. During the data reading phase, the read enable signal is set to a high level, the bit line and complementary bit line of the column where the select unit is located are pre-charged to the power supply voltage, the read select signal corresponding to the column where the select unit is located is set to a low level, and the word line corresponding to the row where the select unit is located is set to a high level to read the data stored in the select unit.

[0014] The SRAM chip control method provided in this invention sets the write enable signal and read enable signal to low level during the data retention phase.

[0015] An electronic device provided by an embodiment of the present invention uses any of the above-described SRAM chips as its SRAM chip.

[0016] This invention provides an SRAM chip, an SRAM chip control method, and an electronic device. The ground terminal of each column of 6T-SRAM cells is grounded through a discharge NMOS transistor. The column decoder is equipped with a write enable signal terminal, a read enable signal terminal, and an OR gate. For each column of discharge NMOS transistors, the column decoder is equipped with a read select signal terminal, a write select signal terminal, and a NAND gate. The write enable signal terminal and the read enable signal terminal are connected to the input terminals of the OR gates, and the output terminals of the OR gates are connected to the input terminals of the NAND gates in each column. The input terminals of each column's NAND gates are also connected to the read select signal terminal and the write select signal terminal of the corresponding column, and the output terminals of each column's NAND gates are connected to the gates of the discharge NMOS transistors in the corresponding column. By turning off the discharge NMOS transistors and controlling the word lines of the row decoder, the discharge path of the half-select cell can be cut off during the data writing and data reading stages, significantly reducing the power consumption caused by the half-select cell. Simultaneously, it reduces memory area overhead and control timing complexity compared to an 8T-SRAM array. This addresses the problem that related SRAM arrays struggle to simultaneously achieve low power consumption, low area overhead, and simple control timing. Attached Figure Description

[0017] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other embodiments based on these drawings without creative effort.

[0018] Figure 1This is a schematic diagram of the structure of an SRAM chip using a 6T-SRAM array but without a discharge NMOS transistor in an embodiment of the present invention.

[0019] Figure 2 This is a schematic diagram of the structure of the 6T-SRAM cell in an embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram of the structure of the 8T-SRAM cell in an embodiment of the present invention.

[0021] Figure 4 This is a schematic diagram of a low-frequency SRAM chip with a discharge NMOS transistor in an embodiment of the present invention.

[0022] Figure 5 This is a schematic diagram of the structure of a high-frequency SRAM chip with a discharge NMOS transistor in an embodiment of the present invention.

[0023] Figure 6 yes Figure 1 The diagram shows the control timing of the SRAM array in the SRAM chip.

[0024] Figure 7 yes Figure 4 The diagram shows the control timing of the SRAM array in the SRAM chip. Detailed Implementation

[0025] Embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While some embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0026] Static Random Access Memory (SRAM) is often used in the form of arrays. In an SRAM array, when an SRAM cell in a certain row or column is activated, the cells in that row or column that are not fully selected, i.e., half-selected cells, will generate additional leakage current paths due to the conduction of some of their transistors, resulting in redundant power consumption.

[0027] In multi-port SRAM or large-capacity arrays, frequent row / column activation operations can significantly increase the number of half-select cells. In nanoscale processes, the power consumption generated by half-select cells can reach 20% to 40% of the total static power consumption. Therefore, reducing the power consumption generated by half-select cells can be a breakthrough for optimizing SRAM arrays.

[0028] Specifically, SRAM cells in an SRAM array can be categorized into selected cells, half-selected cells, and unselected cells during operation. For selected cells, both the word line (WL) and bit line (BL) are active, allowing for read or write operations. For unselected cells, both the word line and bit line are in the off state.

[0029] Half-select units can be divided into WL half-select units and BL half-select units. During read or write operations on a select unit, when the word line (WL) corresponding to the select unit is open, other SRAM units located in the same row as the select unit are WL half-select units; when the bit line (BL) corresponding to the select unit is open, other SRAM units located in the same column as the select unit are BL half-select units. It's important to understand that a half-select unit is relative to the select unit, and half-select units share word lines or bit lines with the select unit.

[0030] When performing read or write operations on the select unit, the pre-charged charge on the bit line corresponding to the WL half-select unit will be discharged through the discharge circuit formed by the transmission transistor and pull-down transistor of the WL half-select unit, while the transmission transistor of the BL half-select unit is in the off state, and only leakage current exists.

[0031] For example, please refer to Figure 1 As shown, this embodiment provides an explanation of the related technologies for an SRAM chip that uses a 6T-SRAM array but does not have a discharge NMOS transistor. Specifically, Figure 1 The SRAM chip shown, and the SRAM chip with a discharge NMOS transistor provided later in this embodiment, have read / write control circuits and auxiliary circuits such as pre-charge circuits and sensitive amplifiers that are not shown, which are prior art known to those skilled in the art.

[0032] exist Figure 1 In the SRAM chip shown, the row decoder provides word line signals to the selection cell, while the column decoder provides bit line signals, complementary bit line signals, write select signals, and read select signals. The word line signals can simultaneously control the on / off state of the transmission transistors of all 6T-SRAM cells in the row containing the selection cell. The word line signals and bit line / complementary bit line signals work together to determine the selection cell. The write select signals and read select signals are used to perform data write or read operations on the selection cell.

[0033] For example, Figure 1The 6T-SRAM cell located in the first row and first column of the 6T-SRAM array shown is the 6T-SRAM cell defined by word line WL0, bit line BL0 / complementary bit line BLB0, and is used as the first selection cell for read and write operations. If word line WL0 is set to high, the transmission transistors of all 6T-SRAM cells in the first row containing the first selection cell are turned on. The first selection cell, the second selection cell of the 8T-SRAM array described later, and the third selection cell of the SRAM array in an SRAM chip equipped with a discharge NMOS transistor are used only to distinguish the selection cells in different SRAM arrays and do not limit the order or importance of the selection cells. Figure 1 In the diagram, VSS represents the ground terminal of the 6T-SRAM array, bit line BL1 is used to provide bit line signals to the second column of 6T-SRAM cells, BL2 is used to provide bit line signals to the third column of 6T-SRAM cells, and BL3 is used to provide bit line signals to the fourth column of 6T-SRAM cells.

[0034] For details, please refer to Figure 2 As shown, the 6T-SRAM cell includes a first pull-up transistor PU1, a second pull-up transistor PU2, a first transmission transistor PG1, a second transmission transistor PG2, a first pull-down transistor PD1, and a second pull-down transistor PD2. The first pull-up transistor PU1 and the first pull-down transistor PD1 are connected in series to form a first inverter, and the second pull-up transistor PU2 and the second pull-down transistor PD2 form a second inverter. Specifically, the first pull-up transistor PU1 and the second pull-up transistor PU2 are PMOS transistors, and the first transmission transistor PG1, the second transmission transistor PG2, the first pull-down transistor PD1, and the second pull-down transistor PD2 are NMOS transistors.

[0035] VDD represents the power supply terminal, VSC represents the ground terminal, Q represents the storage node, and QB is the complementary node of storage node Q. The logical data stored in storage node Q and complementary node QB are opposite.

[0036] Combination Figure 1 and Figure 2 The following explanation will be based on the example of performing write 0 and read 0 operations on the first selection unit.

[0037] It should be noted that in the column decoder, the write select signal terminal can be divided into two ends, denoted by YSW and YSWB respectively; the read select signal terminal can also be divided into two ends, denoted by YSR and YSRB respectively. YSW, YSWB, YSR, and YSRB satisfy the following conditions: the level states of YSW and YSWB are opposite, the level states of YSR and YSRB are opposite, the level states of YSW and YSR are the same, and the level states of YSWB and YSRB are the same. This is prior art known to those skilled in the art. In the following description of the level states of each write select signal terminal and each read select signal terminal, the embodiment of this invention will use YSWB (write select signal terminal) and YSR (read select signal terminal) as examples.

[0038] When a write-zero operation is performed on the first selection cell, the bit line BL0 corresponding to the first selection cell is set to low, the complementary bit line BLB0 remains high, and the write selection signal YSWB0 is set to low. At this time, the bit lines and complementary bit lines corresponding to the 6T-SRAM cells in other columns remain high. Since the word line WL0 corresponding to the first selection cell is set to high and turned on, the WL half-select cell corresponding to the first selection cell, that is, other 6T-SRAM cells located in the same row as the first selection cell, will experience additional power loss due to discharge.

[0039] Specifically, each WL half-select unit corresponding to the first selection unit will discharge through its own bit line - first transmission tube PG1 - first pull-down tube PD1 - ground terminal VSC first discharge path, or complementary bit line - second transmission tube PG2 - second pull-down tube PD2 - ground terminal VSC second discharge path. The specific discharge path can be determined by the value of the storage node of each WL half-select unit.

[0040] When performing a read 0 operation on the first selection unit, the bit line BL0 and complementary bit line BLB0 corresponding to the first selection unit are pre-charged to the power supply voltage, and the read selection signal terminal YSR0 is set to a low level. At this time, the bit line BL0 corresponding to the first selection unit will discharge through the first transmission transistor PG1 and the first pull-down transistor PD1 of the first selection unit. However, the bit line BL0 corresponding to the first selection unit is connected to a sensitive amplifier, and the sensitive amplifier will immediately charge the bit line BL0 corresponding to the first selection unit after reading the result. Therefore, the voltage change of the bit line BL0 corresponding to the first selection unit is not significant. However, each WL half-select unit corresponding to the first selection unit will discharge its complementary bit line to ground potential through the second discharge path.

[0041] To reduce the power consumption of 6T-SRAM arrays due to half-select cells, related technologies have improved the 6T-SRAM array into an 8T-SRAM array. Each SRAM cell in an 8T-SRAM array is obtained by adding two NMOS transistors to a 6T-SRAM cell. The structure of an 8T-SRAM cell can be found in [reference needed]. Figure 3 As shown, the 8T-SRAM cell uses two additional NMOS transistors PR1 and PR2 to form a separate read loop, which is controlled by the read control signal RWL, enabling read-write separation.

[0042] The control logic for the 8T-SRAM array is the same as that for the 6T-SRAM array during the data writing stage.

[0043] During the data reading phase, for the aforementioned 8T-SRAM array, the read control signal RWL of the second selection unit needs to be set to a high level, and the read bit line RBL needs to be precharged to a high level.

[0044] When the storage node Q of the second selection unit is 1 and the complementary node QB is 0, the NMOS transistor PR1 of the second selection unit is turned off, the discharge circuit between the read bit line RBL and the ground terminal VSC is cut off, and the voltage on the read bit line RBL does not change.

[0045] When the storage node Q of the second selection unit is 0 and the complementary node QB is 1, the NMOS transistor PR1 of the second selection unit is turned on, and the read bit line RBL is discharged through the NMOS transistors PR1 and PR2.

[0046] When reading data from the second selection unit, the word lines WL corresponding to each WL half-select unit of the second selection unit are turned off, the read control signal RWL is turned on, and the read bit line RBL is pre-charged to the power supply voltage. The bit line BL or complementary bit line BLB is also pre-charged to the power supply voltage but has no corresponding discharge path, so the bit line BL or complementary bit line BLB does not generate power consumption. However, when the complementary node QB of the WL half-select unit corresponding to the second selection unit is 1, the read bit line RBL of that WL half-select unit will discharge, generating power consumption; when the complementary node QB of the WL half-select unit corresponding to the second selection unit is 0, the voltage of the read bit line RBL of that WL half-select unit remains unchanged, and no power consumption is generated.

[0047] Therefore, the 8T-SRAM array can reduce the power consumption of the half-select unit to a certain extent during the data reading stage. However, the 8T-SRAM array will greatly increase the memory area overhead compared to the 6T-SRAM array. While separating read and write operations, it will also make the control timing more complex.

[0048] In other words, the 6T-SRAM array and 8T-SRAM array in the related technologies cannot simultaneously achieve the advantages of low power consumption, low area overhead and simple control timing. As the memory capacity increases and the read and write frequency accelerates, the power consumption of the half-select unit will also increase.

[0049] Therefore, please refer to Figure 4 As shown, this invention provides an SRAM chip, including a Static Random Access Memory (SRAM) array, a row decoder, and a column decoder. The row decoder provides word lines for each row of 6T-SRAM cells in the SRAM array, and the column decoder provides bit lines and complementary bit lines for each column of 6T-SRAM cells in the SRAM array. The ground terminal of each column of 6T-SRAM cells is grounded through a discharge NMOS transistor. The column decoder is provided with a write enable signal terminal WE, a read enable signal terminal RE, and an OR gate. The column decoder also provides a read select signal terminal, a write select signal terminal, and a NAND gate for each column of 6T-SRAM cells. The write enable signal terminal WE and the read enable signal terminal RE are connected to the input terminals of the OR gates, and the output terminals of the OR gates are connected to the input terminals of the NAND gates in each column. The input terminals of each column of NAND gates are also connected to the read select signal terminal and the write select signal terminal of the corresponding column, and the output terminals of each column of NAND gates are connected to the gates of the discharge NMOS transistors in the corresponding column.

[0050] Understandable Figure 4 The SRAM array shown includes 16 6T-SRAM cells arranged in a 4x4 grid. This is merely an example; those skilled in the art can determine the specific number of 6T-SRAM cells, rows, and columns according to actual needs. Of course, the number of word lines set in the row decoder, and the number of bit lines, complementary bit lines, read select signal pins, and write select signal pins set in the column decoder must all be adjusted accordingly.

[0051] The grounding terminal of each column of 6T-SRAM cells is grounded through a discharge NMOS transistor, including: the grounding terminal of each column of 6T-SRAM cells shares a discharge NMOS transistor; each 6T-SRAM cell is configured with a discharge NMOS transistor for grounding; in each column of 6T-SRAM cells, a portion of the 6T-SRAM cells share a discharge NMOS transistor for grounding, and a portion of the 6T-SRAM cells are each configured with a discharge NMOS transistor for grounding.

[0052] Therefore, the number of MOS transistors used in the SRAM array of the above-mentioned SRAM chip is always less than the number of MOS transistors used in the 8T-SRAM array of the related technology. In other words, the SRAM array of the above-mentioned SRAM chip can reduce memory area overhead compared to the 8T-SRAM array.

[0053] In applications involving multi-port SRAM or large-capacity arrays, the SRAM array of the aforementioned SRAM chip offers a significant advantage over the 8T-SRAM array in reducing memory area overhead. Furthermore, this embodiment preferably uses a single discharge NMOS transistor for the grounding terminal of each column of 6T-SRAM cells, and each 6T-SRAM cell has its own discharge NMOS transistor for grounding; details will be provided later.

[0054] When writing or reading data in the third selection cell of the SRAM array of the aforementioned SRAM chip equipped with a discharge NMOS transistor, turning off the discharge NMOS transistor cuts off the discharge path of the corresponding WL half-select cell, preventing the WL half-select cell from consuming power. By controlling the word line of the row decoder, the transmission transistor of the corresponding BL half-select cell can be cut off. Combined with the discharge NMOS transistor, the leakage current of the BL half-select cell can be limited in two stages. Therefore, the aforementioned SRAM chip equipped with a discharge NMOS transistor can cut off the discharge paths of both the BL and WL half-select cells during the data writing and reading phases, and effectively limit the leakage current of the BL half-select cell, significantly reducing the power consumption caused by the half-select cells.

[0055] Specifically, by setting a NAND gate, the discharge NMOS transistor corresponding to the third selection unit will be turned on if any one of the read selection signal, write selection signal, or OR gate output is set to a low level. The discharge NMOS transistor will only be turned off when all three are high. Therefore, writing data to the third selection unit requires setting the write selection signal to a low level, and reading data from the third selection unit requires setting the read selection signal to a low level. Other column selection signals are set to high levels when writing or reading data from the third selection unit. Therefore, the control timing for writing or reading data in the SRAM array of the above SRAM chip is similar to that of a 6T-SRAM array in related technologies, and simpler than that of an 8T-SRAM array.

[0056] When holding data in the SRAM array of the aforementioned SRAM chip equipped with discharge NMOS transistors, controlling all discharge NMOS transistors to be turned on can effectively prevent charge leakage and accumulation from affecting the level transition within each SRAM cell.

[0057] Specifically, by setting the OR gate, if either the write enable signal WE or the read enable signal RE is set to high, the OR gate output will be high. The OR gate output will only be low when both the write enable signal WE and the read enable signal RE are low. Therefore, when maintaining data in the SRAM array of the aforementioned SRAM chip equipped with a discharge NMOS transistor, both the write enable signal WE and the read enable signal RE need to be set to low. This avoids the aforementioned level conversion problem and makes full use of existing signal terminals, reducing circuit design complexity while improving control efficiency.

[0058] In summary, to address the issues of high power consumption in the half-select cells of 6T-SRAM arrays and the fact that 8T-SRAM arrays can only reduce half-select cell power consumption to a certain extent while increasing memory area overhead and control timing complexity, this invention provides the aforementioned SRAM chip equipped with a discharge NMOS transistor. This chip can significantly reduce half-select cell power consumption while ensuring simple control timing and has a relatively smaller memory area overhead compared to 8T-SRAM arrays.

[0059] Preferably, in the SRAM chip equipped with a discharge NMOS transistor, the ground terminals of each column of 6T-SRAM cells share a common discharge NMOS transistor for grounding, or each 6T-SRAM cell is equipped with a discharge NMOS transistor for grounding.

[0060] Figure 4 The SRAM chip shown shares a single discharge NMOS transistor for each column of 6T-SRAM cells. Because this single transistor cannot ensure equal physical distances between each 6T-SRAM cell and its corresponding discharge NMOS transistor, a certain delay exists. This chip is suitable for scenarios with low read / write speed requirements and is classified as a low-frequency SRAM chip. In the diagram, VSC0 represents the ground terminal of the first column of 6T-SRAM cells, VSC1 represents the ground terminal of the second column, VSC2 represents the ground terminal of the third column, and VSC3 represents the ground terminal of the fourth column. NM0 represents the discharge NMOS transistor shared by the first column of 6T-SRAM cells, NM1 represents the discharge NMOS transistor shared by the second column, NM2 represents the discharge NMOS transistor shared by the third column, and NM3 represents the discharge NMOS transistor shared by the fourth column.

[0061] Figure 5Each 6T-SRAM cell of the SRAM chip shown is equipped with a discharge NMOS transistor at its ground terminal, which is suitable for scenarios requiring high read and write speeds and belongs to high-frequency SRAM chips.

[0062] Obviously, Figure 4 The SRAM chip shown focuses on sacrificing some read / write speed to reduce memory area overhead. Figure 5 The SRAM chip shown focuses on increasing memory area overhead to improve read and write speeds.

[0063] Those skilled in the art can select or adjust the options according to actual application requirements.

[0064] certainly, Figure 4 The SRAM chip shown is Figure 5 The SRAM chips shown can solve the problems of low power consumption, low area overhead, and simple control timing that are difficult to achieve with SRAM arrays in related technologies.

[0065] in addition, Figure 1 Please refer to the control timing diagram of the SRAM chip without a discharge NMOS transistor shown. Figure 6 As shown, Figure 4 Please refer to the control timing diagram of the SRAM chip with the discharge NMOS transistor shown. Figure 7 As shown, where, Figure 6 and Figure 7 The SRAM chips shown all consist of an SRAM array composed of four rows and four columns of 6T-SRAM cells. Each chip uses a 6T-SRAM cell located in the first row and first column of its respective SRAM array, which can be determined by word line WL0, bit line BL0, and bit line BLB0, as the selection cell. Each chip performs write 0 and read 0 operations on the selection cell.

[0066] Compare Figure 6 and Figure 7 It can be seen that, on the one hand, Figure 4 The SRAM array shown has an SRAM chip with a discharge NMOS transistor, and has and Figure 1 The control timing is similar to that of the SRAM array in the SRAM chip shown, illustrating... Figure 4 The control timing of the SRAM array with the SRAM chip equipped with the discharge NMOS transistor shown is simple.

[0067] On the other hand, with Figure 6 The complementary bit lines BLB1, BLB2, and BLB3 corresponding to the WL half-select unit generate different power consumptions during data writing and reading from the first select unit. Figure 7 The complementary bit lines BLB1, BLB2, and BLB3 corresponding to the WL half-select unit do not discharge when writing and reading data from the third select unit, indicating that... Figure 4The SRAM chip shown, equipped with a discharge NMOS transistor, can effectively reduce the power consumption of the WL half-select cell.

[0068] Preferably, the NAND gate includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor. The first, second, and third PMOS transistors are connected in parallel via a common source and a common drain. The common source is connected to a power supply, and the common drain is connected to the gate of the corresponding discharge NMOS transistor and the drain of the first NMOS transistor. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the source of the second NMOS transistor is connected to the drain of the third NMOS transistor, and the source of the third NMOS transistor is grounded. The gates of the first PMOS transistor and the first NMOS transistor are connected to the corresponding write select signal terminals, the gates of the second PMOS transistor and the second NMOS transistor are connected to the output of an OR gate, and the gates of the third PMOS transistor and the third NMOS transistor are connected to the corresponding read select signal terminals.

[0069] The number of NAND gates is equal to the number of columns of SRAM cells in the SRAM array, and each NAND gate corresponds to each write select signal terminal and each read select signal terminal column by column. By setting the above NAND gates, the conduction and cutoff of each column of discharge NMOS transistors can be controlled.

[0070] Preferably, the SRAM array of the SRAM chip provided in this embodiment is configured with 2 n There are 6T-SRAM cells, where n is an integer greater than or equal to 2.

[0071] On the one hand, it can match the encoding logic of binary addresses, which helps simplify decoder design and reduce circuit complexity; on the other hand, it facilitates memory expansion and modular design. At high frequency operation, 2 n The symmetrical and regular structure of each 6T-SRAM cell can reduce signal timing deviations.

[0072] Preferably, the MOS transistor and discharge NMOS transistor of the 6T-SRAM cell are fin field-effect transistors, and the manufacturing process precision of the fin field-effect transistor is at the 12-nanometer level.

[0073] Compared to planar metal-oxide-semiconductor field-effect transistors, FinFETs (Fin Field-Effect Transistors) can enhance gate control, achieve the same drive current at a lower operating voltage, and significantly reduce dynamic power consumption.

[0074] A manufacturing process precision of 12 nanometers refers to a device whose key feature dimensions are in the 12-nanometer range. This helps to increase integration density and storage capacity. For example, the fin width, gate length, and gate pitch of a fin field-effect transistor are between 10 and 15 nanometers.

[0075] Preferably, there are multiple column decoders, and the multiple column decoders share the write enable signal terminal, read enable signal terminal, write select signal terminal, and read select signal terminal.

[0076] On the one hand, it helps to improve parallel operation capabilities and increase data throughput; on the other hand, it helps to simplify control circuits and reduce wiring complexity.

[0077] Preferably, the column decoder is equipped with a multiplexer, which is used to select the write select signal terminal and the read select signal terminal corresponding to the target column 6T-SRAM cell.

[0078] The target column 6T-SRAM cell refers to the 6T-SRAM cell in the column where the third selection cell is located.

[0079] The function of a multiplexer is to share signal paths. Based on the switching logic of the multiplexer, multiple columns of 6T-SRAM cells can share signal lines. Only when a target column of 6T-SRAM cells is selected, the signal corresponding to the shared signal line is switched to the physical signal line corresponding to the target column. This helps reduce signal crosstalk and dynamic power consumption.

[0080] by Figure 4 Taking the SRAM chip shown as an example, a four-way multiplexer can be used to... Figure 4 The four columns of 6T-SRAM cells shown are used for 4-to-1 control.

[0081] In addition, this invention also provides an SRAM chip control method, wherein the SRAM chip is any of the above-mentioned SRAM chips equipped with a discharge NMOS transistor.

[0082] During the data writing phase, the write enable signal is set to high, the write select signal corresponding to the column where the 6T-SRAM select cell is located is set to low, and the word line corresponding to the row where the select cell is located is set to high. This controls the bit line and complementary bit line corresponding to the column where the select cell is located to write the target data into the select cell. Whether the target data is 0 or 1 is determined by the high or low level of the bit line.

[0083] During the data reading phase, the read enable signal is set to high level, the bit lines and complementary bit lines of the column where the selected cell is located are precharged to the power supply voltage, the read select signal corresponding to the column where the selected cell is located is set to low level, and the word line corresponding to the row where the selected cell is located is set to high level to read the data stored in the selected cell.

[0084] by Figure 4Taking the 6T-SRAM cell located in the first row and first column of the SRAM array in the SRAM chip shown as an example, which can be determined by word line WL0, bit line BL0 and bit line BLB0, as the third selection cell, the process of writing and reading data to the third selection cell will be explained next.

[0085] During the data writing phase, the write enable signal WE is set to high and the read enable signal RE is set to low, so that the GEN signal at the OR gate output is high. At this time, the gate control signal EN0 of the discharge NMOS transistor corresponding to the third selection unit is controlled by the write select signal YSWB0 and the read select signal YSR0. Taking writing 0 as an example, the bit line BL0 corresponding to the column where the third selection unit is located is preset to low, the complementary bit line BLB0 is kept high, the write select signal YSWB0 is set to low, and the word line WL0 corresponding to the row where the third selection unit is located is set to high. At this time, the discharge NMOS transistor, the first transmission transistor PG1, the first pull-down transistor PD1, the second transmission transistor PG2, and the second pull-down transistor PD2 corresponding to the third selection unit are turned on, which can write 0 to the third selection unit.

[0086] Subsequently, the other column selection signals YSWB1, YSR1, YSWB2, YSR2, YSWB3, and YSR3 of the column decoder remain high. Therefore, the gate control signals EN1, EN2, and EN3 of the discharge NMOS transistors corresponding to each WL half-select unit of the third selection unit are all low. The discharge path of each WL half-select unit is cut off due to the turn-off of its corresponding discharge NMOS transistor, and each WL half-select unit does not generate power loss. At the same time, the other word lines WL1, WL2, and WL3 of the row decoder remain low. Therefore, the first transmission transistor PG1 and the second transmission transistor PG2 of each BL half-select unit corresponding to the third selection unit are turned off, the discharge path of each BL half-select unit is cut off, and each BL half-select unit does not generate power loss. Combined with the discharge NMOS transistors corresponding to each BL half-select unit, leakage current can be sufficiently limited.

[0087] During the data reading phase, the write enable signal WE is set to low and the read enable signal RE is set to high, making the GEN signal at the OR gate output high. At this time, the gate control signal EN0 of the discharge NMOS transistor corresponding to the third selection unit is controlled by the write select signal YSWB0 and the read select signal YSR0. The bit line BL0 and complementary bit line BLB0 of the column where the third selection unit is located are precharged to the power supply voltage. The read select signal YSR0 is set to low, and the word line WL0 corresponding to the row where the third selection unit is located is set to high. At this time, the discharge NMOS transistor, the first transmission transistor PG1, the first pull-down transistor PD1, the second transmission transistor PG2, and the second pull-down transistor PD2 corresponding to the third selection unit are turned on, enabling the reading of the data stored in the third selection unit.

[0088] Continuing, if a 0 is read after writing a 0, a voltage drop occurs on the bit line BL0 corresponding to the third selection unit. However, the bit line BL0 corresponding to the third selection unit is connected to a sensitive amplifier, and the sensitive amplifier will immediately charge the bit line BL0 corresponding to the third selection unit after reading the result. Therefore, the voltage change of the bit line BL0 corresponding to the third selection unit is not significant.

[0089] Subsequently, when reading data from the third selection unit, the other column selection signals YSWB1, YSR1, YSWB2, YSR2, YSWB3, and YSR3 of the column decoder remain high. Therefore, as with writing data to the third selection unit, each WL half-select unit does not incur power loss. Simultaneously, the other word lines WL1, WL2, and WL3 of the row decoder remain low. Therefore, as with writing data to the third selection unit, each BL half-select unit does not incur power loss.

[0090] In summary, the SRAM chip control method provided in this embodiment ensures that neither the WL nor BL half-select units consume power during data writing or reading from the select unit. While significantly reducing the power consumption of the half-select units compared to related 6T-SRAM arrays and 8T-SRAM arrays, it also reduces memory area overhead and control timing complexity compared to 8T-SRAM arrays. This addresses the problem that related SRAM arrays struggle to simultaneously achieve low power consumption, low area overhead, and simple control timing.

[0091] Preferably, during the data retention phase, the write enable signal WE and the read enable signal RE are set to low level so that the GEN signal at the output of the OR gate is low level.

[0092] On the one hand, it can make full use of the signals present in the timing multiplexing circuit without increasing the design complexity of the circuit. The signals present in the timing multiplexing circuit include the write enable signal, read enable signal, write select signal, and read select signal of the column decoder.

[0093] On the other hand, it can reduce the power consumption of the half-select cell while ensuring that all discharge NMOS transistors are turned on during the data holding phase, providing a path for the charge leaked from the SRAM array of the above SRAM chip, and avoiding affecting the level transition inside each SRAM cell.

[0094] Furthermore, embodiments of the present invention also provide an electronic device including an SRAM chip, which is any of the aforementioned SRAM chips equipped with a discharge NMOS transistor. This solves the problem that related SRAM arrays struggle to simultaneously achieve low power consumption, low area overhead, and simple control timing.

[0095] It should be noted that the term "comprising" and its variations used in the embodiments of this invention are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The modifications of "one" and "a plurality" mentioned in the embodiments of this invention are illustrative and not restrictive, and those skilled in the art should understand that unless explicitly indicated otherwise in the context, they should be understood as "one or more". The descriptions of terms such as "first", "second", etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features.

[0096] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this invention are all information and data authorized by the user or fully authorized by all parties.

[0097] The steps described in the method embodiments provided by the present invention can be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of protection of the present invention is not limited in this respect.

[0098] The term "embodiment" in this specification refers to a specific feature, structure, or characteristic described in connection with an embodiment that may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily imply the same embodiment, nor does it imply independence or alternativeity from other embodiments. The various embodiments in this specification are described in a related manner, with reference to each other for similar or identical parts. In particular, for apparatus, device, and system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, and relevant details are referred to in the description of the method embodiments.

[0099] The above-described embodiments are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of protection. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. An SRAM chip, characterized in that, It includes a static random access memory (SRAM) array, a row decoder, and a column decoder; the row decoder is provided with word lines for each row of 6T-SRAM cells in the SRAM array, and the column decoder is provided with bit lines and complementary bit lines for each column of 6T-SRAM cells in the SRAM array. The ground terminal of each column of 6T-SRAM cells is grounded through a discharge NMOS transistor; the column decoder is provided with a write enable signal terminal, a read enable signal terminal, and an OR gate; the column decoder is provided with a read select signal terminal, a write select signal terminal, and a NAND gate for each column of 6T-SRAM cells; The write enable signal terminal and the read enable signal terminal are connected to the input terminal of the OR gate, and the output terminal of the OR gate is connected to the input terminal of each column of NAND gates; the input terminal of each column of NAND gates is also connected to the read select signal terminal and the write select signal terminal of the corresponding column, and the output terminal of each column of NAND gates is connected to the gate of the discharge NMOS transistor of the corresponding column. Specifically, if any one of the read select signal terminal, write select signal terminal, or OR gate output terminal corresponding to the third selection unit of the SRAM array is set to a low level, the discharge NMOS transistor corresponding to the third selection unit will be turned on; only when all three of the read select signal terminal, write select signal terminal, and OR gate output terminal corresponding to the third selection unit are at a high level will the discharge NMOS transistor corresponding to the third selection unit be turned off.

2. The SRAM chip according to claim 1, characterized in that, Each column of 6T-SRAM cells shares a common grounding NMOS transistor, or each 6T-SRAM cell is equipped with a separate grounding NMOS transistor.

3. The SRAM chip according to claim 1, characterized in that, The NAND gate includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor; The first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are connected in parallel through a common source and a common drain. The common source is connected to a power supply, and the common drain is connected to the gate of the corresponding discharge NMOS transistor and the drain of the first NMOS transistor. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the source of the second NMOS transistor is connected to the drain of the third NMOS transistor, and the source of the third NMOS transistor is grounded. The gates of the first PMOS transistor and the first NMOS transistor are connected to the corresponding write select signal terminals, the gates of the second PMOS transistor and the second NMOS transistor are connected to the output terminal of the OR gate, and the gates of the third PMOS transistor and the third NMOS transistor are connected to the corresponding read select signal terminals.

4. The SRAM chip according to claim 1, characterized in that, The SRAM array is configured with 2 n There are 6T-SRAM cells, where n is an integer greater than or equal to 2.

5. The SRAM chip according to claim 1, characterized in that, The MOS transistors of the 6T-SRAM cell and the discharge NMOS transistors are fin field-effect transistors, and the manufacturing process precision of the fin field-effect transistors is at the 12-nanometer level.

6. The SRAM chip according to claim 1, characterized in that, There are multiple column decoders, and the multiple column decoders share the write enable signal terminal, the read enable signal terminal, the write select signal terminal, and the read select signal terminal.

7. The SRAM chip according to claim 1, characterized in that, The column decoder is equipped with a multiplexer, which is used to select the write select signal terminal and the read select signal terminal corresponding to the target column 6T-SRAM cell.

8. A method for controlling an SRAM chip, characterized in that, The SRAM chip is the SRAM chip according to any one of claims 1 to 7; During the data writing phase, the write enable signal is set to high level, the write select signal corresponding to the column where the 6T-SRAM select unit is located is set to low level, and the word line corresponding to the row where the select unit is located is set to high level. This controls the bit line and complementary bit line corresponding to the column where the select unit is located, so as to write the target data into the select unit. During the data reading phase, the read enable signal is set to a high level, the bit lines and complementary bit lines of the column where the selection unit is located are pre-charged to the power supply voltage, the read select signal corresponding to the column where the selection unit is located is set to a low level, and the word line corresponding to the row where the selection unit is located is set to a high level to read the data stored in the selection unit.

9. The method according to claim 8, characterized in that, During the data retention phase, the write enable signal and the read enable signal are set to low level.

10. An electronic device comprising an SRAM chip, characterized in that, The SRAM chip is the SRAM chip according to any one of claims 1 to 7.

Images