Memory device, operation method and memory system

Abstract

The embodiment of the invention discloses a memory device, an operation method and a memory system. The memory device includes: a memory cell array; the memory cell array comprises a plurality of memory strings; each storage string comprises a plurality of storage units; each storage unit is configured to be one of a plurality of data states; a plurality of word lines, wherein each word line is coupled with the corresponding storage unit in each storage string; and a peripheral circuit coupled to the plurality of word lines, and configured to: execute a first verification operation, the first verification operation comprising: verifying the first type of memory cells coupled to the selected word line and the threshold voltage of the first type of memory cells reaching a first target threshold voltage when the verification is passed; and executing a second verification operation, the second verification operation comprising: verifying a second type of memory cell coupled to the selected word line, and when the verification is passed, the threshold voltage of the second type of memory cell is greater than a second target threshold voltage.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly to a memory device, an operating method, and a memory system. Background Art

[0002] Memory devices are used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) memory has become a mainstream product in the memory market due to its high storage density, manageable production costs, suitable programming and erasing speeds, and retention characteristics.

[0003] However, as people's requirements for storage devices continue to increase, there is still much room for improvement in memory devices and systems. Summary of the Invention

[0004] According to one aspect of an embodiment of the present application, a memory device is provided, including:

[0005] A memory cell array; the memory cell array includes a plurality of memory strings; each of the memory strings includes a plurality of memory cells; each memory cell is configured to be in one of a plurality of data states;

[0006] a plurality of word lines, each word line being coupled to a corresponding memory cell in each of the memory strings;

[0007] and a peripheral circuit coupled to the plurality of word lines, wherein the peripheral circuit is configured as follows:

[0008] performing a first verification operation, the first verification operation comprising: verifying a first type of memory cell coupled to a selected word line, wherein a threshold voltage of the first type of memory cell reaches a first target threshold voltage when the verification passes; wherein the first target threshold voltage is a threshold voltage corresponding to a first target data state to which the first type of memory cell is intended to be programmed; and the first target data state is one of the plurality of data states;

[0009] and performing a second verification operation, the second verification operation comprising: verifying a second type of memory cell coupled to the selected word line, and when the verification passes, a threshold voltage of the second type of memory cell is greater than a second target threshold voltage; wherein the second target threshold voltage is a threshold voltage corresponding to a second target data state to which the second type of memory cell is expected to be programmed; and the second target data state is also one of the multiple data states.

[0010] In the above solution, before performing the first verification operation and the second verification operation, the peripheral circuit is further configured as follows:

[0011] Applying a pass voltage to the selected word line; and applying a read voltage to word lines adjacent to the selected word line;

[0012] In response to a word line coupled memory cell adjacent to the selected word line in the first memory string being in an off state, determining that the memory cell coupled to the selected word line in the first memory string is of a first type;

[0013] In response to word line coupled memory cells adjacent to the selected word line in the second memory string being in a conductive state, it is determined that memory cells coupled to the selected word line in the second memory string are of a second type.

[0014] In the above solution, the word lines adjacent to the selected word line include: a first unselected word line and a second unselected word line; wherein the same read voltage is provided to the first unselected word line and the second unselected word line by the same voltage source.

[0015] In the above solution, the peripheral circuit is further configured to: perform the second verification operation using the increased target discharge time;

[0016] When a verification operation is performed on the second type of memory cell using the target discharge time, a threshold voltage of the second type of memory cell is equal to the second target threshold voltage.

[0017] In the above solution, when verification is passed, the threshold voltage of the second type of memory cell is less than the third target threshold voltage;

[0018] The third target threshold voltage is a threshold voltage corresponding to a next target data state adjacent to the second target data state among the multiple data states, and the second target threshold voltage is lower than the third target threshold voltage.

[0019] In the above solution, the peripheral circuit is further configured as follows:

[0020] performing a first programming operation to program each memory cell coupled to the selected word line to a corresponding intermediate data state;

[0021] and after each memory cell coupled to the selected word line is programmed to a corresponding intermediate data state, applying the pass voltage to the selected word line and applying the read voltage to word lines adjacent to the selected word line to divide the memory cells coupled to the selected word line into a first memory group and a second memory group;

[0022] The first storage group includes storage units of the first type; and the second storage group includes storage units of the second type.

[0023] In the above solution, the peripheral circuit is further configured as follows:

[0024] performing a second programming operation on the first type memory cells in the first memory group and performing the first verification operation so that the threshold voltage of each of the first type memory cells reaches the corresponding first target threshold voltage when the verification passes;

[0025] A third programming operation is performed on the first type memory cells in the second memory group, and the second verification operation is performed, so that the threshold voltage of each second type memory cell is greater than the corresponding second target threshold voltage when the verification passes.

[0026] In the above solution, the number of the intermediate data states is the same as the number of the multiple data states.

[0027] In the above solution, the second target threshold voltage is equal to, less than or greater than the first target threshold voltage.

[0028] In the above solution, the threshold voltage of the memory cells corresponding to the first memory group among the memory cells coupled to the word line adjacent to the selected word line is lower than the threshold voltage of the memory cells corresponding to the second memory group.

[0029] According to another aspect of an embodiment of the present application, a method for operating a memory device is provided, wherein each memory cell included in the memory device is configured to be in one of a plurality of data states; the method comprising:

[0030] performing a first verification operation, the first verification operation comprising: verifying a first type of memory cell coupled to a selected word line in the memory device, wherein upon successful verification, a threshold voltage of the first type of memory cell reaches a first target threshold voltage; wherein the first target threshold voltage is a threshold voltage corresponding to a first target data state to which the first type of memory cell is intended to be programmed;

[0031] and performing a second verification operation, the second verification operation comprising: verifying a second type of memory cell coupled to the selected word line in the memory device, wherein if the verification passes, a threshold voltage of the second type of memory cell is greater than a second target threshold voltage; wherein the second target threshold voltage is a threshold voltage corresponding to a second target data state to which the second type of memory cell is intended to be programmed;

[0032] The first target data state is one of the multiple data states; and the second target data state is also one of the multiple data states.

[0033] In the above solution, the operation method further includes:

[0034] Applying a pass voltage to the selected word line; and applying a read voltage to word lines adjacent to the selected word line;

[0035] In response to memory cells in a first memory string in the memory device being coupled to a word line adjacent to the selected word line being in a conductive state, determining that the memory cells in the first memory string coupled to the selected word line are of a first type;

[0036] In response to memory cells in a second memory string in the memory device coupled to a word line adjacent to the selected word line being in an off state, it is determined that the memory cells in the second memory string coupled to the selected word line are of a second type.

[0037] In the above solution, the word lines adjacent to the selected word line include: a first unselected word line and a second unselected word line; wherein the same read voltage is provided to the first unselected word line and the second unselected word line by the same voltage source.

[0038] In the above solution, the operation method further includes:

[0039] performing the second verification operation using the increased target discharge duration;

[0040] When a verification operation is performed on the second type of memory cell using the target discharge time, a threshold voltage of the second type of memory cell is equal to the second target threshold voltage.

[0041] In the above solution, the method further includes:

[0042] performing a first programming operation to program each memory cell coupled to the selected word line to a corresponding intermediate data state;

[0043] and after each memory cell coupled to the selected word line is programmed to a corresponding intermediate data state, applying the pass voltage to the selected word line and applying the read voltage to word lines adjacent to the selected word line to divide the memory cells coupled to the selected word line into a first memory group and a second memory group;

[0044] The first storage group includes storage units of the first type; and the second storage group includes storage units of the second type.

[0045] In the above solution, the method further includes:

[0046] performing a second programming operation on the first type memory cells in the first memory group and performing the first verification operation so that the threshold voltage of each of the first type memory cells reaches the corresponding first target threshold voltage when the verification passes;

[0047] A third programming operation is performed on the first type memory cells in the second memory group, and the second verification operation is performed, so that the threshold voltage of each second type memory cell is greater than the corresponding second target threshold voltage when the verification passes.

[0048] In the above solution, the number of the intermediate data states is the same as the number of the multiple data states.

[0049] In the above solution, the threshold voltage of the memory cells corresponding to the first memory group among the memory cells coupled to the word line adjacent to the selected word line is lower than the threshold voltage of the memory cells corresponding to the second memory group.

[0050] According to another aspect of the embodiments of the present application, a memory system is provided, comprising: one or more memory devices as described in any one of the above items and a memory controller coupled to and controlling the memory devices.

[0051] In the above solution, the memory system is included in a solid state drive (SSD) or a memory card.

[0052] Embodiments of the present application provide a memory device, an operating method, and a memory system. The memory device includes: a memory cell array; the memory cell array includes a plurality of memory strings; each of the memory strings includes a plurality of memory cells; each memory cell is configured to be in one of a plurality of data states; a plurality of word lines, each word line coupled to a corresponding memory cell in each of the memory strings; and a peripheral circuit coupled to the plurality of word lines, the peripheral circuit being configured to: perform a first verification operation, the first verification operation comprising: verifying a first type of memory cell coupled to a selected word line, wherein upon verification, a threshold voltage of the first type of memory cell reaches a first target threshold voltage; wherein the first target threshold voltage is a threshold voltage corresponding to a first target data state to which the first type of memory cell is intended to be programmed; the first target data state is one of the plurality of data states; and perform a second verification operation, the second verification operation comprising: verifying a second type of memory cell coupled to the selected word line, wherein upon verification, a threshold voltage of the second type of memory cell is greater than a second target threshold voltage; wherein the second target threshold voltage is a threshold voltage corresponding to a second target data state to which the second type of memory cell is intended to be programmed; the second target data state is also one of the plurality of data states. An embodiment of the present application provides a memory device that, during programming, divides memory cells coupled to a selected word line into two types: a first type and a second type. Furthermore, a first verification operation is performed on the first type memory cells, such that if verification passes, the threshold voltage of the first type memory cells is programmed to a first target threshold voltage. A second verification operation is performed on the second type memory cells, such that if verification passes, the threshold voltage of the second type memory cells programmed is greater than the second target threshold voltage. This improves the read window margin (RWM) of the memory device after placement. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In the accompanying drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like numerals with different letter suffixes may represent different instances of similar components. The accompanying drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0054] Figure 1 A schematic structural diagram of a memory device provided in an embodiment of the present application;

[0055] Figure 2 A schematic diagram of the connections between the peripheral circuits, word lines, and memory cell arrays provided in an embodiment of the present application;

[0056] Figure 3is a side view of a cross section of an exemplary memory cell array including NAND memory strings according to some aspects of the present application;

[0057] Figure 4 A schematic diagram of the organizational structure of a memory cell array provided in an embodiment of the present application;

[0058] Figure 5 A schematic diagram of the structure of a peripheral circuit provided in an embodiment of the present application;

[0059] Figure 6 A schematic diagram of the step programming pulse of the ISPP programming method provided in an embodiment of the present application;

[0060] Figure 7 A schematic diagram of a verification pulse for a verification operation provided in an embodiment of the present application;

[0061] Figure 8 A schematic diagram of a process for determining the type of a memory cell coupled to a selected word line according to an embodiment of the present application;

[0062] Figure 9 A schematic diagram of the threshold voltage distribution and Esum of a QLC type memory cell provided in one embodiment of the present application;

[0063] Figure 10 A schematic diagram of a flow chart for determining the channel state in a memory string according to an embodiment of the present application;

[0064] Figure 11 A schematic diagram of a voltage application method for determining and selecting a word line coupled memory cell as a first type memory cell or a second type memory cell according to an embodiment of the present application;

[0065] Figure 12 A flowchart of an operating method of a memory device provided in an embodiment of the present application;

[0066] Figure 13 A schematic diagram of the structure of a memory system provided in an embodiment of the present application;

[0067] Figure 14A Schematic diagram of an exemplary memory card with a memory system provided in an embodiment of the present application

[0068] Figure 14B A schematic diagram of an exemplary solid-state drive (SSD) having a memory system according to an embodiment of the present application. DETAILED DESCRIPTION

[0069] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to facilitate a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0070] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, to avoid confusion with the present application, certain technical features well known in the art are not described: that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0071] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0072] It should be understood that when an element or layer is referred to as being "on, "adjacent to, "connected to," "coupled to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be an intermediate element or layer. In contrast, when an element is referred to as being "directly on, "directly adjacent to, "directly connected to," or "directly coupled to" another element or layer, there may be no intermediate element or layer. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of this application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. When discussing a second element, component, region, layer or section, it does not necessarily mean that the first element, component, region, layer or section must be present.

[0073] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0074] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0075] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below with reference to the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0076] See also Figure 1 , which shows a schematic structural diagram of a memory device provided by an embodiment of the present application. Figure 1 As shown, the memory device 100 includes:

[0077] Memory cell array 101; the memory cell array includes a plurality of memory strings; each of the memory strings includes a plurality of memory cells; each memory cell is configured to be in one of a plurality of data states;

[0078] a plurality of word lines, each word line being coupled to a corresponding memory cell in each of the memory strings;

[0079] and a peripheral circuit 102 coupled to the plurality of word lines, wherein the peripheral circuit is configured as follows:

[0080] performing a first verification operation, the first verification operation comprising: verifying a first type of memory cell coupled to a selected word line, wherein a threshold voltage of the first type of memory cell reaches a first target threshold voltage when the verification passes; wherein the first target threshold voltage is a threshold voltage corresponding to a first target data state to which the first type of memory cell is intended to be programmed; and the first target data state is one of the plurality of data states;

[0081] and performing a second verification operation, the second verification operation comprising: verifying a second type of memory cell coupled to the selected word line, and when the verification passes, a threshold voltage of the second type of memory cell is greater than a second target threshold voltage; wherein the second target threshold voltage is a threshold voltage corresponding to a second target data state to which the second type of memory cell is expected to be programmed; and the second target data state is also one of the multiple data states.

[0082] It should be noted that the memory device 100 may refer to a device for storing programs and / or data, which may include peripheral circuits, word lines, and memory cell arrays.

[0083] For example, the connection relationship between the peripheral circuit, word line and memory cell array is as follows: Figure 2 See Figure 2 As shown, the memory device 100 may include a memory cell array 101 and peripheral circuits 102 coupled to the memory cells 101 via word lines, wherein the memory cell array 101 may be a NAND flash memory array, wherein the memory cells 206 are provided in the form of an array of NAND memory strings 208, each NAND memory string 208 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 208 includes a plurality of memory cells 206 coupled in series and stacked vertically. Each memory cell 206 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the storage region of the memory cell 206. Each memory cell 206 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0084] In some embodiments, each memory cell 206 is a single-level cell (SLC) having two possible data states and thus storing one bit of data. For example, a first data state "0" may correspond to a first voltage range, and a second data state "1" may correspond to a second voltage range. In some embodiments, the first voltage range and the second voltage range may be referred to as a threshold voltage distribution of the memory cell. In some embodiments, each memory cell 206 may be a multi-level cell (MLC). For example, an MLC may store two bits per cell (also known as a double-level cell (DLC); for another example, store three bits per cell (also known as a tri-level cell (TLC); or for another example, store four bits per cell (also known as a quadruple-level cell (QLC)). Regardless of the type of memory cell, the data state includes an erased state and (one or more) programmed states. When a programming operation is performed on the memory cell, the memory cell is programmed from the erased state to a certain programmed state. Generally speaking, the voltage value in the voltage range corresponding to the programmed state of the memory cell is relatively large, and the voltage in the voltage range corresponding to a higher programming state (or referred to as a threshold voltage distribution) is larger.

[0085] like Figure 2As shown, each NAND string 208 may include a source select gate (SSG) 210 at its source terminal and a drain select gate (DSG) 212 at its drain terminal. The SSG 210 and DSG 212 may be configured to activate a selected NAND string 208 (column of the array) during read and program (or write) operations. In some embodiments, the sources of the NAND strings 208 in the same memory block 204 are coupled via the same source line (SL) 214 (e.g., a common SL). In other words, according to some embodiments, all NAND strings 208 in the same memory block 204 have an array common source (ACS). According to some embodiments, the DSG 212 of each NAND string 208 is coupled to a corresponding bit line 216, from which data can be read and written via an output bus (not shown). In some embodiments, each NAND memory string 208 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having DSG 212) or a deselect voltage (e.g., 0 volts (V)) to the corresponding DSG 212 via one or more drain select lines (Drain Selective Line) or top select lines (Top Selective Line) 213 and / or applying a select voltage (e.g., higher than the threshold voltage of the transistor having SSG 210) or a deselect voltage (e.g., 0 V) ​​to the corresponding SSG 210 via one or more source select lines (Source Selective Line) or bottom select lines (Bottom Selective Line) 215.

[0086] like Figure 2 As shown, the NAND memory string 208 can be organized into a plurality of memory blocks 204, each of which can have a common source line 214 (e.g., coupled to ground). In some embodiments, each memory block 204 is a basic data unit with an erase operation, that is, all memory cells 206 on the same memory block 204 are erased at the same time. In order to erase the memory cells 206 in the selected memory block 204, the source lines 214 coupled to the selected memory block 204 and the unselected memory blocks 204 in the same plane (Plane) as the selected memory block 204 can be biased with an erase voltage (Vers) (e.g., a high positive voltage of 20V or higher). It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of blocks or any suitable fraction of blocks. As shown in FIG. Figure 2 As shown, the memory cells 206 of adjacent NAND memory strings 208 can be coupled via word lines 218 , that is, the same word line 218 can be coupled to memory cells at the same position (ie, corresponding memory cells) in multiple memory strings.

[0087] Figure 3 1 shows a side view of a cross section of an exemplary memory cell array 101 including NAND memory strings 208 according to some aspects of the present application. Figure 3 As shown in FIG, NAND memory string 208 may include a stacked structure 310, which includes multiple gate layers 311 and multiple insulating layers 312 that are alternately stacked in sequence, and a memory string 208 that vertically penetrates the gate layers 311 and the insulating layers 312. The gate layers 311 and the insulating layers 312 may be alternately stacked, with two adjacent gate layers 311 separated by a layer of insulating layer 312. The number of pairs of gate layers 311 and insulating layers 312 in the stacked structure 310 may determine the number of memory cells included in the memory cell array 101.

[0088] The gate layer 311 may be formed of a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 311 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 311 includes a doped polysilicon layer. Each gate layer 311 may include a control gate surrounding a memory cell. The gate layer 311 at the top of the stacked structure 310 can extend laterally to serve as an upper select gate line 313, also known as a TSG line 213. The upper select gate line 313 is also the lead line of the upper select gate (TSG) 212 described above, which is used to connect to the corresponding select voltage or cancel voltage. The gate layer 311 at the bottom of the stacked structure 310 can extend laterally to serve as a lower select gate line 314, also known as a source select line (source selective line or bottom select line) 215. The lower select gate line 314 is also the lead line of the lower select gate (BSG) 310 described above, which is used to connect to the corresponding select voltage or cancel voltage. The gate layer 311 extending laterally between the upper select gate line and the lower select gate line can serve as a word line layer 303. These word line layers 303 are also the word lines 218 described above.

[0089] In some embodiments, the stacked structure 310 may be disposed on a substrate 301. The substrate 301 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0090] In some embodiments, NAND memory string 208 includes a channel structure extending vertically through stacked structure 310. In some embodiments, the channel structure includes a channel hole filled with one or more semiconductor materials (e.g., serving as a semiconductor channel) and one or more dielectric materials (e.g., serving as a memory film). In some embodiments, the semiconductor channel includes silicon, such as polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). In some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0091] Front Figure 2 and Figure 3 The positional relationship between word lines, bit lines, and memory cells contained in the memory cell array in the memory device is shown in detail. From a product perspective, a memory device, such as NAND flash memory, may include several flash memory chips; each flash memory chip includes several die (DIE) (or LUN). Each DIE includes: peripheral circuits and a memory cell array, wherein the memory cell array includes several storage planes (Plane); each Plane includes several storage blocks (Block) 204; each storage block includes several storage pages (Page). For example, Figure 4 As shown, it shows a schematic diagram of the internal structure of the NAND flash memory chip provided according to an embodiment of the present application. Figure 4 In the embodiment, the flash memory chip 400 includes: DIE0 and DIE1, wherein DIE0 and DIE1 each include two storage planes (such as Plane0 and Plane1); each Plane includes multiple storage blocks (such as Block0 to Block1023); each storage block includes multiple storage pages (such as Page0 to Page255).

[0092] It should be noted that Figure 4 The structure is only an example. In actual use, the number of DIEs, Planes, Blocks, and Pages included in the storage cell array can be designed according to actual conditions.

[0093] Return Reference Figure 2, the peripheral circuit 102 may be coupled to the memory cell array 101 via the bit lines 216, word lines 218, source lines 214, SSG lines 215, and DSG lines 213. The peripheral circuit 102 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 101 by applying a voltage signal and / or a current signal to each target memory cell 206 and sensing a voltage signal and / or a current signal from each target memory cell 206 via the bit lines 216, word lines 218, source lines 214, SSG lines 215, and DSG lines 213. The peripheral circuit 102 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuits are shown, and the peripheral circuit 102 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, the peripheral circuit 102 may also include Figure 5 Additional circuitry not shown.

[0094] Specifically, the page buffer / sense amplifier 504 can be configured to read data from the memory cell array 101 and program (write) data to the memory cell array 101 based on control signals from the control logic 512. In one example, the page buffer / sense amplifier 504 can store program data (or write data) to be programmed into the memory cells coupled to a word line in the memory cell array 101. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 206 coupled to the selected word line 218. In yet another example, the page buffer / sense amplifier 504 can also sense low-power signals from the bit line 216 representing the data bits stored in the memory cell 206 and amplify small voltage swings to recognizable logic levels during a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and select one or more NAND memory strings 208 by applying bit line voltages generated by the voltage generator 510.

[0095] The row decoder / word line driver 508 can be configured to be controlled by the control logic 512 and to select / deselect the memory block 204 of the memory cell array 101 and to select / deselect the word line 218 of the memory block 204. The row decoder / word line driver 508 can also be configured to drive the word line 218 using the word line voltage generated from the voltage generator 510 so that the memory cell coupled to the word line 218 performs a program operation, a read operation, or an erase operation. The voltage generator 510 can be configured to be controlled by the control logic 512 and to generate the word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verify voltage, etc.), the bit line voltage, and the source line voltage to be supplied to the memory cell array 101. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive the SSG line 215 and the DSG line 213.

[0096] In some specific embodiments, the programming operation may include multiple phases. For example, the programming operation may include a channel precharge phase, a channel boost phase, a programming pulse phase, and a recovery phase. During the channel precharge phase, a voltage generator may generate voltages required for the subsequent phase, such as voltages applied to each gate and a channel boost voltage. During the channel boost phase, a channel boost voltage may be applied to the selected word line. During the programming pulse phase, a target voltage for each programming operation may be applied to the selected word line. During the recovery phase, the voltage of both the unselected and selected word lines may be reduced to a corresponding lower voltage, such as Vcc or Vdd. During the recovery phase, the voltage may be reduced to the corresponding voltage in one or more steps, such as by first reducing the voltage to an intermediate voltage and maintaining it at the intermediate voltage for a period of time before finally reducing the voltage to the corresponding voltage.

[0097] Among them, the control logic 512 can be coupled to each circuit described above and is configured to control the operation of each peripheral circuit. The register 514 can be coupled to the control logic 512 and includes a status register, a command register, and an address register for storing status information, command operation code (OP code), and command address for controlling the operation of each peripheral circuit. The interface 516 can be coupled to the control logic 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, as well as buffer status information received from the control logic 512 and relay it to the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data I / O interface and data buffer to buffer data and relay it to the memory cell array 101 or relay or buffer data from the memory cell array 101.

[0098] In this application, the memory blocks, memory strings, memory cells, peripheral circuits, word lines and the connections between them can refer to the previous Figures 2 to 5 As shown, in order to save space, it will not be repeated here. This application focuses on the improvement of some operations for programming memory cells. That is, the peripheral circuit is configured to: perform a first verification operation on a first type of memory cell coupled to a selected word line, and when the verification passes, the threshold voltage of the first type of memory cell reaches a first target threshold voltage; perform a second verification operation on a second type of memory cell coupled to a selected word line, and when the verification passes, the threshold voltage of the second type of memory cell is greater than a second target threshold voltage. Wherein, the first target threshold voltage is the threshold voltage corresponding to the first target data state to which the first type of memory cell is expected to be programmed; the first target data state is one of the multiple data states; the second target threshold voltage is the threshold voltage corresponding to the second target data state to which the second type of memory cell is expected to be programmed; the second target data state is also one of the multiple data states.

[0099] Here, the multiple data states mentioned here can be the data states corresponding to one of the aforementioned SLC, DLC, TLC, and QLC, for example, SLC corresponds to 2 data states; DLC corresponds to 4 data states; TLC corresponds to 8 data states; and QLC corresponds to 16 data states. The first target data state mentioned here can be one of the multiple data states; the second target data state mentioned here can also be one of the multiple data states. Moreover, since the first verification operation and the second verification operation are two types of verifications, they do not limit the data states configured by the corresponding storage cells. Therefore, the first target data state and the second target data state can be the same or different. The first target threshold voltage can be a voltage value in the threshold voltage distribution corresponding to the first target data state. The second target threshold voltage can be a voltage value in the threshold voltage distribution corresponding to the second target data state. If the first target data state and the second target data state are not the same data state, then the first target threshold voltage and the second target threshold voltage are not equal. If the first target data state and the second target data state are the same data state, then, based on the threshold voltage distribution corresponding to a certain data state as described above, which is a voltage range, programming is successful as long as the threshold voltage of the programmed memory cell is programmed to any voltage value in the threshold voltage distribution corresponding to the data state. Therefore, the first target threshold voltage and the second target threshold voltage can be equal to or different. More specifically, the second target threshold voltage is equal to, less than, or greater than the first target threshold voltage.

[0100] The memory cells are usually programmed using Incremental Step Pulse Programming (ISPP), where the so-called ISPP can be based on a step voltage to gradually increase the word line bias voltage while programming multiple memory cells (or a page) several times. pgm For reference Figure 6 . That is, the programming pulse applied to the word line coupled to the programmed memory cell is gradually increased in a certain increment until the programmed memory cell is programmed to the target data state or the programming fails. It should be noted that applying a programming pulse once can be called a programming loop (PGM Loop). During the programming of the memory cell, in order to understand whether the programmed memory cell is programmed to the target data state, a verification operation (verify) is added between the application of two programming pulses to determine whether the programmed memory cell is programmed to the target data state. Among them, the programming operation and the verification operation can be performed alternately, or the verification operation can be performed after applying multiple programming pulses according to actual conditions. The verification operation can be one or a group of verification voltage pulses, and the verification voltage pulse is such as Figure 7 As shown, Figure 7 701 and 703 are step programming pulses V pgm 702 is a verification voltage pulse. The first verification operation and the second verification operation here are also described as verify. In order to save space, the basic description of the corresponding verification operations is not repeated.

[0101] In order to determine whether the memory cell coupled to the selected word line belongs to the first type or the second type, in some embodiments, as Figure 8 As shown, before performing the first verification operation and the second verification operation, the peripheral circuit may further be configured as follows:

[0102] Applying a pass voltage to the selected word line; and applying a read voltage to word lines adjacent to the selected word line;

[0103] In response to a word line coupled memory cell adjacent to the selected word line in the first memory string being in an off state, determining that the memory cell coupled to the selected word line in the first memory string is of a first type;

[0104] In response to word line coupled memory cells adjacent to the selected word line in the second memory string being in a conductive state, it is determined that memory cells coupled to the selected word line in the second memory string are of a second type.

[0105] It should be noted that before programming the memory cells coupled to the selected word line, in order to determine whether each of these memory cells belongs to the first type or the second type, the peripheral circuit is configured such that: a pass voltage is applied to the selected word line, and a read voltage is applied to the word lines adjacent to the selected word line. The word lines adjacent to the selected word line can be as follows: Figure 2 The word lines of the memory cells above and below the selected word line are shown. Figure 2 As shown, assuming the selected word line is word line 218a; the word lines adjacent to the selected word line may be word lines 218b and word line 218b'. In the memory cells in the same memory string 208, the memory cells coupled to the selected word line are in a conductive state due to the applied pass voltage. If the memory cells coupled to the word lines adjacent to the selected word line are in a conductive state due to the read voltage, the memory cells coupled to the selected word line are determined to be of the first type. If the memory cells coupled to the word lines adjacent to the selected word line are still in an off state due to the read voltage, the memory cells coupled to the selected word line are determined to be of the second type. The memory cells coupled to the selected word line in the same memory string are either of the first type or the second type. That is, in response to the word line coupled memory cells adjacent to the selected word line in the first memory string being in the off state, the memory cells coupled to the selected word line in the first memory string are determined to be of the first type; in response to the word line coupled memory cells adjacent to the selected word line in the second memory string being in the on state, the memory cells coupled to the selected word line in the second memory string are determined to be of the second type. Based on the above description of the relationship between memory strings, word lines, and memory cells, each word line corresponds to a memory cell in each memory string. Therefore, the first memory string and the second memory string are two different memory strings.

[0106] It should be understood that in addition to applying a pass voltage to the selected word line and applying a read voltage to the word lines adjacent to the selected word line, other word lines should also be applied with a pass voltage so that the type of the memory cell coupled to the selected word line can be determined based on the read voltage.

[0107] In actual application, the word lines adjacent to the selected word line may include one or two. Figure 2 As shown in FIG. 218b, there is only one word line 218a adjacent to word line 218b. Figure 2 As shown, the word lines adjacent to the word line 218 a include two word lines. In some embodiments, the word lines adjacent to the selected word line include: word line 218 b and word line 218 b ′.

[0108] When the word line adjacent to the selected word line can include one, only one read voltage is required.

[0109] In some embodiments, the word lines adjacent to the selected word line may include two, for example, the word lines adjacent to the selected word line include: a first non-selected word line and a second non-selected word line; wherein the same read voltage is provided to the first non-selected word line and the second non-selected word line through the same voltage source.

[0110] That is, the same read voltage is provided to the first unselected word line and the second unselected word line through the same voltage source. This allows for simultaneous acquisition of the threshold voltage states of the memory cells coupled to the two word lines adjacent to the selected word line during a single read operation, and further, to determine whether the memory cells coupled to the two unselected word lines adjacent to the selected word line are in a conductive or OFF state, thereby determining the type of the memory cells coupled to the selected word line. As described above, the memory cells coupled to the selected word line and the memory cells coupled to the other word lines are in a conductive state due to the pass voltage. If the memory cells coupled to the two unselected word lines adjacent to the selected word line are in a conductive state, the channel of the entire memory string is open; if the memory cells coupled to the two unselected word lines adjacent to the selected word line are in an OFF state, the channel of the entire memory string is closed. When the channel of a certain storage string is opened, it is determined that the threshold voltages of the storage cells coupled to the two word lines adjacent to the selected word line are both low. It is necessary to program the storage cells coupled to the selected word line to compensate for the threshold voltage, so that the Esum of the storage cells in the early and late stages of their lifespan is improved after high-temperature accelerated placement. Among them, the read window margin (RWM) is an important parameter for correctly reading the data of the storage cells. In some embodiments, the RWM of the storage cells configured to correspond to multiple data states includes multiple readable distributions, and the sum of these multiple readable distributions can be called the edge sum (Esum, Edge summary), wherein each readable distribution Ei can be a voltage range that can be used to read the data on the storage cell in a certain data state. Wherein, i is an integer greater than or equal to 0.

[0111] For example, Figure 9 As shown, it shows a schematic diagram of Esum in a QLC type storage unit. Figure 9In the figure, for QLC type storage cells, the total readable distribution can include: E0, E1, ..., E29, a total of 30 readable distributions, which can be written as: Esum = E0 + E1 + ... + E29. Among them, E0 is the first readable distribution, which is the voltage interval between the lower tail of the threshold voltage distribution corresponding to the data state P0 and the voltage Vr1 (read voltage), which is the voltage interval that can be used to read the data on the storage cell in the erased state. E1 is the second readable distribution, which is the voltage area for reading the data on the storage cell in the P1 state. It is the voltage interval between the minimum voltage value of the threshold voltage distribution corresponding to the data state P0 and the voltage Vr1 (read voltage). The understanding of other readable distributions is similar.

[0112] In some embodiments, the peripheral circuit may be further configured to: perform the second verification operation using an increased target discharge time;

[0113] When a verification operation is performed on the second type of memory cell using the target discharge time, a threshold voltage of the second type of memory cell is equal to the second target threshold voltage.

[0114] It should be noted that the target discharge duration is increased to verify the second type of memory cell coupled to the selected word line, so that the threshold voltage of the second type of memory cell is greater than the second target threshold voltage when verification passes. The target discharge duration is the discharge duration required to bring the threshold voltage of the second type of memory cell to the second target threshold voltage during the verification operation on the second type of memory cell. In other words, a longer discharge duration is used on the original basis to ensure that the threshold voltage of the second type of memory cell is greater than the second target threshold voltage when verification passes.

[0115] In some embodiments, when verification passes, the threshold voltage of the second type of memory cell is less than a third target threshold voltage;

[0116] The third target threshold voltage is a threshold voltage corresponding to a next target data state adjacent to the second target data state among the multiple data states, and the second target threshold voltage is lower than the third target threshold voltage.

[0117] It should be noted that what is described here is that after the second type of memory cell is successfully programmed, its threshold voltage increases and is greater than the second target threshold voltage, but cannot be greater than the third target threshold voltage corresponding to the next target data state.

[0118] For example, assuming that the multiple data states include: P0, P1, P2, P3, P4, P5, P6, and P7, where P0 is an erased state and the remaining programmed states have threshold voltage distributions with increasing voltages in order, if the second target data state is P2, then after the second verification operation is performed, the threshold voltage of the second type of memory cell is greater than the voltage value in the threshold voltage distribution corresponding to P2, but less than the voltage value in the threshold voltage distribution corresponding to P3.

[0119] In some embodiments, the peripheral circuit may further be configured as follows:

[0120] performing a first programming operation to program each memory cell coupled to the selected word line to a corresponding intermediate data state;

[0121] and after each memory cell coupled to the selected word line is programmed to a corresponding intermediate data state, applying the pass voltage to the selected word line and applying the read voltage to word lines adjacent to the selected word line to divide the memory cells coupled to the selected word line into a first memory group and a second memory group;

[0122] The first storage group includes storage units of the first type; and the second storage group includes storage units of the second type.

[0123] In some embodiments, the peripheral circuit may further be configured as follows:

[0124] performing a second programming operation on the first type memory cells in the first memory group and performing the first verification operation so that the threshold voltage of each of the first type memory cells reaches the corresponding first target threshold voltage when the verification passes;

[0125] A third programming operation is performed on the first type memory cells in the second memory group, and the second verification operation is performed, so that the threshold voltage of each second type memory cell is greater than the corresponding second target threshold voltage when the verification passes.

[0126] It should be noted that when programming employs multi-programming, in a non-final programming pass (also known as coarse programming), each memory cell coupled to the selected word line is first programmed to a corresponding intermediate data state. Then, based on the determination of whether a memory cell belongs to the first type or the second type, the memory cells coupled to the selected word line that are programmed to the intermediate data state are divided into two memory groups: a first memory group comprising first-type memory cells and a second memory group comprising second-type memory cells. A final programming pass is then performed, and in the final programming pass (fine programming), different programming operations are applied to memory cells in different memory groups: a third programming operation and a fourth programming operation; and different verification operations are applied to memory cells in different memory groups: a third programming operation and a fourth programming operation, a first verification operation, and a second verification operation, to achieve different threshold voltages. In other words, the classification of memory cells during coarse programming guides the subsequent fine programming.

[0127] The number of the intermediate data states is the same as the number of the multiple data states.

[0128] For example, in the 16-16 double-side programming corresponding to QLC, the first 16 refers to 16 intermediate data states, and the second 16 refers to 16 target data states (i.e., multiple data states). For another example, the 8-8 double-side programming corresponding to TLC can be understood in the same way and will not be repeated here.

[0129] In some embodiments, a threshold voltage of memory cells corresponding to the first memory group among memory cells coupled to a word line adjacent to the selected word line is lower than a threshold voltage of memory cells corresponding to the second memory group.

[0130] It should be noted that, based on the previous description, after the pass voltage is applied to the selected word line and the read voltage is applied to the word line adjacent to the selected word line, when the channel of a certain storage string is opened, it is judged that the threshold voltages of the storage cells coupled to the two word lines adjacent to the selected word line are both low; when the channel of a certain storage string is turned off, it is judged that the threshold voltages of the storage cells coupled to the two word lines adjacent to the selected word line are both high, that is, the threshold voltage of the storage cells corresponding to the first storage group among the storage cells coupled to the word line adjacent to the selected word line is lower than the threshold voltage of the storage cells corresponding to the second storage group.

[0131] In order to understand this application, Figure 10 and Figure 11 As shown, Figure 10 A schematic diagram illustrating a flow chart of determining a channel state in a memory string according to an embodiment of the present application is shown; Figure 11 A schematic diagram illustrating a voltage application method for determining and selecting whether a word line coupled memory cell belongs to a first type memory cell or a second type memory cell according to an embodiment of the present application is shown.

[0132] like Figure 10 As shown, before programming and verifying the memory cells coupled to the selected word line, the upper and lower layers (i.e., selected) of the programming WL (i.e., the selected word line) are read, and a certain vrd voltage (i.e., read voltage) is applied to the upper and lower layers at the same time to detect the channel turn on / off state. When the channel state is turned on, the verification threshold voltage of the memory cell corresponding to the programming WL in the channel is set higher than that of other memory cells in the channel. Figure 10 As shown, this method of applying vrd to the upper and lower layers at the same time can accurately find the LL group of memory cells, and then make additional compensation for their programming target threshold voltage. It should be noted that Figure 10 and Figure 11 The description is merely made by taking the eight data states corresponding to the TLC as an example.

[0133] During programming, a memory device provided by an embodiment of the present application divides memory cells coupled to a selected word line into two types: a first type and a second type. A first verification operation is performed on the first type memory cells, so that if verification passes, the threshold voltage of the first type memory cells is programmed to a first target threshold voltage. A second verification operation is performed on the second type memory cells, so that if verification passes, the threshold voltage of the second type memory cells programmed is greater than the second target threshold voltage. This improves the read window margin of the memory device after placement.

[0134] like Figure 12 According to another aspect of an embodiment of the present application, a method for operating a memory device is provided, wherein each memory cell included in the memory device is configured to be in one of a plurality of data states; the method may include:

[0135] performing a first verification operation, the first verification operation comprising: verifying a first type of memory cell coupled to a selected word line in the memory device, wherein upon successful verification, a threshold voltage of the first type of memory cell reaches a first target threshold voltage; wherein the first target threshold voltage is a threshold voltage corresponding to a first target data state to which the first type of memory cell is intended to be programmed;

[0136] and performing a second verification operation, the second verification operation comprising: verifying a second type of memory cell coupled to the selected word line in the memory device, wherein if the verification passes, a threshold voltage of the second type of memory cell is greater than a second target threshold voltage; wherein the second target threshold voltage is a threshold voltage corresponding to a second target data state to which the second type of memory cell is intended to be programmed;

[0137] The first target data state is one of the multiple data states; and the second target data state is also one of the multiple data states.

[0138] In some embodiments, the operating method further includes:

[0139] Applying a pass voltage to the selected word line; and applying a read voltage to word lines adjacent to the selected word line;

[0140] In response to memory cells in a first memory string in the memory device being coupled to a word line adjacent to the selected word line being in a conductive state, determining that the memory cells in the first memory string coupled to the selected word line are of a first type;

[0141] In response to memory cells in a second memory string in the memory device coupled to a word line adjacent to the selected word line being in an off state, it is determined that the memory cells in the second memory string coupled to the selected word line are of a second type.

[0142] In some embodiments, the word lines adjacent to the selected word line include: a first unselected word line and a second unselected word line; wherein the same read voltage is provided to the first unselected word line and the second unselected word line by the same voltage source.

[0143] In some embodiments, the operating method further includes:

[0144] performing the second verification operation using the increased target discharge duration;

[0145] When a verification operation is performed on the second type of memory cell using the target discharge time, a threshold voltage of the second type of memory cell is equal to the second target threshold voltage.

[0146] In some embodiments, the method further comprises:

[0147] performing a first programming operation to program each memory cell coupled to the selected word line to a corresponding intermediate data state;

[0148] and after each memory cell coupled to the selected word line is programmed to a corresponding intermediate data state, applying the pass voltage to the selected word line and applying the read voltage to word lines adjacent to the selected word line to divide the memory cells coupled to the selected word line into a first memory group and a second memory group;

[0149] The first storage group includes storage units of the first type; and the second storage group includes storage units of the second type.

[0150] In some embodiments, the method further comprises:

[0151] performing a second programming operation on the first type memory cells in the first memory group and performing the first verification operation so that the threshold voltage of each of the first type memory cells reaches the corresponding first target threshold voltage when the verification passes;

[0152] A third programming operation is performed on the first type memory cells in the second memory group, and the second verification operation is performed, so that the threshold voltage of each second type memory cell is greater than the corresponding second target threshold voltage when the verification passes.

[0153] In some embodiments, the number of the intermediate data states is the same as the number of the plurality of data states.

[0154] In some embodiments, a threshold voltage of memory cells corresponding to the first memory group among memory cells coupled to a word line adjacent to the selected word line is lower than a threshold voltage of memory cells corresponding to the second memory group.

[0155] It should be noted that this operating method is based on the operation of the memory device described above. The operation of the memory device has been described in detail above. Therefore, the nouns and features appearing in this operating method have been described above and will not be repeated here to save space.

[0156] See also Figure 13 According to another aspect of an embodiment of the present application, a memory system 1300 is provided, comprising: one or more memory devices 1301 as described in any one of the above items and a memory controller 1302 coupled to and controlling the memory device.

[0157] In some embodiments, the memory system is contained in a solid state drive (SSD) or a memory card.

[0158] It should be noted that the memory system 1300 can communicate with the host. The host and / or the memory system 1300 can be included in various products, such as Internet of Things (IoT) devices, such as refrigerators or other devices, sensors, motors, mobile communication devices, cars, unmanned driving, etc., to support product processing, communication or control. In one embodiment, the memory system 1300 can be a discrete memory or memory component of the host device. In other embodiments, the memory system 1300 can also be part of an integrated circuit, such as part of a system on chip (SOC). At this time, the memory system 1300 is stacked or otherwise assembled with one or more components of the host. In other embodiments, the aforementioned memory system can be implemented and packaged in products such as memory cards, drives, etc., such as Figure 14A and Figure 14B As shown, Figure 14A A schematic diagram illustrating an exemplary memory card having a memory system according to aspects provided herein; Figure 14B Schematic diagram of an exemplary solid-state drive (SSD) having a memory system according to some aspects of the present invention is shown. Figure 14A In one example shown in FIG, a memory controller 1302 and a single memory device 1301 of a memory system may be integrated into a memory card 140. The memory card 140 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMC micro), an SD card (SD, mini SD, micro SD, SDHC), a UFS, etc. The memory card 140 may also include a memory card connector 1401 for coupling the memory card 140 to a host. Figure 14B In another example shown in , the memory controller 1302 and the plurality of memory devices 1301 can be integrated into the SSD 141. The SSD 141 can also include an SSD connector 1411 for coupling the SSD 141 to the host. In some embodiments, the storage capacity and / or operating speed of the SSD 141 is greater than the storage capacity and / or operating speed of the memory card 140.

[0159] In some embodiments, the host described above may include a processor and a host RAM, wherein the host RAM may include DRAM, SDRAM, or any other suitable volatile or non-volatile memory device. The memory system 1300 may be provided with one or more communication interfaces to communicate with one or more components in the host. The one or more components in the host may be a Serial Advanced Technology Attachment (SATA) interface, a high-speed peripheral component interconnect (PCIe) interface, a Universal Serial Bus (USB) interface, a Universal Flash Storage (UFS) interface, an eMMC TM interface, etc. The host may also include electronic components, a memory card reader, or one or more other electronic components external to the memory system 1300.

[0160] In some embodiments, the memory controller 1302 can receive instructions from the host and communicate with the memory device 1301. For example, the memory controller 1302 can execute write or erase instructions to transfer data to one or more memory cells, planes, sub-blocks, blocks, or pages in the memory device 1301, or the memory controller 1302 can execute read instructions to transfer data to the host. In hardware, the memory controller 1302 may include one or more controller units, circuits, or components configured to control access across the memory device 1301 and provide a translation layer between the host and the memory system 1300. The memory controller 1302 may also include one or more input / output (I / O) circuits, lines, or interfaces to transfer data to or from the memory device 1301. The memory controller 1302 may also include a memory management unit and an array control unit. The memory management unit may include circuit hardware or firmware, such as multiple components or integrated circuits associated with various memory management functions. Taking NAND memory as an example, memory system operation or management functions are described. Those skilled in the art will appreciate that other forms of non-volatile memory may have similar memory operation or management functions. NAND memory management functions may include wear leveling, such as garbage collection or reclamation, error detection or correction, block retirement, or one or more other memory management functions. The memory management unit may process host instructions into commands recognizable by the memory system 1300, such as parsing or formatting instructions received from the host into commands related to the operation of the memory device 1301. Alternatively, the memory management unit may generate device commands for the array control unit or one or more other components of the memory system 1300, such as commands that implement various memory management functions. The memory management unit may be configured to include a set of management tables for maintaining various information associated with one or more components of the memory system 1300, such as various information related to a memory cell array or one or more memory cells coupled to the memory controller 1302. For example, the management tables may include information such as block age, block erase count, error history, or one or more error counts of one or more blocks of memory cells coupled to the memory controller 1302. Error counts may include operation error counts, read bit error counts, and the like. In some embodiments, if the detected error count exceeds a certain threshold, the bit error is considered uncorrectable. In some embodiments, the management table may maintain counts of correctable or uncorrectable bit errors, among other things. The management table may also include one or more L2P tables, each containing one or more L2P pointers that associate a logical address with a physical address at the memory device 1301. In some embodiments, the management table may include an unencrypted L2P table and / or an encrypted L2P table.The unencrypted L2P table may include L2P pointers indicating unencrypted logical addresses and unencrypted physical addresses; the encrypted L2P table may include encrypted physical addresses and encrypted L2P pointers indicating unencrypted logical addresses. In actual implementation, the management table may be stored in the memory management unit, meaning that the management table may be stored in the RAM of the memory controller 1302. In other embodiments, the management table may also be stored in the memory device 1301. During use, the memory management unit may read part or all of the cached management table from the RAM of the memory controller 1302; alternatively, the management table may be read from the memory device 1301.

[0161] The array control unit may include circuit systems or components configured to control and complete the following memory device operations, such as controlling the writing of data to one or more memory cells in the memory system 1300 coupled to the memory controller 1302, reading data from the one or more memory cells, or erasing the one or more memory cells. The array control unit may receive commands sent by the host or host commands generated internally by the memory management unit. The host commands may be commands associated with wear leveling, error detection or correction, etc.

[0162] The array control unit may also include an error correction code (ECC) component, which may include an ECC engine or other circuitry for detecting or correcting errors associated with writing data to or reading data from one or more memory cells in the memory system 1300 coupled to the memory controller 1302. The memory controller 1302 is configured to efficiently detect and recover from error events associated with various operations or data storage, such as bit errors, operational errors, etc., while maintaining the integrity of data transmitted between the host and the memory system 1300 or maintaining the integrity of stored data, such as by using redundant RAID storage, etc., and removing, such as retiring, failed memory resources, such as memory cells, memory arrays, pages, blocks, etc., to prevent future errors.

[0163] In the aforementioned memory system, in some embodiments, a memory device is provided, including:

[0164] A memory cell array; the memory cell array includes a plurality of memory strings; each of the memory strings includes a plurality of memory cells; each memory cell is configured to be in one of a plurality of data states;

[0165] a plurality of word lines, each word line being coupled to a corresponding memory cell in each of the memory strings;

[0166] and a peripheral circuit coupled to the plurality of word lines, wherein the peripheral circuit is configured as follows:

[0167] performing a first verification operation, the first verification operation comprising: verifying a first type of memory cell coupled to a selected word line, wherein a threshold voltage of the first type of memory cell reaches a first target threshold voltage when the verification passes; wherein the first target threshold voltage is a threshold voltage corresponding to a first target data state to which the first type of memory cell is intended to be programmed; and the first target data state is one of the plurality of data states;

[0168] and performing a second verification operation, the second verification operation comprising: verifying a second type of memory cell coupled to the selected word line, and when the verification passes, a threshold voltage of the second type of memory cell is greater than a second target threshold voltage; wherein the second target threshold voltage is a threshold voltage corresponding to a second target data state to which the second type of memory cell is expected to be programmed; and the second target data state is also one of the multiple data states.

[0169] In some embodiments, before performing the first verification operation and the second verification operation, the peripheral circuit is further configured to:

[0170] Applying a pass voltage to the selected word line; and applying a read voltage to word lines adjacent to the selected word line;

[0171] In response to a word line coupled memory cell adjacent to the selected word line in the first memory string being in an off state, determining that the memory cell coupled to the selected word line in the first memory string is of a first type;

[0172] In response to word line coupled memory cells adjacent to the selected word line in the second memory string being in a conductive state, it is determined that memory cells coupled to the selected word line in the second memory string are of a second type.

[0173] In some embodiments, the word lines adjacent to the selected word line include: a first unselected word line and a second unselected word line; wherein the same read voltage is provided to the first unselected word line and the second unselected word line by the same voltage source.

[0174] In some embodiments, the peripheral circuit is further configured to: perform the second verification operation using an increased target discharge time;

[0175] When a verification operation is performed on the second type of memory cell using the target discharge time, a threshold voltage of the second type of memory cell is equal to the second target threshold voltage.

[0176] In some embodiments, when verification passes, the threshold voltage of the second type of memory cell is less than a third target threshold voltage;

[0177] The third target threshold voltage is a threshold voltage corresponding to a next target data state adjacent to the second target data state among the multiple data states, and the second target threshold voltage is lower than the third target threshold voltage.

[0178] In some embodiments, the peripheral circuit is further configured to:

[0179] performing a first programming operation to program each memory cell coupled to the selected word line to a corresponding intermediate data state;

[0180] and after each memory cell coupled to the selected word line is programmed to a corresponding intermediate data state, applying the pass voltage to the selected word line and applying the read voltage to word lines adjacent to the selected word line to divide the memory cells coupled to the selected word line into a first memory group and a second memory group;

[0181] The first storage group includes storage units of the first type; and the second storage group includes storage units of the second type.

[0182] In some embodiments, the peripheral circuit is further configured to:

[0183] performing a second programming operation on the first type memory cells in the first memory group and performing the first verification operation so that the threshold voltage of each of the first type memory cells reaches the corresponding first target threshold voltage when the verification passes;

[0184] A third programming operation is performed on the first type memory cells in the second memory group, and the second verification operation is performed, so that the threshold voltage of each second type memory cell is greater than the corresponding second target threshold voltage when the verification passes.

[0185] In some embodiments, the number of the intermediate data states is the same as the number of the plurality of data states.

[0186] In some embodiments, the second target threshold voltage is equal to, less than, or greater than the first target threshold voltage.

[0187] In some embodiments, a threshold voltage of memory cells corresponding to the first memory group among memory cells coupled to a word line adjacent to the selected word line is lower than a threshold voltage of memory cells corresponding to the second memory group.

[0188] It should be noted that the memory system includes the aforementioned memory device, and therefore, the two have the same technical features. The terms appearing in the memory system have been explained in detail in the aforementioned memory device and are also applicable here and will not be repeated one by one.

[0189] The above description is intended to be illustrative, not restrictive. For example, the above examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments may be used, such as those available to a person of ordinary skill in the art upon reading the above description. It should be understood that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features may be combined together to simplify the present invention. This should not be interpreted as meaning that unclaimed disclosed features are essential to any claim. On the contrary, the disclosed subject matter may be less than all the features of a particular disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, with each claim independently serving as a separate embodiment, and it is expected that these embodiments may be combined with each other in various combinations or permutations. The scope of the present invention should be determined with reference to the appended claims and the full scope of equivalents to which these claims are entitled.

Claims

1. A memory device, characterized in that: include: memory cell array; The memory cell array includes a plurality of memory strings; Each of the storage strings includes a plurality of storage units; Each memory cell is configured in one of a plurality of data states; a plurality of word lines, each word line being coupled to a corresponding memory cell in each of the memory strings; and a peripheral circuit coupled to the plurality of word lines, wherein the peripheral circuit is configured as follows: performing a first verification operation, the first verification operation comprising: verifying a first type of memory cell coupled to a selected word line, wherein a threshold voltage of the first type of memory cell reaches a first target threshold voltage when the verification passes; wherein the first target threshold voltage is a threshold voltage corresponding to a first target data state to which the first type of memory cell is intended to be programmed; and the first target data state is one of the plurality of data states; and performing a second verification operation, the second verification operation comprising: verifying a second type of memory cell coupled to the selected word line, and when the verification passes, a threshold voltage of the second type of memory cell is greater than a second target threshold voltage; wherein the second target threshold voltage is a threshold voltage corresponding to a second target data state to which the second type of memory cell is expected to be programmed; and the second target data state is also one of the multiple data states.

2. The memory device according to claim 1, wherein Before performing the first verification operation and the second verification operation, the peripheral circuit is further configured to: Applying a pass voltage to the selected word line; and applying a read voltage to word lines adjacent to the selected word line; In response to a word line coupled memory cell adjacent to the selected word line in the first memory string being in an off state, determining that the memory cell coupled to the selected word line in the first memory string is of a first type; In response to word line coupled memory cells adjacent to the selected word line in the second memory string being in a conductive state, it is determined that memory cells coupled to the selected word line in the second memory string are of a second type.

3. The memory device according to claim 2, wherein: The word lines adjacent to the selected word line include: a first unselected word line and a second unselected word line; wherein the same read voltage is provided to the first unselected word line and the second unselected word line through the same voltage source.

4. The memory device according to claim 1, wherein: The peripheral circuit is further configured to: perform the second verification operation using an increased target discharge time; When a verification operation is performed on the second type of memory cell using the target discharge time, a threshold voltage of the second type of memory cell is equal to the second target threshold voltage.

5. The memory device according to claim 1, wherein When the verification passes, the threshold voltage of the second type of memory cell is less than the third target threshold voltage; The third target threshold voltage is a threshold voltage corresponding to a next target data state adjacent to the second target data state among the multiple data states, and the second target threshold voltage is lower than the third target threshold voltage.

6. The memory device according to claim 2, wherein: The peripheral circuit is further configured as follows: performing a first programming operation to program each memory cell coupled to the selected word line to a corresponding intermediate data state; and after each memory cell coupled to the selected word line is programmed to a corresponding intermediate data state, applying the pass voltage to the selected word line and applying the read voltage to word lines adjacent to the selected word line to divide the memory cells coupled to the selected word line into a first memory group and a second memory group; The first storage group includes storage units of the first type; and the second storage group includes storage units of the second type.

7. The memory device according to claim 6, wherein: The peripheral circuit is further configured as follows: performing a second programming operation on the first type memory cells in the first memory group and performing the first verification operation so that the threshold voltage of each of the first type memory cells reaches the corresponding first target threshold voltage when the verification passes; A third programming operation is performed on the first type memory cells in the second memory group, and the second verification operation is performed, so that the threshold voltage of each second type memory cell is greater than the corresponding second target threshold voltage when the verification passes.

8. The memory device according to claim 7, wherein: The number of the intermediate data states is the same as the number of the multiple data states.

9. The memory device according to claim 1, wherein: The second target threshold voltage is equal to, less than, or greater than the first target threshold voltage.

10. The memory device according to claim 6, wherein A threshold voltage of a memory cell corresponding to the first memory group among memory cells coupled to a word line adjacent to the selected word line is lower than a threshold voltage of a memory cell corresponding to the second memory group.

11. A method for operating a memory device, characterized in that: Each memory cell included in the memory device is configured to be in one of a plurality of data states; the method comprising: performing a first verification operation, the first verification operation comprising: verifying a first type of memory cell coupled to a selected word line in the memory device, wherein upon successful verification, a threshold voltage of the first type of memory cell reaches a first target threshold voltage; wherein the first target threshold voltage is a threshold voltage corresponding to a first target data state to which the first type of memory cell is intended to be programmed; and performing a second verification operation, the second verification operation comprising: verifying a second type of memory cell coupled to the selected word line in the memory device, wherein if the verification passes, a threshold voltage of the second type of memory cell is greater than a second target threshold voltage; wherein the second target threshold voltage is a threshold voltage corresponding to a second target data state to which the second type of memory cell is intended to be programmed; The first target data state is one of the multiple data states; and the second target data state is also one of the multiple data states.

12. The operating method according to claim 11, characterized in that: The operation method further includes: Applying a pass voltage to the selected word line; and applying a read voltage to word lines adjacent to the selected word line; In response to memory cells in a first memory string in the memory device being coupled to a word line adjacent to the selected word line being in a conductive state, determining that the memory cells in the first memory string coupled to the selected word line are of a first type; In response to memory cells in a second memory string in the memory device coupled to a word line adjacent to the selected word line being in an off state, it is determined that the memory cells in the second memory string coupled to the selected word line are of a second type.

13. The operating method according to claim 12, characterized in that: The word lines adjacent to the selected word line include: a first unselected word line and a second unselected word line; wherein the same read voltage is provided to the first unselected word line and the second unselected word line through the same voltage source.

14. The operating method according to claim 11, characterized in that: The operation method further includes: performing the second verification operation using the increased target discharge duration; When a verification operation is performed on the second type of memory cell using the target discharge time, a threshold voltage of the second type of memory cell is equal to the second target threshold voltage.

15. The operating method according to claim 12, characterized in that: The method further comprises: performing a first programming operation to program each memory cell coupled to the selected word line to a corresponding intermediate data state; and after each memory cell coupled to the selected word line is programmed to a corresponding intermediate data state, applying the pass voltage to the selected word line and applying the read voltage to word lines adjacent to the selected word line to divide the memory cells coupled to the selected word line into a first memory group and a second memory group; The first storage group includes storage units of the first type; and the second storage group includes storage units of the second type.

16. The operating method according to claim 15, characterized in that: The method further comprises: performing a second programming operation on the first type memory cells in the first memory group and performing the first verification operation so that the threshold voltage of each of the first type memory cells reaches the corresponding first target threshold voltage when the verification passes; A third programming operation is performed on the first type memory cells in the second memory group, and the second verification operation is performed, so that the threshold voltage of each second type memory cell is greater than the corresponding second target threshold voltage when the verification passes.

17. The operating method according to claim 16, characterized in that: The number of the intermediate data states is the same as the number of the multiple data states.

18. The operating method according to claim 15, characterized in that: A threshold voltage of a memory cell corresponding to the first memory group among memory cells coupled to a word line adjacent to the selected word line is lower than a threshold voltage of a memory cell corresponding to the second memory group.

19. A memory system, characterized in that: include: The memory device of any one of one or more claims 1 to 10, and a memory controller coupled to and controlling the memory device.

20. The memory system according to claim 19, wherein: The memory system is included in a solid state drive SSD or a memory card.

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