Memory detection device, memory detection method and related equipment

Abstract

The invention provides a memory detection device, a memory detection method and related equipment. The memory detection device comprises a plurality of registers and a processing module, wherein the plurality of registers are used for storing the number of to-be-detected ports in a memory, the number of cycles N, a plurality of address hopping modes, a plurality of data types and a plurality of operation groups. The processing module is used for writing data into each to-be-detected port of the memory according to the nth address hopping mode in the N address hopping modes and the nth data type in the N data types and according to the write operation in the multiple operation groups, and obtaining the data stored in the memory according to the read operation in the multiple operation groups; and determining whether the memory is normal according to the stored data. According to the memory detection device, the number of registers in the memory detection device is reduced through the cycle index N, a relatively complex detection algorithm can be realized, and the detection efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of memory, and more particularly, to a memory detection device, a memory detection method, a chip, and an electronic device. Background Art

[0002] Along with the chip process evolution, the design for testability (DFT) test becomes more and more complicated, causing the DFT circuit area to become larger and larger. According to existing technology, the memory built-in self-test (MBIST) circuit area accounts for a large proportion in the DFT circuit area. In the currently used MBIST circuit, a register group is generally adopted to realize the detection algorithm of the memory. Specifically, from a plurality of registers, at least one data type, an address jump mode and an operation group corresponding to each data type are obtained, and according to each data type and the address jump mode corresponding to the data type, the operation included in the corresponding operation group is performed on the memory. Because the operations of the detection algorithm are more, the quantity of the registers used for storing the data type, the address jump mode of the corresponding data type and the operation group is just more, causing the number of registers in the MBIST circuit to account for a large proportion. When the detection algorithm is relatively complicated, a large amount of registers are needed in the MBIST circuit, thereby causing the area of ​​the MBIST circuit to be larger. In the actual memory detection process, if the number of registers in the MBIST circuit is small but the detection algorithm is relatively complex, the detection personnel are required to repeatedly perform multiple operations in the MBIST circuit to update at least one of the data type, address jump mode or operation group, resulting in high detection cost and low efficiency.

[0003] Therefore, how to improve the detection efficiency of the memory while reducing the number of registers has become an urgent problem to be solved. Summary of the Invention

[0004] The present application provides a memory detection device, a memory detection method, a chip, and an electronic device, which can improve the detection efficiency of the memory while reducing the number of registers.

[0005] In a first aspect, a memory detection device is provided. The memory detection device includes at least one port mode register, at least one cycle mode register, at least one address mode register, at least one data mode register, at least one operation group register, and a processing module. The at least one port mode register is used to store the number of ports to be detected in the memory. The at least one cycle mode register is used to store a cycle number N, where N is a positive integer greater than 1. The at least one address mode register is used to store multiple address transition modes. The at least one data mode register is used to store multiple data types. The at least one operation group register is used to store multiple operation groups, each operation group including at least one operation, wherein the at least one operation includes any one or more of the following: a read operation, a write operation, or a no-operation. The processing module is used to write data to the memory for each port to be detected in the memory according to the nth address transition mode among N address transition modes and the nth data type among N data types, according to the write operation included in the multiple operation groups, where n=1, ..., N. The N address transition modes belong to the multiple address transition modes. The N data types belong to the multiple data types. The processing module is further configured to obtain, for each port to be detected of the memory, data stored in the memory according to the nth address jump mode and the nth data type, and according to the read operations included in the plurality of operation groups. The processing module is further configured to determine whether the memory is a normal memory or an abnormal memory based on the data stored in the memory.

[0006] In the embodiment of the present application, a loop mode register in the memory detection device stores the number of loops N, eliminating the need to allocate a register for storing the corresponding operation group for each data type and address transition mode in the memory detection device, thereby reducing the number of registers in the memory detection device. Furthermore, based on the number of loops N, the memory detection device can execute the operations in all operation groups on the memory according to each of the N data types and N address transition modes, thereby implementing a more complex detection algorithm without requiring manual repeated detection by detection personnel, thereby improving detection efficiency.

[0007] In combination with the first aspect, in certain implementations of the first aspect, the processing module is used to: for the pth port to be detected of the memory, determine n according to the loop count value, where p is a positive integer; determine the nth address jump mode and the nth data type from multiple address jump modes and multiple data types; and update the loop count value after performing an operation on the memory through the pth port to be detected according to the operations included in each operation group in the multiple operation groups based on the nth address jump mode and the nth data type.

[0008] In combination with the first aspect, in some implementations of the first aspect, n corresponding to the initial value of the loop count value is 1, and the updated loop count value is the loop count value before the update plus 1.

[0009] In the embodiments of the present application, a loop count value is set to determine the address transition mode and data type to be tested from among multiple address transition modes and multiple data types. Thus, the memory is tested according to the operations in all operation groups, based on each selected address transition mode and data type. In other words, looping is achieved through the loop count value, thereby implementing a more complex detection algorithm, thereby reducing the number of registers in the memory detection device while improving the efficiency of memory testing.

[0010] In combination with the first aspect, in certain implementations of the first aspect, before updating the loop count value, the processing module is further used to: determine whether n is less than N; when n is equal to N, determine that for the pth port to be detected, an operation has been performed according to each address jump mode in the N address jump modes and each data type in the N data types, according to each operation group in the multiple operation groups; when n is less than N, update the loop count value.

[0011] In combination with the first aspect, in certain implementations of the first aspect, after updating the loop count value, the processing module is further used to: determine whether n is greater than N; when n is greater than N, determine that for the pth port to be detected, an operation has been performed according to each address jump mode in the N address jump modes and each data type in the N data types, according to each operation group in the multiple operation groups; when n is less than or equal to N, re-determine n based on the updated loop count value.

[0012] In an embodiment of the present application, before or after updating the loop count value, the memory detection device can determine whether all detections have been performed on the current port to be detected, thereby determining whether the next address jump mode and data type need to be selected to detect the current port to be detected.

[0013] In combination with the first aspect, in certain implementations of the first aspect, each of the multiple address jump modes is used to indicate a change mode between a starting storage address of the data and multiple storage addresses of the data.

[0014] In the embodiment of the present application, at least one storage address for performing an operation in the memory through the current port to be detected can be determined according to an address jump mode.

[0015] In combination with the first aspect, in some implementations of the first aspect, each of the multiple data types is used to indicate an arrangement of data in a storage array of the memory.

[0016] In combination with the first aspect, in some implementations of the first aspect, each data type is further used to indicate data corresponding to each operation in each operation group.

[0017] In an embodiment of the present application, based on a data type, the data to be written when a write operation is performed on each storage address to be operated on in the memory and the expected read data when a read operation is performed can be determined through the current port to be detected.

[0018] In combination with the first aspect, in certain implementations of the first aspect, the read operation is further used to indicate expected read data, and the expected read data is used to determine whether the memory is a normal memory or an abnormal memory.

[0019] In combination with the first aspect, in certain implementations of the first aspect, the processing module is used to: determine that the memory is a normal memory when the expected read data and the stored data are the same; or determine that the memory is an abnormal memory when the expected read data and the stored data are different.

[0020] In an embodiment of the present application, the memory detection device can also determine whether the memory is normal based on the expected read data indicated by the read operation and the actual data read from the memory after each read operation is performed, thereby realizing memory detection.

[0021] In combination with the first aspect, in certain implementations of the first aspect, the number of ports to be detected, the number of loops N, multiple address jump modes, multiple data types and multiple operation groups are determined according to a detection file, the detection file includes at least one detection statement, and the detection file is used to detect the memory.

[0022] In the embodiments of the present application, the detection file includes a detection algorithm, which is represented by at least one detection statement. The detection algorithm is used to detect whether the memory is normal. The memory detection device can be connected to other devices to obtain the number of ports to be tested, the number of loops N, multiple address jump modes, multiple data types, and multiple operation groups. The other devices can be computing devices, storage devices, etc., and the embodiments of the present application are not limited to this.

[0023] In a second aspect, a memory testing method is provided. The method is performed by a memory testing device, which includes at least one port mode register, at least one cycle mode register, at least one address mode register, at least one data mode register, and at least one operation group register. The at least one port mode register is used to store the number of ports to be tested in the memory. The at least one cycle mode register is used to store a cycle number N, where N is a positive integer greater than 1. The at least one address mode register is used to store multiple address transition modes. The at least one data mode register is used to store multiple data types. The at least one operation group register is used to store multiple operation groups, each operation group including at least one operation, each operation including any one or more of the following: a read operation, a write operation, or a no-operation. The method includes: for each port to be tested in the memory, writing data to the memory according to the nth address transition mode among N address transition modes and the nth data type among N data types, in accordance with the write operations included in the multiple operation groups, where n=1, ..., N, and the N address transition modes belong to the multiple address transition modes. The N data types belong to the multiple data types; for each port to be detected of the memory, according to the nth address jump mode and the nth data type, according to the read operations included in the multiple operation groups, the data stored in the memory is obtained; based on the data stored in the memory, it is determined whether the memory is a normal memory or an abnormal memory.

[0024] In the embodiment of the present application, the number of loops N eliminates the need to allocate a register for storing the corresponding operation group for each data type and address transition mode in the memory detection device, thereby reducing the number of registers in the memory detection device. Furthermore, with this number of loops N, the memory detection device can execute the operations in all operation groups on the memory according to each of the N data types and N address transition modes, thereby implementing a more complex detection algorithm without requiring manual repeated detection by detection personnel, thereby improving detection efficiency.

[0025] In combination with the second aspect, in certain implementations of the second aspect, the method further includes: for the pth port to be detected of the memory, determining n according to the loop count value, where p is a positive integer; determining the nth address jump mode and the nth data type from multiple address jump modes and multiple data types; and updating the loop count value after performing an operation on the memory through the pth port to be detected according to the operations included in each operation group in the multiple operation groups based on the nth address jump mode and the nth data type.

[0026] In combination with the second aspect, in some implementations of the second aspect, n corresponding to the initial value of the loop count value is 1, and the updated loop count value is the loop count value before the update plus 1.

[0027] In combination with the second aspect, in certain implementations of the second aspect, before updating the loop count value, the method further includes: determining whether n is less than N; when n is equal to N, determining that for the pth port to be detected, operations have been performed according to each address jump mode in the N address jump modes and each data type in the N data types, according to each operation group in the multiple operation groups; when n is less than N, updating the loop count value.

[0028] In combination with the second aspect, in certain implementations of the second aspect, after updating the loop count value, the method further includes: determining whether n is greater than N; when n is greater than N, determining that for the pth port to be detected, operations have been performed according to each address jump mode in the N address jump modes and each data type in the N data types, according to each operation group in the multiple operation groups; when n is less than or equal to N, re-determining n based on the updated loop count value.

[0029] In combination with the second aspect, in certain implementations of the second aspect, each of the multiple address jump modes is used to indicate a change mode between a starting storage address of the data and multiple storage addresses of the data.

[0030] In combination with the second aspect, in some implementations of the second aspect, each data type of the plurality of data types is used to indicate an arrangement of data in a storage array of the memory.

[0031] In combination with the second aspect, in certain implementations of the second aspect, each data type is further used to indicate data corresponding to each operation in each operation group.

[0032] In combination with the second aspect, in certain implementations of the second aspect, the read operation is further used to indicate expected read data, and the expected read data is used to determine whether the memory is a normal memory or an abnormal memory.

[0033] In combination with the second aspect, in certain implementations of the second aspect, the method further includes: determining that the memory is a normal memory when the expected read data and the stored data are the same; or determining that the memory is an abnormal memory when the expected read data and the stored data are different.

[0034] In combination with the second aspect, in certain implementations of the second aspect, the number of ports to be detected, the number of loops N, multiple address jump modes, multiple data types and multiple operation groups are determined according to a detection file, the detection file includes at least one detection statement, and the detection file is used to detect the memory.

[0035] It should be understood that certain implementations of the second aspect have similar technical effects to those corresponding to certain implementations of the first aspect, and will not be repeated here.

[0036] In a third aspect, a chip is provided, which includes a memory and a memory detection device, wherein the memory is used to store data, and the memory detection device is as described in the first aspect or any possible implementation of the first aspect.

[0037] In a fourth aspect, an electronic device is provided, which includes the chip according to the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic structural diagram of a memory detection system.

[0039] Figure 2 is a schematic structural diagram of a memory detection system according to an embodiment of the present application.

[0040] Figure 3 is a schematic flowchart of a memory detection method according to an embodiment of the present application.

[0041] Figure 4 is a schematic flowchart of a memory detection method according to an embodiment of the present application.

[0042] Figure 5 is a schematic flowchart of a memory detection method according to an embodiment of the present application.

[0043] Figure 6 2 is a schematic diagram comparing the number of registers according to an embodiment of the present application.

[0044] Figure 7 is a schematic structural diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0045] In the embodiments of this application, words such as "exemplary" and "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" in the embodiments of this application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of the word "exemplary" is intended to present concepts in a concrete manner.

[0046] The business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field will know that with the evolution of technology and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0047] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0048] In the embodiments of the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: including the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0049] The memory detection device in the embodiment of the present application can be applied to DFT detection technology, for example, it can be applied to DFT circuit or MBIST circuit. The memory detection device in the embodiment of the present application can be used to detect static random access memory (SRAM).

[0050] Figure 1 is a schematic structural block diagram of the memory detection system 100. Figure 1 The memory detection system 100 includes a memory detection device 110 and a memory 120. The memory 120 is used to store data and is an SRAM. The memory detection device 110 includes at least one port mode register 111, at least one address mode register 112, at least one data mode register 113, at least one operation group register 114, and a processing module 115. The at least one port mode register 111 is used to store the number of ports to be detected in the memory 120.

[0051] The at least one address mode register 112 is used to store at least one address transition mode. One or more address mode registers 112 are used to store an address transition mode. Each address transition mode indicates the transition between the starting storage address of data and multiple storage addresses of the data. The present application does not limit the specific type of address transition mode. When the at least one address mode register 112 stores multiple address transition modes, at least two of the multiple address transition modes may be the same or different, and this is not a limitation in the present application.

[0052] The at least one data mode register 113 is used to store at least one data type. One or more data mode registers 113 are used to store a data type. Each data type is used to indicate how data is arranged in the storage array of the memory 120. Each data type is also used to indicate the data corresponding to each operation. The present application does not limit the specific type of data type. When the at least one data mode register 113 stores multiple data types, at least two of the multiple data types may be the same or different, which is not limited in the present application.

[0053] The at least one operation group register 114 is used to store at least one operation group, and each operation group in the at least one operation group includes at least one operation. Among them, one or more operation group registers are used to store an operation. Alternatively, one or more operation group registers are used to store an operation group. Each operation in the at least one operation includes any one of a read operation, a write operation, or a null operation. The null operation indicates that no read operation or write operation is performed on the memory. When the at least one operation group register 114 is used to store multiple operation groups, the operations included in at least two of the multiple operation groups may be the same or different, and the embodiments of the present application are not limited to this. The two operation groups being the same include: the number of operations included in the two operation groups is the same, and each operation in the two operation groups is the same. The two operation groups being different include: the number of operations included in the two operation groups is different, or at least one operation in the two operation groups is different.

[0054] The number of address transition modes stored in the at least one address mode register 112, the number of data types stored in the at least one data mode register 113, and the number of operation groups stored in the at least one operation group register 114 are the same. In other words, the memory detection device 110 needs to store a corresponding data type and operation group for each address transition mode, so that when there are more address transition modes, the number of registers in the memory detection device 110 is larger.

[0055] The processing module 115 is configured to initialize a first count value. The processing module 115 is further configured to determine n1 based on the first count value, obtain an n1th address transition mode from the at least one address transition mode, obtain an n1th data type from the at least one data type, and obtain an n1th operation group from the at least one operation group. The processing module 115 is further configured to perform each operation in the n1th operation group on the memory based on the n1th address transition mode and the n1th data type. Specifically, if the operation to be performed is a write operation, the processing module 115 writes data to the memory. If the operation to be performed is a read operation, the processing module 115 obtains data stored in the memory and, based on the stored data, determines whether the memory is normal. After performing each operation in the n1th operation group on the memory, the processing module 115 is further configured to update the first count value and re-determine n1 based on the updated first count value, thereby performing operations on the memory based on the re-determined n1th address transition mode, n1th data type, and n1th operation group.

[0056] exist Figure 1 In the illustrated memory detection system 100, if a more complex detection algorithm needs to be executed on the memory 120, the memory detection device 110 needs to include a large number of registers to store multiple address transition modes, the data type and operation group corresponding to each address transition mode, resulting in the memory detection device 110 occupying a relatively large area of ​​the entire memory detection system 100. If the number of registers included in the memory detection device 110 is relatively small, the memory detection device 110 can only store a small number of address transition modes, the data type and operation group corresponding to each address transition mode at a time. When executing a more complex detection algorithm, the detection personnel need to repeatedly manually update at least one address transition mode, the data type or operation group corresponding to each address transition mode in the memory detection device 110, resulting in high labor and time costs for detection and low detection efficiency.

[0057] Figure 2 2 is a schematic structural diagram of a memory detection system 200 provided in an embodiment of the present application. Figure 2 The memory detection system 200 includes a memory detection device 210 and a memory 220. The memory 220 and Figure 1 The memory detection device 210 includes at least one port mode register 211, at least one address mode register 212, at least one data mode register 213, at least one operation group register 214, at least one cycle mode register 215 and a processing module 216.

[0058] The at least one port mode register 211 is used to store the number of ports to be detected by the memory 220. For example, when the number of ports to be detected by the memory 220 needs to be represented by one bit, if one port mode register 211 is used to store one bit of data, then the memory detection device 210 includes one port mode register 211. When the number of ports to be detected by the memory 220 needs to be represented by two bits, if one port mode register 211 is used to store one bit of data, then the memory detection device 210 includes two port mode registers 211. The embodiment of the present application does not limit the number of bits representing the number of ports, and can be, for example, a positive integer such as 1 or 2.

[0059] The at least one address mode register 212 is used to store at least one address transition mode. One or more address mode registers 212 are used to store one address transition mode. For example, when one address transition mode needs to be represented by one bit, if one address mode register 212 is used to store one bit of data, then one address mode register 212 is used to store one address transition mode. When one address transition mode needs to be represented by two bits, if one address mode register 212 is used to store one bit of data, then two address mode registers 212 are used to store one address transition mode. The embodiments of the present application do not limit the number of bits representing each address transition mode, and may be, for example, positive integers such as 1 or 2. Each address transition mode is used to indicate the starting storage address of data and the change method between multiple storage addresses of data. The embodiments of the present application do not limit the specific type of address transition mode. For example, the at least one address transition mode includes any one or more of the following: an incrementing mode, a decrementing mode, a back-and-forth transition mode, etc. When the at least one address mode register 212 stores multiple address transition modes, at least two of the multiple address transition modes may be the same or different, which is not limited in this embodiment of the present application.

[0060] In some embodiments, the at least one address mode register 212 may store identification information of each address transition mode when storing the address transition mode, and the identification information may be represented by binary data. The embodiment of the present application does not limit the specific representation method of the identification information.

[0061] The at least one data pattern register 213 is used to store at least one data type. One or more data pattern registers 213 are used to store one data type. For example, if one data type needs to be represented by one bit, and one data pattern register 213 is used to store one bit of data, then one data pattern register 213 is used to store one data type. If one data type needs to be represented by two bits, and one data pattern register 213 is used to store one bit of data, then two data pattern registers 213 are used to store one data type. This embodiment of the present application does not limit the number of bits representing each data type; for example, it may be a positive integer such as 1 or 2. Each data type is used to indicate how data is arranged in the memory array of the memory. Each data type is also used to indicate the data corresponding to each operation. This embodiment of the present application does not limit the specific type of data type; for example, it may be a solid type or a checkerboard type. When the at least one data pattern register 213 stores multiple data types, at least two of the multiple data types may be the same or different, and this embodiment of the present application does not limit this.

[0062] In some embodiments, the at least one data mode register 213 may store identification information of each data type when storing data types, and the identification information may be represented by binary data. The embodiment of the present application does not limit the specific representation method of the identification information.

[0063] The at least one operation group register 214 is used to store at least one operation group, each operation group in the at least one operation group including at least one operation. One or more operation group registers are used to store one operation. Alternatively, one or more operation group registers are used to store one operation group. For example, if one operation requires one bit to represent one operation, and one operation group register 214 is used to store one bit of data, then one operation group register 214 is used to store one operation. If one operation requires two bits to represent one operation, and one operation group register 214 is used to store one bit of data, then two operation group registers 214 are used to store one operation. This embodiment of the present application does not limit the number of bits used to represent each operation; for example, it can be a positive integer such as 1 or 2. Each operation in the at least one operation includes any one of a read operation, a write operation, or a no operation. A no operation indicates that a read operation or a write operation is not performed on the memory. When the at least one operation group register 214 is used to store multiple operation groups, the operations included in at least two of the multiple operation groups may be the same or different, and this embodiment of the present application does not limit this. The two operation groups are the same including: the number of operations included in the two operation groups is the same, and each operation in the two operation groups is the same. The two operation groups are different including: the number of operations included in the two operation groups is different, or at least one operation in the two operation groups is different.

[0064] In some embodiments, the at least one operation group register 214 may store identification information of each operation when storing operations, and the identification information may be represented by binary data. The embodiment of the present application does not limit the specific representation method of the identification information.

[0065] The number of address transition modes stored in the at least one address mode register 212 is the same as the number of data types stored in the at least one data mode register 213 .

[0066] In some embodiments, the number of operation groups stored in the at least one operation group register 214 may be the same as or different from the number of address transition modes stored in the at least one address mode register 212, and this is not limited in the present embodiment. For example, the number of operation groups stored in the at least one operation group register 214 may be greater than or equal to the number of address transition modes stored in the at least one address mode register 212. Alternatively, the number of operation groups stored in the at least one operation group register 214 may be less than the number of address transition modes stored in the at least one address mode register 212.

[0067] The at least one cycle mode register 215 is used to store the number of cycles N, where N is a positive integer greater than 1. For example, when N needs to be represented by 1 bit, if one cycle mode register 215 is used to store 1 bit of data, then the memory detection device 210 includes one cycle mode register 215. When N needs to be represented by 2 bits, if one cycle mode register 215 is used to store 1 bit of data, then the memory detection device 210 includes two cycle mode registers 215. The embodiment of the present application does not limit the number of bits representing N, and for example, it can be a positive integer such as 1 or 2.

[0068] In some embodiments, the number of ports to be tested in the memory 220, the at least one address transition mode, the at least one data type, the at least one operation group, and the number of loops N are determined based on a test file. The test file includes at least one test statement, which is used to detect whether the memory is normal. In other words, the test file includes a test algorithm, which is expressed as at least one test statement. The test algorithm is used to detect whether the memory is normal.

[0069] For each port of the memory to be tested, the processing module 216 is configured to write data into the memory according to the nth address transition mode among N address transition modes and the nth data type among N data types, in accordance with the read operations in all operation groups stored in the at least one operation group register 214, where n=1, ..., N. The N address transition modes belong to the address transition modes stored in the at least one address mode register 212, and the N data types belong to the data types stored in the at least one data mode register 213. For each port of the memory to be tested, the processing module 216 is further configured to obtain data stored in the memory according to the nth address transition mode and the nth data type, in accordance with the read operations included in all operation groups stored in the at least one operation group register 214. The processing module 216 is further configured to determine whether the memory 220 is a normal memory or an abnormal memory based on the data stored in the memory 220 after the read operation is performed.

[0070] Figure 2The memory detection system 200 in the embodiment stores the number of loops N via the loop mode register 215 in the memory detection device 210. This eliminates the need to allocate a register for storing the corresponding operation group for each address transition mode and data type in the memory detection device 210, thereby reducing the number of registers in the memory detection device 210. Furthermore, based on the number of loops N, the memory detection device 210 can execute the operations in all operation groups on the memory according to each of the N data types and N address transition modes, thereby implementing a more complex detection algorithm without requiring manual repeated detection by detection personnel, thereby improving detection efficiency.

[0071] Figure 3 It is a schematic flow chart of the memory detection method provided in an embodiment of the present application. Figure 3 The memory detection method in Figure 2 Memory detection system 200 is shown. Figure 3 The memory detection method in can be Figure 2 The memory detection device 210 in the embodiment of the present invention performs the following operations: Figure 3 The memory detection method in can be Figure 2 The processing module 216 in is executed. Figure 3 The method includes the following steps.

[0072] S310 , for each port to be detected of the memory, write data into the memory according to an nth address transition mode among N address transition modes and an nth data type among N data types and according to read operations included in multiple operation groups.

[0073] The N address jump modes belong to the address jump modes stored in the memory detection device, and the N data types belong to the data types stored in the memory detection device. N is the number of cycles, n=1, . . . , N.

[0074] For each port of the memory to be tested, the memory testing device selects an address transition mode from the stored address transition modes and a data type from the stored data types. The memory testing device then performs operations from all stored operation groups on the memory based on the currently selected address transition mode and data type.

[0075] Optionally, the memory detection device determines the port of the memory currently to be detected and initializes a loop count value. The memory detection device determines n based on the loop count value. The memory detection device determines the nth address jump mode from the stored address jump modes and determines the nth data type from the stored data types. The memory detection device performs operations on the memory through the port currently to be detected according to each operation group in the stored operation groups based on the nth address jump mode and the nth data type. After executing the operations in all operation groups, the memory detection device updates the loop count value, thereby determining the next address jump mode and the next data type based on the updated loop count value, and executes the operations in all stored operation groups on the memory.

[0076] In some embodiments, the memory detection device performs operations on the memory through the port to be detected according to the nth address jump mode and the nth data type and each operation group in the stored operation group, including: the memory detection device writes data in the memory through the port to be detected according to the nth address jump mode and the nth data type and the write operation included in the stored operation group.

[0077] In some embodiments, before updating the loop count value, the memory detection device determines whether n is less than the loop count N. When n is equal to the loop count N, the memory detection device determines that, for the port currently to be detected, operations in all operation groups have been executed according to each of the N address transition modes and N data types. When n is less than N, the memory detection device updates the loop count value.

[0078] In some embodiments, after updating the loop count value, the memory detection device determines whether n is greater than the loop count N. If n is greater than the loop count N, the memory detection device determines that, for the port currently to be detected, operations in all operation groups have been executed according to each of the N address transition modes and N data types. If n is less than or equal to N, the memory detection device redetermines n based on the updated loop count value.

[0079] In some embodiments, an address transition mode is used to indicate the starting storage address of data and the manner in which the data changes between multiple storage addresses. The present application does not limit the specific type of address transition mode. For example, the address transition mode includes any of the following: an incrementing mode, a decrementing mode, a back-and-forth transition mode, etc. The incrementing mode includes a sequential incrementing mode or an interval incrementing mode. The decrementing mode includes a sequential decrementing mode or an interval decrementing mode.

[0080] In the sequential increasing method, the starting storage address of the data is the minimum storage address of the memory, and the next storage address of the data and the previous storage address of the data are continuous storage addresses. In other words, the next storage address of the data is the previous storage address of the data + 1. In the interval increasing method, the starting storage address of the data is the minimum storage address of the memory, and the interval between the next storage address of the data and the previous storage address of the data is a1. In other words, the next storage address of the data is the previous storage address of the data + a1. Wherein, a1 represents a preset interval value, and a1 is a positive integer. The embodiment of the present application does not limit the specific value of a1. When the value of a1 is 1, the storage address determined according to the interval increasing method and the sequential increasing method is the same.

[0081] In the sequential decreasing mode, the starting storage address of the data is the maximum storage address of the memory, and the next storage address of the data and the previous storage address of the data are continuous storage addresses. In other words, the next storage address of the data is the previous storage address of the data - 1. In the interval decreasing mode, the starting storage address of the data is the maximum storage address of the memory, and the interval between the next storage address of the data and the previous storage address of the data is a2. In other words, the next storage address of the data is the previous storage address of the data - a2. Wherein, a2 represents a preset interval value, and a2 is a positive integer. The embodiment of the present application does not limit the specific value of a2. When the value of a2 is 1, the storage address determined according to the interval decreasing mode and the sequential decreasing mode is the same.

[0082] In the back-and-forth jump mode, each storage address of the data may follow a certain mathematical rule, or may not follow the mathematical rule, and the embodiments of the present application are not limited to this.

[0083] In some embodiments, a data type is used to indicate how data is arranged in a memory array. A data type is also used to indicate the data corresponding to each operation. The present application does not limit the specific type of data type. For example, the data type may include "solid" or "checkerboard."

[0084] When the data type is solid, the data corresponding to each write operation is the same, so that after performing the same one or more write operations on each storage location in the storage array of the memory, the values ​​stored in each storage location in the storage array are the same. The data corresponding to the write operation is the data written to the memory during the write operation. When the data type is checkerboard, the data corresponding to each write operation may be the same or different, so that after performing the same one or more write operations on each storage location in the storage array of the memory, the values ​​stored in adjacent storage locations in the storage array are different. Adjacent storage locations in the storage array include adjacent storage locations in the same storage row or adjacent storage locations in the same storage column of the storage array.

[0085] In some embodiments, each operation group includes at least one operation, and each operation includes any one of a read operation, a write operation, or a null operation. The null operation indicates that no read operation or write operation is performed on the memory.

[0086] Exemplarily, the write operation includes a first write operation and a second write operation, and the data written in the first write operation and the second write operation are different.

[0087] Optionally, the number of ports to be tested in the memory, at least one address transition mode, at least one data type, at least one operation group, and the number of loops N are determined based on a test file. The test file includes at least one test statement, and the test file is used to detect whether the memory is normal. In other words, the test file includes a test algorithm, and the test algorithm is expressed as at least one test statement. The test algorithm is used to detect whether the memory is normal.

[0088] In some embodiments, the memory testing apparatus is connected to a computing device that stores a test file. When the computing device executes the test file, the memory testing apparatus receives the following data from the computing device: the number of ports to be tested in the memory, the at least one address transition mode, the at least one data type, the at least one operation group, and the number of loops N.

[0089] In some embodiments, N is less than or equal to M, where M is the number of address transition modes stored in the memory detection device. Alternatively, N is greater than M. When N is greater than M, when the value of n is greater than M, the nth address transition mode is a preset address transition mode, and the nth data type is a preset data type. The embodiments of the present application do not limit the specific types of the preset address transition mode and the preset data type.

[0090] S320 , for each port to be detected of the memory, according to the nth address jump mode and the nth data type, and in accordance with the read operations included in the plurality of operation groups, obtain data stored in the memory.

[0091] In some embodiments, the memory detection device described in step S310 performs operations on the memory through the port to be detected according to the nth address jump mode and the nth data type and each operation group in the stored operation group, including: the memory detection device obtains the data stored in the memory through the port to be detected according to the nth address jump mode and the nth data type and the read operation included in the stored operation group.

[0092] The present embodiment of the present application does not limit the order in which steps S310 and S320 are executed. After determining the nth address transition mode and the nth data type, the memory detection device sequentially performs operations on the memory based on the operations in all stored operation groups. If the current operation to be executed is a write operation, step S310 is executed; if the current operation to be executed is a read operation, step S320 is executed. After completing the read operation, the memory detection device executes step S330.

[0093] In some embodiments, the read operation is further used to indicate expected read data, which is used to determine whether the memory is normal.

[0094] Exemplarily, the read operation includes a first read operation and a second read operation, wherein the first read operation and the second read operation correspond to different expected read data.

[0095] S330: Determine whether the memory is a normal memory or an abnormal memory according to the data stored in the memory.

[0096] After executing the read operation in step S320 , the memory detection device determines whether the memory is a normal memory or an abnormal memory based on the data stored in the memory.

[0097] In some embodiments, the memory detection device compares the expected read data corresponding to the read operation in step S320 with the data stored in the memory. If the expected read data and the data stored in the memory are different, the memory is determined to be an abnormal memory. If the expected read data and the data stored in the memory are the same, the memory is determined to be a normal memory.

[0098] Figure 3The method described herein, through a number of loops N, eliminates the need to allocate a register for storing the corresponding operation group for each data type and address transition mode in the memory testing device, thereby reducing the number of registers in the memory testing device. Furthermore, through this number of loops N, the memory testing device can execute the operations in all operation groups on the memory for each of the N data types and N address transition modes, thereby implementing a more complex testing algorithm without requiring manual repetitive testing by a tester, thereby improving testing efficiency.

[0099] Figure 4 It is a schematic flow chart of the memory detection method provided in an embodiment of the present application. Figure 4 The memory detection method in Figure 2 Memory detection system 200 is shown. Figure 4 The memory detection method in can be Figure 2 The memory detection device 210 in the embodiment of the present invention performs the following operations: Figure 4 The memory detection method in can be Figure 2 The processing module 216 in is executed. Figure 4 The method in Figure 3 A possible implementation of the method in . Figure 4 The method includes the following steps.

[0100] S410, determining p according to the port count value, and setting the loop count value as an initial value.

[0101] The memory detection device starts executing Figure 4 When using the method in the embodiment, the port count value is set to an initial value. The memory detection device determines p based on the port count value. Specifically, the memory detection device determines the pth port to be detected among the P ports to be detected in the memory, where p = 1, ..., P. P is the total number of ports to be detected in the memory, and P is a positive integer. After the memory detection device determines the pth port to be detected in the memory, the memory detection device sets the loop count value to the initial value.

[0102] The embodiments of the present application do not limit the initial value of the port count value. For example, the initial value of the port count value can be a natural number such as 0, 1, or 2. p, determined based on the initial value of the port count value, is 1. For example, when the initial value of the port count value is 0, p = port count value + 1. When the initial value of the port count value is 1, p is the port count value. When the initial value of the port count value is 2, p = port count value - 1, and so on, so that p corresponding to the initial value of the port count value is 1.

[0103] Optionally, after the memory detection device sets the port count value to the initial value, the memory detection device determines whether the number of loops N is 0.

[0104] When the number of loops N is 0, the memory detection device sets the second count value as an initial value. The memory detection device determines n2 based on the second initial value, where n2 is a positive integer. The memory detection device determines the n2th address jump mode from the multiple stored address jump modes, determines the n2th data type from the multiple stored data types, and determines the n2th operation group from the multiple stored operation groups. Based on the n2th address jump mode and the n2th data type, the memory detection device performs all operations in the n2th operation group on the memory through the pth port to be detected. After performing all operations in the n2th operation group on the memory, the memory detection device updates the second count value and repeats the above process based on the updated second count value until the operations in the corresponding operation group have been performed for the pth port to be detected of the memory based on all stored address jump modes and all stored data types. After executing all operations in the operation group on the pth port to be detected, the memory detection device updates the port count value, determines the next port to be detected based on the updated port count value, and repeats the above process until all operations are executed on all ports to be detected in the memory.

[0105] When executing all operations included in the n2th operation group, if the current operation to be executed is a write operation, the memory testing device writes data to the memory through the pth port to be tested. If the current operation to be executed is a read operation, the memory testing device obtains the data stored in the memory through the pth port to be tested. The memory testing device also determines whether the memory is normal based on the stored data. For specific implementation methods, see the description of step S330.

[0106] For example, the address jump mode, data type, and operation group can be found in Figure 2 or Figure 3 The description in , will not be repeated here.

[0107] Exemplarily, the memory detection device performs all operations in the n2th operation group on the memory according to the n2th address jump mode and the n2th data type, including: the memory detection device determines the first storage address to be operated according to the n2th address jump mode. The memory determines the data corresponding to each operation in the n2th operation group according to the n2th data type. The memory detection device performs all operations included in the n2th operation group at the first storage address. If the current operation to be performed is a write operation, the memory detection device writes data to the first storage address of the memory. If the current operation to be performed is a read operation, the memory detection device obtains the data stored in the first storage address in the memory. The memory detection device also determines whether the memory is normal based on the data stored in the first storage address. For the specific implementation method, please refer to the description in step S330. When multiple storage addresses can be determined according to the n2th address jump mode, after the memory detection device determines that all operations included in the n2th operation group have been performed on the first storage address, the memory detection device determines the second storage address to be operated according to the n2th address jump mode, and repeats the above process until all operations included in the n2th operation group have been performed on all storage addresses determined according to the n2th address jump mode.

[0108] The embodiments of the present application do not limit the initial value of the second count value. For example, the initial value of the second count value can be a natural number such as 0, 1, or 2. n2 determined based on the initial value of the second count value is 1. For example, when the initial value of the second count value is 0, n2 = the second count value + 1. When the initial value of the second count value is 1, n2 is the second count value. When the initial value of the second count value is 2, n2 = the second count value - 1, and so on, so that n2 corresponding to the initial value of the second count value is 1.

[0109] Exemplarily, updating the second count value includes: adding 1 to the second count value to obtain an updated second count value. That is, the updated second count value = the second count value before the update + 1. Similarly, updating the port count value includes: adding 1 to the port count value to obtain an updated port count value. That is, the updated port count value = the port count value before the update + 1.

[0110] When the number of loops N is 0, the memory detection device determines whether n2 is equal to the number of stored address transition modes before updating the second count value. If n2 is equal to the number of stored address transition modes, the memory detection device determines that the operations in the corresponding operation group have been executed for the pth port to be detected according to all stored address transition modes and all data types. If n2 is less than the number of stored address transition modes, the memory detection device updates the second count value, re-determines n2 based on the updated second count value, and repeats the above process. Alternatively, when the number of loops N is 0, the memory detection device determines whether n2 is greater than the number of stored address transition modes after updating the second count value. If n2 is greater than the number of stored address transition modes, the memory detection device determines that the operations in the corresponding operation group have been executed for the pth port to be detected according to all stored address transition modes and all data types. When n2 is less than or equal to the number of stored address transition modes, the memory detection device re-determines n2 according to the updated second count value and repeats the above process.

[0111] When the number of loops N is 0, the memory detection device determines whether p is equal to the total number of ports P to be detected in the memory before updating the port count value. When p is equal to P, the memory detection device determines that the operations in the corresponding operation group have been executed for all ports to be detected in the memory according to all stored address transition modes and all data types. When p is less than P, the memory detection device updates the port count value, redetermines p based on the updated port count value, and repeats the above process. Alternatively, when the number of loops N is 0, the memory detection device determines whether p is greater than the total number of ports P to be detected in the memory after updating the port count value. When p is greater than P, the memory detection device determines that the operations in the corresponding operation group have been executed for all ports to be detected in the memory according to all stored address transition modes and all data types. When p is less than or equal to P, the memory detection device redetermines p based on the updated port count value and repeats the above process.

[0112] When the number of loops is not 0, steps S420 to S490 are executed.

[0113] S420 : For the pth port to be detected of the memory, determine n according to the loop count value.

[0114] After determining the pth port to be detected of the memory, the memory detection device determines n according to the loop count value. n=1, ..., N, where N is the number of loops.

[0115] The embodiments of the present application do not limit the initial value of the loop count value. For example, the initial value of the loop count value is a natural number such as 0, 1, or 2. n determined based on the initial value of the loop count value is 1. For example, when the initial value of the loop count value is 0, n = loop count value + 1. When the initial value of the loop count value is 1, n is the loop count value. When the initial value of the loop count value is 2, n = loop count value - 1, and so on, so that n corresponding to the initial value of the loop count value is 1.

[0116] S430: Determine an nth address jump mode from a plurality of address jump modes, and determine an nth data type from a plurality of data types.

[0117] After determining n according to the loop count value, the memory detection device determines an nth address jump mode from a plurality of stored address jump modes, and determines an nth data type from a plurality of stored data types.

[0118] In some embodiments, at least two of the multiple address transition modes may be the same or different. The embodiments of the present application do not limit the specific types of the multiple address transition modes. The embodiments of the present application do not limit the ordering of the multiple address transition modes. For example, the ordering of the multiple address transition modes may be determined based on a detection file. The detection file includes at least one detection statement, which is used to detect whether the memory is normal. In other words, the detection file includes a detection algorithm, which is expressed as at least one detection statement. The detection algorithm is used to detect whether the memory is normal.

[0119] In some embodiments, at least two of the multiple data types may be the same or different. The embodiments of the present application do not limit the specific types of the multiple data types. The embodiments of the present application do not limit the ordering of the multiple data types. For example, the ordering of the multiple data types may be determined based on a detection file.

[0120] S440 , performing an operation on the memory through the pth port to be detected of the memory according to each operation group in the plurality of operation groups according to the nth address jump mode and the nth data type.

[0121] Optionally, the memory detection device determines a first memory address to be operated on based on the nth address transition pattern. The memory determines, based on the nth data type, the data corresponding to each operation in a first operation group among the multiple operation groups. The memory detection device performs all operations included in the first operation group at the first memory address through the pth port to be detected. Specifically, if the current operation to be performed is a write operation, the memory detection device writes data to the first memory address in the memory. If the current operation to be performed is a read operation, the memory detection device retrieves the stored data from the first memory address in the memory. The memory detection device also determines whether the memory is normal based on the stored data. For details, see the description of step S330. Thereafter, the memory determines, based on the nth data type, the data corresponding to each operation in a second operation group among the multiple operation groups. The second operation group is different from the first operation group. The memory detection device performs all operations included in the second operation group at the first memory address through the pth port to be detected until the memory detection device has completed performing all operations in the operation group at the first memory address.

[0122] When multiple storage addresses can be determined according to the nth address jump mode, after the memory detection device determines that all operations in the operation group have been performed on the first storage address, the memory detection device determines the second storage address to be operated according to the nth address jump mode, and repeats the above process until all operations included in the operation group have been performed on all storage addresses determined according to the nth address jump mode.

[0123] Alternatively, when multiple storage addresses can be determined according to the nth address hopping method, after the memory detection device determines that all operations in the first operation group have been performed on the first storage address, the memory detection device determines a second storage address to be operated on according to the nth address hopping method, and performs all operations in the first operation group at the second storage address, until all operations included in the first operation group have been performed on all storage addresses determined according to the nth address hopping method. After all operations included in the first operation group have been performed on all storage addresses determined according to the nth address hopping method, the memory detection device performs all operations in the second operation group at the first storage address, and then performs all operations in the second operation group at the second storage address, until all operations included in the second operation group have been performed on all storage addresses determined according to the nth address hopping method. The above process is repeated until all operations included in all operation groups have been performed on all storage addresses determined according to the nth address hopping method.

[0124] S450: Determine whether n is less than N.

[0125] After performing an operation on the memory through the pth port to be detected of the memory according to all operation groups based on the nth address jump mode and the nth data type, the memory detection device determines whether n is less than N.

[0126] When n is equal to N, the memory detection apparatus determines that, for the pth port to be detected, an operation has been performed according to each of the plurality of operation groups according to each of the N address transition modes and each of the N data types. The memory detection apparatus then executes step S470.

[0127] When n is smaller than N, the memory detection apparatus executes step S460 .

[0128] S460, updating the cycle count value.

[0129] When n is less than N, the memory detection device updates the loop count value. The updating of the loop count value includes: adding 1 to the loop count value to obtain an updated loop count value. That is, the updated loop count value = the loop count value before updating + 1.

[0130] After updating the cycle count value, the memory detection device repeats steps S420-S490. In other words, for the pth port to be detected of the memory, the memory detection device re-determines n according to the updated cycle count value and repeats steps S430-S490.

[0131] S470, determine whether p is less than P.

[0132] When n is equal to N, the memory testing device determines whether p is less than P. If p is less than P, the memory testing device executes step S480. If p is equal to P, the memory testing device determines that operations have been performed on the memory according to each address transition mode and each data type, in accordance with all operations in the operation groups, for all ports to be tested. The memory testing device executes step S490.

[0133] S480: Update the port count value.

[0134] When p is less than P, the memory detection device updates the port count value. The updating of the port count value includes: adding 1 to the port count value to obtain an updated port count value. That is, the updated port count value = the port count value before updating + 1.

[0135] After updating the port count value, the memory detection apparatus repeats steps S410 to S490. In other words, the memory detection apparatus redetermines p based on the updated port count value, sets the loop count value to the initial value, and repeats steps S420 to S490.

[0136] S490: Determine whether the detection algorithm has been completed.

[0137] When p is equal to P, the memory detection device has performed operations on each port to be detected in the memory, that is, the detection algorithm has been completed.

[0138] Optionally, when n is equal to N, the memory detection device may not perform step S470. When n is equal to N, the memory detection device updates the port count value and redetermines p based on the updated port count value. The memory detection device may also determine whether p is greater than P. If p is greater than P, the memory detection device performs step S490. If p is less than or equal to P, the memory detection device repeats steps S410-S490. In other words, if p is less than or equal to P, the memory detection device sets the loop count value to the initial value and repeats steps S420-S490.

[0139] Figure 5 It is a schematic flow chart of the memory detection method provided in an embodiment of the present application. Figure 5 The memory detection method in Figure 2 Memory detection system 200 is shown. Figure 5 The memory detection method in can be Figure 2 The memory detection device 210 in the embodiment of the present invention performs the following operations: Figure 5 The memory detection method in can be Figure 2 The processing module 216 in is executed. Figure 5 The method in Figure 3 Another possible implementation of the method in . Figure 5 The method includes the following steps.

[0140] S510, determining p according to the port count value, and setting the loop count value to an initial value. Step S510 is similar to step S410 and will not be described again here.

[0141] S520: For the pth port to be detected of the memory, determine n according to the loop count value. Step S520 is similar to step S420 and will not be described again here.

[0142] S530, determining an nth address jump mode from a plurality of address jump modes, and determining an nth data type from a plurality of data types. Step S530 is similar to step S430 and will not be described in detail here.

[0143] S540, according to the nth address jump mode and the nth data type, according to each operation group in the plurality of operation groups, perform an operation on the memory through the pth port to be detected of the memory. Step S540 is similar to step S440 and will not be repeated here.

[0144] S550: Update the loop count value, and re-determine n according to the updated loop count value.

[0145] After performing an operation on the memory through the pth port to be tested of the memory according to all operation groups in the plurality of operation groups based on the nth address transition mode and the nth data type, the memory testing apparatus updates the cycle count value and redetermines n based on the updated cycle count value. The method for updating the cycle count value is described in step S460.

[0146] S560: Determine whether n is greater than N.

[0147] After re-determining n, the memory detection device determines whether n is greater than N.

[0148] When n is greater than N, the memory detection apparatus determines that, for the pth port to be detected, an operation has been performed according to each of the multiple operation groups according to each of the N address transition modes and each of the N data types. The memory detection apparatus then executes step S570.

[0149] When n is less than or equal to N, the memory detection apparatus re-executes steps S530-S590. In other words, when n is less than or equal to N, the memory detection apparatus re-executes steps S530-S590 according to the re-determined n.

[0150] S570: Update the port count value, and re-determine p according to the updated port count value.

[0151] When n is greater than N, the memory detection device updates the port count value and re-determines p based on the updated port count value. The method for updating the port count value is described in step S480.

[0152] S580: Determine whether p is greater than P.

[0153] After re-determining p, the memory detection device determines whether p is greater than P.

[0154] When p is greater than P, the memory detection device determines that, for all ports to be detected in the memory, operations in all operation groups have been performed on the memory according to each address jump mode and each data type. The memory detection device then executes step S590.

[0155] When p is less than or equal to P, the memory detection apparatus repeatedly executes steps S510 to S590. In other words, the memory detection apparatus sets the loop count value to the initial value according to the re-determined p, and repeatedly executes steps S520 to S590.

[0156] S590: Determine whether the detection algorithm has been completed. Step S590 is similar to step S490 and will not be described again here.

[0157] Alternatively, when n is greater than N, the memory detection device may not perform step S570. When n is greater than N, the memory detection device determines whether p is less than P. When p is equal to P, the memory detection device performs step S590. When p is less than P, the memory detection device updates the port count value and repeats steps S510-S590. In other words, the memory detection device updates the port count value, re-determines p based on the updated port count value, sets the loop count value to the initial value, and repeats steps S420-S490.

[0158] Figure 4 or Figure 5 The method described herein, through a number of loops N, eliminates the need to allocate a register for storing the corresponding operation group for each data type and address transition mode in the memory testing device, thereby reducing the number of registers in the memory testing device. Furthermore, through this number of loops N, the memory testing device can execute the operations in all operation groups on the memory for each of the N data types and N address transition modes, thereby implementing a more complex testing algorithm without requiring manual repetitive testing by a tester, thereby improving testing efficiency.

[0159] For example, it is assumed that a plurality of address jump modes and a plurality of data types stored in the memory detection device are as shown in Table 1 below, and a plurality of operation groups stored in the memory detection device are as shown in Table 2 below.

[0160] Table 1 Multiple address jump modes and multiple data types stored in the memory detection device

[0161] Address jump mode Data Type X up solid X up solid X up solid X up solid Y up checkerboard Y up checkerboard Y up checkerboard Y up checkerboard

[0162] Table 2 Multiple operation groups stored in the memory detection device

[0163] Operation 1 Operation 2 Operation 3 Operation 4 Operation 5 Operation 6 w r ～w ～w ～r w r ～w ～r w r ～w ～r w r r r ～w ～r w r r ～w ～r ～w ～r w w r ～w ～r w r ～w ～r w r ～w ～r ～r ～r w r ～w ～r ～r w r

[0164] As shown in Table 1, the memory detection device has stored eight address transition modes and eight data types. These eight address transition modes include four X-up modes and four Y-up modes. The X-up mode refers to a sequentially increasing mode within the memory rows of the memory array. That is, when determining a memory address based on the X-up mode, the memory address is first determined sequentially within a memory row, then the memory address is determined sequentially within the next memory row, and so on, until the memory address is determined sequentially within all memory rows. The Yup mode refers to a sequentially increasing mode within the memory columns of the memory array. That is, when determining a memory address based on the Y-up mode, the memory address is first determined sequentially within a memory column, then the memory address is determined sequentially within the next memory column, and so on, until the memory address is determined sequentially within all memory columns. The eight data types include four solid types and four checkerboard types, as described in step S310.

[0165] As shown in Table 2, eight operation groups are stored in the memory detection device, where the first operation group includes the six operations in the first row of Table 2, the second operation group includes the six operations in the second row of Table 2, and so on. In Table 2, w represents the first write operation, and ~w represents the second write operation, where the data written by the first write operation and the second write operation are different. For example, assume that the data written by the first write operation is 0 and the data written by the second write operation is 1. In Table 2, r represents the first read operation, and ~r represents the second read operation. The expected read data indicated by the first read operation and the second read operation are different. The first read operation corresponds to the first write operation, that is, the expected read data indicated by the first read operation is the data written by the first write operation. The second read operation corresponds to the second write operation, that is, the expected read data indicated by the second read operation is the data written by the second write operation.

[0166] In some embodiments, the number of bits of the data written by the first write operation and the second write operation is determined according to the bit width of the memory. The specific data written by the first write operation and the second write operation is determined according to the corresponding data type. For example, in the case of solid type, the data written by w is b 0s, and the data written by ~w is b 1s. Wherein, b is the bit width of the memory, and the embodiment of the present application does not limit the specific value of b, and b is a positive integer. In the case of checkerboard type, at the first storage address, the data written by w is b 0s, and the data written by ~w is b 1s; at the second storage address, the data written by w is b 1s, and the data written by ~w is b 0s. The first storage address and the second storage address belong to storage addresses in the memory, and the first storage address and the second storage address are adjacent storage addresses in the same storage row or the same storage column.

[0167] Assuming the number of loops is 1, the memory testing device selects the first address transition mode and the first data type from Table 1 and performs operations on the memory according to the operations in each of the six operation groups in Table 2. Specifically, the memory testing device determines, based on the X up mode, that the first memory address is the first memory address in the first memory row. Based on solid, the memory testing device determines that the data written by w is 0 and the data written by ~w is 1. At the first memory address, the memory testing device performs operations on the memory according to the operations in each of the six operation groups in Table 2. For example, the memory testing device writes 0 to the first memory address according to the first operation w in the first operation group in Table 2. The memory testing device reads the data stored at the first memory address according to the second operation r in the first operation group in Table 2. The memory testing device determines whether the memory is normal based on the data stored at the first memory address and the expected read data indicated by operation r, and so on. Then, based on the X up mode, the memory testing device determines that the second memory address is the second memory address in the first memory row. The memory detection device performs an operation on the memory at the second memory address according to the operation of each of the six operation groups in Table 2 until all memory addresses determined according to the X up method are operated according to the six operation groups in Table 2.

[0168] Alternatively, after determining the first storage address, the memory performs operations on the memory according to all operations in the first operation group in Table 2. The memory then determines the second storage address and performs operations on the memory according to all operations in the first operation group in Table 2, until all storage addresses determined according to the X up method have been operated according to the first operation group in Table 2. The memory detection device then performs operations on the memory according to all operations in the second operation group in Table 2 for the first storage address. The memory detection device then performs operations on the memory according to all operations in the second operation group in Table 2 for the second storage address, until all storage addresses determined according to the X up method have been operated according to the second operation group in Table 2. This process continues in this manner until the memory detection device has performed operations on all storage addresses determined according to the X up method according to the six operation groups in Table 2.

[0169] Assuming the number of loops is 2, the memory detection device first selects the first address transition mode and the first data type from Table 1, and performs an operation on the memory according to the operation of each of the six operation groups in Table 2. Then, the memory detection device selects the second address transition mode and the second data type from Table 1, and performs an operation on the memory according to the operation of each of the six operation groups in Table 2. The specific implementation method is similar to that of the method based on the first address transition mode and the first data type, and will not be repeated here.

[0170] Assuming that the memory is tested according to the same test file and the storage capacity of registers of the same type is the same, the comparison diagram of the number of registers required by the method in the embodiment of the present application and the number of registers required according to method 1 is as shown in FIG. Figure 6 The test file is used to indicate multiple address transition modes and multiple data types as shown in Table 1, multiple operation groups as shown in Table 2, and the data type and operation group corresponding to each address transition mode. The two registers being of the same type means that both registers are used to store the number of ports to be tested in the memory, or are used to store address transition modes, or are used to store data types, or are used to store operations.

[0171] exist Figure 6 In the method 1, Figure 1 The memory detection method performed by the memory detection system 100 in the embodiment of the present application is described in detail. Figure 6 In the equation, the horizontal axis is the number of cycles N, and the vertical axis is the number of registers. Figure 6 As shown, when the number of loops is 1, when Method 1 and Method 2 perform detection based on the same detection file, the number of registers required is relatively small. However, when the number of loops is greater than 1, when Method 1 and Method 2 perform detection based on the same detection file, the number of registers required by Method 1 is greater than the number of registers required by Method 2. Moreover, the greater the number of loops, the greater the ratio of the number of registers required by Method 1 to the number of registers required by Method 2 for the same detection file. In other words, according to the method in the embodiment of the present application, a more complex detection algorithm can be implemented while reducing the number of registers in the memory detection device, thereby improving detection efficiency.

[0172] The embodiment of the present application also provides a chip, which includes a memory detection device and a memory. The memory is used to store data. The memory detection device is used to execute Figure 3 、 Figure 4 or Figure 5 The method in .

[0173] Figure 7 is a schematic structural diagram of an electronic device according to an embodiment of the present application. Figure 7 The electronic device 700 includes a memory detection device 710 and a memory 720. The memory detection device 710 includes at least one port mode register, at least one cycle mode register, at least one address mode register, at least one data mode register, at least one operation group register and a processing module. The at least one port mode register is used to store the number of ports to be detected in the memory. The port mode register is connected to the memory 720. Figure 2 The at least one cycle mode register is used to store the number of cycles N, where N is a positive integer greater than 1. Figure 2 The at least one address mode register is used to store multiple address jump modes. Figure 2 The at least one data mode register is used to store multiple data types, and the data mode register is similar to the address mode register 212 in FIG. Figure 2 The at least one operation group register is used to store multiple operation groups, each of which includes at least one operation. Figure 2 The operation group register 214 in is similar. The processing module is used to perform Figure 3 、 Figure 4 or Figure 5 The method in this processing module is Figure 2 The memory 720 is similar to the processing module 216 in FIG. Figure 2 The memory 220 in is similar.

[0174] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0175] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0176] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0177] In addition, the functional units in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0178] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A memory detection device, characterized in that: The memory detection device includes at least one port mode register, at least one cycle mode register, at least one address mode register, at least one data mode register, at least one operation group register and a processing module, wherein the at least one port mode register is used to store the number of ports to be detected in the memory, the at least one cycle mode register is used to store the number of cycles N, the at least one address mode register is used to store multiple address jump modes, the at least one data mode register is used to store multiple data types, and the at least one operation group register is used to store multiple operation groups, each of the multiple operation groups includes at least one operation, and the at least one operation includes any one or more of the following: a read operation, a write operation or a no operation, and N is a positive integer greater than 1; the processing module is configured to, for each port to be detected of the memory, write data into the memory according to an nth address hopping mode among N address hopping modes and an nth data type among N data types, according to a write operation included in the multiple operation groups, wherein the N address hopping modes belong to the multiple address hopping modes, and the N data types belong to the multiple data types, where n=1, ..., N; The processing module is further configured to obtain, for each port to be detected of the memory, data stored in the memory according to the nth address jump mode and the nth data type and according to the read operations included in the multiple operation groups; The processing module is further configured to determine whether the memory is a normal memory or an abnormal memory based on the stored data.

2. The device according to claim 1, characterized in that The processing module is used for: For the pth port to be detected of the memory, n is determined according to the loop count value, where p is a positive integer; Determining an nth address jump mode and an nth data type from the plurality of address jump modes and the plurality of data types; After performing an operation on the memory through the pth port to be detected according to the nth address jump mode and the nth data type and the operations included in each of the multiple operation groups, the loop count value is updated.

3. The device according to claim 2, characterized in that The initial value of the loop count value corresponds to n being 1, and the updated loop count value is the loop count value before updating plus 1.

4. The device according to claim 2 or 3, characterized in that Before updating the cycle count value, the processing module is further configured to: Determine whether n is less than N; When n is equal to N, determining that, for the p-th port to be detected, an operation has been performed according to each of the multiple operation groups according to each of the N address hopping modes and each of the N data types; When n is less than N, the loop count value is updated.

5. The device according to claim 2 or 3, characterized in that After updating the cycle count value, the processing module is further configured to: Determine whether n is greater than N; When n is greater than N, determining that, for the pth port to be detected, an operation has been performed according to each of the multiple operation groups according to each of the N address hopping modes and each of the N data types; When n is less than or equal to N, n is re-determined according to the updated loop count value.

6. The device according to any one of claims 1 to 5, characterized in that Each of the multiple address jump modes is used to indicate a change mode between a starting storage address of data and multiple storage addresses of the data.

7. The device according to any one of claims 1 to 6, characterized in that Each data type of the plurality of data types is used to indicate how data is arranged in a storage array of a memory.

8. The device according to claim 7, characterized in that Each data type is also used to indicate data corresponding to each operation in each operation group.

9. The device according to any one of claims 1 to 8, characterized in that The read operation is further used to indicate expected read data, and the expected read data is used to determine whether the memory is a normal memory or an abnormal memory.

10. The device according to claim 9, characterized in that The processing module is used to: In a case where the expected read data and the stored data are identical, determining that the memory is a normal memory; or, When the expected read data and the stored data are different, the memory is determined to be an abnormal memory.

11. The device according to any one of claims 1 to 10, characterized in that The number of ports to be detected, the number of loops N, the multiple address jump modes, the multiple data types and the multiple operation groups are determined according to a detection file, the detection file includes at least one detection statement, and the detection file is used to detect the memory.

12. A memory detection method, characterized in that: The method is performed by a memory detection device, which includes at least one port mode register, at least one cycle mode register, at least one address mode register, at least one data mode register, and at least one operation group register. The at least one port mode register is used to store the number of ports to be detected in the memory, the at least one cycle mode register is used to store the number of cycles N, the at least one address mode register is used to store multiple address jump modes, the at least one data mode register is used to store multiple data types, and the at least one operation group register is used to store multiple operation groups. Each of the multiple operation groups includes at least one operation, and the at least one operation includes any one or more of the following: a read operation, a write operation, or a no operation, and N is a positive integer greater than 1. The method includes: For each port to be detected of the memory, writing data into the memory according to an nth address transition mode among N address transition modes and an nth data type among N data types, according to a write operation included in the multiple operation groups, the N address transition modes belonging to the multiple address transition modes, the N data types belonging to the multiple data types, n=1, ..., N; For each port to be detected of the memory, obtaining data stored in the memory according to the nth address jump mode and the nth data type and according to the read operations included in the multiple operation groups; According to the stored data, it is determined whether the memory is a normal memory or an abnormal memory.

13. The method according to claim 12, characterized in that The method further comprises: For the pth port to be detected of the memory, n is determined according to the loop count value, where p is a positive integer; Determining an nth address jump mode and an nth data type from the plurality of address jump modes and the plurality of data types; After performing an operation on the memory through the pth port to be detected according to the nth address jump mode and the nth data type and the operations included in each of the multiple operation groups, the loop count value is updated.

14. The method according to claim 13, characterized in that The initial value of the loop count value corresponds to n being 1, and the updated loop count value is the loop count value before updating plus 1.

15. The method according to claim 13 or 14, characterized in that Before updating the loop count value, the method further includes: Determine whether n is less than N; When n is equal to N, determining that, for the p-th port to be detected, an operation has been performed according to each of the multiple operation groups according to each of the N address hopping modes and each of the N data types; When n is less than N, the loop count value is updated.

16. The method according to claim 13 or 14, characterized in that After updating the loop count value, the method further includes: Determine whether n is greater than N; When n is greater than N, determining that, for the pth port to be detected, an operation has been performed according to each of the multiple operation groups according to each of the N address hopping modes and each of the N data types; When n is less than or equal to N, n is re-determined according to the updated loop count value.

17. The method according to any one of claims 12 to 16, characterized in that Each of the multiple address jump modes is used to indicate a change mode between a starting storage address of data and multiple storage addresses of the data.

18. The method according to any one of claims 12 to 17, characterized in that Each data type of the plurality of data types is used to indicate how data is arranged in a storage array of a memory.

19. The method according to claim 18, characterized in that Each data type is also used to indicate data corresponding to each operation in each operation group.

20. The method according to any one of claims 12 to 19, characterized in that The read operation is further used to indicate expected read data, and the expected read data is used to determine whether the memory is a normal memory or an abnormal memory.

21. The method according to claim 20, characterized in that The method further comprises: In a case where the expected read data and the stored data are identical, determining that the memory is a normal memory; or, When the expected read data and the stored data are different, the memory is determined to be an abnormal memory.

22. The method according to any one of claims 12 to 21, characterized in that The number of ports to be detected, the number of loops N, the multiple address jump modes, the multiple data types and the multiple operation groups are determined according to a detection file, the detection file includes at least one detection statement, and the detection file is used to detect the memory.

23. A chip, characterized in that: include: A memory and a memory detection device, wherein the memory is used to store data, and the memory detection device is as claimed in any one of claims 1 to 11.

24. An electronic device, characterized in that: Comprising the chip as claimed in claim 23.

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