A method, circuit and apparatus for dynamic frequency modulation suitable for AXI streaming protocol

Abstract

The application relates to the field of communication technology, in particular to a dynamic frequency adjustment method, circuit and device suitable for AXI stream transmission protocol, wherein valid data sent by a host computer is temporarily stored in a storage module, and whether the valid data is sent to a slave computer is determined according to the state of the slave computer; empty packets can be filtered out before the data is added to the storage module, only valid data is cached, resources are saved, and the data transmission efficiency is improved; and the clock frequency signal is determined according to the load size, the clock frequency signal is sent to the slave computer, so that the slave computer adjusts the frequency according to the clock frequency signal, the clock frequency is dynamically adjusted according to the upstream and downstream load conditions, the power consumption of the overall circuit is reduced under the premise of not affecting the performance, load balance is achieved, and the system bandwidth performance is not lost.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, in particular to a dynamic frequency adjustment method, circuit and device suitable for AXI stream transmission protocol. BACKGROUND

[0002] AXI (English full name: Advanced eXtensible Interface) stream protocol is an evolved version of AXI bus. AXI4 stream protocol, as a standard interface, is mainly used for transmitting data stream and connecting high-bandwidth data stream processing units, such as image / video processing, high-speed communication interface, neural network processing and other scenarios. AXI stream interface can be used to connect a plurality of hosts and slaves to build a general interconnection structure, which can perform upsizing, downsizing and routing operations, and has the advantages of high efficiency, high speed and low delay.

[0003] However, in actual application, due to concurrent writing of multiple data sources to the AXI stream channel (data streams from multiple data sources are merged into a single data stream), data conflicts and loss may occur. At the same time, due to the mismatch between the number of hosts and slaves and the fact that the host does not always have data to transmit, it is usually difficult to achieve load balancing between the upstream and downstream, that is, the system bandwidth utilization is always low, and the common interconnection structure generally does not have a cache function. If the clock frequency is too high, resources will be wasted, and if the frequency is too low, data may be lost.

[0004] In view of this, it is urgent to overcome the defects of the prior art in the technical field. SUMMARY

[0005] The technical problem to be solved by the present application is how to achieve load balancing between the upstream and downstream and improve the system bandwidth utilization of AXI stream in actual application.

[0006] The present application adopts the following technical solutions:

[0007] In a first aspect, a dynamic frequency adjustment method suitable for AXI stream transmission protocol is provided, comprising:

[0008] receiving valid data from a host, storing the valid data in a storage module, and determining the number of temporary data packets according to the valid data received by the storage module in the current clock cycle and the valid data sent to the slave in the current clock cycle;

[0009] obtaining the load size of each clock cycle according to the number of temporary data packets;

[0010] obtaining a clock frequency signal according to the load size of a plurality of clock cycles;

[0011] The clock frequency signal is sent to the slave device, so that the slave device adjusts its clock frequency according to the clock frequency signal.

[0012] Preferably, the method further comprises:

[0013] The total number of clock cycles N is set according to the capacity of the storage module; every N clock cycles, the following operations are performed:

[0014] The data variation Δ of the storage module within N clock cycles is obtained according to the load size;

[0015] The clock frequency signal is determined according to the total number of clock cycles N, the data variation Δ, and the data bit width of the slave device.

[0016] Preferably, the method further comprises:

[0017] The average load is obtained according to the total number of clock cycles N and the data variation Δ, wherein the average load = Δ / N;

[0018] The average load is taken as the numerator, and the data bit width of the slave device is taken as the denominator to obtain the load ratio;

[0019] When the load ratio is a positive number, the master module sends a clock frequency signal to the slave device to suggest that the slave device increase the frequency, and the frequency increase ratio is the load ratio;

[0020] When the load ratio is a negative number, the master module sends a clock frequency signal to the slave device to suggest that the slave device decrease the frequency, and the frequency decrease ratio is the absolute value of the load ratio.

[0021] Preferably, the method further comprises:

[0022] When it is detected that the memory of the storage module is empty and the number of currently stored data packets is 0, no data is transmitted to the slave device, and a power control signal is sent to the slave device to inform the slave device that it can be powered off and enter a low-power state.

[0023] Preferably, the method further comprises:

[0024] When valid data is received from the host and / or it is detected that the storage module is not empty, a power control signal is sent to the slave device to inform the slave device that there is data transmission to be powered on;

[0025] After waiting for the slave device to complete the power-on, valid data is sent to the slave device.

[0026] Preferably, the method further comprises:

[0027] The counting module records the variation of the number of temporarily stored data packets in each clock cycle of the storage module;

[0028] In the initial state, the data amount of the storage module is 0, and as the system runs, the counting module records the temporary data packet amount of the current storage module in each clock cycle and calculates the difference between the temporary data packet amount of each clock cycle and that of the previous clock cycle to obtain the load amount size of each clock cycle.

[0029] In a second aspect, a dynamic frequency adjustment circuit suitable for an AXI streaming protocol is provided for implementing the dynamic frequency adjustment method suitable for the AXI streaming protocol as described in the first aspect, which comprises a storage module, a counting module, a master control module and a data sending module; the storage module is used to connect with a host computer, and the storage module is further connected with the master control module, the counting module and the data sending module respectively; the master control module is connected with the counting module, the data sending module and at least one slave respectively; the data sending module is used to connect with a slave;

[0030] The storage module is used to receive valid data from the host computer and feed back the current temporary data packet amount stored to the counting module;

[0031] The counting module is used to obtain the load amount size of each clock cycle according to the temporary data packet amount;

[0032] The master control module is further used to obtain a clock frequency signal according to the load amount size and issue the clock frequency signal to the slave, so that the slave adjusts its clock frequency according to the clock frequency signal to achieve load balancing.

[0033] Preferably, a sub-control module and a data filter connected in sequence are further included, and the sub-control module and the data filter are used to connect with the host computer respectively, and the data filter is further connected with the storage module;

[0034] The sub-control module is used to receive a configuration instruction from the host computer;

[0035] The data filter is used to receive a data signal carrying to-be-transmitted data from the host computer;

[0036] The sub-control module is used to control the data filter to screen out non-empty packets from the to-be-transmitted data according to the configuration instruction to obtain the valid data.

[0037] In a third aspect, a dynamic frequency adjustment device suitable for an AXI streaming protocol is provided, which comprises a processor and a memory for storing processor-executable instructions;

[0038] The processor is configured to execute the dynamic frequency adjustment method suitable for the AXI streaming protocol.

[0039] In a fourth aspect, a non-transitory computer storage medium storing computer-executable instructions that, when executed by one or more processors, perform the method for dynamic frequency adjustment for AXI stream transmission protocol according to the first aspect is provided.

[0040] In a fifth aspect, a chip is provided, comprising: a processor and an interface for calling and running a computer program stored in a memory to perform the method for dynamic frequency adjustment for AXI stream transmission protocol according to the first aspect.

[0041] In a sixth aspect, a computer program product containing instructions that, when executed on a computer or processor, cause the computer or processor to perform the method for dynamic frequency adjustment for AXI stream transmission protocol according to the first aspect is provided.

[0042] Compared with the prior art, the present application has the following beneficial effects:

[0043] The present application temporarily stores the valid data sent by the host into the storage module, and then decides whether to send the valid data to the slave according to the state of the downstream slave. The empty packet can be filtered out before the data is added to the storage module, and only the valid data is cached, so that the resources are saved and the data transmission efficiency is improved. On the other hand, the clock frequency signal can be determined according to the load size, and the clock frequency signal is sent to the slave to suggest the slave to increase or decrease the frequency, so that the clock frequency is dynamically adjusted according to the upstream and downstream load conditions, the power consumption of the overall circuit is reduced under the premise of not affecting the performance, and the load balancing is achieved without losing the system bandwidth performance by reasonably adjusting the clock frequency of the downstream slave. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0045] Figure 1 is a flowchart of a method for dynamic frequency adjustment for AXI stream transmission protocol provided by an embodiment of the present application;

[0046] Figure 2 is a flowchart of a method for dynamic frequency adjustment for AXI stream transmission protocol provided by an embodiment of the present application;

[0047] Figure 3 is a flowchart of a method for dynamic frequency adjustment for AXI stream transmission protocol provided by an embodiment of the present application;

[0048] Figure 4 is a flow diagram of a method for dynamically adjusting frequency according to upstream data provided by an embodiment of the present application;

[0049] Figure 5 is a structural diagram of a dynamic frequency adjustment circuit suitable for AXI stream transmission protocol provided by an embodiment of the present application;

[0050] Figure 6 is a structural diagram of a dynamic frequency adjustment device suitable for AXI stream transmission protocol provided by an embodiment of the present application. DETAILED DESCRIPTION

[0051] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0052] Unless otherwise required by context, the term "comprises" in the specification and claims is to be construed as open-ended, i.e. as "comprises but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example" or "some examples" are intended to mean that a particular feature, structure, material or characteristic included in at least one embodiment or example of the present disclosure. The illustrative representation of the above terms does not necessarily mean the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any one or more embodiments or examples in any appropriate manner, i.e. although they can be carried by the embodiments or examples of the above terms due to the order of appearance and location, they are not limited to the combination of one embodiment or example.

[0053] In the description of the present application, the terms "first", "second" are only used for description purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features limited by "first", "second" can be explicitly or implicitly included in one or more features. In the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of "multiple" is two or more. In addition, for example, in the description, the same type of nouns can also be described as two independent individuals by adding "A", "B" at the end, in which case the features limited by "A", "B" are only used for the purpose of distinguishing the same type of individual description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.

[0054] In describing some embodiments, the use of "coupling," "coupled," and "connection" and variations thereof are used. For example, the term "connected" can be used to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, the term "coupled" can be used to indicate that two or more elements are in either direct physical or electrical contact with each other, or that two or more elements are not in direct contact with each other, but yet still cooperate or interact with each other. The disclosed embodiments are not necessarily limited to any particular recited implementation.

[0055] Furthermore, the technical features involved in each of the embodiments of the present application described below can be combined with each other as long as there is no conflict.

[0056] To solve the problems in the prior art, the embodiment provides a dynamic frequency adjustment method suitable for an AXI streaming protocol, as shown in Figure 1 The method comprises the following steps:

[0057] Step 101: receiving valid data from a host, storing the valid data in a storage module, and determining a number of temporarily stored data packets according to valid data received by the storage module in a current clock cycle and valid data transmitted to a slave in the current clock cycle.

[0058] In the system of the AXI streaming protocol, valid data obtained by processing data from a host is transmitted to a corresponding storage module according to the rules of the AXI streaming protocol. The specific manner of processing data from the host will be described below.

[0059] During system operation, the storage module receives valid data from the host on one hand, and on the other hand, according to the processing manner of a downstream slave, the storage module transmits the valid data to the slave for processing in real time. Since the number or bit width (i.e. processing rate) of the upstream host and the downstream slave is inconsistent, the temporary storage of the valid data is caused, i.e. the number of temporarily stored data packets of the storage module is the difference between the number of data packets from the host and the number of data packets transmitted to the slave.

[0060] In an embodiment, the storage module monitors the memory usage state of itself in real time, and feeds back the fullness of the memory to a master module. The master module can determine the load pressure of the system according to the fullness of the memory in the storage module. For example, if the memory is close to the full state, it indicates that the speed of data transmission of the host can be too fast, and the storage module will soon reach the upper limit of storage; on the contrary, if the memory is in an idle state for a long time, it indicates that the speed of data transmission of the host is slow or the speed of data processing of the slave is too fast. The storage module feeds back the number of temporarily stored data packets currently stored to a counting module.

[0061] Step 102: obtaining the load size of each clock cycle according to the temporary data packet quantity.

[0062] The counting module obtains the load size according to the temporary data packet quantity, and the master module sends a control signal to the data sending module according to the load size and the memory fullness of the storage module. In an embodiment, after the counting module receives the temporary data packet quantity fed back by the storage module, the load size of each clock cycle is calculated, and the specific calculation method will be described below.

[0063] Step 103: obtaining the clock frequency signal according to the load size of multiple clock cycles; and sending the clock frequency signal to the slave to make the slave adjust its clock frequency according to the clock frequency signal.

[0064] In an embodiment, the master module also adjusts the clock frequency signal according to the load size to send a suggestion to the slave to increase or decrease the frequency, so as to achieve load balancing. The master module adjusts the clock frequency signal according to the load size provided by the counting module. The clock frequency is a key factor affecting the data processing speed of the slave. After receiving the clock frequency signal, the slave can change its working speed.

[0065] When the load size is large, it means that the processing speed of the slave may not keep up with the data sending speed of the master. At this time, the master module adjusts the clock frequency signal and sends a frequency increase suggestion to the slave, so that the slave can work at a higher frequency to speed up the data processing speed and reduce the data backlog in the storage module. Conversely, when the load size is small, the processing speed of the slave may be too fast, resulting in resource waste. The master module sends a frequency decrease suggestion to the slave to reduce the working frequency, so as to achieve the purpose of load balancing.

[0066] In an embodiment, the dynamic frequency adjustment method suitable for AXI stream transmission protocol further comprises: the data sending module receives valid data from the storage module and sends the valid data to the slave according to the control signal. The data sending module receives valid data from the storage module and sends the valid data received by the storage module to the slave according to the control signal sent by the master module.

[0067] In summary, the embodiment temporarily stores the valid data sent by the host into the storage module, and then determines whether to send the valid data to the slave according to the state of the downstream slave. The empty packet can be filtered out before the data is added to the storage module, and only the valid data is cached, thereby saving resources and improving the data transmission efficiency. On the other hand, the clock frequency signal can be determined according to the load size, and the clock frequency signal is sent to the slave to suggest the slave to increase or decrease the frequency, so as to dynamically adjust the clock frequency according to the upstream and downstream load conditions, reduce the power consumption of the overall circuit without affecting the performance, and achieve load balancing without losing the system bandwidth performance by reasonably adjusting the clock frequency of the downstream slave.

[0068] In one embodiment, the dynamic frequency adjustment method suitable for the AXI streaming protocol further includes: when it is detected that the memory of the storage module is empty and the number of currently stored data packets is 0, no data is transmitted to the slave, and an electric control signal is sent to the slave to inform the slave that the slave can be powered off and enter a low-power state. In one embodiment, as shown in FIG. 8, when the host does not send data to the slave, the method further includes: Figure 2

[0069] Step 201: The storage module feeds back to the host module that the memory is empty, and feeds back to the counting module that the number of currently stored data packets is 0.

[0070] The storage module monitors the memory state of the storage module in real time. When the host stops sending data to the slave, the valid data in the storage module is gradually transmitted to the slave, and the valid data in the storage module is continuously reduced until the memory is empty. At this time, the storage module feeds back to the host module that the memory is empty.

[0071] At the same time, when the host stops sending data and the valid data in the storage module is completely processed, the number of temporarily stored data packets in the storage module becomes 0. The storage module feeds back to the counting module that the number of temporarily stored data packets becomes 0, and the counting module can calculate the load size based on this.

[0072] Step 202: The load size is calculated by the counting module, and the load size is fed back to the host module. The host module sends an electric control signal to inform the slave that the slave can be powered off and enter a low-power state.

[0073] ​The count module receives the information that the number of temporary storage data packets fed back by the storage module is 0, and at this time, the storage module has no valid data, so the load size is 0. After the master control module receives the information that the load size is 0 and the signal that the storage module is empty (at this time, since the number of temporary storage data packets is 0, it may also represent that the rate at which the host sends valid data matches the rate at which the slave processes valid data, so the signal that the storage module is empty needs to be combined for subsequent judgment), it is judged that the current system is in an idle state, that is, there is no data for the slave to process. In order to reduce the power consumption of the system and improve the energy utilization efficiency, the master control module issues a power control signal to the slave. The power control signal is used to inform the slave that it can perform power-off operation and enter a low-power state. In the low-power state, part of the circuit or functional module of the slave will be turned off or the working frequency will be reduced, thereby reducing the energy consumption.

[0074] Step 203: The master control module also issues a control signal to the data sending module to control the data sending module not to transmit data to the slave.

[0075] In addition to controlling the slave to enter a low-power state, the master control module also issues a control signal to the data sending module. The purpose of the control signal is to prevent the data sending module from transmitting invalid data to the slave when the host does not send data, thereby avoiding unnecessary energy consumption and waste of system resources. After receiving the control signal from the master control module, the data sending module stops transmitting data to the slave. It suspends its data sending operation until the host starts sending data again or the master control module issues a new instruction.

[0076] Through the above steps, when the host does not send data to the slave, the system can automatically enter a low-power state, reduce unnecessary energy consumption, and avoid transmission of invalid data, thereby improving the energy utilization efficiency and stability of the entire system.

[0077] The dynamic frequency adjustment method suitable for the AXI stream transmission protocol further includes: when receiving valid data from the host and / or detecting that the storage module is not empty, issuing a power control signal to the slave to inform the slave that there is data transmission to be powered on; and after waiting for the slave to complete power-on, transmitting valid data to the slave. In one embodiment, as shown in Figure 3 The method includes the following steps when the host starts sending data to the slave:

[0078] Step 301: The storage module receives valid data from the host and feeds back to the master control module that the memory is not empty, and the master control module issues a power control signal to inform the slave that there is data transmission to be powered on at this time.

[0079] When the host starts to send data to the slave, the storage module receives valid data from the host according to the rules of the AXI streaming protocol. As the valid data from the host is continuously input, the memory state in the storage module changes from an empty state to a non-empty state. The storage module monitors the memory state in real time and feeds back information that the memory is in a non-empty state to the host control module.

[0080] After receiving the information that the memory is in a non-empty state from the storage module, the host control module determines that data needs to be processed by the slave at this time. In order to enable the slave to process the data, the host control module sends a power control signal to the slave to inform the slave that data transmission is required at this time and that a power-on operation is required. After receiving the power control signal, the slave starts its power-on process and prepares to enter a working state to process the incoming data.

[0081] Step 302: The host control module sends a control signal to the data sending module after the slave completes the power-on to control the data sending module to send valid data to the slave.

[0082] After sending the power control signal to the slave to power on, the host control module waits for the slave to complete the power-on process. After confirming that the slave has completed the power-on, the host control module sends a control signal to the data sending module. After receiving the control signal from the host control module, the data sending module reads valid data from the storage module according to the requirements of the AXI streaming protocol and sends it to the slave. During the data transmission process, the data sending module ensures the integrity and accuracy of the data and transmits it according to the specified timing and format.

[0083] Through the above two steps, when the host starts to send data to the slave, the system can automatically respond so that the slave is powered on in time and receives data for processing, ensuring the continuity and efficiency of data transmission in the AXI streaming system and realizing automatic control and coordination of the system during data transmission.

[0084] In one embodiment, the load size of each clock cycle is obtained according to the number of temporarily stored data packets, specifically including: a counting module records the change of the number of temporarily stored data packets in the storage module in each clock cycle; wherein, in the initial state, the data amount of the storage module is 0, as the system runs, the counting module records the number of temporarily stored data packets in the current storage module in each clock cycle and calculates the difference between the number of temporarily stored data packets in each clock cycle and the number of temporarily stored data packets in the previous clock cycle to obtain the load size of each clock cycle.

[0085] In one embodiment, for example, in the storage module, the number of temporary data packets in the first clock cycle cycle cnt=0 (Byte), the number of temporary data packets in the second clock cycle cycle cnt=20 (Byte), the number of temporary data packets in the third clock cycle cycle cnt=30 (Byte), the number of temporary data packets in the fourth clock cycle cycle cnt=50 (Byte), and the number of temporary data packets in the fifth clock cycle cycle cnt=80 (Byte). The difference between the number of temporary data packets in each clock cycle and the number of temporary data packets in the previous clock cycle is calculated by the counting module to inform the master module, i.e. 0-0=0, 20-0=20, 30-20=10, 50-30=20, and 80-50=30. The master module is informed of 0, 20, 10, 20, and 30 (i.e. the load size corresponding to each clock cycle).

[0086] In order to realize real-time monitoring of AXI flow data load, dynamically adjust the frequency of the slave, and realize efficient and stable load balancing, in one embodiment, as shown in Figure 4 According to the load size of a plurality of clock cycles, the clock frequency signal is obtained, which includes: setting the total number of clock cycles N according to the capacity of the storage module; every N clock cycles, the following operations are performed: obtaining the data change amount Δ of the storage module within N clock cycles according to the load size; determining the clock frequency signal according to the total number of clock cycles N, the data change amount Δ, and the data bit width of the slave.

[0087] According to the total number of clock cycles N, the data change amount Δ, and the data bit width of the slave, the clock frequency signal is determined, which includes: obtaining the average load according to the total number of clock cycles N and the data change amount Δ, wherein the average load = Δ / N; taking the average load as the numerator and the data bit width of the slave as the denominator to obtain the load ratio; when the load ratio is positive, the master module issues a clock frequency signal suggesting that the slave increases the frequency, and the frequency increase ratio is the load ratio; when the load ratio is negative, the master module issues a clock frequency signal suggesting that the slave reduces the frequency, and the frequency reduction ratio is the absolute value of the load ratio.

[0088] The master module first sets the total number of clock cycles N according to the capacity of the storage module. The capacity of the storage module determines the upper limit of the amount of data that the system can store. If the capacity of the storage module is large, it means that the system has more buffer space to cope with fluctuations in data, and a larger N value can be set at this time, which can more accurately reflect the long-term load of the system; on the contrary, if the capacity of the storage module is small, the N value should be set relatively small in order to respond to changes in system load in a timely manner. For example, when the capacity of the storage module is 1 GB, N can be set to 1000 clock cycles; when the capacity of the storage module is 100 MB, N can be set to 100 clock cycles. In an embodiment, the total number of clock cycles N can also be 5, 10, 20, or 50.

[0089] In an embodiment, every N clock cycles, the master module calculates the amount of data change Δ of the storage module in the N clock cycles according to the load size. After obtaining the amount of data change Δ, the master module calculates the average load according to the total number of clock cycles N and the amount of data change Δ. Finally, the master module takes the calculated average load as the numerator and the data bit width of the slave as the denominator to obtain the load ratio. The data bit width of the slave refers to the amount of data that the slave can process in one clock cycle.

[0090] When the load ratio is positive, it means that the amount of data in the storage module as a whole is increasing in the N clock cycles, that is, the speed of data transmission by the upstream (master) exceeds the speed of data processing by the slave. At this time, the master module will issue a clock frequency signal suggesting that the slave increase the frequency, and the frequency increase ratio is the load ratio. For example, the load ratio is 0.5, which means that the slave needs to increase the clock frequency by 50% to speed up data processing and reduce data accumulation in the storage module, achieving load balancing.

[0091] When the load ratio is negative, it means that the amount of data in the storage module as a whole is decreasing in the N clock cycles, that is, the speed of data processing by the slave exceeds the speed of data transmission by the upstream. In order to avoid resource waste, the master module will issue a clock frequency signal suggesting that the slave decrease the frequency, and the frequency decrease ratio is the absolute value of the load ratio. For example, the load ratio is -0.5, which means that the slave needs to decrease the clock frequency by 50% to match the data transmission speed of the upstream, achieving the purpose of load balancing. It should be noted that the master module in this embodiment only gives a suggestion to the slave to adjust the clock frequency, and cannot directly control the clock frequency of the slave.

[0092] Taking the number of temporary data packets stored in the storage module for 5 clock cycles as an example, the load size of each clock cycle is respectively: 0-0=0, 20-0=20, 30-20=10, 50-30=20, 80-50=30; then, the data change amount Δ of the storage module in 5 clock cycles is 0+20+10+20+30=80 Byte. The average load = Δ / N = 80 / 5 = 16. If the bit width of the slave machine at this time is 16, the load ratio = 16 / 16 = 1, then the master module needs to issue the corresponding recommended clock frequency signal of the slave machine to increase the frequency by 100% to meet the load balancing.

[0093] Through the above steps, the master module can monitor the AXI stream data load in real time and dynamically adjust the frequency of the slave machine according to the load condition, so as to realize efficient and stable load balancing and improve the performance and stability of the entire AXI stream transmission system.

[0094] In order to further illustrate the dynamic frequency adjustment method suitable for the AXI stream transmission protocol in the foregoing embodiment, the present embodiment proposes a dynamic frequency adjustment circuit suitable for the AXI stream transmission protocol, as shown in Figure 5 The storage module is used to connect with the host computer, and is further connected with the master module, the counting module and the data sending module. The master module is connected with the counting module, the data sending module and at least one slave machine. The data sending module is used to connect with the slave machine. The storage module is used to receive valid data (such as valid data 1 and valid data 2) from the host computer, and feed back the memory empty / full condition (i.e. empty / full signal) to the master module, and feed back the number of temporarily stored data packets to the counting module. The counting module is used to obtain the load size of each clock cycle according to the number of temporarily stored data packets. The master module is used to issue a control signal to the data sending module according to the load size and the memory empty / full condition of the storage module. The master module is further used to obtain a clock frequency signal according to the load size, and issue the clock frequency signal to the slave machine, so that the slave machine adjusts its clock frequency according to the clock frequency signal to achieve load balancing. The data sending module is used to receive valid data (including valid data and validity indication signal) from the storage module, and send the valid data to the slave machine according to the control signal.

[0095] In one embodiment, refer to Figure 5The dynamic frequency modulation circuit suitable for AXI streaming protocol further comprises a sub-control module and a data filter connected in sequence, the sub-control module and the data filter are used for connecting with a host respectively, and the data filter is further connected with the storage module; the sub-control module and the data filter are used for cooperating to filter empty packets in data from the host according to the content of AXI streaming standard protocol to obtain the valid data. Wherein, the number of the sub-control module and the data filter is determined according to the number of the host, and other modules are unique. Wherein, the sub-control module is used for receiving configuration instructions (i.e. configuration instruction 1 and configuration instruction 2) from the host; the data filter is used for receiving data signals (i.e. data signal 1 and data signal 2) carrying to-be-transmitted data from the host; the sub-control module (including sub-control module 1 and sub-control module 2) is used for controlling the data filter (including data filter 1 and data filter 2) to filter non-empty packets from the to-be-transmitted data according to the configuration instructions (including configuration instruction 1 and configuration instruction 2) to obtain the valid data (including valid data 1 and valid data 2).

[0096] Wherein, referring to Figure 5 For the configuration instruction 3 and the data signal 3, the data sending module sends instructions to the slave through the configuration instruction 3 and sends the to-be-transmitted valid data to the slave through the data signal 3, the configuration instruction 3 is used for transmitting control information (such as operation type, address, data length, etc.) for indicating the start, direction, format and target of data transmission. The data signal 3 is used for carrying the actual transmission data content (i.e. valid data).

[0097] Wherein, Figure 5 As shown in the figure, the system comprises two hosts (i.e. host 1 and host 2) and a slave (i.e. slave), because two hosts are included, the corresponding sub-control module 1, sub-control module 2, data filter 1 and data filter 2 are included.

[0098] In one embodiment, taking host 1 as an example, when host 1 starts transmitting data to slave, it transmits the data to be transmitted to sub-control module 1 and data filter 1 via configuration instruction 1 and data signal 1. Sub-control module 1 and data filter 1 filter empty packets from the data from the host according to the AXI streaming standard protocol to obtain the valid data 1, and send the valid data 1 to the storage module. The storage module informs the master control module that the host is transmitting data via an empty / full signal. The master control module sends a power control signal to the slave. After the slave completes power-on, it transmits a power-on signal to the master control module to inform it that power-on is complete and it can receive data. The master control module then controls the data transmission module to read the corresponding valid data from the storage module via control signals. In one embodiment, the storage module and the data transmission module communicate via a handshake protocol (i.e., validity indication signal and valid data) to read the valid data in the storage module and transmit the valid data to the slave, thus completing the transition of the slave from power-down to receiving valid data after power-on. The data transmission operation of host 2 is similar to the above process and will not be described in detail here.

[0099] In one embodiment, a typical interconnect bus generally lacks buffering capabilities; it simply routes data input from multiple hosts to different slave devices after arbitration. Internally, it typically only contains an arbitration module and a routing module. This embodiment incorporates a storage module. Data is not directly output to the slave devices; data from the hosts is processed and temporarily stored in the storage module, with the decision to send it based on the downstream status. The advantage of this approach is that the AXI streaming protocol allows for empty packets and placeholder bytes. Adding a storage module filters out empty packets, buffering only valid data, thus saving resources and improving efficiency.

[0100] To further illustrate the dynamic frequency modulation method of this invention, please refer to... Figure 4 and Figure 5 Taking a system consisting of two masters and one slave as an example. The system runs at a 100MHz clock speed. The data width of both the master and slave is 16 bytes. Under full load conditions, if the master does not send empty packets, the storage module will add 16 x 2 – 16 x 1 = 16 bytes of effective data per clock cycle (that is, the number of temporary data packets mentioned above. Here, specific limits are made for the master and slave, so the number of temporary data packets increases by 16 bytes per clock cycle). Therefore, the clock rate of the slave must be twice that of the master to achieve load balancing.

[0101] In one embodiment, the number of temporary data packets in five clock cycles are respectively 16, 32, 48, 64, and 80. The load size of each clock cycle is 16, and the data change amount Δ of the memory module in N clock cycles is obtained according to the load size, that is, Δ = 16 x 5 = 80 Byte. The average load is Δ / N = 80 / 5 = 16. The bit width of the slave is 16, and the load ratio is 16 / 16 = 1. Therefore, the master module needs to issue a corresponding recommended clock frequency signal to the slave to increase the frequency by 100%, that is, the clock rate of the slave is twice the clock rate of the master, so as to satisfy the load balancing.

[0102] Through the above steps, the master module can monitor the AXI stream data load in real time, and dynamically adjust the frequency of the slave according to the load condition, so as to realize efficient and stable load balancing, and improve the performance and stability of the entire AXI stream transmission system.

[0103] Based on the dynamic frequency adjustment method for the AXI stream transmission protocol provided in the foregoing embodiment, in this embodiment, a dynamic frequency adjustment device for the AXI stream transmission protocol will be provided. The dynamic frequency adjustment device for the AXI stream transmission protocol comprises a processor and a memory for storing processor-executable instructions. The processor is configured to execute the dynamic frequency adjustment method for the AXI stream transmission protocol.

[0104] As shown in Figure 6 The dynamic frequency adjustment device for the AXI stream transmission protocol comprises a processor 21 and a memory 22. The processor 21 and the memory 22 can be connected through a bus or other means.

[0105] The processor 21 can be a central processing unit (CPU). The processor 21 can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or a combination of the above-mentioned chips.

[0106] The memory 22, as a non-transitory computer readable storage medium, can be used to store non-transitory software programs, non-transitory computer executable programs and modules, such as the program instructions / modules corresponding to the dynamic frequency adjustment method suitable for AXI streaming protocol in the embodiments of the present application. The processor executes various functions of the processor and training processing by running the non-transitory software programs, instructions and modules stored in the memory.

[0107] The memory 22 can include a program storage area and a training storage area, wherein the program storage area can store an operating system and application programs required by at least one function; and the training storage area can store training created by the processor, etc. In addition, the memory can include a high-speed random access memory, and can also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some embodiments, the memory 22 can optionally include a memory remotely arranged with respect to the processor, and these remote memories can be connected to the processor through a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof. The one or more modules are stored in the memory 22, and when executed by the processor 21, perform the dynamic frequency adjustment method suitable for AXI streaming protocol as shown. Figure 1 The specific details of the above-mentioned dynamic frequency adjustment method suitable for AXI streaming protocol can be understood by referring to the corresponding related descriptions and effects in the embodiments shown in Figure 1 、 Figure 2 and Figure 3 , and will not be described here.

[0108] The embodiments also provide a computer storage medium, which stores a computer program executable by a processor to complete the dynamic frequency adjustment method suitable for AXI streaming protocol.

[0109] The computer storage medium stores computer executable instructions, and the computer executable instructions can execute the dynamic frequency adjustment method suitable for AXI streaming protocol in any method embodiment described above. The storage medium can be a disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD), etc.; and the storage medium can also include a combination of the above-mentioned types of memories.

[0110] The specific steps of the dynamic frequency modulation method suitable for the AXI streaming protocol are described in the foregoing embodiments, and will not be described here again in the embodiment.

[0111] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for dynamic frequency adjustment suitable for AXI streaming protocol, characterized in that, The method comprises the following steps: receiving valid data from the host, storing the valid data in the storage module, and determining the number of temporarily stored data packets according to the valid data received by the storage module in the current clock cycle and the valid data sent to the slave in the current clock cycle; obtaining the load size of each clock cycle according to the number of temporarily stored data packets; obtaining the clock frequency signal according to the load size of multiple clock cycles; sending the clock frequency signal to the slave to make the slave adjust its clock frequency according to the clock frequency signal.

2. The method for dynamic frequency modulation suitable for AXI streaming protocol according to claim 1, characterized in that, The method further comprises the following steps: setting the total number of clock cycles N according to the capacity of the storage module; every N clock cycles, the following operations are performed: obtaining the data variation Δ of the storage module within N clock cycles according to the load size; determining the clock frequency signal according to the total number of clock cycles N, the data variation Δ, and the data bit width of the slave.

3. The method for dynamic frequency modulation suitable for AXI streaming protocol according to claim 2, characterized in that, The method further comprises the following steps: obtaining the average load according to the total number of clock cycles N and the data variation Δ, wherein the average load = Δ / N; taking the average load as the numerator and the data bit width of the slave as the denominator to obtain the load ratio; when the load ratio is positive, the master module sends the clock frequency signal to the slave to suggest that the slave increase the frequency, and the frequency increase ratio is the load ratio; when the load ratio is negative, the master module sends the clock frequency signal to the slave to suggest that the slave decrease the frequency, and the frequency decrease ratio is the absolute value of the load ratio.

4. The method for dynamic frequency modulation suitable for AXI streaming protocol according to claim 1, characterized in that, The method further comprises the following steps: when it is detected that the memory of the storage module is empty and the number of currently stored data packets is 0, no data is transmitted to the slave, and a power control signal is sent to the slave to inform the slave that it can be powered off and enter a low-power state.

5. The method for dynamic frequency modulation suitable for AXI streaming protocol according to claim 1, characterized in that, The method further comprises the following steps: when valid data from the host is received and / or it is detected that the storage module is not empty, a power control signal is sent to the slave to inform the slave that data transmission needs to be powered on; after waiting for the slave to complete the power-on, valid data is sent to the slave.

6. The method for dynamic frequency modulation suitable for AXI streaming protocol according to claim 1, characterized in that, The method further comprises the following steps: the counting module records the variation of the number of temporarily stored data packets in each clock cycle of the storage module; wherein, in the initial state, the data amount of the storage module is 0, as the system runs, the counting module records the number of temporarily stored data packets of the current storage module in each clock cycle, and calculates the difference between the number of temporarily stored data packets of each clock cycle and that of the previous clock cycle to obtain the load size of each clock cycle.

7. A dynamic frequency modulation circuit suitable for AXI stream protocol, characterized in that, The method for dynamically adjusting the frequency suitable for the AXI stream transmission protocol according to any one of claims 1 to 6 comprises a storage module, a counting module, a master module, and a data sending module; the storage module is used to connect with the host, and the storage module is further connected with the master module, the counting module, and the data sending module respectively; the master module is connected with the counting module, the data sending module, and at least one slave; the data sending module is used to connect with the slave; the storage module is used to receive valid data from the host and feed back the number of temporarily stored data packets currently stored to the counting module; the counting module is used to obtain the load size of each clock cycle according to the number of temporarily stored data packets; The master module is further configured to obtain a clock frequency signal according to the load size, and send the clock frequency signal to the slave to adjust the clock frequency of the slave according to the clock frequency signal, so as to achieve load balancing.

8. The dynamic frequency modulation circuit adapted for AXI streaming protocol according to claim 7, characterized in that, The system further comprises a sub-control module and a data filter connected in sequence, wherein the sub-control module and the data filter are configured to be connected with the host, and the data filter is further connected with the storage module; The sub-control module is configured to receive a configuration instruction from the host; The data filter is configured to receive a data signal carrying to-be-transmitted data from the host; The sub-control module is configured to control the data filter to filter out non-empty packets from the to-be-transmitted data according to the configuration instruction, so as to obtain the effective data.

9. A dynamic frequency adjustment device suitable for AXI streaming protocol, characterized in that, The dynamic frequency adjustment device suitable for AXI stream transmission protocol comprises a processor and a memory for storing processor-executable instructions. The processor is configured to execute the dynamic frequency adjustment method suitable for AXI stream transmission protocol according to any one of claims 1 to 6.

10. A non-transitory computer storage medium, comprising, The computer storage medium stores computer-executable instructions, which are executed by one or more processors to complete the dynamic frequency adjustment method suitable for AXI stream transmission protocol according to any one of claims 1 to 6.

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