Split-gate flash memory and manufacturing method thereof
By adopting a three-dimensional source-floating gate coupling structure and top erase mechanism in the split gate flash memory, the problem of floating gate size limitation is solved, the memory cell is reduced and power consumption is reduced, and the memory density and reliability are improved.
Patent Information
- Application Number
- CN202510656788.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-20
- Publication Date
- 2025-09-02
AI Technical Summary
In traditional sub-gate flash memory, the critical size of the floating gate is limited, making it difficult to reduce the memory cell area, and high voltage operation increases power consumption and read interference risks.
The three-dimensional source-floating gate coupling structure is adopted, and the floating gate is embedded in the trench, and the three-dimensional coupling is formed with the floating gate through the source line polysilicon, combining the top erase mechanism and low voltage selection gate, optimizing coupling efficiency and reducing power consumption.
It further reduces the memory cell size, improves memory density, reduces power consumption and read interference risks, simplifies peripheral circuit design, and is compatible with existing CMOS processes.
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Figure CN120583684A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a split-gate flash memory and a manufacturing method thereof. Background Art
[0002] Flash memory is a non-volatile memory. Due to its advantages such as electrically erasable, low power consumption, high integration, and good shock resistance, it has been widely used in computer systems, consumer electronics, communication equipment, Internet of Things (IoT) devices, and other fields.
[0003] Split-gate flash memory is an important type of flash memory. Each memory cell typically consists of a floating gate (FG) transistor and a select gate (SG, also often called a transistor controlled by a word line (WL)) connected in series. The floating gate is used to store charge to represent the data state (e.g., "0" or "1"), while the select gate is used to select the target memory cell during read and write operations.
[0004] In traditional split-gate flash memory designs, particularly those for low-voltage threshold (LVT) cells, programming relies primarily on capacitive coupling from the source line junction (SL junction) to the floating gate. To ensure sufficient coupling efficiency, sufficient overlap between the source line junction and the floating gate is required. This structure is typically planar, with the floating gate and source line junction overlapping in a two-dimensional plane near the substrate surface.
[0005] However, with the continuous advancement of semiconductor process technology, electronic products are increasingly demanding higher memory capacity and integration, driving the continuous shrinking of memory cell size. In traditional planar coupling structures, to maintain the coupling coefficient required for programming, the overlap area between the source line junction and the floating gate is difficult to scale down proportionally. This limits the critical dimension (CD) of the floating gate, particularly its dimension along the channel length, and prevents it from being made too small. This has become a bottleneck in further reducing the overall flash memory cell area.
[0006] Furthermore, the rise of low-power applications like the Internet of Things (IoT) has placed stricter demands on both static and dynamic power consumption for memory. Traditional split-gate flash memory may require higher voltages for read and write operations, which not only increases power consumption but also introduces reliability risks like read disturbances. This also places higher demands on the design of peripheral driver circuits.
[0007] In order to solve the above problems, it is necessary to propose a new type of split-gate flash memory and a manufacturing method thereof. Summary of the Invention
[0008] In view of the above-mentioned shortcomings of the prior art, the present invention aims to provide a split-gate flash memory and a manufacturing method thereof, so as to solve the bottleneck problem in the prior art in that the critical dimension of the floating gate is limited and the area of the entire flash memory cell is reduced.
[0009] To achieve the above-mentioned and other related objectives, the present invention provides a split-gate flash memory, comprising:
[0010] substrate;
[0011] an isolation structure disposed within the substrate;
[0012] an active region disposed in the substrate, the active region being bounded by the isolation structure;
[0013] A gate stack structure is provided on a portion of the active area, the gate stack structure comprising:
[0014] a floating gate, a portion of which is embedded in a trench formed in the substrate;
[0015] a coupling dielectric layer, disposed on the sidewalls and bottom of the trench, isolating the floating gate from the substrate;
[0016] an inter-electrode dielectric layer, disposed on top of the floating gate;
[0017] An erase gate is provided on the inter-electrode dielectric layer;
[0018] An upper sidewall of the erase gate is provided on the upper surface of the erase gate;
[0019] An inner sidewall of the erase gate is provided on a sidewall of the erase gate facing the polysilicon of the source line;
[0020] The inner sidewall of the floating gate is arranged on the sidewall of the floating gate facing the polysilicon of the source line;
[0021] a source line doping region, disposed in the substrate and adjacent to the gate stack structure;
[0022] a source line polysilicon layer, disposed above the source line doped region, the source line polysilicon layer being adjacent to the inner sidewall of the erase gate and the inner sidewall of the floating gate, and having a portion adjacent to the floating gate, so as to couple the floating gate through the source line doped region and the source line polysilicon layer during programming of the split-gate flash memory;
[0023] A tunnel dielectric layer is provided between the source line polysilicon and the sidewall of the floating gate, and may be located on the inner sidewall of the erase gate and the upper sidewall of the erase gate;
[0024] a select gate disposed on the active region and adjacent to a sidewall of the gate stack structure;
[0025] a gate dielectric layer, disposed between the select gate and the active region;
[0026] The bit line doping region is disposed in the substrate and adjacent to the selection gate.
[0027] Preferably, a first outer spacer is provided on the sidewall of the structure formed by the gate stack structure and the source line polysilicon; and the select gate is formed adjacent to the first outer spacer.
[0028] Preferably, a second outer spacer is provided on the sidewall of the selection gate; the second outer spacer is used to define a formation area of the bit line doping region.
[0029] Preferably, the floating gate, the erase gate, the source line polysilicon and the select gate are made of polysilicon.
[0030] Preferably, the material of the coupling dielectric layer, the inter-electrode dielectric layer, the gate dielectric layer, the tunnel dielectric layer, the erase gate upper sidewall, the erase gate inner sidewall and the floating gate inner sidewall is selected from oxide, nitride, oxynitride or a combination thereof.
[0031] Preferably, the isolation structure is a shallow trench isolation structure.
[0032] Preferably, the operating voltage of the selection gate is 1 to 2V.
[0033] Preferably, the operating voltage of the selection gate is 1.5V.
[0034] The present invention also provides a method for manufacturing the above-mentioned split-gate flash memory, comprising:
[0035] Step 1: providing a substrate, and forming an isolation structure and an active area in the substrate;
[0036] Step 2: forming a trench in a portion of the active area and adjacent to the isolation structure;
[0037] Step 3: forming a coupling dielectric layer in the groove;
[0038] Step 4: depositing a first conductive material in the trench to form a floating gate;
[0039] Step 5: forming an inter-electrode dielectric layer on the floating gate;
[0040] Step 6: depositing a second conductive material on the inter-electrode dielectric layer to form an erase gate;
[0041] Step 7: forming an opening for accommodating the source line polysilicon and defining a portion of the gate stack, including:
[0042] depositing a hard mask layer on the erase gate;
[0043] performing patterning on the hard mask layer to form an opening pattern above the erase gate, the inter-electrode dielectric layer and the floating gate to expose the underlying area;
[0044] Performing ion implantation into the substrate through the opening pattern to form a source line doping region;
[0045] forming a tunnel dielectric layer on the sidewalls of the opening pattern;
[0046] forming a first sidewall spacer on the tunnel dielectric layer;
[0047] Using the patterned hard mask layer and the first sidewall as masks, etching the erase gate below the opening pattern;
[0048] forming a second sidewall spacer on the etched sidewall of the erase gate;
[0049] Using the patterned hard mask layer, the first sidewall spacer, the second sidewall spacer, and the etched erase gate as masks, etching a portion of the exposed floating gate;
[0050] A third sidewall is formed on the bottom and sidewall of the pattern formed after etching;
[0051] Step eight, forming source line polysilicon, including depositing a third conductive material and performing a planarization process, wherein the third conductive material fills the area defined by the hard mask layer, the tunnel dielectric layer, the first spacer, the second spacer, and the third spacer;
[0052] Step nine, patterning and etching the floating gate, the inter-electrode dielectric layer, the erase gate, the source line polysilicon, and the layers covering them to define a gate structure region of the memory cell;
[0053] Step 10: forming a select gate, including:
[0054] forming a fourth spacer on the sidewall of the gate structure region formed in step nine;
[0055] depositing a gate dielectric layer material and a fourth conductive material;
[0056] Etching the fourth conductive material and the gate dielectric layer material to form a select gate and a gate dielectric layer thereunder on the fourth sidewall;
[0057] Step 11: forming a fifth spacer on the sidewall of the select gate;
[0058] Step 12: Using the select gate and the fifth sidewall as masks, a bit line doping region is formed in the substrate.
[0059] Preferably, the first conductive material, the second conductive material, the third conductive material and the fourth conductive material include polysilicon.
[0060] Preferably, the coupling dielectric layer, the inter-electrode dielectric layer, the gate dielectric layer and the tunnel dielectric layer are made of a material selected from oxide, nitride, oxynitride or a combination thereof, and are formed by a deposition process.
[0061] Preferably, the isolation structure is a shallow trench isolation structure, which is formed by etching the substrate to form a shallow trench, then depositing an insulating material and performing chemical mechanical polishing.
[0062] Preferably, the source line doping region and the bit line doping region are formed by an ion implantation process.
[0063] Preferably, the materials of the first spacer, the second spacer, the third spacer, the fourth spacer and the fifth spacer formed in step seven, step ten and step eleven are selected from nitride, oxide or a combination thereof, and are formed by deposition and anisotropic etching.
[0064] As described above, the split-gate flash memory and the manufacturing method thereof of the present invention have the following beneficial effects:
[0065] The present invention provides a split-gate flash memory and a method for forming the same. By placing a portion of the floating gate within a trench and forming source line polysilicon adjacent to the trench, a three-dimensional source-floating gate coupling structure is constructed. This design effectively reduces the planar size of the floating gate without sacrificing or even optimizing the coupling coefficient, thereby significantly facilitating further reductions in flash memory cell size and improving storage density. Furthermore, the use of a top erase mechanism and a lower select gate operating voltage (e.g., 1.5V) helps reduce device power consumption, minimize read disturbance risks, and simplify peripheral circuit design. Furthermore, the proposed manufacturing method is highly compatible with existing CMOS or flash memory processes and can be easily integrated into existing production lines. BRIEF DESCRIPTION OF THE DRAWINGS
[0066] Figure 1 Shown is a schematic diagram of the process flow of the present invention;
[0067] Figure 2 It is a schematic diagram showing the sequential formation of a pad oxide layer and a silicon nitride mask layer on a substrate according to the present invention;
[0068] Figure 3 Shown is a schematic diagram of forming a shallow trench (cross-sectional view in the X direction) according to the present invention;
[0069] Figure 4 Shown is a schematic diagram of forming a shallow trench isolation (STI) structure according to the present invention;
[0070] Figure 5 Schematic diagram showing the removal of the remaining pad oxide layer and silicon nitride mask layer according to the present invention;
[0071] Figure 6 Schematic diagram showing a trench formed in a portion of an active region and adjacent to an isolation structure (a cross-sectional view in the Y direction) according to the present invention;
[0072] Figure 7 It is a schematic diagram showing the formation of a coupling dielectric layer in a trench according to the present invention;
[0073] Figure 8 Schematic diagram showing the formation of a floating gate (cross-sectional view in the X direction) of the present invention;
[0074] Figure 9 Schematic diagram showing the formation of a floating gate (cross-sectional view in the Y direction) of the present invention;
[0075] Figure 10 Schematic diagram showing the deposition of a hard mask layer on an erase gate according to the present invention;
[0076] Figure 11 Shown is a schematic diagram of forming an opening pattern of the present invention;
[0077] Figure 12 Schematic diagram showing the formation of a first sidewall on the edge sidewall of the opening pattern according to the present invention;
[0078] Figure 13 Shown is a schematic diagram of an erase gate below the etched opening pattern of the present invention;
[0079] Figure 14 It is a schematic diagram showing the formation of a second sidewall spacer on the erase gate sidewall after etching according to the present invention;
[0080] Figure 15 Shown is a schematic diagram of the floating gate after etching of the present invention;
[0081] Figure 16 It is a schematic diagram showing the formation of a source line doping region according to the present invention;
[0082] Figure 17 Shown is a schematic diagram of forming a third sidewall according to the present invention;
[0083] Figure 18 Shown is a schematic diagram of forming the source line polysilicon of the present invention;
[0084] Figure 19 It is a schematic diagram showing the formation of a protection layer on the erase gate according to the present invention;
[0085] Figure 20 Shown is a schematic diagram of a gate structure region forming a memory cell according to the present invention;
[0086] Figure 21 Shown is a schematic diagram of forming a fourth sidewall according to the present invention;
[0087] Figure 22 Shown is a schematic diagram of the device structure prepared by the present invention. DETAILED DESCRIPTION
[0088] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.
[0089] Example 1
[0090] See also Figure 22 The present invention provides a split-gate flash memory, comprising:
[0091] Substrate 101; isolation structure 104; active region; gate stack structure; inner sidewall of erase gate 108; inner sidewall of floating gate 106; source line doped region 112 (VSS); source line polysilicon 115; tunneling dielectric layer 113; select gate 119; gate dielectric layer 118; and bit line doped region 121. Substrate 101 may be, for example, a silicon substrate 101 or other semiconductor substrate 101. Isolation structure 104 disposed within substrate 101 is used to electrically isolate different devices or adjacent active regions.
[0092] In some embodiments, the isolation structure 104 is a shallow trench isolation (STI) structure. For example, an STI structure can be formed by etching a shallow trench in the substrate 101, then filling it with an insulating material (such as silicon oxide) and performing chemical mechanical polishing (CMP). This structure provides good isolation and a small footprint, which helps improve device integration. The active area within the substrate 101 is defined by the isolation structure 104. The active area is the region where the transistor channel and source and drain doping regions are formed.
[0093] The gate stack structure is disposed on a portion of the active area. It includes a floating gate 106; a coupling dielectric layer 105; an inter-electrode dielectric layer 107; and an erase gate 108. A portion of the floating gate 106 is embedded in a trench formed in the substrate 101. Placing a portion of the floating gate 106 within the trench changes the traditional planar structure of the floating gate 106, facilitating the subsequent formation of a three-dimensional coupling structure.
[0094] In some embodiments, the floating gate 106 is made of polysilicon. Other suitable conductive materials, such as doped polysilicon or metal materials, may also be used.
[0095] The coupling dielectric layer 105 is disposed on the sidewalls and bottom of the trench to isolate the floating gate 106 from the substrate 101 . The coupling dielectric layer 105 mainly functions as an electrical insulator to prevent charges stored in the floating gate 106 from leaking into the substrate 101 .
[0096] In some embodiments, the material of coupling dielectric layer 105 is selected from oxides, nitrides, oxynitrides, or combinations thereof. For example, thermally grown silicon oxide or deposited silicon oxide can be used as coupling dielectric layer 105, which has excellent insulation and interface properties. Interelectrode dielectric layer 107 is disposed on top of floating gate 106. Interelectrode dielectric layer 107 is located between floating gate 106 and erase gate 108, allowing electrons to tunnel through this layer during an erase operation.
[0097] In some embodiments, the material of the inter-electrode dielectric layer 107 is selected from oxide, nitride, oxynitride, or a combination thereof. For example, a high-quality silicon oxide layer or a multi-layer composite dielectric structure such as oxide-nitride-oxide (ONO) can be used to optimize charge retention and erase efficiency.
[0098] The erase gate 108 is disposed on the inter-electrode dielectric layer 107. The present invention employs a top erase method, which implements an erase operation by applying a suitable voltage to the erase gate 108, causing electrons to tunnel out of the floating gate 106 through the inter-electrode dielectric layer 107. This top erase method can simplify the design of peripheral circuits compared to traditional source-side or drain-side erase methods.
[0099] In some embodiments, the erase gate 108 is made of polysilicon. The erase gate 108 is used to apply an erase voltage. The upper sidewall of the erase gate 108 (corresponding to the first sidewall 110 in the method) is disposed on the upper surface of the erase gate 108; the inner sidewall of the erase gate 108 (corresponding to the second sidewall 111 in the method) is disposed on the sidewall of the erase gate 108 facing the source line polysilicon 115; and the inner sidewall of the floating gate 106 (corresponding to the third sidewall 114 in the method) is disposed on the sidewall of the floating gate 106 facing the source line polysilicon 115. These inner sidewall structures are formed during the manufacturing process and help precisely define the boundaries of the subsequently formed source line polysilicon 115. They also protect the sidewalls of the erase gate 108 and floating gate 106, ensuring the integrity of the device structure and the stability of its electrical performance.
[0100] In some embodiments, the inner sidewalls of the erase gate 108 and the inner sidewalls of the floating gate 106 are made of a material selected from oxide, nitride, oxynitride, or a combination thereof. For example, silicon nitride can be used as the inner sidewall material, which has a good etching selectivity compared to materials such as silicon oxide, facilitating process control.
[0101] A source line doped region 112 (VSS) is disposed within substrate 101, adjacent to the gate stack structure. This doped region typically serves as the common source of the memory cell array, connected to ground or a specific source voltage. A source line polysilicon 115 is disposed above the source line doped region 112. The source line polysilicon 115 is adjacent to the inner sidewalls of the erase gate 108 and the inner sidewalls of the floating gate 106, and includes a portion adjacent to the floating gate 106. This allows for coupling of the floating gate 106 via the source line doped region 112 and the source line polysilicon 115 during programming of the split-gate flash memory. This is a key feature of the present invention: the source line polysilicon 115 forms a three-dimensional coupling structure with the floating gate 106 disposed within the trench. Compared to conventional planar coupling, this three-dimensional coupling structure increases the effective coupling area and coupling capacitance between the source line (including the doped region and polysilicon portion) and the floating gate 106. Therefore, even if the length of the floating gate 106 in the plane (e.g., the dimension in the channel length direction) is reduced to reduce the cell size, a sufficient coupling coefficient can still be maintained to achieve effective programming operations (e.g., through source side injection (SSI) or FN tunneling). This greatly facilitates further reduction of the flash cell size (Flash cell size shrinkage) and improves storage density.
[0102] In some embodiments, the material of the source line polysilicon 115 includes polysilicon.
[0103] The tunneling dielectric layer 113 is disposed between the sidewalls of the source line polysilicon 115 and the floating gate 116, and may be located on the inner sidewalls and upper sidewalls of the erase gate 108. The tunneling dielectric layer 113 primarily isolates the sidewalls of the source line polysilicon 115 from the erase gate 108, preventing undesirable charge tunneling or leakage between them.
[0104] In some embodiments, the material of the tunnel dielectric layer 113 is selected from oxide, nitride, oxynitride, or a combination thereof.
[0105] The select gate 119 is disposed on the active region and adjacent to the sidewall of the gate stack structure. The select gate 119 (usually controlled by a word line WL) is used to select or inhibit access to the memory cell during read, write, or erase operations.
[0106] In some embodiments, the material of the select gate 119 includes polysilicon.
[0107] In some embodiments, the operating voltage of the select gate 119 is 1 to 2V, for example, 1.5V. Using a lower operating voltage of the select gate 119 (for example, 1.5V) can significantly reduce the dynamic power consumption and static power consumption of the device compared to the higher voltage (such as 2.5V or higher) that may be required by traditional flash memory, which is especially important for power-sensitive applications (such as IoT devices, portable electronic products, etc.). At the same time, a lower operating voltage can simplify the design of peripheral drive circuits and reduce chip cost and area. In addition, a lower read voltage also helps to reduce the read interference (ReadDisturb) effect on adjacent cells, thereby improving the reliability of the device.
[0108] The gate dielectric layer 118 is disposed between the select gate 119 and the active region. The gate dielectric layer 118 is used to isolate the select gate 119 from the channel region below, and its quality directly affects the performance of the select transistor.
[0109] In some embodiments, the material of gate dielectric layer 118 is selected from oxide, nitride, oxynitride, or a combination thereof. For example, high-quality grown silicon oxide or deposited silicon oxide can be used. Bitline doped region 121 is disposed within substrate 101, adjacent to select gate 119. Bitline doped region 121 typically serves as the drain of the memory cell and is connected to a bit line (BL) for data reading and writing.
[0110] In some embodiments, a first outer spacer is disposed on the sidewalls of the structure formed by the gate stack and the source line polysilicon 115; the select gate 119 is formed adjacent to the first outer spacer. This first outer spacer (corresponding to the fourth sidewall 117 in the method) helps precisely control the position of the select gate 119 relative to the gate stack and source line, and also provides isolation.
[0111] In some embodiments, a second outer spacer is disposed on the sidewalls of the select gate 119; the second outer spacer is used to define the formation area of the bitline doping region 121. This second outer spacer (corresponding to the fifth sidewall 120 in the method) is typically used to implement self-aligned bitline doping implantation, which can precisely control the boundaries of the doped region, reduce device size, and improve process repeatability.
[0112] Example 2
[0113] See also Figure 1 The present invention also provides a method for forming a split-gate flash memory, comprising the following steps:
[0114] Step 1: Provide a substrate 101 and form an isolation structure 104 and an active region in the substrate 101 .
[0115] In some embodiments, the isolation structure 104 is a shallow trench isolation (STI) structure. Specifically, a liner oxide layer 102 and a silicon nitride mask layer 103 may be sequentially formed on the substrate 101 to form a structure such as Figure 2 The structure shown in FIG. 1 is formed by etching the pad oxide layer 102 and the silicon nitride mask layer 103 and the substrate 101 thereunder to form a shallow trench. Figure 3 The structure shown in FIG. 1 is then formed by depositing an insulating material (for example, silicon oxide is deposited using a high density plasma chemical vapor deposition (HDP-CVD) method) and performing chemical mechanical polishing (CMP) to form a structure as shown in FIG. Figure 4 Finally, the remaining pad oxide layer 102 and silicon nitride mask layer 103 are removed by etching to form the structure shown in FIG. Figure 5 The active area (AA) can be defined on the substrate 101 by using a photoresist mask and etching process.
[0116] Step 2: forming a trench in a portion of the active area and adjacent to the isolation structure 104, forming a trench as shown in FIG. Figure 6 The depth and shape of the trench can be optimized according to the device design to accommodate a portion of the floating gate 106 and achieve the desired coupling effect.
[0117] Step 3: forming a coupling dielectric layer 105 in the groove, forming Figure 7 The structure shown.
[0118] In some embodiments, the coupling dielectric layer 105 is made of a material selected from oxide, nitride, oxynitride, or a combination thereof and is formed by a deposition process. For example, a layer of silicon oxide may be formed on the inner wall and bottom of the trench by thermal oxidation or chemical vapor deposition (CVD).
[0119] Step 4: depositing a first conductive material in the trench to form a floating gate 106, forming a Figure 8 、 9 The structure shown.
[0120] In some embodiments, the first conductive material includes polysilicon. For example, doped or undoped polysilicon can be deposited by low-pressure chemical vapor deposition (LPCVD), and then the polysilicon outside the trench is removed by a planarization process such as chemical mechanical polishing (CMP), so that the polysilicon fills the trench and forms a flat surface.
[0121] Step 5: forming an inter-electrode dielectric layer 107 on the floating gate 106 .
[0122] In some embodiments, the inter-electrode dielectric layer 107 is made of a material selected from oxides, nitrides, oxynitrides, or combinations thereof, and is formed by a deposition process. For example, a high-quality silicon oxide layer or an oxide / nitride / oxide (ONO) composite layer can be deposited. Controlling the thickness and quality of this layer is crucial for ensuring the device's erase speed and data retention characteristics.
[0123] Step six: deposit a second conductive material on the inter-electrode dielectric layer 107 to form an erase gate 108 .
[0124] In some embodiments, the second conductive material includes polysilicon, and the polysilicon layer can also be deposited by LPCVD or other methods.
[0125] Step 7: forming an opening for accommodating the source line polysilicon 115 and defining a portion of the gate stack, including:
[0126] A hard mask layer 109 is deposited on the erase gate 108 to form a Figure 10 The structure shown;
[0127] The hard mask layer 109 is patterned to form an opening pattern above the erase gate 108, the inter-electrode dielectric layer 107 and the floating gate 106, forming a Figure 11 The structure shown exposes the underlying area;
[0128] A first sidewall 110 is formed on the edge sidewall of the opening pattern. Figure 12 The structure shown;
[0129] Using the patterned hard mask layer 109 and the first sidewall 110 as a mask, the erase gate 108 below the opening pattern is etched to form a Figure 13 After etching, a second sidewall spacer 111 is formed on the erase gate 108 to form a structure as shown; Figure 14 The structure shown;
[0130] Using the patterned hard mask layer 109, the first spacer 110, the second spacer 111, and the etched erase gate 108 as masks, a portion of the exposed floating gate 106 is etched. After etching, a portion of the floating gate 106 is embedded in the trench formed in the substrate 101, forming a structure as shown in FIG15 ;
[0131] Through the etched opening pattern, ions are implanted into the substrate 101 to form a source line doping region 112. Figure 16 The structure shown;
[0132] A sidewall tunnel dielectric layer 113 is formed on the sidewall of the opening pattern; a third sidewall 114 is formed on the bottom and sidewall of the pattern formed after etching, forming a Figure 17The structure shown.
[0133] This complex multi-step process is the key to building the core structure of the present invention. By precisely controlling the hard mask pattern, the formation of multiple sidewalls (first, second, and third sidewalls 114), and step-by-step etching (first etching the erase gate 108, then etching the floating gate 106), a space with a specific contour can be accurately created on the side of the gate stack. Source (VSS) ion implantation is then performed. Next, a sidewall tunneling dielectric layer 113 is deposited for isolation. The third sidewall 114 formed last (ultimately manifested as the inner sidewall of the erase gate 108 and the inner sidewall of the floating gate 106) further defines the cavity for filling the source line polysilicon 115 and protects the formed structure.
[0134] In some embodiments, the source line doping region 112 is formed by an ion implantation process, for example, implanting corresponding types of dopants (such as phosphorus, arsenic, or boron) according to the device design (NMOS or PMOS).
[0135] In some embodiments, the tunnel dielectric layer 113 is made of a material selected from oxide, nitride, oxynitride, or a combination thereof and is formed by a deposition process. For example, a thin layer of silicon oxide or silicon nitride may be deposited to electrically isolate the subsequently formed source line polysilicon 115 from the sidewalls of the erase gate 108.
[0136] In some embodiments, the materials of the first sidewall spacer 110, the second sidewall spacer 111, the third sidewall spacer 114, the fourth sidewall spacer 117 and the fifth sidewall spacer 120 formed in step seven, step ten and step eleven are selected from nitride, oxide or a combination thereof, and are formed by deposition and anisotropic etching. For example, silicon nitride can be used as the sidewall material. By conformally depositing a silicon nitride layer and then performing anisotropic dry etching (such as reactive ion etching RIE), a sidewall structure can be left only on vertical or nearly vertical sidewalls. The width of these sidewalls can be precisely controlled, thereby determining the profile of subsequent etching and the shape of the final source line polysilicon 115.
[0137] Step 8: Form the source line polysilicon 115, forming Figure 18 The structure shown includes depositing a third conductive material and performing a planarization process. The third conductive material fills the area defined by the hard mask layer 109, the tunnel dielectric layer 113, the first spacer 110, the second spacer 111, and the third spacer 114. This step forms the critical source line polysilicon structure 115, whose sides are adjacent to the floating gate 106 portion of the gate stack (through the inner spacer and possible tunnel dielectric layer 113), achieving the required three-dimensional coupling. This structural design allows the floating gate 106 to be reduced in size by increasing the vertical coupling area, ensuring sufficient programming efficiency and being key to further reducing cell size.
[0138] In some embodiments, the third conductive material includes polysilicon. For example, the polysilicon can be deposited by LPCVD and then planarized by CMP to remove excess polysilicon, leaving only the portion within the complex topography region formed in step seven.
[0139] Step 9: Pattern the floating gate 106, inter-electrode dielectric layer 107, erase gate 108, source line polysilicon 115, and overlying layers to define the gate structure area of the memory cell. This step defines the overall gate structure outline of a single memory cell, including the gate stack and the adjacent source line polysilicon 115, paving the way for the subsequent formation of the select gate 119 and bit line.
[0140] In some embodiments, the method of patterning and etching the floating gate 106, the inter-electrode dielectric layer 107, the erase gate 108, the source line polysilicon 115 and the layers covering the same includes: forming a protective layer 116 on the erase gate 108, forming a protective layer 116 as shown in FIG. Figure 19 The structure shown in FIG. 1 , the material of the protective layer 116 can be an oxide; the hard mask layer 109 can be removed by wet etching, and the pattern of the removed hard mask layer 109 is anisotropically etched to form a gate structure region of the memory cell, forming Figure 20 The structure shown.
[0141] The overall process design of the present invention takes into account compatibility with existing mature flash memory process platforms. For example, many steps such as etching, deposition, photolithography, and ion implantation can utilize existing equipment and process modules, reducing the cost and risk of introducing new processes and ensuring good process compatibility.
[0142] Step 10: Forming the select gate 119 includes: forming a fourth spacer 117 on the sidewalls of the gate structure region formed in step 9 to form a structure as shown in FIG21; depositing a gate dielectric layer 118 material and a fourth conductive material; and etching the fourth conductive material and the gate dielectric layer 118 material to form the select gate 119 on the fourth spacer 117 and the gate dielectric layer 118 thereunder. The formation of the fourth spacer 117 (corresponding to the first outer spacer in the structural claims) helps to isolate the gate stack / source line structure from the subsequently formed select gate 119 and controls the size and position of the select gate 119.
[0143] In some embodiments, the fourth spacer 117 formed in step 10 is made of a material selected from nitride, oxide, or a combination thereof, and is formed by deposition and anisotropic etching.
[0144] In some embodiments, the fourth conductive material includes polysilicon. The deposition and etching of the select gate 119 (word line) polysilicon forms the gate electrode of the select transistor.
[0145] In some embodiments, the gate dielectric layer 118 is made of a material selected from oxide, nitride, oxynitride, or a combination thereof and is formed by a deposition process. For example, after forming the fourth sidewall spacer 117, a high-quality gate oxide layer may be grown or deposited before depositing the select gate 119 polysilicon.
[0146] As mentioned above, the select gate 119 designed in the present invention has a low operating voltage (for example, 1.5V), which not only reduces power consumption and simplifies peripheral circuits, but also helps to reduce interference with unselected cells (especially adjacent cells on the same bit line) during read operations, that is, reduces the risk of read disturbance (Read Disturb) and improves the reliability of the memory.
[0147] Step 11: Form a fifth spacer 120 on the sidewall of the select gate 119. The fifth spacer 120 (corresponding to the second outer spacer in the structural claims) is the key to forming a self-aligned source-drain structure.
[0148] In some embodiments, the fifth spacer 120 formed in step 11 is made of a material selected from nitride, oxide, or a combination thereof, and is formed by deposition and anisotropic etching.
[0149] Step 12: Using the select gate 119 and the fifth sidewall 120 as a mask, a bit line doping region 121 is formed in the substrate 101, as shown in FIG. Figure 22 Through the self-aligned masking effect of the select gate 119 and the fifth sidewall 120, a bit line doping region 121 (usually N+ or P+ doping) can be accurately formed in the active area next to the select gate 119, completing the fabrication of the memory cell transistor structure.
[0150] In some embodiments, the bit line doping region 121 is formed by an ion implantation process.
[0151] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.
[0152] In summary, the present invention provides a split-gate flash memory and a method for forming the same. By placing a portion of the floating gate 106 within a trench and forming source line polysilicon on its side, a three-dimensional source-floating gate 106 coupling structure is constructed. This design can effectively reduce the planar size of the floating gate 106 without sacrificing or even optimizing the coupling coefficient, thereby greatly facilitating further reductions in the size of the flash memory cell and improving storage density. At the same time, the use of a top erase mechanism and a lower select gate operating voltage (e.g., 1.5V) helps reduce device power consumption, minimize read interference risks, and simplify peripheral circuit design. In addition, the proposed manufacturing method has good compatibility with existing CMOS or flash memory processes and can be easily integrated into existing production lines. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.
[0153] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.
Claims
1. A split-gate flash memory, characterized in that: include: substrate; an isolation structure disposed within the substrate; an active region disposed in the substrate, the active region being bounded by the isolation structure; A gate stack structure is provided on a portion of the active area, the gate stack structure comprising: a floating gate, a portion of which is embedded in a trench formed in the substrate; a coupling dielectric layer, disposed on the sidewalls and bottom of the trench, isolating the floating gate from the substrate; an inter-electrode dielectric layer, disposed on top of the floating gate; An erase gate is provided on the inter-electrode dielectric layer; An upper sidewall of the erase gate is provided on the upper surface of the erase gate; An inner sidewall of the erase gate is provided on a sidewall of the erase gate facing the polysilicon of the source line; The inner sidewall of the floating gate is arranged on the sidewall of the floating gate facing the polysilicon of the source line; a source line doping region, disposed in the substrate and adjacent to the gate stack structure; The source line polysilicon is disposed above the source line doped region, the source line polysilicon is adjacent to the inner sidewall of the erase gate and the inner sidewall of the floating gate, and has a portion adjacent to the floating gate, so as to couple the floating gate through the source line doped region and the source line polysilicon during programming of the split-gate flash memory; A tunnel dielectric layer is provided between the source line polysilicon and the sidewall of the floating gate, and may be located on the inner sidewall of the erase gate and the surface of the upper sidewall of the erase gate; a select gate disposed on the active region and adjacent to a sidewall of the gate stack structure; a gate dielectric layer, disposed between the select gate and the active region; The bit line doping region is disposed in the substrate and adjacent to the selection gate.
2. The split-gate flash memory according to claim 1, wherein: A first outer spacer is provided on a sidewall of a structure formed by the gate stack structure and the source line polysilicon; and the select gate is formed adjacent to the first outer spacer.
3. The split-gate flash memory according to claim 1 or 2, wherein: A second outer spacer is provided on the sidewall of the selection gate; the second outer spacer is used to define a formation area of the bit line doping region.
4. The split-gate flash memory according to claim 1, wherein: The floating gate, the erase gate, the source line polysilicon, and the select gate are made of polysilicon.
5. The split-gate flash memory according to claim 1, wherein: The coupling dielectric layer, the inter-electrode dielectric layer, the gate dielectric layer, the tunnel dielectric layer, the erase gate upper sidewall, the erase gate inner sidewall and the floating gate inner sidewall are made of materials selected from oxides, nitrides, oxynitrides or combinations thereof.
6. The split-gate flash memory according to claim 1, wherein: The isolation structure is a shallow trench isolation structure.
7. The split-gate flash memory according to claim 1, wherein: The operating voltage of the selection gate is 1 to 2V.
8. The split-gate flash memory according to claim 7, wherein: The operating voltage of the selection gate is 1.5V.
9. A method for manufacturing a split-gate flash memory, characterized in that: include: Step 1: providing a substrate, and forming an isolation structure and an active area in the substrate; Step 2: forming a trench in a portion of the active area and adjacent to the isolation structure; Step 3: forming a coupling dielectric layer in the groove; Step 4: depositing a first conductive material in the trench to form a floating gate; Step 5: forming an inter-electrode dielectric layer on the floating gate; Step 6: depositing a second conductive material on the inter-electrode dielectric layer to form an erase gate; Step 7: forming an opening for accommodating the source line polysilicon and defining a portion of the gate stack, including: depositing a hard mask layer on the erase gate; performing patterning on the hard mask layer to form an opening pattern above the erase gate, the inter-electrode dielectric layer and the floating gate to expose the underlying area; forming a first sidewall on the edge sidewall of the opening pattern; Using the patterned hard mask layer and the first sidewall as masks, etching the erase gate below the opening pattern; forming a second sidewall spacer on the etched sidewall of the erase gate; Using the patterned hard mask layer, the first sidewall spacer, the second sidewall spacer, and the etched erase gate as masks, etching a portion of the exposed floating gate, so that the portion of the floating gate is embedded in the trench formed in the substrate after etching; Performing ion implantation into the substrate through the etched opening pattern to form a source line doping region; forming a tunnel dielectric layer on the sidewalls of the opening pattern; A third sidewall is formed on the bottom and sidewall of the pattern formed after etching; Step eight, forming source line polysilicon, including depositing a third conductive material and performing a planarization process, wherein the third conductive material fills the area defined by the hard mask layer, the tunnel dielectric layer, the first spacer, the second spacer, and the third spacer; Step nine, patterning and etching the floating gate, the inter-electrode dielectric layer, the erase gate, the source line polysilicon, and the layers covering them to define a gate structure region of the memory cell; Step 10: forming a select gate, including: forming a fourth spacer on the sidewall of the gate structure region formed in step nine; depositing a gate dielectric layer material and a fourth conductive material; Etching the fourth conductive material and the gate dielectric layer material to form a select gate and a gate dielectric layer thereunder on the fourth sidewall; Step 11: forming a fifth spacer on the sidewall of the select gate; Step 12: Using the select gate and the fifth sidewall as masks, a bit line doping region is formed in the substrate.
10. The method for manufacturing a split-gate flash memory according to claim 9, wherein: The first conductive material, the second conductive material, the third conductive material, and the fourth conductive material include polysilicon.
11. The method for manufacturing a split-gate flash memory according to claim 9, wherein: The coupling dielectric layer, the inter-electrode dielectric layer, the gate dielectric layer and the tunnel dielectric layer are made of materials selected from oxide, nitride, oxynitride or a combination thereof, and are formed by a deposition process.
12. The method for manufacturing a split-gate flash memory according to claim 9, wherein: The isolation structure is a shallow trench isolation structure, which is formed by etching the substrate to form a shallow trench, then depositing an insulating material and performing chemical mechanical polishing.
13. The method for manufacturing a split-gate flash memory according to claim 9, wherein: The source line doping region and the bit line doping region are formed by an ion implantation process.
14. The method for manufacturing a split-gate flash memory according to claim 9, wherein: The first spacer, the second spacer, the third spacer, the fourth spacer and the fifth spacer formed in step seven, step ten and step eleven are made of a material selected from nitride, oxide or a combination thereof and are formed by deposition and anisotropic etching.
15. The method for manufacturing a split-gate flash memory according to claim 9, wherein: The method of patterning and etching the floating gate, the inter-electrode dielectric layer, the erase gate, the source line polysilicon and the layers covering them in step nine includes: forming a protective layer on the erase gate; removing the hard mask layer, and anisotropically etching the pattern of the removed hard mask layer to form the gate structure area of the storage unit.