Display panel and display device

Abstract

The display panel and the display device provided by the embodiment of the present application, the display panel comprises a display area and a non-display area surrounding the display area at least partially; the display panel further comprises a substrate and a power supply conductive line, the power supply conductive line is located on one side of the substrate, and the power supply conductive line is located in the display area; the power supply conductive line comprises a plurality of first power supply conductive lines and at least one second power supply conductive line; by replacing the first power supply conductive line with the second power supply conductive line, the consistency of the second power supply voltage on the display panel can be improved without adjusting the preparation process of the display panel too much, the voltage difference of the second power supply voltage between the regions of the display panel can be improved, the limitation on the second power supply voltage can be reduced, and a relatively high second power supply voltage can be provided to the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) display technology is considered the most promising next-generation display technology. Compared with liquid crystal display technology, OLED display technology has advantages such as low energy consumption, low cost, self-emissiveness, wide viewing angle, and fast response speed.

[0003] In the traditional OLED display panel manufacturing process, a fine metal mask (FMM) is typically used to pattern the light-emitting pixels. FMM technology is mature and has extensive mass production experience. However, FMM technology also suffers from limitations in precision and high cost. Fine metal maskless technology eliminates the limitations of traditional OLED processes on display size, resolution, and other screen performance characteristics, offering advantages such as high performance, full-size display, and agile delivery. Patents CN117251982A and CN115666161A describe relevant content of fine metal maskless technology for reference.

[0004] However, since current display panels typically achieve electrical connection by connecting ELVSS (Emit Light Voltage Supply for Sub-pixel) traces across the entire cathode area in the bezel region, the ELVSS signal voltage drop of the display panel is relatively large. In order to meet the performance requirements of the product, the ELVSS voltage must be set lower, which leads to an increase in product power consumption. Summary of the Invention

[0005] In order to overcome the technical problems mentioned in the above technical background, this application provides a display panel and display device to solve the problems existing in the prior art.

[0006] A first aspect of this application provides a display panel, including: a display area and a non-display area at least partially surrounding the display area; the display panel further includes: a substrate; power conductive lines located on one side of the substrate and located in the display area, the power conductive lines including a plurality of first power conductive lines and at least one second power conductive line; both the first power conductive lines and the second power conductive lines extend along a first direction, and both the first power conductive lines and the second power conductive lines are sequentially spaced along a second direction, the first direction intersecting the second direction; the first power conductive lines are used to transmit a first power supply voltage, and the second power conductive lines are used to transmit a second power supply voltage, wherein the first power supply voltage is greater than the second power supply voltage.

[0007] In one embodiment, the first power conductive line and the second power conductive line are arranged in the same layer, and the spacing between any two adjacent power conductive lines is equal.

[0008] In one embodiment, the display panel further includes a first power supply line located in the non-display area, the first power supply line being connected to each of the second power conductive lines, the first power supply line being used to transmit the second power supply voltage; the first power supply line at least partially surrounds the display area.

[0009] In one embodiment, the number of first power conductive lines between any two adjacent second power conductive lines is equal.

[0010] In one embodiment, the ratio of the number of the second power conductive lines to the number of the first power conductive lines is between 1:3 and 1:20.

[0011] In one embodiment, the display panel further includes a plurality of third power conductive lines, and two adjacent first power conductive lines located on both sides of the same second power conductive line are connected through the third power conductive lines, wherein the third power conductive lines are located on the side of the second power conductive lines closer to the substrate.

[0012] In one embodiment, the display panel further includes a circuit layer, an isolation structure, and a plurality of light-emitting devices; the circuit layer is located on one side of the substrate, the power supply conductive line is located on the circuit layer, the isolation structure is located on the side of the circuit layer away from the substrate and forms a plurality of isolation openings, and the plurality of light-emitting devices are located on the side of the circuit layer away from the substrate, at least some of the light-emitting devices are located within the isolation openings.

[0013] In one embodiment, the isolation structure includes an isolation portion and a blocking portion stacked along a direction away from the substrate, wherein the orthographic projection of the isolation portion on the substrate is located within the orthographic projection of the blocking portion on the substrate; the display panel further includes a pixel defining layer, the isolation structure is disposed on the pixel defining layer, and the pixel defining layer has a pixel opening communicating with the isolation opening; the isolation structure is electrically connected to the second power conductive line through a first connecting via, the first connecting via penetrating the pixel defining layer.

[0014] In one embodiment, the circuit layer further includes a planarization layer located on the side of the power conductive line away from the substrate; the first connection via penetrates the planarization layer and the pixel defining layer.

[0015] In one embodiment, the display panel further includes a first half-region and a second half-region arranged sequentially along the first direction. The first half-region includes at least one first connection via, and the second half-region includes at least one external power terminal. The second power conductive line is connected to the second power voltage through the external power terminal.

[0016] In one embodiment, the isolation structure further includes a base located on the side of the isolation portion closer to the substrate.

[0017] In one embodiment, the light-emitting device includes a first electrode, a light-emitting structure, and a second electrode stacked along a direction away from the substrate. The first electrode is disposed on the circuit layer, the pixel defining layer covers the edge of the first electrode and exposes the first electrode through the pixel opening, the light-emitting structure is located in the pixel opening and contacts the first electrode, and the second electrode covers the light-emitting structure and is electrically connected to the isolation structure.

[0018] In one embodiment, the display panel further includes a fourth power conductive line, which is disposed on the same layer as the first electrode. The fourth power conductive line is used to transmit the second power voltage and is electrically connected to the isolation structure through a second connection via.

[0019] In one embodiment, the display panel further includes a first encapsulation layer, which includes a plurality of encapsulation portions located on the side of the second electrode away from the circuit layer and extending through the sidewall of the isolation structure to the side of the isolation structure away from the circuit layer; the orthographic projection of the first connection via on the substrate does not overlap with the orthographic projection of the first encapsulation layer on the substrate, and the orthographic projection of the second connection via on the substrate does not overlap with the orthographic projection of the first encapsulation layer on the substrate.

[0020] A second aspect of this application provides a display panel, including: a display area and a non-display area at least partially surrounding the display area; the display panel further includes: a substrate; a light-emitting device located on one side of the substrate and located in the display area, the light-emitting device including a first electrode, a light-emitting structure, and a second electrode stacked along a direction away from the substrate; and a fourth power conductive line for transmitting a second power supply voltage, the fourth power conductive line being disposed in the same layer as the first electrode.

[0021] In one embodiment, the display panel further includes a first power supply line located in the non-display area, the first power supply line being electrically connected to the four power conductive lines, the first power supply line being used to transmit the second power supply voltage; the first power supply line at least partially surrounds the display area.

[0022] In one embodiment, the display panel further includes a circuit layer and an isolation structure; the circuit layer is located on one side of the substrate, the isolation structure is located on the side of the circuit layer away from the substrate, and forms a plurality of isolation openings, a plurality of light-emitting devices are located on one side of the circuit layer, and at least some of the light-emitting devices are located within the isolation openings; the isolation structure is electrically connected to the fourth power conductive line through a second connection via.

[0023] In one embodiment, the display panel further includes a first encapsulation layer, which includes a plurality of encapsulation portions located on the side of the second electrode away from the circuit layer and extending through the sidewall of the isolation structure to the side of the isolation structure away from the circuit layer; the orthographic projection of the second connection via on the substrate does not overlap with the orthographic projection of the first encapsulation layer on the substrate.

[0024] In one embodiment, the display panel further includes a first half-region and a second half-region arranged sequentially along a first direction. The first half-region includes at least one second connection via, and the second half-region includes at least one external power supply terminal. The fourth power supply conductive line is connected to the second power supply voltage through the external power supply terminal.

[0025] A third aspect of this application provides a display device, including the display panel as described above.

[0026] The beneficial effects of this application embodiment compared with the prior art are as follows: when the multiple power conductive lines include multiple first power conductive lines and at least one second power conductive line, by replacing the first power conductive line with the second power conductive line, the consistency of the second power voltage on the display panel can be improved without making too many adjustments to the manufacturing process of the display panel, the voltage difference of the second power voltage between different areas of the display panel can be improved, the limitation on the second power voltage can be reduced, and a relatively high second power voltage can be provided to the display panel. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A schematic diagram of a display panel provided in one embodiment of this application;

[0029] Figure 2This is a schematic diagram of a power supply conductor provided in an embodiment of this application;

[0030] Figure 3 A schematic diagram of a first power supply line provided in an embodiment of this application;

[0031] Figure 4 A cross-sectional schematic diagram of a circuit layer provided in an embodiment of this application;

[0032] Figure 5 A cross-sectional schematic diagram of a display panel provided in an embodiment of this application;

[0033] Figure 6 A schematic diagram of an isolation opening provided in an embodiment of this application;

[0034] Figure 7 This is another cross-sectional schematic diagram of a display panel provided in one embodiment of this application;

[0035] Figure 8 A schematic diagram of an external power supply terminal provided in an embodiment of this application;

[0036] Figure 9 This is another schematic diagram of an external power supply terminal provided in an embodiment of this application;

[0037] Figure 10 This is a cross-sectional schematic diagram of a light-emitting structure provided in an embodiment of this application;

[0038] Figure 11 This is a schematic diagram of a fourth power supply conductor provided in an embodiment of this application;

[0039] Figure 12 This is a schematic diagram of a second power supply conductor provided in an embodiment of this application;

[0040] Figure 13 This is another cross-sectional schematic diagram of a display panel provided in one embodiment of this application;

[0041] Figure 14 This is another cross-sectional schematic diagram of a circuit layer provided in an embodiment of this application;

[0042] Figure 15 A schematic diagram of a pixel circuit provided in an embodiment of this application;

[0043] Figure 16 A flowchart illustrating a method for manufacturing a display panel according to an embodiment of this application;

[0044] Figure 17 A schematic diagram of a display device provided in an embodiment of this application;

[0045] Figure 18 This is a schematic diagram of an electronic device provided in an embodiment of this application.

[0046] Explanation of reference numerals: 10, Display panel; 100, Substrate; 200, Circuit layer; 200a, First insulating layer; 200b, Second insulating layer; 200c, Third insulating layer; 210, Power supply line; 211, First power supply line; 212, Second power supply line; 220, First power supply line; 230, Third power supply line; 240, Fourth power supply line; 250, Planarization layer; 260, Transistor; 271, First connection via; 272, Second connection via; 281, First half-region; 282, Second half-region; 283, External power supply terminal; 300, Isolation structure; 300a, Isolation opening; 300a1, First isolation opening ; 300a2, Second isolation opening; 300a3, Third isolation opening; 310, Blocking portion; 320, Isolation portion; 330, Base; 400, Light-emitting device; 400a, First light-emitting device; 400b, Second light-emitting device; 400c, Third light-emitting device; 410, First electrode; 420, Light-emitting structure; 430, Second electrode; 500, Pixel defining layer; 600, Encapsulation portion; 600a, First encapsulation portion; 600b, Second encapsulation portion; 600c, Third encapsulation portion; 700, Second encapsulation layer; 800, Third encapsulation layer; 20, Display device; 30, Electronic device; 31, Memory; 32, Processor; 33, Computer program. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0048] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0049] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0050] For ease of understanding, the accompanying diagram shows the mutually orthogonal X-axis, Y-axis, and Z-axis. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction relative to the plane containing the X and Y directions. Furthermore, a view where various elements are observed parallel to the plane containing the X and Y directions is called a top view. Alternatively, the planes in the X and Y directions can be planes parallel to the display surface of the display panel, and the Z-direction can be a direction parallel to the thickness direction of the display panel.

[0051] For certain elements, terms like "above" or "overhead" are sometimes used when describing the position of an element in the Z direction, and "below" or "under" are used when describing the position of an element in the opposite direction. Furthermore, when using terms like "above," "overhead," "below," "under," or "relative" to define the positional relationship between two elements, this includes not only the state where the two elements are directly adjacent, but also the state where the two elements are separated by gaps or other elements. Additionally, terms like "first," "second," and "third" are used only for distinguishing descriptions and should not be interpreted as indicating or implying relative importance.

[0052] Currently, traditional display panels typically include ELVSS and ELVDD traces. The display panel can illuminate the corresponding light-emitting devices based on the second power supply voltage provided by the ELVSS traces and the ELVDD voltage provided by the ELVDD traces. ELVSS traces are usually located only at the edges of the display panel, while ELVDD traces, in addition to being located at the edges, typically include multiple sub-traces spaced apart in sequence. Each sub-traces provides ELVDD voltage to a column or row of light-emitting devices. The light-emitting devices on the display panel can be connected to the ELVSS traces via conductive traces to obtain the ELVSS voltage. For the brightness of the light-emitting devices to meet requirements, the ELVSS voltage obtained by the devices needs to be less than a certain voltage threshold.

[0053] In traditional solutions, there is a certain voltage difference between the portion of the ELVSS trace that is close to the voltage source providing the ELVSS voltage and the portion of the ELVSS trace that is far from the external power supply terminal. In order to ensure that the voltage on the ELVSS trace is less than the voltage threshold, the ELVSS voltage provided to the ELVSS trace needs to be further reduced so that the ELVSS voltage on the ELVSS trace is less than the voltage threshold, which ultimately leads to an increase in the overall power consumption of the display panel.

[0054] Figure 1This is a schematic diagram of the structure of a display panel 10 according to one embodiment of this application. The display panel 10 may be an organic light-emitting diode display panel or a quantum dot electroluminescent display panel. The display panel 10 includes a display area AA with display function and a non-display area NA surrounding the display area.

[0055] The display area AA of the display panel 10 can be rectangular, square, circular, oval, or other shapes.

[0056] The display area AA includes a plurality of pixels PX arranged in the X and Y directions. Each pixel PX includes a plurality of sub-pixels SPX displaying different colors. In some embodiments, a pixel PX includes a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. For example, the first sub-pixel SPX1 is a blue sub-pixel, the second sub-pixel SPX2 is a green sub-pixel SPX2, and the third sub-pixel SPX3 is a red sub-pixel SPX3. In some embodiments, in addition to sub-pixels SPX1, SPX2, and SPX3, a pixel PX also includes sub-pixels SPX that emit white or other colors of light.

[0057] A sub-pixel (SPX) includes a pixel circuit and a light-emitting device driven by the pixel circuit to emit light of the corresponding color. The first sub-pixel (SPX1) includes a first light-emitting device, the second sub-pixel (SPX2) includes a second light-emitting device, and the third sub-pixel (SPX3) includes a third light-emitting device. One pixel circuit drives at least one light-emitting device to emit light. For example, the display area AA includes a normal display area and a light-transmitting display area. The light-transmitting display area is a display area set according to a corresponding sensor and has light-transmitting properties, while the normal display area is a display area not set according to a corresponding sensor. In the normal display area, one pixel circuit drives one light-emitting device to emit light, and in the light-transmitting display area, one pixel circuit drives one or more light-emitting devices to emit light.

[0058] like Figure 2 As shown, the display panel 10 includes a substrate 100 and a power conductive line 210, with the power conductive line 210 located on one side of the substrate 100.

[0059] The multiple power conductive lines 210 include multiple first power conductive lines 211 and at least one second power conductive line 212. Both the first power conductive lines 211 and 212 extend along a first direction, and are sequentially spaced along a second direction, with the first and second directions intersecting. The second power conductive line 212 transmits a second power supply voltage, and the first power conductive line 211 transmits a first power supply voltage. The second power supply voltage is lower than the first power supply voltage. Specifically, the first power supply voltage can be an ELVDD voltage, and the second power supply voltage can be an ELVSS voltage.

[0060] It is understood that in the prior art, power conductive lines are typically used only to transmit the first power supply voltage; that is, in the prior art, power conductive lines only include the first power conductive line. In this embodiment, when multiple power conductive lines 210 include multiple first power conductive lines 211 and at least one second power conductive line 212, replacing the first power conductive line 211 with the second power conductive line 212 can improve the consistency of the second power supply voltage on the display panel 10 without making too many adjustments to the manufacturing process of the display panel 10, improve the voltage drop of the second power supply voltage between different areas of the display panel 10, reduce the limitation on the second power supply voltage, and provide a relatively high second power supply voltage to the display panel 10.

[0061] Specifically, substrate 100 may include a glass substrate or a flexible substrate.

[0062] In one embodiment, such as Figure 2 As shown, the first power conductive line 211 and the second power conductive line 212 are arranged in the same layer, and the spacing between any two adjacent power conductive lines 210 is equal.

[0063] Including the first power conductive line 211 and the second power conductive line 212, the synchronous construction of each power conductive line 210 can be achieved during the manufacturing process of the display panel 10.

[0064] By making the spacing between adjacent power conductive lines 210 equal, the distribution of power conductive lines 210 in the display area AA can be made more uniform, avoiding the problem of uneven density of power conductive lines 210 in some areas, which leads to reduced voltage consistency in areas with low density of power conductive lines 210.

[0065] It should be noted that in traditional panels, each power conductive line 210 is usually used to transmit the first power supply voltage. However, in this embodiment, by having some of the power conductive lines 210 transmit the second power supply voltage, the consistency of the second power supply voltage in the display panel 10 can be improved without adding extra steps. This eliminates the need to set an excessively low second power supply voltage and achieves the effect of increasing the upper limit of the second power supply voltage.

[0066] In one embodiment, such as Figure 3 As shown, the display panel 10 also includes a first power supply line 220 located in the non-display area. The first power supply line 220 is connected to each of the second power conductive lines 212 and is used to transmit the second power supply voltage. The first power supply line 220 at least partially surrounds the display area.

[0067] The first power supply line 220 can connect all the second power supply conductors 212 to balance the second power supply voltage on each second power supply conductor 212. The specific layout of the first power supply line 220 can be set according to actual needs.

[0068] The connection between the first power supply line 220 and the external circuit can be configured according to actual needs. For example, the first power supply line 220 can also be connected to an external power source or a grounded metal layer to obtain a second power supply voltage.

[0069] In some embodiments, the display panel 10 further includes a second power supply line located in a non-display area, the second power supply line being connected to each of the first power conductive lines 211 and used to provide a first power supply voltage to the first power conductive lines 211.

[0070] The second power supply line can be connected to an external power source to obtain the first power supply voltage.

[0071] In one embodiment, the first power supply line 220 includes a first power supply line and a second power supply line, both of which extend along a second direction. The first power supply line, the display area, and the second power supply line are arranged sequentially at intervals along a first direction.

[0072] It is understandable that one of the first power supply line and the second power supply line can be connected to the power supply via an external terminal to obtain the second power supply voltage. When one power supply line is connected to the external terminal, the other power supply line is the far end of the first power supply line 220. Connecting the two ends of the second power supply conductive line 212 to the first power supply line and the second power supply line respectively can reduce the voltage difference between the first power supply line and the second power supply line, improve the voltage drop on the first power supply line 220, and thus allow the power supply to provide a relatively high second power supply voltage to the display panel 10, thereby meeting the requirement for the second power supply voltage.

[0073] In some embodiments, the second power supply line is used to connect to the grounded metal layer to directly obtain the second power supply voltage. The first power supply line is the far end of the first power supply line 220. The first power supply line can obtain the second power supply voltage from the second power supply line through the second power supply conductive line 212. Connecting the two ends of the second power supply conductive line 212 to the first power supply line and the second power supply line respectively can reduce the voltage difference between the first power supply line and the second power supply line.

[0074] In one embodiment, the number of first power conductive lines 211 between any two adjacent second power conductive lines 212 is equal.

[0075] It is understandable that when multiple power conductive lines 210 include multiple second power conductive lines 212, and the number of first power conductive lines 211 between adjacent second power conductive lines 212 is equal, each second power conductive line 212 is set separately, that is, at least one high-voltage conductive line is provided between two adjacent second power conductive lines 212.

[0076] By ensuring that the number of first power conductive lines 211 between adjacent second power conductive lines 212 is equal, the distribution of first power conductive lines 211 and second power conductive lines 212 in the display area AA can be made more uniform. This avoids the problem of reduced voltage consistency in areas where the density of first power conductive lines 211 and / or the density of second power conductive lines 212 is uneven, which leads to areas with excessively low density of first power conductive lines 211 and / or second power conductive lines 212.

[0077] In one embodiment, the ratio of the number of second power conductive lines 212 to the number of first power conductive lines 211 is between 1:3 and 1:20.

[0078] Understandably, the larger the ratio, the higher the proportion of the second power conductive line 212 among the multiple power conductive lines 210, and the higher the consistency of the second power supply voltage in the display panel 10. Conversely, the lower the proportion of the first power conductive line 211 among the multiple power conductive lines 210, and the lower the consistency of the first power supply voltage in the display panel 10. Similarly, the smaller the ratio, the lower the proportion of the second power conductive line 212 among the multiple power conductive lines 210, and the lower the consistency of the second power supply voltage in the display panel 10. Conversely, the higher the proportion of the first power conductive line 211 among the multiple power conductive lines 210, and the higher the consistency of the first power supply voltage in the display panel 10.

[0079] Therefore, the ratio of the number of second power supply conductive lines 212 to the number of first power supply conductive lines 211 needs to be set according to actual needs, that is, according to the consistency requirements for the first power supply voltage and the consistency requirements for the second power supply voltage.

[0080] In one embodiment, three first power conductive lines 211 are provided between each adjacent second power conductive line 212.

[0081] Understandably, having three first power conductive lines 211 between adjacent second power conductive lines 212 ensures a 1:3 ratio between the number of second power conductive lines 212 and the number of first power conductive lines 211. In this configuration, the second power conductive lines 212 have the highest proportion among the multiple power conductive lines 210, resulting in the highest consistency of the second power supply voltage across the display panel 10. Conversely, the first power conductive lines 211 have a lower proportion among the multiple power conductive lines 210, leading to lower consistency of the first power supply voltage across the display panel 10.

[0082] In one embodiment, such as Figure 4 As shown, the display panel 10 also includes multiple third power conductive lines 230, and two adjacent first power conductive lines 211 located on both sides of the same second power conductive line 212 are connected by the third power conductive lines 230. The third power conductive lines 230 are located on the side of the second power conductive line 212 closer to the substrate 100.

[0083] It should be noted that connecting two first power conductors 211 located on both sides of the same second power conductor 212 via multiple third power conductors 230 can improve the consistency of the first power supply voltage between the two first power conductors 211 located on both sides of the same second power conductor 212. Simultaneously, the third power conductors 230 can replace the replaced first power conductors 211 to transmit the first power supply voltage to the corresponding circuit.

[0084] In one embodiment, such as Figure 4 As shown, the circuit layer 200 includes a first insulating layer 200a, a second insulating layer 200b, and a third insulating layer 200c, which are stacked sequentially along a direction away from the substrate 100. Each first power conductive line 211, each third power conductive line 230, and each second power conductive line 212 can be respectively disposed on the corresponding insulating layer according to actual needs.

[0085] The insulating layer may include at least one of inorganic insulating layers and organic insulating layers.

[0086] In some embodiments, each first power conductive line 211 and each second power conductive line 212 can be disposed between the second insulating layer 200b and the third insulating layer 200c, and the third power conductive line 230 can be disposed between the first insulating layer 200a and the second insulating layer 200b, that is, the third power conductive line 230 is located on the side of the second power conductive line 212 closer to the substrate 100. The third power conductive line 230 can be electrically connected to the first power conductive line 211 through a corresponding via. It is understood that two first power conductive lines 211 located on both sides of the same second power conductive line 212 can be connected by the third power conductive line 230 bypassing the second power conductive line 212.

[0087] In some embodiments, each first power conductive line 211 and each second power conductive line 212 can be disposed between the first insulating layer 200a and the second insulating layer 200b, and the third power conductive line 230 can be disposed between the second insulating layer 200b and the third insulating layer 200c, that is, the third power conductive line 230 is located on the side of the second power conductive line 212 away from the substrate 100. The position of each power conductive line in the circuit layer 200 can be set according to actual needs.

[0088] In one embodiment, such as Figure 5 As shown, the display panel 10 also includes a circuit layer 200, an isolation structure 300, and multiple light-emitting devices 400.

[0089] The circuit layer 200 is located on one side of the substrate 100, the power conductive line 210 is located on the circuit layer 200, the isolation structure 300 is located on the side of the circuit layer 200 away from the substrate 100, and forms a plurality of isolation openings 300a, a plurality of light-emitting devices 400 are located on the side of the circuit layer 200 away from the substrate 100, and at least some of the light-emitting devices 400 are located within the isolation openings 300a; the isolation structure 300 is electrically connected to the second power conductive line 212.

[0090] By setting an isolation structure 300 at the gap between the light-emitting devices 400, the functional film layers of adjacent light-emitting devices 400 are separated. Thus, in the evaporation process of multiple functional film layers, it is only necessary to perform evaporation on the entire display panel 10, without using a mask to evaporate the area where the light-emitting devices 400 are located to form the functional film layer. Therefore, the evaporation process using the isolation structure 300 does not need to consider the alignment accuracy problem during evaporation, thereby allowing the gap between the light-emitting devices 400 to be designed to be smaller, thereby increasing the pixel density.

[0091] refer to Figure 5 and Figure 6An isolation structure 300 is located on one side of the circuit layer 200 and encloses multiple isolation openings 300a. These multiple isolation openings 300a include multiple first isolation openings 300a1, multiple second isolation openings 300a2, and multiple third isolation openings 300a3. Multiple light-emitting devices 400 are located on one side of the circuit layer 200 and include multiple first light-emitting devices 400a, multiple second light-emitting devices 400b, and multiple third light-emitting devices 400c. The first light-emitting devices 400a are positioned corresponding to the first isolation openings 300a1, the second light-emitting devices 400b are positioned corresponding to the second isolation openings 300a2, and the third light-emitting devices 400c are positioned corresponding to the third isolation openings 300a3.

[0092] Specifically, the light-emitting colors of the first light-emitting device 400a, the second light-emitting device 400b, and the third light-emitting device 400c can be red, green, and blue, respectively.

[0093] In one embodiment, a light-emitting device 400 is correspondingly disposed with an isolation opening 300a. For example, a first light-emitting device 400a is correspondingly disposed with a first isolation opening 300a1, a second light-emitting device 400b is correspondingly disposed with a second isolation opening 300a2, and a third light-emitting device 400c is correspondingly disposed with a third isolation opening 300a3. At least a portion of the first light-emitting device 400a is disposed within the corresponding first isolation opening 300a1, at least a portion of the second light-emitting device 400b is disposed within the corresponding second isolation opening 300a2, and at least a portion of the third light-emitting device 400c is disposed within the corresponding third isolation opening 300a3.

[0094] In another embodiment, multiple light-emitting devices 400 are correspondingly arranged with an isolation opening 300a. For example, multiple light-emitting devices 400 with the same light emission color are corresponding to an isolation opening 300a.

[0095] The specific number of light-emitting devices 400 in an isolation opening 300a can be set according to actual needs.

[0096] In one embodiment, such as Figure 5 As shown, the isolation structure 300 includes an isolation portion 320 and a blocking portion 310 stacked in a direction away from the substrate 100. The orthographic projection of the isolation portion 320 on the substrate 100 is located within the orthographic projection of the blocking portion 310 on the substrate 100, that is, the width of the blocking portion 310 is greater than the width of the isolation portion 320.

[0097] Therefore, the two ends of the blocking portion 310 protrude compared to the sides of the isolation portion 320, and this isolation structure 300 is also referred to as a hanging shape. The isolation portion 320 and the blocking portion 310 are made of different materials, and the etching rate of the blocking portion 310 is lower than that of the isolation portion 320. The material of the isolation portion 320 includes conductive materials, specifically including at least one of aluminum and aluminum alloys. The aluminum alloy may include at least one of aluminum-neodymium alloy, aluminum-yttrium alloy, or aluminum-silicon alloy. The blocking portion 310 can be a single-layer structure or a multi-layer structure. When the blocking portion 310 is a single-layer structure, the material of the blocking portion 310 may include at least one of titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy, or molybdenum-niobium alloy. When the blocking portion 310 is a multi-layer structure, one layer of the blocking portion 310 is made of at least one of titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy, or molybdenum-niobium alloy, and the other layer of the blocking portion 310 may be made of conductive oxide or inorganic insulating material. The conductive oxide is, for example, indium tin oxide or indium zinc oxide.

[0098] The isolation section 320 not only provides physical isolation through the isolation opening 300a, but also allows for the transmission of a second power supply voltage.

[0099] In some embodiments, reference Figure 7 The isolation structure 300 may further include a base 330 located on the side of the isolation portion 320 near the substrate 100. The base 330 protrudes relative to the isolation portion 320 in a direction toward the isolation opening 300a, and the orthographic projection of the isolation portion 320 on the substrate 100 lies within the orthographic projection of the base 330 on the substrate 100. The material of the base 330 may include at least one of molybdenum, titanium, titanium nitride, molybdenum-tungsten alloy, or molybdenum-niobium alloy.

[0100] Compared to the isolation part 320 made of aluminum or aluminum alloy, the base part 330 can be more firmly attached to the circuit layer 200, improving the stability of the isolation structure 300, reducing the probability of the isolation structure 300 falling off the circuit layer 200, and improving the product yield.

[0101] In one embodiment, reference Figure 5 and Figure 7 The display panel 10 also includes a pixel limiting layer 500, an isolation structure 300 disposed on the pixel limiting layer 500, and the pixel limiting layer 500 having a pixel opening communicating with the isolation opening 300a.

[0102] Specifically, the pixel defining layer 500 is provided with a first pixel opening communicating with a first isolation opening 300a1, a second pixel opening communicating with a second isolation opening 300a2, and a third pixel opening communicating with a third isolation opening 300a3. The areas of the orthographic projections of the first pixel opening, the second pixel opening, and the third pixel opening on the substrate 100 may be the same or different. The shapes of the orthographic projections of the pixel openings and the corresponding isolation openings 300a on the substrate 100 may be the same or different. Generally, the area of ​​the orthographic projection of the isolation opening 300a on the substrate 100 is larger than the area of ​​the orthographic projection of the pixel opening communicating with the isolation opening 300a on the substrate 100. The orthographic projections of the pixel openings of the light-emitting device 400 on the substrate 100 overlap with the orthographic projections of the isolation openings 300a on the substrate 100. The pixel defining layer 500 is made of an inorganic material, such as an inorganic insulating material formed using at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0103] In another embodiment, the isolation structure 300 is disposed within the recess of the pixel limiting layer 500. Alternatively, the pixel limiting layer 500 may not be provided in the display panel 10, and the isolation structure 300 may be disposed on one side of the circuit layer 200, with the isolation structure 300 in contact with one side of the circuit layer 200.

[0104] In one embodiment, the isolation structure 300 is electrically connected to the second power conductive line 212 through a first connection via 271, which penetrates the pixel limiting layer 500.

[0105] The second power supply conductor 212 can transmit the second power supply voltage to the isolation structure 300 through the first connection via 271, thereby improving the problem of excessive voltage drop on the isolation structure 300.

[0106] In one embodiment, such as Figure 4 As shown, the circuit layer 200 also includes a planarization layer 250, which is located on the side of the power conductive line 210 away from the substrate 100.

[0107] The planarization layer 250 can provide a relatively flat surface to facilitate the construction of structures such as the light-emitting device 400 and the pixel defining layer 500 on the planarization layer 250.

[0108] The first connection via 271 can simultaneously penetrate the planarization layer 250 and the pixel limiting layer 500, thereby realizing the electrical connection between the isolation structure 300 and the second power conductive line 212.

[0109] In one embodiment, such as Figure 8 , Figure 12As shown, the display panel 10 also includes a first half-region 281 and a second half-region 282 arranged sequentially along a first direction. The first half-region 281 includes at least one first connection via 271, and the second half-region 282 includes at least one external power terminal 283. The second power conductive line 212 is connected to the second power supply voltage through the external power terminal 283.

[0110] Specifically, the first half-area 281 may refer to the upper half-area of ​​the display panel 10, and the second half-area 282 may refer to the lower half-area of ​​the display panel 10. The external circuit may specifically include a power supply circuit.

[0111] It is understood that one power supply terminal 283 can be electrically connected to multiple second power supply conductors 212 simultaneously. An external circuit can transmit the second power supply voltage to the power supply terminal 283, and then the power supply terminal 283 transmits the second power supply voltage to each of the second power supply conductors 212. The power supply terminal 283 may specifically include conductive structures such as solder pads or metal contacts.

[0112] It should be noted that when the external power supply terminal 283 is located in the second half-zone 282, there will be a certain voltage difference between the isolation structure 300 located in the first half-zone 281 and the isolation structure 300 located in the second half-zone 282. The second power supply voltage is transmitted to the isolation structure 300 located in the first half-zone 281 through the second power supply conductive line 212 and the first connection via 271, which can improve the problem of excessive voltage drop on the isolation structure 300.

[0113] In some embodiments, the external power supply terminal 283 may also be electrically connected to the first power supply line 220 to transmit the second power supply voltage to the first power supply line 220.

[0114] In some embodiments, when the second power supply voltage provided by an external circuit is received by the power supply external terminal 283 located in the second half-region 282, the first connection via 271 may be provided only in the first half-region 281 to maximize the uniformity of the second power supply voltage on the isolation structure 300 while minimizing the number of first connection vias 271.

[0115] In some embodiments, the first connection via 271 may also be provided only at the end of the second power conductor 212 away from the external power terminal 283, in order to specifically optimize the voltage drop on the isolation structure 300 away from the external power terminal 283.

[0116] In some embodiments, the first half-region 281 and the second half-region 282 may both be provided with a first connection via 271 to further improve the uniformity of the second power supply voltage on the isolation structure 300.

[0117] In one embodiment, reference Figure 5 and Figure 7 The light-emitting device 400 includes a first electrode 410, a light-emitting structure 420, and a second electrode 430 stacked along a direction away from the substrate 100. The first electrode 410 is disposed on the circuit layer 200. The pixel limiting layer 500 covers the first electrode 410 and exposes the first electrode 410 through a pixel opening. The light-emitting structure 420 is located in the pixel opening and is in contact with the first electrode 410. The second electrode 430 covers the light-emitting structure 420 and is electrically connected to the isolation structure 300.

[0118] Specifically, the first light-emitting device 400a, the second light-emitting device 400b, and the third light-emitting device 400c emit light of different colors. Each of the three devices includes a first electrode 410, a light-emitting structure 420, and a second electrode 430 stacked along a direction away from the substrate 100. The first electrode 410 is disposed above the circuit layer 200, and a pixel defining layer 500 covers the end of the first electrode 410. A pixel opening is provided on the pixel defining layer 500, through which the first electrode 410 is exposed. The light-emitting structure 420 of the first light-emitting device 400a, the second light-emitting device 400b, and the third light-emitting device 400c covers the sidewall of the pixel opening of the pixel defining layer 500 and the side of the pixel defining layer 500 facing away from the substrate 100. Each light-emitting structure 420 is located within the pixel opening and is in contact with the first electrode 410.

[0119] The second electrodes 430 of the first light-emitting device 400a, the second light-emitting device 400b, and the third light-emitting device 400c respectively cover the corresponding light-emitting structure 420. The second electrodes 430 are electrically connected to the isolation structure 300. For example, the second electrodes 430 are connected to the isolation portion 320 of the isolation structure 300, and / or the second electrodes 430 are connected to the base portion 330 of the isolation structure 300.

[0120] The first electrode 410 can be an anode, and the second electrode 430 can be a cathode. The first electrode 410 of each light-emitting device 400 can be connected to the pixel circuit through a via, so that the pixel circuit drives the light-emitting device 400 to emit light.

[0121] The first electrode 410 may include a multilayer structure, such as a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. The reflective layer can be formed, for example, using silver, a metallic material with excellent light reflectivity. Each conductive oxide layer can be formed, for example, using a transparent conductive oxide such as ITO, IZO, or IGZO. The second electrode 430 is formed, for example, using a metallic material such as an alloy of magnesium and silver.

[0122] Figure 10This is a schematic diagram of a light-emitting structure 420 according to one embodiment of this application. The light-emitting structure 420 of at least one of the first light-emitting device 400a, the second light-emitting device 400b, and the third light-emitting device 400c includes a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a light-emitting material layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL stacked along a direction away from the substrate 100. The light-emitting structure 420 may include one light-emitting material layer EML, or a stacked light-emitting structure 420 including multiple light-emitting material layers EML.

[0123] In order for the light-emitting structure 420 to emit light, a driving current is provided to the first electrode 410 and a second power supply voltage is provided to the second electrode 430, respectively, forming a potential difference between the first electrode 410 and the second electrode 430, so that the light-emitting structure 420 disposed between the first electrode 410 and the second electrode 430 emits light. In one embodiment, if a potential difference is formed between the first electrode 410 and the second electrode 430 of the first light-emitting device 400a, the light-emitting material layer EML of the light-emitting structure 420 emits blue light; if a potential difference is formed between the first electrode 410 and the second electrode 430 of the second light-emitting device 400b, the light-emitting material layer EML of the light-emitting structure 420 emits green light; and if a potential difference is formed between the first electrode 410 and the second electrode 430 of the third light-emitting device 400c, the light-emitting material layer EML of the light-emitting structure 420 emits red light.

[0124] In this configuration, the driving current of the first electrode 410 is provided by the pixel circuit, and the second power supply voltage of the second electrode 430 is provided by the isolation structure 300. Specifically, the second electrode 430 is electrically connected to the isolation structure 300, and by providing the second power supply voltage to the isolation structure 300, the second power supply voltage is supplied to the second electrode 430. That is, the isolation structure 300 has the function of supplying the second power supply voltage to the second electrode 430.

[0125] In one embodiment, the circuit layer 200 further includes a plurality of pixel circuits electrically connected to the first power supply conductive line 211, and the pixel circuits are used to provide driving current to each light-emitting device 400.

[0126] Specifically, a pixel circuit can be used to drive a light-emitting device 400. The pixel circuit can control the brightness of the light-emitting device 400 by controlling the magnitude of the driving current. Based on the first power supply voltage provided by the first power supply conductor 211, the pixel circuit generates and outputs a driving current according to the received data signal and scan signal. This driving current can be used to illuminate the light-emitting device 400. By controlling whether to provide driving current to the light-emitting device 400, the illumination of the light-emitting device 400 can be controlled. By controlling the magnitude of the driving current, the brightness of the light-emitting device 400 can be controlled.

[0127] In one embodiment, such as Figure 4 As shown, multiple pixel circuits are arranged in a matrix, with a column of pixel circuits arranged sequentially along the first direction and a row of pixel circuits arranged sequentially along the second direction.

[0128] One power conductive line 210 corresponds to one column of pixel circuits, and the orthographic projection of the pixel circuit on the substrate 100 at least partially overlaps with the orthographic projection of the corresponding power conductive line 210 on the substrate 100.

[0129] Specifically, the orthographic projection of the power supply conductor 210 onto the substrate 100 can at least partially overlap with the orthographic projection of the gate of the transistor in the pixel circuit onto the substrate 100. It is understood that, since the voltage of the power supply conductor 210 is relatively stable, the influence of external electromagnetic signals on the transistor can be reduced.

[0130] The pixel circuits can be all set in the display area AA to facilitate connection with the corresponding light-emitting device 400.

[0131] Pixel circuits that at least partially overlap with the orthographic projection of the first power conductive line 211 on the substrate 100 can be connected to the first power conductive line 211 to obtain a first power supply voltage. Pixel circuits that at least partially overlap with the orthographic projection of the second power conductive line 212 on the substrate 100 can be connected to the nearest third power conductive line 230 to obtain a first power supply voltage. The third power conductive line 230, while connecting the two first power conductive lines 211 located on both sides of the same second power conductive line 212, can transmit the first power supply voltage to the pixel sub-circuit corresponding to the second power conductive line 212.

[0132] Preferably, the number of third power conductive lines 230 located between two first power conductive lines 211 on both sides of the same second power conductive line 212 is equal to the number of a column of pixel sub-circuits, and the third power conductive lines 230 correspond one-to-one with the pixel sub-circuits. That is, the number of third power conductive lines 230 located between two first power conductive lines 211 on both sides of the same second power conductive line 212 is equal to the number of rows of pixel sub-circuits.

[0133] In one embodiment, such as Figure 11 As shown, the display panel 10 also includes a fourth power conductive line 240, which is disposed on the same layer as the first electrode 410 and is used to transmit the second power supply voltage.

[0134] In one embodiment, the first power supply line 220 is also electrically connected to the fourth power supply conductor line 240.

[0135] Specifically, the first power supply line 220 can be electrically connected to the fourth power supply line 240 through a via, and the first power supply line 220 can provide a second power supply voltage to the fourth power supply line 240.

[0136] In some embodiments, the fourth power conductive line 240 is electrically connected to the isolation structure 300 through the second connection via 272.

[0137] By transmitting the second power supply voltage through the fourth power supply conductor 240, the voltage drop across the isolation structure 300 can be further reduced, resulting in higher consistency of the second power supply voltage across the isolation structure 300.

[0138] In some embodiments, the orthographic projection of the fourth power conductive line 240 on the substrate 100 lies within the orthographic projection of the isolation structure 300 on the substrate 100.

[0139] The specific layout of the fourth power conductor 240 can be set according to actual needs.

[0140] For example, in some embodiments, the fourth power conductive line 240 extends along a second direction, and multiple fourth power conductive lines 240 are arranged sequentially at intervals along a first direction. In some embodiments, the fourth power conductive lines 240 are distributed in a mesh pattern in the circuit layer 200. In some embodiments, the orthographic projection of the fourth power conductive line 240 on the substrate 100 completely coincides with the orthographic projection of the isolation structure 300 on the substrate 100.

[0141] like Figure 5 As shown, the display panel 10 further includes a first encapsulation layer, which includes a plurality of encapsulation portions 600. Each encapsulation portion 600 is located on the side of the second electrode 430 facing away from the circuit layer 200, and extends through the sidewall of the isolation structure 300 to the side of the isolation structure 300 facing away from the circuit layer 200. The plurality of encapsulation portions 600 includes a plurality of first encapsulation portions 600a corresponding to a plurality of first light-emitting devices 400a, a plurality of second encapsulation portions 600b corresponding to a plurality of second light-emitting devices 400b, and a plurality of third encapsulation portions 600c corresponding to a plurality of third light-emitting devices 400c. The first encapsulation portion 600a is disposed on the side of the corresponding first light-emitting device 400a facing away from the circuit layer 200, the second encapsulation portion 600b is disposed on the side of the corresponding second light-emitting device 400b facing away from the circuit layer 200, and the third encapsulation portion 600c is disposed on the side of the corresponding third light-emitting device 400c facing away from the circuit layer 200.

[0142] In one embodiment, such as Figure 12As shown, the orthographic projection of the first connection via 271 on the substrate 100 does not overlap with the orthographic projection of the first encapsulation layer on the substrate 100. When the display panel 10 is provided with an isolation structure 300, the second power conductive line 212 can be electrically connected to the isolation structure 300 through one or more of the first connection vias 271.

[0143] The first power supply line 220 and the second power supply conductor 212 can transmit the second power supply voltage to the isolation structure 300, which in turn can supply the second power supply voltage to each light-emitting device 400. The position of the first connecting via 271 can be set according to actual needs. For example, the position and number of the first connecting via 271 can be set according to the voltage drop changes on the isolation structure 300 to optimize the voltage drop on the isolation structure 300 and improve the consistency of the second power supply voltage on the isolation structure 300.

[0144] By ensuring that the orthographic projection of the first connection via 271 on the substrate 100 does not overlap with the orthographic projection of the first encapsulation layer on the substrate 100, the first connection via 271 can avoid affecting the structure of the first encapsulation layer and causing the first encapsulation layer to break.

[0145] In one embodiment, such as Figure 11 As shown, the orthographic projection of the second connection via 272 on the substrate 100 does not overlap with the orthographic projection of the first encapsulation layer on the substrate 100, so as to avoid the second connection via 272 and the first encapsulation layer from overlapping each other. This can prevent the second connection via 272 from affecting the structure of the first encapsulation layer and causing the first encapsulation layer to break.

[0146] In one embodiment, such as Figure 9 , Figure 11 As shown, the first half-region 281 includes at least one second connection via 272, and the fourth power supply conductor 240 is connected to the second power supply voltage through the power supply external terminal 283.

[0147] It is understood that one power supply terminal 283 can be electrically connected to multiple fourth power supply conductors 240 simultaneously. An external circuit can transmit a second power supply voltage to the power supply terminal 283, and then the power supply terminal 283 transmits the second power supply voltage to each of the fourth power supply conductors 240. The power supply terminal 283 may specifically include conductive structures such as solder pads or metal contacts.

[0148] It should be noted that when the external power supply terminal 283 is located in the second half-zone 282, there will be a certain voltage difference between the isolation structure 300 located in the first half-zone 281 and the isolation structure 300 located in the second half-zone 282. The second power supply voltage is transmitted to the isolation structure 300 located in the first half-zone 281 through the fourth power supply conductive line 240 and the second connection via 272, which can improve the problem of excessive voltage drop on the isolation structure 300.

[0149] In some embodiments, when the second power supply voltage provided by an external circuit is received by the power supply external terminal 283 located in the second half-region 282, the second connection via 272 may be provided only in the first half-region 281 to maximize the uniformity of the second power supply voltage on the isolation structure 300 while minimizing the number of second connection vias 272.

[0150] In some embodiments, the second connection via 272 may also be provided only at the end of the fourth power conductor 240 away from the power external terminal 283, in order to specifically optimize the voltage drop on the isolation structure 300 away from the power external terminal 283.

[0151] In some embodiments, the first half-region 281 and the second half-region 282 may both be provided with a second connection via 272 to further improve the uniformity of the second power supply voltage on the isolation structure 300.

[0152] like Figure 13 As shown, the display panel 10 further includes a second encapsulation layer 700 and a third encapsulation layer 800. The second encapsulation layer 700 covers the isolation structure 300 and the encapsulation portion 600, and the third encapsulation layer 800 covers the second encapsulation layer 700. Both the first and third encapsulation layers 800 are inorganic materials, and the materials of the first and third encapsulation layers 800 include at least one of silicon nitride, silicon oxide, and silicon oxynitride (SiON). The second encapsulation layer 700 is an organic insulating material, such as epoxy resin, acrylic resin, or other resin materials. The second and third encapsulation layers 700 are continuously disposed at least over the entire display area AA, with a portion also disposed in the non-display area NA.

[0153] The display panel 10 may also include at least one film layer such as a touch layer, a polarizer, a color filter substrate, and a protective cover. This film layer may also be bonded to the display panel 10 via an adhesive layer such as OCA.

[0154] Figure 14 The diagram shows a transistor 260 in the pixel circuit. The first electrode 410 can be electrically connected to the transistor 260 through a via in the planarization layer 250. Furthermore, the circuit layer 200 also includes scan lines providing the scan signal Scan and data lines providing the data signal Data to the pixel circuit.

[0155] refer to Figure 15 The pixel circuit includes a driving transistor T1 and a data transistor T2. The source of the data transistor T2 is connected to the data line that provides the data signal Data, the gate of the data transistor T2 is connected to the scan line that provides the scan signal Scan, and the drain of the data transistor T2 is connected to the gate of the driving transistor T1. The two ends of the storage capacitor C1 are respectively connected to the gate and the source of the driving transistor T1, and the drain of the driving transistor T1 is connected to the light-emitting device 400. Figure 15 This is one implementation of a pixel circuit; the pixel circuit described in this application is not limited to... Figure 15 The 2T1C pixel circuit shown can also be other pixel circuits, such as 7T1C, 8T1C pixel circuits, etc.

[0156] The manufacturing method of the display panel 10 according to the embodiments of this application will be described below.

[0157] refer to Figure 16 The manufacturing method of the display panel 10 includes steps S11 to S15.

[0158] Step S11: Provide circuit layer 200.

[0159] Step S12: An isolation structure 300 is formed on one side of the circuit layer 200. The isolation structure 300 is provided with a plurality of isolation openings 300a, including a plurality of first isolation openings 300a1, a plurality of second isolation openings 300a2 and a plurality of third isolation openings 300a3.

[0160] Step S13: Fabricate the film layer of the first light-emitting device 400a. The film layer of the first light-emitting device 400a includes the light-emitting structure layer of the first light-emitting device 400a and the second electrode layer.

[0161] Step S14: Fabricate the first encapsulation layer of the first light-emitting device 400a. Since the film layer and the first encapsulation layer of the first light-emitting device 400a are both fabricated as a single layer, the film layer and the first encapsulation layer of the first light-emitting device 400a are present at the positions of the multiple first isolation openings 300a1, the multiple second isolation openings 300a2, and the multiple third isolation openings 300a3.

[0162] Step S15: Etch away the film layer and the first encapsulation layer of the first light-emitting device 400a at the locations of the plurality of second isolation openings 300a2 and the plurality of third isolation openings 300a3, thereby forming the light-emitting structure 420 and the second electrode 430 of the first light-emitting device 400a, as well as the first encapsulation portion 600a of the first light-emitting device 400a, only at the locations of the plurality of first isolation openings 300a1.

[0163] Based on the above steps S13 to S15, the light-emitting structure 420 and the second electrode 430 of the second light-emitting device 400b and the second encapsulation part 600b of the second light-emitting device 400b are respectively provided at the positions of multiple second isolation openings 300a2, and the light-emitting structure 420 and the second electrode 430 of the third light-emitting device 400c and the third encapsulation part 600c of the third light-emitting device 400c are respectively provided at the positions of multiple third isolation openings 300a3.

[0164] In one embodiment, step S11 specifically includes: providing a substrate 100 and constructing a circuit layer 200 on one side surface of the substrate 100.

[0165] In some possible implementations, refer to Figure 17 This application also provides a display device 20, which includes the display panel 10 described in this application. The display device 20 may include devices with image processing capabilities, such as mobile phones, desktop computers, laptops, tablets, in-vehicle displays, wearable devices, etc.

[0166] Figure 18 A schematic diagram of an electronic device according to an embodiment of this application is shown. For ease of explanation, only the parts related to this embodiment are shown, and the details are as follows:

[0167] An electronic device 30 includes a memory 31, a processor 32, and a computer program 33 stored in the memory 31 and executable on the processor 32. When the processor 32 executes the computer program 33, it implements a method for manufacturing a display panel 10 as described in any of the above embodiments.

[0168] The processor 32 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0169] In some embodiments, memory 31 may be an internal storage unit of electronic device 30, such as a hard disk or memory of electronic device 30. In other embodiments, memory 31 may be an external storage device of electronic device 30, such as a plug-in hard disk, smart media card (SMC), secure digital card (SD), flash card, etc., equipped on electronic device 30. Furthermore, memory 31 may include both internal and external storage units of electronic device 30. Memory 31 is used to store operating system, application programs, bootloader, data, and other programs, such as the program code of computer program 33. Memory 31 may also be used to temporarily store data that has been output or will be output.

[0170] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0171] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0172] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

[0173] From the above description of the embodiments, those skilled in the art will understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0174] It should be understood that the apparatuses and methods disclosed in the several embodiments provided in this application can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of modules or units is only a logical functional division. In actual implementation, there may be other division methods, such as multiple units or components being combined or integrated into another device. In addition, some features may be omitted or not performed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0175] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units. That is, it can be located in one place or distributed in multiple different locations. Depending on the actual needs, some or all of the units can be selected to achieve the purpose of this solution.

[0176] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit; they can also exist physically separately; or some units can be integrated into one unit while others exist physically separately. The integrated units described above can be implemented in hardware or as software functional units.

[0177] It should be noted that all or part of the above embodiments provided in this application (e.g., part or all of any feature) can be arbitrarily combined or combined with each other.

[0178] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display panel, characterized in that, include: A display area and a non-display area that at least partially surrounds the display area; The display panel (10) also includes: substrate(100); A power conductive line (210) is located on one side of the substrate (100) and the power conductive line (210) is located in the display area. The power conductive line (210) includes multiple first power conductive lines (211) and at least one second power conductive line (212). The first power conductive line (211) and the second power conductive line (212) both extend along the first direction, and the first power conductive line (211) and the second power conductive line (212) are arranged alternately along the second direction, and the first direction intersects the second direction; The first power supply conductor (211) is used to transmit a first power supply voltage, and the second power supply conductor (212) is used to transmit a second power supply voltage, wherein the first power supply voltage is greater than the second power supply voltage; The display panel (10) also includes a plurality of third power conductive lines (230), and two adjacent first power conductive lines (211) located on both sides of the same second power conductive line (212) are connected by the third power conductive line (230). The third power conductive line (230) is located on the side of the second power conductive line (212) closer to the substrate (100). The number of third power conductive lines (230) located between two first power conductive lines (211) on both sides of the same second power conductive line (212) is equal to the number of a column of pixel sub-circuits, and the third power conductive lines (230) correspond one-to-one with the pixel sub-circuits.

2. The display panel as described in claim 1, characterized in that, The first power conductive line (211) and the second power conductive line (212) are arranged in the same layer, and the spacing between any two adjacent power conductive lines (210) is equal.

3. The display panel as described in claim 1, characterized in that, The display panel (10) further includes a first power supply line (220) located in the non-display area. The first power supply line (220) is connected to each of the second power conductive lines (212). The first power supply line (220) is used to transmit the second power supply voltage. The first power supply line (220) at least partially surrounds the display area.

4. The display panel as described in claim 1, characterized in that, The number of first power conductors (211) between any two adjacent second power conductors (212) is equal.

5. The display panel as described in claim 1, characterized in that, The ratio of the number of the second power conductive wires (212) to the number of the first power conductive wires (211) is between 1:3 and 1:

20.

6. The display panel as described in claim 1, characterized in that, The display panel (10) also includes a circuit layer (200), an isolation structure (300), and multiple light-emitting devices (400). The circuit layer (200) is located on one side of the substrate (100), the power supply conductive line (210) is located on the circuit layer (200), the isolation structure (300) is located on the side of the circuit layer (200) away from the substrate (100) and forms a plurality of isolation openings (300a), a plurality of light-emitting devices (400) are located on the side of the circuit layer (200) away from the substrate (100), and at least some of the light-emitting devices (400) are located within the isolation openings (300a).

7. The display panel as described in claim 6, characterized in that, The isolation structure (300) includes an isolation portion (320) and a blocking portion (310) stacked in a direction away from the substrate (100), wherein the orthographic projection of the isolation portion (320) on the substrate (100) is located within the orthographic projection of the blocking portion (310) on the substrate (100); The display panel (10) further includes a pixel limiting layer (500), the isolation structure (300) is disposed on the pixel limiting layer (500), and the pixel limiting layer (500) is provided with a pixel opening communicating with the isolation opening (300a); The isolation structure (300) is electrically connected to the second power conductive line (212) through a first connection via (271), the first connection via (271) penetrating the pixel limiting layer (500).

8. The display panel as described in claim 7, characterized in that, The circuit layer (200) further includes a planarization layer (250) located on the side of the power conductive line (210) away from the substrate (100). The first connection via (271) penetrates the planarization layer (250) and the pixel definition layer (500).

9. The display panel as described in claim 7, characterized in that, The display panel (10) further includes a first half-zone (281) and a second half-zone (282) arranged sequentially along the first direction. The first half-zone (281) includes at least one first connection via (271), and the second half-zone (282) includes at least one external power terminal (283). The second power conductive line (212) is connected to the second power voltage through the external power terminal (283).

10. The display panel as claimed in claim 7, characterized in that, The isolation structure (300) also includes a base (330) located on the side of the isolation portion (320) near the substrate (100).

11. The display panel as claimed in claim 10, characterized in that, The light-emitting device (400) includes a first electrode (410), a light-emitting structure (420), and a second electrode (430) stacked in a direction away from the substrate (100). The first electrode (410) is disposed on the circuit layer (200). The pixel limiting layer (500) covers the edge of the first electrode (410) and exposes the first electrode (410) through the pixel opening. The light-emitting structure (420) is located in the pixel opening and is in contact with the first electrode (410). The second electrode (430) covers the light-emitting structure (420) and is electrically connected to the isolation structure (300).

12. The display panel as claimed in claim 11, characterized in that, The display panel (10) further includes a fourth power conductive line (240), which is disposed on the same layer as the first electrode (410). The fourth power conductive line (240) is used to transmit the second power voltage and is electrically connected to the isolation structure (300) through the second connection via (272).

13. The display panel as claimed in claim 12, characterized in that, The display panel (10) further includes a first encapsulation layer, which includes a plurality of encapsulation portions (600). The encapsulation portions (600) are located on the side of the second electrode (430) away from the circuit layer (200) and extend through the sidewall of the isolation structure (300) to the side of the isolation structure (300) away from the circuit layer (200). The orthographic projection of the first connecting via (271) on the substrate (100) does not overlap with the orthographic projection of the first encapsulation layer on the substrate (100), and the orthographic projection of the second connecting via (272) on the substrate (100) does not overlap with the orthographic projection of the first encapsulation layer on the substrate (100).

14. A display panel, characterized in that, include: A display area and a non-display area that at least partially surrounds the display area; The display panel (10) also includes: substrate(100); A light-emitting device (400) is located on one side of the substrate (100) and the light-emitting device (400) is located in the display area. The light-emitting device (400) includes a first electrode (410), a light-emitting structure (420) and a second electrode (430) stacked in a direction away from the substrate (100). The fourth power conductive line (240) is used to transmit the second power voltage, and the fourth power conductive line (240) is disposed in the same layer as the first electrode (410).

15. The display panel as claimed in claim 14, characterized in that, The display panel (10) further includes a first power supply line (220) located in the non-display area, the first power supply line (220) being electrically connected to the fourth power conductive line (240), the first power supply line (220) being used to transmit the second power supply voltage; the first power supply line (220) at least partially surrounds the display area.

16. The display panel as claimed in claim 14, characterized in that, The display panel (10) also includes a circuit layer (200) and an isolation structure (300). The circuit layer (200) is located on one side of the substrate (100), the isolation structure (300) is located on the side of the circuit layer (200) away from the substrate (100), and encloses to form a plurality of isolation openings (300a), a plurality of light-emitting devices (400) are located on one side of the circuit layer (200), and at least some of the light-emitting devices (400) are located within the isolation openings (300a); The isolation structure (300) is electrically connected to the fourth power supply conductor (240) through the second connection via (272).

17. The display panel as claimed in claim 16, characterized in that, The display panel (10) further includes a first encapsulation layer, which includes a plurality of encapsulation portions (600). The encapsulation portions (600) are located on the side of the second electrode (430) away from the circuit layer (200) and extend through the sidewall of the isolation structure (300) to the side of the isolation structure (300) away from the circuit layer (200). The orthographic projection of the second connection via (272) on the substrate (100) does not overlap with the orthographic projection of the first encapsulation layer on the substrate (100).

18. The display panel as claimed in claim 17, characterized in that, The display panel (10) further includes a first half-zone (281) and a second half-zone (282) arranged sequentially along a first direction. The first half-zone (281) includes at least one second connection via (272), and the second half-zone (282) includes at least one external power terminal (283). The fourth power conductive line (240) is connected to the second power voltage through the external power terminal (283).

19. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 18.

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