Intelligent extended reality usage data (XR-DOU) framework for competitive power solutions

Abstract

A method for memory management is described. The method includes detecting a mobile device entering a deep sleep state. The method also includes monitoring a lag counter for entering the deep sleep state with respect to a time period that the mobile device is in the deep sleep state to calculate a lag statistic threshold. The method further includes comparing the lag statistic threshold to a threshold configuration value. The method also includes adjusting memory management and / or frequency scaling of the mobile device when the lag statistic threshold is greater than the threshold configuration value.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Patent Application No. 18 / 104,223, filed January 31, 2023, entitled “SMART EXTENDED REALITY DATA OFUSAGE (XR-DOU) FRAMEWORK FOR COMPETITIVE POWER SOLUTION SCHEME,” the entire disclosure of which is expressly incorporated herein by reference. Technical Field

[0003] This disclosure relates generally to processing systems, and more specifically to one or more technologies for a smart extended reality usage data (XR-DOU) framework for competitive power and performance solutions. Background Technology

[0004] The mobile gaming market is becoming one of the most important markets in the mobile world. In this market, users are highly concerned about game performance. When users play games on mobile devices, video game apps running on these devices may sacrifice game performance to improve battery life by controlling power consumption. Successful game apps running on mobile devices can provide superior game performance while reducing power consumption to improve the device's battery life.

[0005] Mobile extended reality (XR) gaming devices are part of a relatively new mobile gaming market that is gaining significant attention. These XR mobile gaming devices are implemented using integrated connectivity solutions to support a variety of communication applications. During operation, these integrated connectivity solutions participate in periodic activities such as paging (e.g., New Radio (NR) / 5G / Sub-6), Connected Mode Discontinuous Reception (CDRx), Delivery Traffic Indication Messages (DTIM), scanning, and sniffing. Supporting these integrated connectivity solutions involves allocating increased cache memory resources to enable successful operation of the mobile XR gaming devices.

[0006] Furthermore, mobile XR gaming devices are configured to enter a deep sleep state to utilize battery power. Unfortunately, activity from the connectivity solution can lead to frequent exits from this deep sleep state. Specifically, the specific system cache refresh and rebuild strategies in response to exiting deep sleep become particularly problematic due to the provision of increased system cache memory to enable high-performance operation of mobile XR gaming devices. Therefore, a power consumption reduction technology is desired to provide an improved user experience without sacrificing gaming performance when operating XR mobile gaming devices due to system cache refresh and rebuild strategies in response to exiting deep sleep. Summary of the Invention

[0007] A method for memory management is described. The method includes: detecting that a mobile device has entered a deep sleep state. The method further includes: monitoring a hysteresis counter for the period during which the mobile device has been in the deep sleep state to calculate a hysteresis statistics threshold. The method further includes: comparing the hysteresis statistics threshold with a configured threshold value. The method further includes: adjusting memory management and / or frequency scaling of the mobile device when the hysteresis statistics threshold is greater than the configured threshold value.

[0008] A non-transitory computer-readable medium is described, on which program code for memory management is recorded. This program code is executed by a processor. The non-transitory computer-readable medium includes program code for detecting when a mobile device enters a deep sleep state. The non-transitory computer-readable medium also includes program code for monitoring a hysteresis counter relative to the time period during which the mobile device is in the deep sleep state to calculate a hysteresis statistics threshold. The non-transitory computer-readable medium also includes program code for comparing the hysteresis statistics threshold with a configured threshold value. The non-transitory computer-readable medium also includes program code for adjusting memory management and / or frequency scaling of the mobile device when the hysteresis statistics threshold is greater than the configured threshold value.

[0009] This has broadly outlined the features and technical advantages of this disclosure in order to facilitate a better understanding of the following detailed description. Additional features and advantages of this disclosure will be described below. Those skilled in the art will understand that this disclosure can be readily used as the basis for modifying or designing other structures for implementing the same purposes of this disclosure. Those skilled in the art will also recognize that such equivalent constructions do not depart from the teachings of this disclosure set forth in the appended claims. Novel features considered characteristic of this disclosure, in both their organization and manner of operation, along with further objects and advantages, will be better understood when considered in conjunction with the accompanying drawings. However, it is to be clearly understood that each drawing is provided for illustrative and descriptive purposes only and is not intended to be a limiting definition of this disclosure. Attached Figure Description

[0010] Details of one or more examples of this disclosure are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of this disclosure will become apparent from the description, the drawings, and the claims.

[0011] Figure 1 Example implementations of a system-on-a-chip (SoC) according to certain aspects of this disclosure are illustrated, the SoC including a graphics processing unit (GPU) for supporting extended reality (XR) gaming applications.

[0012] Figure 2 This is a block diagram illustrating an example content generation and decoding system for implementing extended reality (XR) game applications according to various aspects of this disclosure.

[0013] Figure 3A and Figure 3B This is a timing diagram illustrating a standby usage data (DOU) scenario caused by an XR mobile gaming device during Extended Reality (XR) standby power mode.

[0014] Figure 4A and Figure 4B Examples illustrate real-time cache and memory management (LCM) according to various aspects of this disclosure. 2 The flowchart of the framework method.

[0015] Figure 5 This is an example of various aspects according to this disclosure. Figure 4A and Figure 4B The flowchart illustrates the intelligent cache management process of the real-time cache memory management framework method.

[0016] Figure 6 This is an example of various aspects according to this disclosure. Figure 4A and Figure 4B A flowchart of the adaptive system frequency scaling process of the real-time cache memory management framework method.

[0017] Figure 7 This is an example of various aspects according to this disclosure. Figure 4A and Figure 4B The flowchart illustrates the real-time memory state management process of the real-time cache memory management framework method.

[0018] Figure 8 This is an example of various aspects according to this disclosure. Figure 4A and Figure 4B The flowchart illustrates the real-time progressive refresh mode management process of the real-time cache memory management framework.

[0019] Figure 9 This is a flowchart illustrating various aspects of a method for memory management according to this disclosure. Detailed Implementation

[0020] Various aspects of the systems, apparatuses, computer program products, and methods will be described more fully below with reference to the accompanying drawings. However, this disclosure may be embodied in many different forms and should not be construed as limited to any particular structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be comprehensive and complete, and will fully communicate the scope of this disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art will understand that the scope of this disclosure is intended to cover any aspect of the systems, apparatuses, computer program products, and methods disclosed herein, whether implemented independently of or in combination with other aspects of this disclosure. For example, any number of aspects set forth herein may be used to implement an apparatus or practice. Furthermore, the scope of this disclosure is intended to cover such apparatuses or methods practiced using structures, functionalities, or structures and functionalities other than or different from the various aspects of the disclosure set forth herein. Any aspect disclosed herein may be embodied by one or more elements of the claims.

[0021] While various aspects are described herein, numerous variations and substitutions of these aspects fall within the scope of this disclosure. Although some potential benefits and advantages of the aspects of this disclosure have been mentioned, the scope of this disclosure is not intended to be limited to a particular benefit, use, or objective. Rather, the aspects of this disclosure are intended to be broadly applicable to different wireless technologies, system configurations, networks, and transmission protocols, some of which are illustrated by way of example in the accompanying drawings and the description below. The detailed description and drawings are merely illustrative and not limiting of this disclosure, and the scope of this disclosure is defined by the appended claims and their equivalents.

[0022] Several aspects are presented with reference to various apparatuses and methods. These apparatuses and methods are described in the following detailed embodiments and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the system as a whole.

[0023] For example, an element, any part of an element, or any combination of elements can be implemented as a “processing system” including one or more processors (which may also be referred to as processing units). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, system-on-a-chip (SoCs), baseband processors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionalities described throughout this disclosure. One or more processors in the processing system can execute software. Whether referred to as software, firmware, middleware, microcode, hardware description language, or other names, software should be broadly interpreted as meaning instructions, instruction sets, code, code segments, program code, programs, subroutines, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, etc. The term “application” can refer to software. As described herein, one or more technologies can refer to an application (i.e., software) configured to perform one or more functions. In such examples, the application may be stored on memory (e.g., on-chip memory of a processor, system memory, or any other memory). Hardware described herein, such as a processor, may be configured to execute the application. For example, an application may be described as including code that, when executed by the hardware, causes the hardware to perform one or more technologies described herein. As an example, the hardware may access and execute code accessed from memory to perform one or more technologies described herein. In some examples, components are identified in this disclosure. In such examples, a component may be hardware, software, or a combination thereof. Each component may be a separate component or a subcomponent of a single component.

[0024] Therefore, in one or more examples described herein, the described functionality can be implemented in hardware, software, or any combination thereof. If implemented in software, the functionality can be stored on a non-transitory computer-readable medium or encoded as one or more instructions or code on a non-transitory computer-readable medium. Non-transitory computer-readable media include computer storage media. Storage media can be any available medium capable of being accessed by a computer. By way of example, and not limitation, such non-transitory computer-readable media can include random access memory (RAM), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), optical disc storage devices, magnetic disk storage devices, other magnetic storage devices, combinations of non-transitory computer-readable media of the types described above, or any other medium capable of storing computer-executable code in the form of instructions or data structures accessible by a computer.

[0025] Generally, this disclosure describes techniques for: having a graphics processing pipeline across multiple devices, improving the decoding of graphics content, and / or reducing the load on processing units (i.e., any processing unit configured to perform one or more of the techniques described herein, such as a graphics processing unit (GPU)). For example, this disclosure describes techniques for graphics processing in a communication system. Other example benefits are described throughout this disclosure.

[0026] As used herein, the term "decoder" can generally refer to encoders and / or decoders. For example, a reference to "content decoder" can include a reference to a content encoder and / or content decoder. Similarly, as used herein, the term "decode" can generally refer to encoding and / or decoding. As used herein, the terms "encode" and "compress" are used interchangeably. Similarly, the terms "decode" and "decompress" are used interchangeably.

[0027] As used herein, instances of the term "content" can refer to the terms "video," "graphic content," "image," and vice versa. This is true regardless of whether these terms are used as adjectives, nouns, or other parts of speech. For example, a reference to "content decoder" can include a reference to "video decoder," "graphic content decoder," or "image decoder," and a reference to "video decoder," "graphic content decoder," or "image decoder" can include a reference to "content decoder." As another example, a reference to a processing unit providing content to a content decoder can include a reference to that processing unit providing graphical content to a video encoder. In some examples, as used herein, the term "graphic content" can refer to content produced by one or more processes in a graphics processing pipeline. In some examples, as used herein, the term "graphic content" can refer to content produced by a processing unit configured to perform graphics processing. In some examples, as used herein, the term "graphic content" can refer to content produced by a graphics processing unit.

[0028] As used herein, instances of the term "content" can refer to graphical content or display content. In some examples, as used herein, the term "graphical content" can refer to content generated by a processing unit configured to perform graphics processing. For example, the term "graphical content" can refer to content generated by one or more processes in a graphics processing pipeline. In some examples, as used herein, the term "graphical content" can refer to content generated by a graphics processing unit. In some examples, as used herein, the term "display content" can refer to content generated by a processing unit configured to perform display processing. In some examples, as used herein, the term "display content" can refer to content generated by a display processing unit. Graphical content can be processed to become display content. For example, a graphics processing unit can output graphical content (such as frames) to a buffer (which may be referred to as a frame buffer). A display processing unit can read graphical content (such as one or more frames) from the buffer and perform one or more display processing techniques on that display processing unit to generate display content. For example, a display processing unit can be configured to perform compositing on one or more rendering layers to generate frames. For example, the display processing unit may be configured to composite, blend, or otherwise combine two or more layers into a single frame. The display processing unit may be configured to perform scaling (e.g., zooming in or out) on the frame. In some examples, a frame may refer to a layer. In other examples, a frame may refer to two or more layers that have already been blended together to form the frame (i.e., the frame comprises two or more layers, and the frame comprising two or more layers can be subsequently blended).

[0029] As cited herein, a first component (e.g., a processing unit) may provide content, such as graphical content, to a second component (e.g., a content decoder). In some examples, the first component may provide content to the second component by storing the content in memory accessible to the second component. In such examples, the second component may be configured to read content stored in memory by the first component. In other examples, the first component may provide content to the second component without any intermediate components (e.g., no memory or another component). In such examples, the first component may be described as providing content directly to the second component. For example, the first component may output content to the second component, and the second component may be configured to store the content received from the first component in memory such as a buffer.

[0030] The mobile gaming market is becoming one of the most important markets in the mobile world. In this market, users are highly concerned about game performance. When users play games on mobile devices, video game apps running on these devices can sacrifice game performance to improve battery life by controlling power consumption. Successful game apps running on mobile devices offer superior game performance while reducing power consumption to improve the device's battery life.

[0031] Mobile extended reality (XR) gaming devices are part of a relatively new mobile gaming market that is gaining significant attention. These XR mobile gaming devices are implemented using integrated connectivity solutions to support a variety of communication applications. During operation, these integrated connectivity solutions participate in periodic activities such as paging (e.g., New Radio (NR) / 5G / Sub-6), Connected Mode Discontinuous Reception (CDRx), Delivery Traffic Indication Messages (DTIM), scanning, and sniffing. Supporting these integrated connectivity solutions involves allocating increased cache memory resources to enable successful operation of the mobile XR gaming devices.

[0032] Furthermore, mobile XR gaming devices are configured to enter a deep sleep state to utilize battery power. Unfortunately, activity from the connectivity solution can lead to frequent exits from this deep sleep state. Specifically, the specific system cache refresh and rebuild strategies in response to exiting deep sleep become particularly problematic due to the increased system cache storage required for the operation of mobile XR gaming devices. Therefore, a power consumption reduction technology is desired to provide an improved user experience without sacrificing gaming performance when operating XR mobile gaming devices due to system cache refresh and rebuild strategies in response to exiting deep sleep.

[0033] Some aspects of this disclosure provide several advantages and solutions for mobile gaming, such as providing improved battery life for XR mobile gaming devices. These aspects of this disclosure rely on a Smart Extended Reality Usage Data (XR-DOU) framework, which reduces power consumption and improves battery life for mobile devices. Some aspects of this disclosure relate to a Real-Time Caching and Memory Management (LCM) system. 2 This framework helps improve the user experience without sacrificing game performance when operating XR mobile gaming devices. Some aspects of this disclosure use the following to detect XR-specific standby scenarios: a combination of elemental feedback as a trigger point of "no user eye presence / closed state," and a hysteretic / historical periodic intelligent assessment associated with repeated entry / exit due to incoming messages / notifications / XR-specific wake-ups / system exit from a regular sleep loop. This intelligent assessment is compared to a desired threshold as part of a statistical evaluation to enable real-time caching and memory management (LCM). 2 The framework is used to overcome the challenges identified.

[0034] Figure 1 An example implementation of a system-on-a-chip (SoC) 100 according to certain aspects of this disclosure is illustrated, the SoC having a graphics processing unit (GPU) for supporting extended reality (XR) gaming applications. The host SoC 100 includes processing blocks tailored for specific functions, such as connectivity block 110. Connectivity block 110 may include fifth-generation (5G) New Radio (NR) connectivity, fourth-generation Long Term Evolution (4G LTE) connectivity, Wi-Fi connectivity, USB connectivity, and Bluetooth. ® Connections, Secure Digital (SD) connections, etc.;

[0035] In this configuration, the SoC 100 includes various processing units that support multi-threaded operation. Figure 1 As shown in the configuration, SoC 100 includes a multi-core central processing unit (CPU) 102, a graphics processing unit (GPU) 104, a digital signal processor (DSP) 106, and a neural processing unit (NPU) 108. SoC 100 may also include a sensor processor 114, an image signal processor (ISP) 116, a navigation module 120, and a memory 118, which may include a global positioning system. The multi-core CPU 102, GPU 104, DSP 106, NPU 108, and multimedia engine 112 support various functions such as video, audio, graphics, extended reality (XR) games, artificial intelligence networks, etc. Each processor core of the multi-core CPU 102 can be a Reduced Instruction Set Computing (RISC) machine, an Advanced RISC machine (ARM), a microprocessor, or some other type of processor. The NPU 108 may be based on the ARM instruction set.

[0036] In some aspects of this disclosure, the instructions loaded into the multi-core CPU 102 may include program code for detecting when a mobile device enters a deep sleep state. The instructions loaded into the multi-core CPU 102 may also include program code for monitoring a hysteresis counter relative to the time period during which the mobile device is in the deep sleep state to calculate a hysteresis statistics threshold. The instructions loaded into the multi-core CPU 102 may also include program code for comparing the hysteresis statistics threshold with a configured threshold value. The instructions loaded into the multi-core CPU 102 may also include program code for adjusting memory management and / or frequency scaling of the mobile device when the hysteresis statistics threshold is greater than the configured threshold value.

[0037] Figure 2 This is a block diagram illustrating an example Extended Reality (XR) gaming system 200 configured to implement an Extended Reality (XR) gaming application according to various aspects of this disclosure. The XR gaming system 200 includes a source device 202 and a destination device 204. According to the techniques described herein, the source device 202 may be configured to encode graphical content generated by the processing unit 206 using a content encoder 208 before transmission to the destination device 204. The content encoder 208 may be configured to output a bitstream having a bit rate. The processing unit 206 may be configured to control and / or influence the bit rate of the content encoder 208 based on how the processing unit 206 generates the graphical content.

[0038] Source device 202 may include one or more components (or circuitry) for performing the various functions described herein. Destination device 204 may include one or more components (or circuitry) for performing the various functions described herein. In some examples, one or more components of source device 202 may be components of a system-on-a-chip (SoC). Similarly, in some examples, one or more components of destination device 204 may be components of a SoC.

[0039] Source device 202 may include one or more components configured to perform one or more technologies of this disclosure. In the illustrated example, source device 202 may include processing unit 206, content encoder 208, system memory 210, and communication interface 212. Processing unit 206 may include internal memory 209. Processing unit 206 may be configured to perform graphics processing, such as in graphics processing pipeline 207-1. Content encoder 208 may include internal memory 211.

[0040] Memory such as system memory 210 external to processing unit 206 and content encoder 208 may be accessible to processing unit 206 and content encoder 208. For example, processing unit 206 and content encoder 208 may be configured to read from and / or write to external memory such as system memory 210. Processing unit 206 and content encoder 208 may be communicatively coupled to system memory 210 via a bus. In some examples, processing unit 206 and content encoder 208 may be communicatively coupled to each other via this bus or a different connection.

[0041] Content encoder 208 can be configured to receive graphic content from any source such as system memory 210 and / or processing unit 206. System memory 210 can be configured to store graphic content generated by processing unit 206. For example, processing unit 206 can be configured to store graphic content in system memory 210. Content encoder 208 can be configured to receive graphic content in the form of pixel data (e.g., from system memory 210 and / or processing unit 206). Alternatively, content encoder 208 can be configured to receive pixel data of graphic content generated by processing unit 206. For example, content encoder 208 can be configured to receive the value of each component (e.g., each color component) of one or more pixels of graphic content. As an example, a pixel in the RGB color space may include a first value for the red component, a second value for the green component, and a third value for the blue component.

[0042] Internal memory 209, system memory 210, and / or internal memory 211 may include one or more volatile or non-volatile memories or storage devices. In some examples, internal memory 209, system memory 210, and / or internal memory 211 may include random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic data media, optical storage media, or any other type of memory.

[0043] According to some examples, internal memory 209, system memory 210, and / or internal memory 211 may be non-transitory storage media. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or propagating signal. However, the term "non-transitory" should not be construed as meaning that internal memory 209, system memory 210, and / or internal memory 211 are inmovable or that their contents are static. As an example, system memory 210 may be removed from source device 202 and moved to another device. As another example, system memory 210 may not be removable from source device 202.

[0044] Processing unit 206 may be a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or any other processing unit that can be configured to perform graphics processing. In some examples, processing unit 206 may be integrated into the motherboard of source device 202. In some examples, processing unit 206 may reside on a graphics card mounted in a port on the motherboard of source device 202, or may otherwise be incorporated into a peripheral device configured to interoperate with source device 202.

[0045] Processing unit 206 may include one or more processors, such as one or more microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, processing unit 206 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 209) and may use one or more processors to execute instructions in hardware to perform the technology of this disclosure. Any of the foregoing (including hardware, software, combinations of hardware and software, etc.) may be considered as one or more processors.

[0046] Content encoder 208 can be any processing unit configured to perform content encoding. In some examples, content encoder 208 may be integrated into the motherboard of source device 202. Content encoder 208 may include one or more processors, such as one or more microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, content encoder 208 may store instructions for software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 211) and may use one or more processors to execute instructions in hardware to perform the technology of this disclosure. Any of the foregoing (including hardware, software, combinations of hardware and software, etc.) can be considered as one or more processors.

[0047] Communication interface 212 may include receiver 214 and transmitter 216. Receiver 214 may be configured to perform any of the receiving functions described herein with respect to source device 202. For example, receiver 214 may be configured to receive information from destination device 204, which may include a request for content. In some examples, in response to receiving a request for content, source device 202 may be configured to perform one or more techniques described herein, such as generating or otherwise producing graphical content for delivery to destination device 204. Transmitter 216 may be configured to perform any of the transmitting functions described herein with respect to source device 202. For example, transmitter 216 may be configured to transmit encoded content to destination device 204, such as encoded graphical content generated by processing unit 206 and content encoder 208 (i.e., the graphical content is generated by processing unit 206, and content encoder 208 receives the graphical content as input to generate or otherwise produce the encoded graphical content). Receiver 214 and transmitter 216 may be combined to form transceiver 218. In such examples, transceiver 218 may be configured to perform any of the receive and / or transmit functions described herein for source device 202.

[0048] Destination device 204 may include one or more components configured to perform one or more technologies of this disclosure. In the illustrated example, destination device 204 may include processing unit 220, content decoder 222, system memory 224, communication interface 226, and one or more displays 231. Reference to display 231 may refer to one or more displays 231. For example, display 231 may include a single display or multiple displays. Display 231 may include a first display and a second display. The first display may be a left-eye display, and the second display may be a right-eye display. In some examples, the first display and the second display may receive different frames for presentation on the first display and the second display. In other examples, the first display and the second display may receive the same frames for presentation on the first display and the second display.

[0049] Processing unit 220 may include internal memory 221. Processing unit 220 may be configured to perform graphics processing, such as in graphics processing pipeline 207-2. Content decoder 222 may include internal memory 223. In some examples, destination device 204 may include a display processor, such as display processor 227, to perform one or more display processing techniques on one or more frames generated by processing unit 220 before being rendered by one or more displays 231. Display processor 227 may be configured to perform display processing. For example, display processor 227 may be configured to perform one or more display processing techniques on one or more frames generated by processing unit 220. One or more displays 231 may be configured to display content generated using decoded content. For example, display processor 227 may be configured to process one or more frames generated by processing unit 220, wherein the one or more frames are generated by processing unit 220 using decoded content derived from encoded content received from source device 202. Subsequently, display processor 227 may be configured to perform display processing on one or more frames generated by processing unit 220. One or more displays 231 may be configured to display or otherwise present frames processed by display processor 227. In some examples, one or more display devices may include one or more of the following: liquid crystal display (LCD), plasma display, organic light-emitting diode (OLED) display, projection display device, augmented reality display device, virtual reality display device, head-mounted display, or any other type of display device.

[0050] Memory (such as system memory 224) external to processing unit 220 and content decoder 222 may be accessible to processing unit 220 and content decoder 222. For example, processing unit 220 and content decoder 222 may be configured to read from and / or write to external memory (such as system memory 224). Processing unit 220 and content decoder 222 may be communicatively coupled to system memory 224 via a bus. In some examples, processing unit 220 and content decoder 222 may be communicatively coupled to each other via this bus or different connections.

[0051] Content decoder 222 can be configured to receive graphic content from any source, such as system memory 224 and / or communication interface 226. System memory 224 can be configured to store received encoded graphic content, such as encoded graphic content received from source device 202. Content decoder 222 can be configured to receive encoded graphic content in the form of encoded pixel data (e.g., from system memory 224 and / or communication interface 226). Content decoder 222 can be configured to decode the encoded graphic content.

[0052] Internal memory 221, system memory 224, and / or internal memory 223 may include one or more volatile or non-volatile memories or storage devices. In some examples, internal memory 221, system memory 224, and / or internal memory 223 may include random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic data media, optical storage media, or any other type of memory.

[0053] According to some examples, internal memory 221, system memory 224, and / or internal memory 223 may be non-transitory storage media. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or propagating signal. However, the term "non-transitory" should not be construed as meaning that internal memory 221, system memory 224, and / or internal memory 223 are inmovable or that their contents are static. As an example, system memory 224 may be removed from destination device 204 and moved to another device. As another example, system memory 224 may not be removable from destination device 204.

[0054] Processing unit 220 may be a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or any other processing unit that can be configured to perform graphics processing. In some examples, processing unit 220 may be integrated into the motherboard of destination device 204. In some examples, processing unit 220 may reside on a graphics card mounted in a port on the motherboard of destination device 204, or may otherwise be incorporated into a peripheral device configured to interoperate with destination device 204.

[0055] Processing unit 220 may include one or more processors, such as one or more microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, processing unit 220 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 221) and may use one or more processors to execute instructions in hardware to perform the technology of this disclosure. Any of the foregoing (including hardware, software, combinations of hardware and software, etc.) may be considered as one or more processors.

[0056] Content decoder 222 can be any processing unit configured to perform content decoding. In some examples, content decoder 222 may be integrated into the motherboard of destination device 204. Content decoder 222 may include one or more processors, such as one or more microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, content decoder 222 may store instructions for software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 223) and may use one or more processors to execute instructions in hardware to perform the technology of this disclosure. Any of the foregoing (including hardware, software, combinations of hardware and software, etc.) may be considered as one or more processors.

[0057] Communication interface 226 may include receiver 228 and transmitter 230. Receiver 228 may be configured to perform any of the receiving functions described herein for destination device 204. For example, receiver 228 may be configured to receive information from source device 202, which may include encoded content, such as encoded graphical content generated or otherwise produced by processing unit 206 and content encoder 208 of source device 202 (i.e., the graphical content is generated by processing unit 206, and content encoder 208 receives the graphical content as input to generate or otherwise produce the encoded graphical content). As another example, receiver 228 may be configured to receive location information from source device 202, which may be encoded or unencoded (i.e., not encoded). In some examples, destination device 204 may be configured to decode the encoded graphical content received from source device 202 according to the techniques described herein. For example, content decoder 222 may be configured to decode the encoded graphical content to generate or otherwise produce decoded graphical content. Processing unit 220 may be configured to use the decoded graphical content to generate or otherwise produce one or more frames for rendering on one or more displays 231. Transmitter 230 may be configured to perform any of the transmission functions described herein for destination device 204. For example, transmitter 230 may be configured to send information to source device 202, which may include a request for content. Receiver 228 and transmitter 230 may be combined to form transceiver 232. In such an example, transceiver 232 may be configured to perform any of the receiving and / or transmitting functions described herein for destination device 204.

[0058] The content encoder 208 and content decoder 222 of the XR gaming system 200 represent examples of computing components (e.g., processing units) that can be configured to perform one or more techniques for encoding and decoding content, respectively, according to various examples described in this disclosure. In some examples, the content encoder 208 and content decoder 222 may be configured to operate according to content decoding standards, such as video decoding standards, display streaming compression standards, or image compression standards.

[0059] like Figure 2 As shown, source device 202 can be configured to generate encoded content. Therefore, source device 202 can be referred to as a content encoding device or content encoding apparatus. Destination device 204 can be configured to decode the encoded content generated by source device 202. Therefore, destination device 204 can be referred to as a content decoding device or content decoding apparatus. In some examples, source device 202 and destination device 204 can be separate devices, as shown. In other examples, source device 202 and destination device 204 can be on the same computing device, or can be part of the same computing device. In any example, the graphics processing pipeline can be distributed between the two devices. For example, a single graphics processing pipeline can include multiple graphics processes. Graphics processing pipeline 207-1 can include one or more of the multiple graphics processes. Similarly, graphics processing pipeline 207-2 can include one or more of the multiple graphics processes. In this respect, graphics processing pipeline 207-1, cascaded with graphics processing pipeline 207-2 or otherwise configured as graphics processing pipeline 207-2, can produce a complete graphics processing pipeline. Alternatively, graphics processing pipeline 207-1 can be a partial graphics processing pipeline, and graphics processing pipeline 207-2 can be a partial graphics processing pipeline; when combined, they produce a distributed graphics processing pipeline.

[0060] In some examples, graphics processing performed in graphics processing pipeline 207-1 may not be performed in graphics processing pipeline 207-2 or may be repeated in other ways. For example, graphics processing pipeline 207-1 may include: receiving first position information corresponding to a first orientation of the device. Graphics processing pipeline 207-1 may also include: generating first graphic content based on the first position information. Additionally, graphics processing pipeline 207-1 may include: generating motion information for distorting the first graphic content. Graphics processing pipeline 207-1 may also include: encoding the first graphic content. Additionally, graphics processing pipeline 207-1 may include: providing the motion information and the encoded first graphic content. Graphics processing pipeline 207-2 may include: providing first position information corresponding to a first orientation of the device. Graphics processing pipeline 207-2 may also include: receiving the encoded first graphic content generated based on the first position information. Furthermore, graphics processing pipeline 207-2 may include: receiving motion information. The graphics processing pipeline 207-2 may further include: decoding the encoded first graphics content to generate decoded first graphics content. Additionally, the graphics processing pipeline 207-2 may include: distorting the decoded first graphics content based on the motion information. In some examples, by distributing the graphics processing pipeline between the source device 202 and the destination device 204, the destination device may be able to render graphics content that would otherwise be unable to render and therefore unpresentable. Other example benefits are described throughout this disclosure.

[0061] As described herein, devices such as source device 202 and / or destination device 204 can refer to any device, apparatus, or system configured to perform one or more of the technologies described herein. For example, a device can be a server, base station, user equipment, client device, station, access point, computer (e.g., personal computer, desktop computer, laptop computer, tablet computer, computer workstation, or mainframe computer), end product, apparatus, telephone, smartphone, server, video game platform or console, handheld device (e.g., portable video game device or personal digital assistant (PDA)), wearable computing device (e.g., smartwatch, augmented reality device, or virtual reality device), non-wearable device, augmented reality device, virtual reality device, display (e.g., display device), television, set-top box, intermediate network device, digital media player, video streaming device, content streaming device, in-vehicle computer, any mobile device, any device configured to generate graphical content, or any device configured to perform one or more of the technologies described herein.

[0062] Source device 202 may be configured to communicate with destination device 204. For example, destination device 204 may be configured to receive encoded content from source device 202. In some examples, the communication coupling between source device 202 and destination device 204 is shown as link 234. Link 234 may include any type of medium or device capable of moving encoded content from source device 202 to destination device 204.

[0063] exist Figure 2 In one example, link 234 may include a communication medium enabling source device 202 to transmit encoded content to destination device 204 in real time. The encoded content may be modulated according to a communication standard, such as a wireless communication protocol, and transmitted to destination device 204. The communication medium may include any wireless or wired communication medium, such as radio frequency (RF) spectrum or one or more physical transmission lines. The communication medium may form part of a packet-based network such as a local area network, a wide area network, or a global network (such as the Internet). The communication medium may include a router, a switch, a base station, or any other equipment that may be useful in facilitating communication from source device 202 to destination device 204. In other examples, link 234 may be a point-to-point connection between source device 202 and destination device 204, such as a wired or wireless display link connection (e.g., an HDMI link, a DisplayPort link, a MIPI DSI link, or another link through which encoded content traverses from source device 202 to destination device 204).

[0064] In another example, link 234 may include a storage medium configured to store encoded content generated by source device 202. In this example, destination device 204 may be configured to access the storage medium. The storage medium may include various locally accessible data storage media, such as Blu-ray discs, DVDs, CD-ROMs, flash memory, or other suitable digital storage media for storing encoded content.

[0065] In another example, link 234 may include a server or another intermediate storage device configured to store encoded content generated by source device 202. In this example, destination device 204 may be configured to access encoded content stored on the server or other intermediate storage device. The server may be a type of server capable of storing encoded content and sending that encoded content to destination device 204.

[0066] The devices described herein, such as source device 202 and destination device 204, may be configured to communicate with each other. Communication may include sending and / or receiving information. Information may be carried in one or more messages. As an example, a first device communicating with a second device may be described as communicatively coupled to or otherwise communicatively coupled to the second device. For example, a client device and a server may be communicatively coupled. As another example, a server may be communicatively coupled to multiple client devices. As another example, any device described herein configured to perform one or more technologies of this disclosure may be communicatively coupled to one or more other devices configured to perform one or more technologies of this disclosure. In some examples, when communicatively coupled, the two devices may actively send or receive information, or may be configured to send or receive information. If not communicatively coupled, any two devices may be configured to communicatively couple with each other, such as according to one or more communication protocols conforming to one or more communication standards. The reference to “any two devices” does not mean that only two devices may be configured to be communicatively coupled with each other; rather, any two devices include more than two devices. For example, a first device may be communicatively coupled with a second device, and a first device may be communicatively coupled with a third device. In this example, the first device could be a server.

[0067] refer to Figure 2Source device 202 can be described as communicatively coupled to destination device 204. In some examples, the term "communically coupled" can refer to a communication connection, which can be direct or indirect. In some examples, link 234 can represent the communication coupling between source device 202 and destination device 204. The communication connection can be wired and / or wireless. A wired connection can refer to a conductive path, trace, or physical medium (excluding wireless physical media) through which information can travel. A conductive path can refer to any conductor of any length, such as a conductive pad, conductive via, conductive plane, conductive trace, or any conductive medium. A direct communication connection can refer to a connection in which no intermediate component resides between the two communicatively coupled components. An indirect communication connection can refer to a connection in which at least one intermediate component resides between the two communicatively coupled components. The two communicatively coupled devices can communicate with each other through one or more different types of networks (e.g., wireless networks and / or wired networks) according to one or more communication protocols. In some examples, the two communicatively coupled devices can be associated with each other through an association process. In other examples, the two communicatively coupled devices can communicate with each other without participating in an association process. For example, a device such as source device 202 is configured to unicast, broadcast, multicast, or otherwise send information (e.g., encoded content) to one or more other devices (e.g., one or more destination devices, including destination device 204). Destination device 204 in this example can be described as communicatively coupled to each of the one or more other devices. In some examples, the communication connection enables the sending and / or receiving of information. For example, according to the techniques of this disclosure, a first device communicatively coupled to a second device can be configured to send information to and / or receive information from the second device. Similarly, according to the techniques of this disclosure, a second device in this example can be configured to send information to and / or receive information from a first device. In some examples, the term "communicatively coupled" can refer to a temporary, intermittent, or permanent communication connection.

[0068] Any device described herein, such as source device 202 and destination device 204, may be configured to operate according to one or more communication protocols. For example, source device 202 may be configured to communicate with destination device 204 using one or more communication protocols (e.g., receiving information from and / or sending information to destination device 204). In such an example, source device 202 may be described as communicating with destination device 204 via a connection. The connection may adhere to or otherwise conform to a communication protocol. Similarly, destination device 204 may be configured to communicate with source device 202 using one or more communication protocols (e.g., receiving information from and / or sending information to source device 202). In such an example, destination device 204 may be described as communicating with source device 202 via a connection. The connection may adhere to or otherwise conform to a communication protocol.

[0069] As used herein, the term "communication protocol" can refer to any communication protocol, such as a communication protocol that conforms to a communication standard. As used herein, the term "communication standard" can include any communication standard, such as wireless communication standards and / or wired communication standards. Wireless communication standards can correspond to wireless networks. As an example, a communication standard can include any wireless communication standard corresponding to a Wireless Personal Area Network (WPAN) standard, such as Bluetooth (e.g., IEEE 802.15) or Bluetooth Low Energy (BLE) (e.g., IEEE 802.15.4). As another example, a communication standard can include any wireless communication standard corresponding to a Wireless Local Area Network (WLAN) standard, such as Wi-Fi (e.g., any 802.11 standard, such as 802.11a, 802.11b, 802.11c, 802.11n, or 802.11ax). As yet another example, a communication standard can include any wireless communication standard corresponding to a Wireless Wide Area Network (WWAN) standard, such as 3G, 4G, 4G LTE, 5G, or 6G.

[0070] refer to Figure 2Content encoder 208 can be configured to encode graphical content. In some examples, content encoder 208 can be configured to encode graphical content into one or more video frames of extended reality (XR) content. When content encoder 208 encodes content, it can generate a bitstream. The bitstream can have a bit rate, such as bits / time units, where the time unit is any time unit, such as seconds or minutes. The bitstream can include a sequence of bits that forms a decoded representation of the graphical content and associated data. To generate the bitstream, content encoder 208 can be configured to perform encoding operations on pixel data, such as pixel data corresponding to a shadow texture atlas. For example, when content encoder 208 performs encoding operations on image data (e.g., one or more blocks of a shadow texture atlas) provided as input, it can generate a series of decoded images and associated data. The associated data can include a set of decoding parameters, such as quantization parameters (QP).

[0071] The mobile gaming market is becoming one of the most important markets in the mobile world. In this market, users are highly concerned about game performance. When users play games on mobile devices, video game apps running on these devices may sacrifice game performance to improve battery life by controlling power consumption. Successful game apps on mobile devices offer superior game performance while reducing power consumption to improve the device's battery life.

[0072] Mobile extended reality (XR) gaming devices are a relatively new segment of the mobile gaming market that is gaining significant attention. Unfortunately, the power consumption of these mobile XR gaming devices is a significant drain on their batteries. Therefore, longer battery life is an important feature for providing a user experience without sacrificing gaming performance when operating XR mobile gaming devices. A power consumption reduction technology is desired to provide an improved user experience without compromising gaming performance when operating XR mobile gaming devices.

[0073] like Figure 1As shown, mobile gaming devices can be implemented using SoC 100, which includes memory 118 that provides a significant amount of volatile and non-volatile memory to achieve improved performance and power efficiency. For example, SoC 100 is implemented using a system cache (e.g., approximately 16 megabytes (MB) or 32 MB) including non-volatile memory (NVM), such as Universal Flash Storage (UFS). While initial versions of Artificial Reality (AR) / Virtual Reality (VR) type products are implemented using a 1 MB Last-Level Cache Subsystem (LLCC), the memory 118 of SoC 100 can be configured with 32 MB of LLCC, including 6 MB of note-taking memory, to support AR / VR type products. As described, these AR / VR product lines are collectively referred to as Extended Reality (XR) product lines.

[0074] Figure 3A and Figure 3B A timing diagram 300 is shown illustrating a standby usage data (DOU) scenario caused by an XR mobile gaming device during Extended Reality (XR) standby power mode. Figure 3A As shown, XR mobile gaming devices are implemented using integrated connectivity solutions to support a variety of communication applications. During operation, these integrated connectivity solutions participate in periodic activities such as paging (e.g., New Radio (NR) / 5G / Sub-6), Connected Mode Discontinuous Reception (CDRx), Delivery Traffic Indication Messages (DTIM), scanning, and sniffing.

[0075] Unfortunately, when these XR mobile gaming devices transition to XR Standby DOU Power Mode 310, the XR gaming device causes repeated short entry / exit periods 320 after initially entering XR Standby DOU Power Mode 310. In this example, entering and exiting XR Standby DOU Power Mode 310 occurs every three seconds due to incoming network messages and application activity / frames, for a significant duration (e.g., 20 minutes). This example also illustrates a subsequent entry into DOU Standby 330, followed by a sleep period 332 of duration A. Additionally, a subsequent entry into DOU Standby 340, followed by a sleep period 342, is shown.

[0076] like Figure 3BAs shown, during period 320, periodic wake-ups due to the integrated connectivity solution cause repeated short-duration entry / exit after the initial entry into XR standby DOU power mode 310. Additionally, the repeated short-duration entry / exit during period 320 after the initial entry into XR standby DOU power mode 310 triggers large-scale system cache refresh and rebuild activities, which also power on and off the non-volatile UFS memory. In this example, the system cache 350 (e.g., LLCC) includes System Cache Identifier (SCID) clients 360 (360-1, 360-2, ..., 360-N), where one of the SCID clients 360 is the CPU.

[0077] The strategy for system cache 350 may specify that if one SCID client in SCID clients 360 does not utilize a portion of the allocated system cache 350, then other SCID clients in SCID clients 360 utilize that allocated portion. Because the operating system (OS) runs on a CPU (e.g., SCID-CPU), SCID-CPU clients set all lines of system cache 350 to dirty, resulting in increased cache refresh time. Furthermore, the increased refresh time leads to significant power penalties. For example, repeated cache refresh and rebuild periods 370 occur every three seconds within a significant time segment, resulting in wasted system power and increased latency, which is exacerbated as system cache 350 grows. However, before the system cache 350 is rebuilt, incoming messages 380 received from the integrated connectivity solution are stored in memory 118 (e.g., double data rate (DDR) memory). Because incoming messages 380 are new messages / packets, they are stored in memory 118 (…). Figure 1 The system cache 350 is stored in the XR standby power mode 310 (e.g., deep sleep state) and does not need to be refreshed and rebuilt during XR standby power mode 310 (e.g., deep sleep state).

[0078] Specifically, the period 370 of repeated system cache refresh and rebuild activities involves both performance and power penalties. These penalties correspond to refresh time costs and refresh power costs, respectively, and are proportional to the size of the system cache 350. A larger system cache 350 results in increased refresh time, which negatively impacts latency and significantly increases power costs. For example, considering a modem CDRx cycle and assuming paging occurs periodically (e.g., approximately every 20 milliseconds (ms)), the mobile gaming device SoC is delayed to the same amount of time as the CDRx timeline due to the higher refresh time overhead, which affects the modem timeline by preventing entry into CDRx mode. Additionally, the mobile gaming device SoC's external non-volatile memory (e.g., UFS, embedded multimedia card (eMMC) flash memory, etc.) also suffers from a shortened lifespan penalty due to lost deep sleep cycles.

[0079] These external non-volatile memories are configured with a low-power mode to achieve the deepest sleep state based on idle cycles before finally transitioning to a shutdown state. Currently, the UFS memory enters a deep sleep state in response to the system DOU / pause state, where the UFS is transitioned to a shutdown state (e.g., level = 5, referred to as the UFS shutdown state or shutdown state), which conserves minimum trough sleep current (RBSC) power. Figure 3A As shown, each incoming message (e.g., WhatsApp, WeChat, etc.) triggers a UFS wake-up, which results in a re-initialization step involving processing events for each Small Computer System Interface (SCSI) device (e.g., approximately eight events), leading to increased power consumption. This event processing results in additional overhead / workload processing from the User Event Monitor (UeventD). Furthermore, the processing of these events causes the User Event Monitor to migrate up to the main CPU, resulting in power impact across different SoCs. This user event processing activity collectively contributes to a considerable power impact in the indicated standby DOU power scenario.

[0080]

[0081] Table 1 – Power Comparison between Level 5 and Level 3

[0082] Table 1 illustrates the possible power savings of delaying the UFS's entry into a Level 5 deep sleep state (e.g., a sleep state level) by using a Level 3 sleep state. For example, for WhatsApp, the amount of current is 44.29 mA in a Level 5 sleep state compared to a reduced current of 38.09 mA in a Level 3 sleep state. Similarly, for WeChat, the amount of current is 25.50 mA in a Level 5 sleep state compared to a reduced current of 20.96 mA in a Level 3 sleep state.

[0083] Furthermore, the cache refresh time and overhead caused by the operation of the system cache 350 due to the standby DOU power state can be calculated based on the 32MB size of the system cache 350 as follows. First, the number of cache lines (CLs) to be refreshed is approximately 262,144 (= 32-way * 8192 sets, assuming the worst-case scenario where all lines of the system cache 350 are dirty). Additionally, the number of cycles required to refresh one cache line is 4. Therefore, the total number of cache refresh cycles is approximately 1,048,576 (= 4 * 262,144). Assuming a clock pulse at 150MHz = 1 / 150 = 6.7ns, the time taken to complete the system cache refresh is approximately 7.025ms (= 6.7ns * 1048,576). However, in practice, the memory microcontroller (MC) supports half the bandwidth of the system cache 350. Therefore, the total time to refresh the system cache 350 is approximately 14.05ms (= 2 * 7.025ms).

[0084]

[0085] Table 2 – Refresh Overhead Based on Operation Frequency Lookup

[0086] Table 2 illustrates the refresh overhead based on the operating frequencies of the memory microcontroller (e.g., a Double Data Rate (DDR) microcontroller (MC)) and the system cache controller (SHUB). As shown in the first row of Table 2, assuming the MC operates at system default at 200 MHz and the SHUB at system default at 150 MHz, the total time to perform a cache refresh is 42 ms. Assuming that paging occurs periodically (approximately every 20 ms) for an integrated connectivity solution, the 42 ms refresh time impacts the timeline of the integrated connectivity solution by preventing entry into idle states (e.g., CDRx, Discontinuous Reception (DRX), etc.). As shown in Table 2, increasing the frequencies of the MC and SHUB can reduce the refresh time (e.g., 5.5 ms from the highest frequency in Table 2) to achieve entry into idle states. A solution is desired that improves power and performance without degrading the performance matrix and latency specifications to provide a competitive advantage in standby DOU power modes. Another solution is desired that uses modems and connectivity solutions to provide latency improvements to adapt to the XR technology field as cache sizes increase.

[0087] Some aspects of this disclosure relate to a real-time cache and memory management (LCM) system. 2 This framework helps overcome these penalties through the use of intelligent methods and schemes. Some aspects of this disclosure use the following to detect XR-specific standby scenarios: a combination of elemental feedback as a trigger point of "no user eye presence / closed state," and a hysteretic / historical periodic intelligent assessment associated with repeated entry / exit due to incoming messages, notifications, XR-specific wake-ups, and / or system exit from a regular sleep cycle. According to, for example, Figures 4A to 9 The process shown compares this intelligent evaluation with a desired threshold as part of a statistical evaluation to enable Real-Time Cache and Memory Management (LCM). 2 The framework is used to overcome the challenges identified.

[0088] Figure 4A and Figure 4B Examples illustrate real-time cache and memory management (LCM) according to various aspects of this disclosure. 2 The flowchart of the framework method. Figure 4AA flowchart 400 illustrates a method based on a real-time cache and memory management framework. At box 410, each hardware interrupt (HINT) is monitored to detect each device reboot and exit from standby / sleep / hibernation mode for Android devices or from standby mode for Apple devices. After each detected device reboot or exit from standby / sleep / hibernation mode or standby mode, use case scenarios are categorized at box 412 into active and inactive scenarios as defined at box 414. In this example, the inactive scenario is the standby DOU / deep sleep state, which includes the default network mode / active mode and airplane mode, as determined at box 416. The default network mode / active mode involves applications that force a cache refresh after exiting the standby DOU / deep sleep state. At box 416, applications that force a cache refresh can be identified as standby DOU / deep sleep state applications. When airplane mode is detected at box 416, the integrated connectivity solution is disabled at box 418 unless the device is near a field network or other network, in which case network mode / active mode is detected.

[0089] Flowchart 400 illustrates a device and system state evaluator module 420 that determines whether a device is expected to enter a standby DOU / deep sleep state to trigger a real-time cache and memory management framework. The device and system state evaluator module 420 may be registered as a broadcast notification in response to state changes based on certain parameters or polling. The device and system state evaluator module 420 includes a device state condition notification 422. At block 430, the device state condition notification 422 determines whether a device is expected to enter a standby DOU / deep sleep state. In this example, at block 430, the device state condition notification 422 determines whether the following conditions are true: (1) the device screen is locked; (2) the display is off; (3) a proximity sensor indicates that the mobile device is near the user's ear; (4) a light sensor detects that the mobile device is in the user's pocket or handbag; (5) a synthetic aperture radar (SAR) sensor indicates that the user has left; and / or (6) no user's eyes are detected. Based on these conditions, the device status condition notifier 422 determines that the mobile device is expected to enter a standby DOU / deep sleep state, and triggers the Real-Time Cache and Memory Management Framework (LCM) at box 452. 2 ).

[0090] Additionally, the device and system status evaluator module 420 includes a standby status evaluator 424 for network modules. At block 440, the standby status evaluator 424 determines whether the connectivity solution is in an idle state (e.g., DRX / CDRX / paging for deep sleep). At block 442, the standby status evaluator 424 detects all network-enabled modules, removes their resource votes, and requests deep sleep (e.g., paging, IMPS, DTIM, BMPS, etc.). At block 442, the standby status evaluator 424 detects that all network entities are executing their deep sleep paging loops and determines at block 452 whether the real-time cache and memory management framework has been triggered. At block 452, the triggering of the real-time cache and memory management framework can be performed by non-modem clients 426 (e.g., CPU, DSP, graphics (GFX), etc.) using sleep votes set to transition to idle mode. Additionally, the triggering of the real-time cache and memory management framework at box 452 can be performed by the original equipment manufacturer (OEM) / original design manufacturer (ODM) / callback 428, thereby providing a custom notification for entering a deep sleep state.

[0091] Figure 4B Flowchart 450 illustrates various aspects of this disclosure, and further illustrates... Figure 4A The real-time cache and memory management framework method is described. At box 452, it is determined whether the intelligent evaluation of the real-time cache memory management framework method is triggered. When this trigger does not occur, the control flow branches to box 490, where intelligent real-time cache memory management is reset to its original state. This can also occur in response to user actions (e.g., mirroring / user key press / screen unlock / display touch / user SAR presence). At box 460, the intelligent evaluation of the real-time cache memory management framework method is triggered, indicating that the device has entered a deep sleep state (e.g., standby, RBSC, paging mode, deep system low power mode (LPM), or minimum voltage (Vddmin)). As described, in a deep sleep state (e.g., standby DOU state), the device is idle but continues to monitor for received incoming packets to trigger wake-up.

[0092] In some aspects of this disclosure, Figure 4A The real-time cache memory management framework method uses a combination of elemental feedbacks, such as "no user eye presence / closed state," as trigger points to detect specific XR standby scenarios. Figure 4B Examples Figure 4AThis is a continuation of the cache memory management framework method, in which a hysteresis / historical periodic intelligent evaluation occurs associated with repeated entry / exit from standby DOU / deep sleep states. Specifically, the intelligent evaluation analyzes repeated entry / exit due to incoming messages, notifications, XR-specific wake-ups, and system exit from a regular sleep cycle. At box 462, a hysteresis counter for entering a deep sleep state is compared with the time period for tracking entry and exit from the deep sleep state to calculate a hysteresis statistics threshold. Once calculated, hysteresis index bit 464 is used to access direction array 465 to determine the link to hysteresis array 466 to determine a threshold configuration value based on that duration. Next, at box 468, the hysteresis statistics threshold is compared with the threshold configuration value as part of a statistical evaluation to enable real-time cache and memory management (LCM). 2 )frame.

[0093] At box 470, it is determined whether the hysteresis statistics threshold exceeds the threshold configuration value. As noted, the hysteresis statistics threshold can exceed the threshold configuration value when frequent incoming messages are received within a short period of time, as monitored in box 462. For example, WhatsApp, WeChat, social media messages, notifications, time updates, background tasks, and / or housekeeping tasks may result in frequent incoming messages received within a short period of time, leading to frequent exits from deep sleep, as determined at box 480. Otherwise, due to normal device sleep / standby time, the control flow branches to box 490. At box 480, the real-time cache and memory management framework determines that the device is performing frequent standby entry / exit, which causes the noted refresh overhead, involving both increased power consumption and increased latency. That is, the device does not remain in a hibernation mode (e.g., shallow / deep hibernation for Android / MediaTek-based devices) or deep standby (for iPhone devices) for a sufficient duration, referred to as a deep sleep state.

[0094] like Figure 4B As shown, Real-time Cache and Memory Management (LCM) 2 The framework provides four schemes to overcome the penalties associated with cache flushing and rebuilding strategies after exiting a deep sleep state. For example, at box 502, a smart cache management process is performed, such as... Figure 5 As shown. At box 602, an adaptive system scaling process is performed to reduce latency, for example, as... Figure 6 As shown. At box 702, a real-time memory state management process is performed, for example, as... Figure 7 As shown. At box 802, the real-time progressive refresh mode management process is performed, for example, as... Figure 8As shown. In some aspects of this disclosure, one of the four schemes or a combination of the four schemes is implemented to overcome the penalty associated with cache refresh and rebuilding after exiting a deep sleep state. Although four options are described, other options for overcoming the indicated penalty associated with cache refresh and rebuilding after exiting a deep sleep state are contemplated according to various aspects of this disclosure.

[0095] Figure 5 This is an example of various aspects according to this disclosure. Figure 4A and Figure 4B The flowchart of the intelligent cache management process 500 of the real-time cache memory management framework method is shown in block 520. At block 520, the system's real-time cache memory management (LCM) is triggered. 2 This action, as part of the intelligent cache management process 500, involves reducing the System Cache Identifier (SCID) cache allocation size at block 530 to a specified size (e.g., a reduced size or a minimum size) for the corresponding network activity used to trigger device wake-up. Furthermore, the system cache is deallocated from any remaining subsystems; however, received messages can still be accessed from memory (e.g., double data rate (DDR) memory). For example, as... Figure 3B As shown, system cache 350 is shared by SCID clients 360 (360-1, 360-2, ..., 360-N), where one of the SCID clients 360 is the CPU. In this example, the size of system cache 350 allocated to SCID-client 1 360-1 is reduced, and the system cache is deallocated from the remaining SCID clients 360. Therefore, any cache flushing and rebuilding is limited to the minimum size of the system cache allocated to SCID-client 1 360-1.

[0096] At box 540, during the intelligent cache management process 500, the remaining printed circuit board (PCB) traces of the remaining subsystems are kept in a collapsed state. For example, as Figure 3B As shown, keeping the PCB traces of the remaining SCID clients in SCID client 360 in a collapsed state provides further power savings because the collapsed PCB traces of the remaining SCID clients in SCID client 360 do not consume power. At box 550, the cache strategy associated with the intelligent cache management process 500 is modified (e.g., including priority, growth, etc.). For example, as... Figure 3BAs shown, the caching strategy is modified based on priority and growth to expand the minimum size of the system cache allocated to SCID-client 1 360-1 and / or reassign it to one or more of the remaining SCID clients 360.

[0097] Figure 6 This is an example of various aspects according to this disclosure. Figure 4A and Figure 4B The flowchart of the adaptive system frequency scaling process 600 of the real-time cache memory management framework method is shown. At box 610, a check is performed to determine whether network clients (e.g., network applications) requesting Quality of Service (QoS) are operating at a sufficient frequency to meet the timeline. At box 620, system real-time cache memory management (LCM) is triggered. 2 This action is part of the adaptive system frequency scaling process 600. At box 630, dummy voting is added to increase the operating frequency during the standby / pause path to reduce refresh time. For example, as shown in Table 2, dummy voting can be added to increase the frequency of MC and SHUB, thereby enabling entry into an idle state by reducing refresh time and adapting to the requested performance QoS.

[0098] Figure 7 This is an example of various aspects according to this disclosure. Figure 4A and Figure 4B The flowchart illustrates the real-time memory state management process 700 of the real-time cache memory management framework method. At block 710, a check is performed to determine whether the standby DOU entry / exit hysteresis statistics threshold remains above a configured threshold value. If this check fails, the control flow branches to block 740. Otherwise, at block 720, system real-time cache memory management (LCM) is triggered. 2 This action, as part of the real-time memory state management process 700, occurs because the hysteresis statistics threshold remains above the threshold configuration value. At box 730, the low-power mode (LPM) of the universal flash storage device (UFS) is moved to level 3 sleep state, and the LPM is disabled. For example, Table 1 illustrates possible power savings by delaying the UFS from entering level 5 deep sleep state by using level 3 sleep state. At box 740, a wait timer (e.g., one hour) is set for the sleep mode to determine if standby exit / entry exceeds the threshold and if neither a user nor user eye detection and no flight mode detection are detected. If the timer expires, at box 750, the UFS is moved to level 5 sleep state. Otherwise, the control flow branch returns to box 730.

[0099] Figure 8 This is an example of various aspects according to this disclosure. Figure 4A and Figure 4BThe flowchart of the real-time progressive refresh mode management process 800 of the real-time cache memory management framework method is as follows. At box 810, a check is performed to determine whether the standby DOU entry / exit hysteresis statistics threshold remains above the threshold configuration value. If this check fails, the control flow branches to box 840. Otherwise, at box 820, system real-time cache memory management (LCM) is triggered. 2 This action, as part of the real-time progressive refresh mode management process 800, is performed because the hysteresis statistics threshold remains above the threshold configuration value. At box 830, cache memory refresh is avoided, and the contents of the cache memory are preserved. For example, as... Figure 3B As shown, a period 370 is used to avoid repeated cache refreshes and rebuilds. At box 840, a wait timer (e.g., one hour) is set for the hibernation mode to determine if a standby exit / entry threshold has been exceeded. If the timer completes, at box 850, the cache memory is refreshed, and a portion of the cache memory is collapsed based on the associated power rail to conserve memory power. Otherwise, the control flow branch returns to box 830. For example, box 850 includes collapsing the power rail of a predetermined portion of the system cache 350 after refreshing the system cache 350 when the time period based on the timer expires.

[0100] Some aspects of this disclosure perform intelligent evaluation of histograms based on hysteresis / historical periodicity associated with recurring entry / exit statistics due to incoming message notifications, Extended Reality (XR) specific wake-ups, and system exit from a regular sleep cycle. This histogram is compared to a desired threshold as part of the statistical evaluation to determine whether the hysteresis threshold is greater than the desired threshold configuration. Based on this statistical evaluation, some aspects of this disclosure provide dynamic changes to: real-time memory state management, real-time cache size / policy management, real-time progressive cache refresh mode management, and / or adaptive system frequency scaling for latency reduction.

[0101] Figure 9 This is a flowchart illustrating a method for memory management according to various aspects of the present disclosure. Method 900 begins at block 902, where a mobile device is detected to have entered a deep sleep state. For example, as... Figure 4A As shown, flowchart 400 illustrates a device and system state evaluator module 420 that determines whether a device is expected to enter a standby DOU / deep sleep state to trigger a real-time cache and memory management framework. The device and system state evaluator module 420 can be registered as a broadcast notifier in response to state changes based on certain parameters or polling. The device and system state evaluator module 420 includes a device state condition notifier 422. At block 430, the device state condition notifier 422 determines whether a device is expected to enter a standby DOU / deep sleep state.

[0102] At box 904, a hysteresis counter for entering deep sleep is monitored relative to the time period during which the mobile device is in deep sleep to calculate a hysteresis statistics threshold. For example, Figure 4B Examples Figure 4A This is a continuation of the cache memory management framework approach, in which a hysteresis / historical periodic intelligent evaluation occurs associated with repeated entry / exit from standby DOU / deep sleep states. Specifically, the intelligent evaluation analyzes repeated entry / exit due to incoming messages, notifications, XR-specific wake-ups, and system exit from a regular sleep cycle. At box 462, a hysteresis counter for entering a deep sleep state is compared with the time periods tracking entry and exit from deep sleep states to calculate a hysteresis statistics threshold.

[0103] At box 906, the hysteresis statistics threshold is compared to the configured threshold value. For example, as... Figure 4B As shown, once the hysteresis statistics threshold is calculated, hysteresis index 464 is used to access direction array 465 to determine the link to hysteresis array 466, in order to determine the threshold configuration value based on that duration. Next, at box 468, the hysteresis statistics threshold is compared with the threshold configuration value as part of a statistical evaluation to enable Real-Time Cache and Memory Management (LCM). 2 )frame.

[0104] At box 908, when the hysteresis statistics threshold exceeds the configured threshold value, the memory management and / or frequency scaling of the mobile device are adjusted. For example, as... Figure 4B As shown, Real-time Cache and Memory Management (LCM) 2 The framework provides four schemes to overcome the penalties associated with cache flushing and rebuilding strategies after exiting a deep sleep state. For example, at box 502, a smart cache management process is performed, such as... Figure 5 As shown. At box 602, an adaptive system scaling process is performed to reduce latency, for example, as... Figure 6 As shown. At box 702, a real-time memory state management process is performed, for example, as... Figure 7 As shown. At box 802, the real-time progressive refresh mode management process is performed, for example, as... Figure 8 As shown.

[0105] Specific implementation examples are described in the following numbered clauses:

[0106] 1. A method for memory management, the method comprising:

[0107] Detects that the mobile device has entered a deep sleep state;

[0108] The lag counter for entering the deep sleep state is monitored relative to the time period during which the mobile device is in the deep sleep state in order to calculate the lag statistics threshold.

[0109] Compare the hysteresis statistical threshold with the threshold configuration value; and

[0110] When the hysteresis statistics threshold is greater than the threshold configuration value, the memory management and / or frequency scaling of the mobile device are adjusted.

[0111] 2. The method according to Clause 1, wherein monitoring includes:

[0112] The hysteresis counter tracks the lag counter as the mobile device enters the deep sleep state;

[0113] Measure the time period during which the mobile device is in the deep sleep state; and

[0114] The hysteresis statistical threshold is calculated in response to the tracking and the measurement.

[0115] 3. The method according to any one of clauses 1 or 2, wherein the comparison includes:

[0116] Use hysteresis indexes to access the direction array to determine links to the hysteresis array; and

[0117] The threshold configuration value is accessed from the hysteresis array based on the link.

[0118] 4. The method according to any one of clauses 1 to 3, wherein the adjustment includes:

[0119] The network application that triggers device wake-up; and

[0120] Reduce the cache allocation size of the client corresponding to the System Cache Identifier (SCID) of the network application to the specified size.

[0121] 5. The method according to Clause 4, further comprising:

[0122] The SCID client identifies the system cache other than the network application mentioned above;

[0123] Maintain the printed circuit board (PCB) traces of the SCID client in a collapsed state; and

[0124] The strategy for modifying the system cache is based on the identified identifier and the retention mechanism.

[0125] 6. The method according to any one of clauses 1 to 3, wherein the adjustment includes:

[0126] Determine whether the network client requesting Quality of Service (QoS) is operating at a sufficient frequency to meet the timeline; and

[0127] Add dummy voting to increase the operating frequency of the memory microcontroller and system cache controller, thereby reducing cache refresh time.

[0128] 7. The method according to any one of clauses 1 to 3, wherein the adjustment includes:

[0129] Reduce the sleep state level of non-volatile memory (NVM);

[0130] Waiting for a certain period of time; and

[0131] If the time period expires before the mobile device wakes from the deep sleep state, the sleep state level of the NVM is increased.

[0132] 8. The method according to any one of clauses 1 to 3, wherein the adjustment includes:

[0133] Delaying the refresh of the system cache;

[0134] Waiting for a certain period of time; and

[0135] If the time period expires before the mobile device wakes from the deep sleep state, the system cache is refreshed.

[0136] 9. The method according to Clause 8, further comprising: after refreshing the system cache, causing a predetermined portion of the power rails of the system cache to collapse.

[0137] 10. The method according to any one of clauses 1 to 9, wherein the detection includes: confirming the deep sleep state when the network application of the mobile device is performing a deep sleep paging cycle.

[0138] 11. A non-transitory computer-readable medium having program code for memory management recorded thereon, the program code being executed by a processor and comprising:

[0139] Program code used to detect when a mobile device enters a deep sleep state;

[0140] Program code for monitoring the hysteresis counter for entering the deep sleep state relative to the time period during which the mobile device is in the deep sleep state in order to calculate a hysteresis statistics threshold;

[0141] Program code for comparing the hysteresis statistical threshold with the threshold configuration value; and

[0142] Program code for adjusting the memory management and / or frequency scaling of the mobile device when the hysteresis statistics threshold is greater than the threshold configuration value.

[0143] 12. The non-transitory computer-readable medium as described in Clause 11, wherein the program code for monitoring comprises:

[0144] Program code used to track the hysteresis counter as the mobile device enters the deep sleep state;

[0145] Program code for measuring the time period during which the mobile device is in the deep sleep state; and

[0146] Program code used to calculate the hysteresis statistical threshold in response to the tracking and the measurement.

[0147] 13. A non-transitory computer-readable medium according to any one of clauses 11 or 12, wherein the program code used for comparison comprises:

[0148] Program code for using hysteresis indexes to access the direction array to determine links to the hysteresis array; and

[0149] Program code for accessing the threshold configuration value from the hysteresis array based on the link.

[0150] 14. The non-transitory computer-readable medium according to any one of clauses 11 to 13, wherein the program code for adjustment comprises:

[0151] Program code used to identify the network application that triggers device wake-up; and

[0152] Program code used to reduce the cache allocation size of the client corresponding to the System Cache Identifier (SCID) of the network application to a specified size.

[0153] 15. The non-transitory computer-readable medium according to Clause 14, further comprising:

[0154] Program code used to identify the SCID client of the system cache other than the network application;

[0155] Program code used to keep the printed circuit board (PCB) traces of the SCID client in a collapsed state; and

[0156] Program code for modifying the strategy of the system cache based on the program code for identification and the program code for retention.

[0157] 16. The non-transitory computer-readable medium according to any one of clauses 11 to 13, wherein the program code for adjustment comprises:

[0158] The program code used to determine whether the network client requesting Quality of Service (QoS) is operating at a sufficient frequency to meet the timeline; and

[0159] Program code used to add dummy votes to increase the operating frequency of the memory microcontroller and system cache controller in order to reduce cache refresh time.

[0160] 17. The non-transitory computer-readable medium according to any one of clauses 11 to 13, wherein the program code for adjustment comprises:

[0161] Program code used to reduce the sleep state level of non-volatile memory (NVM);

[0162] Program code used to wait for a certain period of time; and

[0163] Program code for incrementing the sleep state level of the NVM if the time period expires before the mobile device wakes from the deep sleep state.

[0164] 18. The non-transitory computer-readable medium according to any one of clauses 11 to 13, wherein the program code for adjustment comprises:

[0165] Program code used to delay the flushing of the system cache;

[0166] Program code used to wait for a certain period of time; and

[0167] Program code for refreshing the system cache if the time period expires before the mobile device wakes up from the deep sleep state.

[0168] 19. The non-transitory computer-readable medium according to Clause 18, further comprising: program code for collapsing the power rails of a predetermined portion of the system cache after the system cache has been refreshed.

[0169] 20. The non-transitory computer-readable medium according to any one of clauses 11 to 19, wherein the program code for detection includes: program code for confirming the deep sleep state when a web application of the mobile device is executing a deep sleep paging cycle.

[0170] According to this disclosure, unless otherwise specified in the context, the term "or" may be interpreted as "and / or". Additionally, while phrases such as "one or more" or "at least one" may be used for some features disclosed herein but not for others; features not using such language may be interpreted as having such implied meaning unless otherwise specified in the context.

[0171] In one or more examples, the functionality described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term “processing unit” is used throughout this disclosure, such a processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any functionality, processing unit, technique, or other module described herein is implemented in software, then the functionality, processing unit, technique, or other module described herein may be stored on or transmitted on a computer-readable medium as one or more instructions or code. A computer-readable medium may include computer data storage media and communication media, including any medium that facilitates the transfer of a computer program from one place to another. In this way, a computer-readable medium may generally correspond to (1) a non-transitory tangible computer-readable storage medium or (2) a communication medium such as a signal or carrier wave. A data storage medium may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, code, and / or data structures for implementing the techniques described herein. By way of example, and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, such as disks and discs as used herein, including compact discs (CDs), laser discs, optical discs, digital multi-purpose discs (DVDs), floppy disks and Blu-ray discs, wherein disks often magnetically reproduce data, while discs optically reproduce data using lasers. Combinations of the above should also be included within the scope of computer-readable media. Computer program products may include computer-readable media.

[0172] The code can be executed by one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), arithmetic logic units (ALUs), field-programmable arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Therefore, the term "processor" as used herein can refer to any of the above-described structures or any other structure suitable for implementing the techniques described herein. Furthermore, these techniques can be fully implemented in one or more circuit or logic elements.

[0173] The techniques disclosed herein can be implemented in a wide variety of devices or apparatuses, including wireless mobile phones, integrated circuits (ICs), or a set of ICs (e.g., chipsets). Various components, modules, or units are described in this disclosure to emphasize functional aspects of a device configured to perform the disclosed techniques, but implementation by different hardware units is not necessarily required. Rather, as described above, various units can be combined in any hardware unit or provided by a collection of interoperable hardware units, including one or more processors as described above, along with suitable software and / or firmware.

[0174] Various examples have been described. These and other examples are within the scope of the following claims.

Claims

1. A method for memory management, the method comprising: Detects that the mobile device has entered a deep sleep state; The lag counter for entering the deep sleep state is monitored relative to the time period during which the mobile device is in the deep sleep state in order to calculate the lag statistics threshold. Compare the hysteresis statistical threshold with the threshold configuration value; When the hysteresis statistics threshold is greater than the threshold configuration value, the period of repeatedly exiting / entering the deep sleep state is detected; as well as Adjust the memory management and / or frequency scaling of the mobile device during the period of repeatedly exiting / entering the deep sleep state.

2. The method of claim 1, wherein monitoring comprises: The hysteresis counter tracks the lag counter as the mobile device enters the deep sleep state; Measure the time period during which the mobile device is in the deep sleep state; as well as The hysteresis statistical threshold is calculated in response to the tracking and the measurement.

3. The method of claim 1, wherein the comparison comprises: Use the hysteresis index to access the direction array to determine the link to the hysteresis array; as well as The threshold configuration value is accessed from the hysteresis array based on the link.

4. The method of claim 1, wherein the adjustment includes: Identify the network application that triggers device wake-up; as well as Reduce the cache allocation size of the client corresponding to the system cache identifier SCID of the network application to the specified size.

5. The method according to claim 4, further comprising: The SCID client identifies the system cache other than the network application mentioned above; Keep the PCB traces of the SCID client in a collapsed state; as well as The strategy for modifying the system cache is based on the identified identifier and the retention mechanism.

6. The method of claim 1, wherein the adjustment comprises: Determine whether the network client requesting Quality of Service (QoS) is operating at a sufficient frequency to meet the timeline. as well as Add dummy voting to increase the operating frequency of the memory microcontroller and system cache controller, thereby reducing cache refresh time.

7. The method of claim 1, wherein the adjustment comprises: Reduce the sleep state level of the non-volatile memory (NVM); Wait for a certain period of time; as well as If the time period expires before the mobile device wakes from the deep sleep state, the sleep state level of the NVM is increased.

8. The method of claim 1, wherein the adjustment comprises: Delaying the refresh of the system cache; Wait for a certain period of time; as well as If the time period expires before the mobile device wakes from the deep sleep state, the system cache is refreshed.

9. The method according to claim 8, further comprising: After refreshing the system cache, the power rails of a predetermined portion of the system cache are collapsed.

10. The method of claim 1, wherein the detection comprises: The deep sleep state is confirmed when the mobile device's network application is executing a deep sleep paging loop.

11. A non-transitory computer-readable medium having program code for memory management recorded thereon, the program code being executed by a processor and comprising: Program code used to detect when a mobile device enters a deep sleep state; Program code for monitoring the hysteresis counter for entering the deep sleep state relative to the time period during which the mobile device is in the deep sleep state in order to calculate a hysteresis statistics threshold; Program code for comparing the hysteresis statistical threshold with the threshold configuration value; Program code for detecting repeated exits / entries into the deep sleep state when the hysteresis statistics threshold is greater than the threshold configuration value; as well as Program code for adjusting the memory management and / or frequency scaling of the mobile device during the period of repeatedly exiting / entering the deep sleep state.

12. The non-transitory computer-readable medium of claim 11, wherein the program code for monitoring comprises: Program code used to track the hysteresis counter as the mobile device enters the deep sleep state; Program code used to measure the time period during which the mobile device is in the deep sleep state; as well as Program code used to calculate the hysteresis statistical threshold in response to the tracking and the measurement.

13. The non-transitory computer-readable medium of claim 11, wherein the program code for comparison comprises: Program code used to access the direction array using hysteresis indexes to determine links to the hysteresis array; as well as Program code for accessing the threshold configuration value from the hysteresis array based on the link.

14. The non-transitory computer-readable medium of claim 11, wherein the program code for adjustment comprises: Program code used to identify the network application that triggers device wake-up; as well as Program code used to reduce the cache allocation size of the client corresponding to the system cache identifier SCID of the network application to a specified size.

15. The non-transitory computer-readable medium according to claim 14, further comprising: Program code used to identify the SCID client of the system cache other than the network application; Program code used to keep the printed circuit board (PCB) traces of the SCID client in a collapsed state; as well as Program code for modifying the strategy of the system cache based on the program code for identification and the program code for retention.

16. The non-transitory computer-readable medium of claim 11, wherein the program code for adjustment comprises: The program code used to determine whether the network client requesting Quality of Service (QoS) is operating at a sufficient frequency to meet the timeline. as well as Program code used to add dummy votes to increase the operating frequency of the memory microcontroller and system cache controller in order to reduce cache refresh time.

17. The non-transitory computer-readable medium of claim 11, wherein the program code for adjustment comprises: Program code used to reduce the sleep state level of non-volatile memory (NVM); Program code used to wait for a certain period of time; as well as Program code for incrementing the sleep state level of the NVM if the time period expires before the mobile device wakes from the deep sleep state.

18. The non-transitory computer-readable medium of claim 11, wherein the program code for adjustment comprises: Program code used to delay the flushing of the system cache; Program code used to wait for a certain period of time; as well as Program code for refreshing the system cache if the time period expires before the mobile device wakes up from the deep sleep state.

19. The non-transitory computer-readable medium according to claim 18, further comprising: Program code used to collapse the power rails of a predetermined portion of the system cache after the system cache has been refreshed.

20. The non-transitory computer-readable medium of claim 11, wherein the program code for detection comprises: Program code used to confirm the deep sleep state when the mobile device's web application is executing a deep sleep paging loop.

21. A computer program product comprising computer-readable instructions that, when executed by a processor, cause the processor to perform the method according to any one of claims 1 to 10.

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