Driving control digital circuit suitable for multi-way electromagnetic valve and driving control method

Abstract

The invention relates to a drive control digital circuit suitable for a multi-way electromagnetic valve and a drive control method. The driving circuit comprises a driving processing circuit which receives driving work information, generates next-period driving control information corresponding to the driving work information and loads the generated next-period driving control information to a driving signal generating circuit, and the driving signal generating circuit generates driving work information corresponding to the next-period driving control information. And generating a channel PWM driving signal corresponding to each path of electromagnetic valve based on the received driving control information of the next period, so as to configure an electromagnetic valve driving circuit to drive and control the connected electromagnetic valve based on the channel PWM driving signal. According to the invention, a digital circuit is adopted to realize driving control of the multi-way electromagnetic valve, and through resource scheduling of driving control, the area and power consumption during driving control can be reduced, so that the driving control cost of the multi-way electromagnetic valve is reduced, and the driving control precision and reliability of the multi-way electromagnetic valve are improved.

Description

Technical Field

[0001] The present invention relates to a drive control digital circuit and a drive control method, in particular to a drive control digital circuit and a drive control method suitable for a multi-way electromagnetic valve. Background Art

[0002] As the core component of the hydraulic actuator, the solenoid valve's drive control accuracy and reliability are directly related to the hydraulic actuator's performance. For example, in the automotive electronic stability control system (ESC), the solenoid valve's drive control accuracy and reliability will directly affect the brake pressure adjustment accuracy and reliability.

[0003] When a hydraulic actuator contains multiple solenoid valves, they need to be driven and controlled to maintain their corresponding operating states, creating a multi-way solenoid valve drive control scenario. Currently, when driving and controlling multi-way solenoid valves, corresponding logical control, such as frequency processing and analog-to-digital conversion, must be implemented. However, due to the lack of effective resource scheduling, this implementation results in a large circuit / chip area and high power consumption, resulting in high drive control costs for multi-way solenoid valves and difficulty in ensuring drive control accuracy. Summary of the Invention

[0004] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a digital drive control circuit and drive control method suitable for multi-way solenoid valves, which adopts a digital circuit to realize the drive control of the multi-way solenoid valves. Through the resource scheduling of the drive control, the area and power consumption during the drive control can be reduced, thereby reducing the drive control cost of the multi-way solenoid valves and improving the drive control accuracy and reliability of the multi-way solenoid valves.

[0005] According to the technical solution provided by the present invention, a drive control digital circuit suitable for a multi-way solenoid valve is used to drive and control the multi-way solenoid valve. The drive control digital circuit includes: The driving processing circuit receives the driving operation information, generates the next cycle driving control information corresponding to the driving operation information, and loads the generated next cycle driving control information into the driving signal generating circuit, wherein: The driving operation information at least includes the driving target frequency and the driving state information when each solenoid valve driving circuit drives the corresponding solenoid valve; The next cycle driving control information at least includes the next cycle driving clock information and the next cycle driving regulation information; The next cycle driving clock information includes the next cycle channel driving clock number corresponding to each solenoid valve; The next cycle driving control information includes the next cycle channel driving start signal corresponding to each solenoid valve; The drive signal generating circuit generates a channel PWM drive signal corresponding to each solenoid valve based on the received next cycle drive control information, so as to configure the solenoid valve drive circuit based on the channel PWM drive signal to drive and control the connected solenoid valve, wherein: When generating the channel PWM drive signal corresponding to each solenoid valve, the next cycle channel drive clock number and the next cycle channel drive start signal corresponding to the current solenoid valve are obtained. Thereafter, the corresponding channel PWM drive signal is generated based on the obtained next cycle channel drive clock number and the next cycle channel drive start signal.

[0006] The driving processing circuit includes a frequency processing unit, a phase scheduling unit and a driving clock number generating unit, wherein: The frequency processing unit processes the driving target frequency and generates a next cycle reference clock number and a next cycle reference start signal corresponding to the driving target frequency, and loads the generated next cycle reference clock number to the driving clock number generating unit; Based on the next cycle reference start signal and the preset working phase of each solenoid valve, the phase scheduling unit generates the next cycle channel drive start signal and clock number generation request information corresponding to each solenoid valve, and loads all the next cycle channel drive start signals to the drive signal generation circuit; Based on the clock number, request information is generated, and the driving status information of each solenoid valve is collected in sequence. Based on the collected driving status information, at least the channel PWM proportion information corresponding to each solenoid valve driving circuit is determined. Thereafter, based on the corresponding channel PWM proportion information and the next cycle reference clock number, the driving clock number generation unit generates the next cycle channel driving clock number corresponding to each solenoid valve.

[0007] The clock number generation request information includes a plurality of generation processing sub-requests, each generation processing sub-request corresponds to a solenoid valve and a solenoid valve driving circuit for driving and controlling the solenoid valve, wherein: When a solenoid valve is a digital solenoid valve, the corresponding generation processing sub-request includes the channel number corresponding to the current solenoid valve and the PWM ratio acquisition request corresponding to the current solenoid valve drive circuit, and the drive status information corresponding to the current solenoid valve is the channel PWM ratio information, where: When generating the channel drive clock number for the next cycle, based on the PWM ratio acquisition request, the channel PWM ratio information of the current solenoid valve drive circuit is obtained. Thereafter, based on the channel PWM ratio information and the reference clock number for the next cycle, the corresponding channel drive clock number for the next cycle is generated; When one solenoid valve is a current-type solenoid valve, the corresponding generation processing sub-request includes the channel number corresponding to the current solenoid valve and the PWM ratio calculation request corresponding to the current solenoid valve drive circuit, and the drive status information of the current solenoid valve drive circuit is at least the channel current, wherein, When generating the channel drive clock number for the next cycle, the corresponding channel current is obtained based on the PWM ratio calculation request, and the corresponding channel PWM ratio information is calculated based on the obtained channel current. Thereafter, the corresponding channel drive clock number for the next cycle is generated based on the channel PWM ratio information and the reference clock number for the next cycle.

[0008] Calculation of channel PWM ratio information includes: Performing AD conversion on the acquired channel current to generate a channel quantized current value corresponding to the channel current; A PID operation is performed on the generated channel quantized current value to generate corresponding channel PWM ratio information after the PID operation.

[0009] For multi-way solenoid valves, when generating the corresponding channel drive clock number for the next cycle, based on the channel number of each solenoid valve, a drive clock number generation unit is configured to generate the corresponding channel drive clock number for the next cycle in a pipeline manner, wherein: When calculating the number of channel driving clocks for the next cycle, we have:

[0010] in, The number of channel driving clocks for the next cycle, is the channel PWM duty cycle information, is the maximum duty cycle, The reference clock number for the next cycle.

[0011] The driving signal generating circuit includes a plurality of independent channel PWM driving signal generating units, wherein: A channel PWM drive signal generating unit is adaptively connected to a solenoid valve drive circuit, and each channel PWM drive signal generating unit receives the corresponding channel drive clock number of the next cycle and the channel drive start signal of the next cycle; Based on the received next cycle channel driving clock number and the next cycle channel driving start signal, the channel PWM driving signal generating unit generates a corresponding channel PWM driving signal and loads the generated channel PWM driving signal to the connected solenoid valve driving circuit.

[0012] When each channel PWM drive signal generating unit generates a channel PWM drive signal, it includes: After receiving a valid next cycle channel drive start signal, the channel PWM drive signal is configured to be in a valid state within the counting time of the next cycle channel drive clock number.

[0013] The frequency processing unit processes the driving target frequency, including: Counting the number of reference clocks of the current cycle, and generating a next cycle reference start signal when counting the number of reference clocks of the current cycle is completed, and when generating the next cycle reference start signal, updating the next cycle reference clock number, wherein, When the next starting reference clock number is updated, the next cycle reference clock number is calculated first. When calculating the next cycle reference clock number, the reference digital clock frequency in the frequency processing unit is obtained, and the result value of dividing the reference digital clock frequency by the driving target frequency is configured as the next cycle reference clock number.

[0014] The drive verification of multi-way solenoid valves includes: The drive processing circuit, the drive signal generating circuit, the multi-way solenoid valve and the solenoid valve drive circuit adapted to the multi-way solenoid valve are comprehensively modeled using the Verilog hardware description language; During drive verification, the drive state information of the multi-channel solenoid valve drive circuit in the comprehensive modeling is loaded into the drive clock number generation unit, so that the drive clock number generation unit generates the next cycle channel drive clock number corresponding to the solenoid valve drive circuit.

[0015] A drive control method suitable for a multi-way electromagnetic valve uses the required drive control digital circuit to drive and control the multi-way electromagnetic valve to be driven and controlled.

[0016] The advantages of the present invention are as follows: the drive processing circuit receives the drive working information and processes the received drive working information to generate the corresponding drive control information for the next cycle; the drive signal generating circuit can generate a PWM drive signal corresponding to each solenoid valve according to the drive signal generating circuit, so as to realize the drive control of multiple solenoid valves; The drive processing circuit, the drive signal generating circuit and the solenoid valve drive circuit are implemented using digital circuits, that is, the drive control of the multi-way solenoid valves is realized using digital circuits. Through the resource scheduling of the drive control, the area and power consumption during the drive control can be reduced, thereby reducing the drive control cost of the multi-way solenoid valves and improving the drive control accuracy and reliability of the multi-way solenoid valves. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a structural block diagram of an embodiment of the digital drive control circuit of the present invention.

[0018] Figure 2This is a circuit schematic diagram of an equivalently simplified solenoid valve drive circuit and an embodiment of the solenoid valve of the present invention. DETAILED DESCRIPTION

[0019] The present invention will be further described below with reference to specific drawings and embodiments.

[0020] In order to reduce the drive control cost of a multi-way solenoid valve and improve the drive control accuracy and reliability of the multi-way solenoid valve, the present invention provides a drive control digital circuit suitable for a multi-way solenoid valve. Specifically, the drive control digital circuit is used to drive and control the multi-way solenoid valve. The drive control digital circuit includes: The driving processing circuit receives the driving operation information, generates the next cycle driving control information corresponding to the driving operation information, and loads the generated next cycle driving control information into the driving signal generating circuit, wherein: The driving operation information at least includes the driving target frequency and the driving state information when each solenoid valve driving circuit drives the corresponding solenoid valve; The next cycle driving control information at least includes the next cycle driving clock information and the next cycle driving regulation information; The next cycle driving clock information includes the next cycle channel driving clock number corresponding to each solenoid valve; The next cycle driving control information includes the next cycle channel driving start signal corresponding to each solenoid valve; The drive signal generating circuit generates a channel PWM drive signal corresponding to each solenoid valve based on the received next cycle drive control information, so as to configure the solenoid valve drive circuit based on the channel PWM drive signal to drive and control the connected solenoid valve, wherein: When generating the channel PWM drive signal corresponding to each solenoid valve, the next cycle channel drive clock number and the next cycle channel drive start signal corresponding to the current solenoid valve are obtained. Thereafter, the corresponding channel PWM drive signal is generated based on the obtained next cycle channel drive clock number and the next cycle channel drive start signal.

[0021] It should be noted that the drive control digital circuit of the present invention is a digital circuit used to control a multi-way solenoid valve. Specifically, a multi-way solenoid valve refers to multiple solenoid valves. Multi-way solenoid valves can be used in the automotive electronic stability control system mentioned above. Generally, each solenoid valve requires a solenoid valve drive circuit, meaning that each solenoid valve has a corresponding solenoid valve drive circuit. Therefore, when controlling a multi-way solenoid valve, "corresponding to one solenoid valve" refers to "corresponding to the solenoid valve drive circuit connected to the current solenoid valve." Specifically, the solenoid valve drive circuit can be used to control the drive of the solenoid valve. The solenoid valve drive circuit can be used in a manner consistent with the prior art and will not be further elaborated here.

[0022] It is understandable that the number of solenoid valves can be selected according to actual needs, so as to meet the actual application requirements. Figure 1 The external solenoid valve (plural) in the embodiment is characterized as multiple solenoid valves, that is, Figure 1 The word "plural" in the sentence always means multiple, such as Figure 1 The term "solenoid valve drive circuit(s)" in this context refers to multiple solenoid valve drive circuits, with a one-to-one correspondence between each solenoid valve. Generally, multiple solenoid valves are independent of each other. However, depending on the operational scenario, the operating phases of different solenoid valves are typically set with a fixed phase difference. This phase difference improves EMC characteristics when driving the solenoid valves, facilitating the scheduling of ADC sampling conversion and PID calculations described below. When there is no phase difference between the operating phases of different solenoid valves, this can be considered a special case where the phase difference is set to 0, allowing the same drive control method to be used.

[0023] The solenoid valve drive circuit can use existing commonly used circuits, such as analog circuits. The circuit form used by the solenoid valve drive circuit can be selected according to needs, so as to meet the drive control of the solenoid valve. When using the solenoid valve drive circuit to drive and control the solenoid valve, the PMW (Pulse Width Modulation) signal should be loaded to the solenoid valve drive circuit. For example, when there are multiple solenoid valves and corresponding solenoid valve drive circuits, the corresponding channel PMW drive signal should be loaded to each solenoid valve drive circuit. In this way, the drive state of the connected solenoid valve can be controlled by the channel PWM drive signal. Figure 1 The PWM drive signal in is the channel PWM drive signal loaded to each solenoid valve drive circuit.

[0024] In order to load the corresponding channel PWM drive signal to the solenoid valve drive circuit, the drive control digital circuit of the present invention should at least include a drive processing circuit and a drive signal generating circuit, wherein the drive processing circuit receives the drive working information and generates the next cycle drive control information corresponding to the drive working information. Specifically, the drive working information at least includes the drive target frequency and the drive status information when each solenoid valve drives the corresponding solenoid valve. The drive target frequency can be determined according to the control requirements in the working scenario. The drive of each solenoid valve on the corresponding solenoid valve specifically refers to the drive of the solenoid valve drive circuit on the connected solenoid valve. The drive status information is generally related to the type of solenoid valve. The drive status will be described in detail below.

[0025] During specific implementation, the next cycle drive control information should at least include the next cycle drive clock information and the next cycle drive regulation information, wherein the next cycle drive clock information includes the next cycle channel drive clock number corresponding to each solenoid valve. Generally, the number of next cycle channel drive clocks should be consistent with the number of solenoid valves in a multi-way solenoid valve, that is, consistent with the number of solenoid valve drive circuits. Therefore, the next cycle channel drive clock number corresponds one-to-one to the solenoid valve drive circuit, and the next cycle channel drive clock number corresponding to each solenoid valve drive circuit may be different.

[0026] Specifically, the next-cycle drive control information includes several next-cycle channel drive start signals. The correspondence between the next-cycle channel drive start signals and the solenoid valve drive circuit can be found in the description of the correspondence between the next-cycle channel drive clock number and the solenoid valve drive circuit herein, and will not be further elaborated here. Generally, the next-cycle channel drive start signal serves as a drive enable signal. Therefore, the phases of different next-cycle channel drive start signals may vary, depending on the drive control requirements for different solenoid valves.

[0027] The drive processing circuit loads the generated drive control information for the next cycle into the drive signal generating circuit, so that the drive signal generating circuit generates a channel PWM drive signal corresponding to each solenoid valve. That is, for multi-way solenoid valves, the drive signal generating circuit generates multiple channel PWM drive signals, and the channel PWM drive signals are also in a one-to-one correspondence with the solenoid valves and the solenoid valve drive circuits. As can be seen from the above description, each PWM drive signal should be loaded into the corresponding solenoid valve drive circuit so that the required drive control of the connected solenoid valve can be performed through the solenoid valve drive circuit.

[0028] Since the PWM drive signal corresponds to the solenoid valve drive circuit and the solenoid valve, when generating the PWM drive signal, the corresponding channel drive clock number for the next cycle and the channel drive start signal for the next cycle should be obtained. Thereafter, the corresponding channel PWM drive signal can be generated. The generation of the channel PWM drive signal will be described in detail below.

[0029] In one embodiment of the present invention, the driving processing circuit includes a frequency processing unit, a phase scheduling unit, and a driving clock number generating unit, wherein: The frequency processing unit processes the driving target frequency and generates a next cycle reference clock number and a next cycle reference start signal corresponding to the driving target frequency, and loads the generated next cycle reference clock number to the driving clock number generating unit; Based on the next cycle reference start signal and the preset working phase of each solenoid valve, the phase scheduling unit generates the next cycle channel drive start signal and clock number generation request information corresponding to each solenoid valve, and loads all the next cycle channel drive start signals to the drive signal generation circuit; Based on the clock number, request information is generated, and the driving status information of each solenoid valve is collected in sequence. Based on the collected driving status information, at least the channel PWM proportion information corresponding to each solenoid valve driving circuit is determined. Thereafter, based on the corresponding channel PWM proportion information and the next cycle reference clock number, the driving clock number generation unit generates the next cycle channel driving clock number corresponding to each solenoid valve.

[0030] Figure 1 An embodiment of a drive processing circuit is shown in FIG. As can be seen from the figure, the drive processing circuit may include a frequency processing unit, a phase scheduling unit, and a drive clock number generating unit. Figure 1 The portion within the red dotted line is the driving clock number generation unit. After receiving the driving target frequency, the driving target frequency can be processed by the frequency processing unit to generate the reference clock number of the next cycle and the reference start signal of the next cycle after processing.

[0031] In one embodiment of the present invention, the frequency processing unit processes the driving target frequency, including: Counting the number of reference clocks of the current cycle, and generating a next cycle reference start signal when counting the number of reference clocks of the current cycle is completed, and when generating the next cycle reference start signal, updating the next cycle reference clock number, wherein, When the next starting reference clock number is updated, the next cycle reference clock number is calculated first. When calculating the next cycle reference clock number, the reference digital clock frequency in the frequency processing unit is obtained, and the result value of dividing the reference digital clock frequency by the driving target frequency is configured as the next cycle reference clock number.

[0032] Specifically, the frequency processing unit should include at least a frequency processing counter and a clock number calculator. The current reference clock number is the reference clock number that already exists in the frequency processing unit before receiving the driving target frequency. It can be understood that the current reference clock number and the next cycle reference clock number have the same meaning. The difference is that the current reference clock number and the next cycle reference clock number are targeted at different driving control cycles.

[0033] It is understood that the current cycle reference clock number is a clock count value. After determining the current cycle reference clock number, a frequency processing counter can be used for counting. The specific technical method is related to the base digital clock frequency used by the frequency processing counter. The specific calculation method and process can be consistent with the existing technology. After the current cycle reference clock number is counted, a next cycle reference start signal is immediately generated. The next cycle reference start signal is generally an identification signal. The generated next cycle reference start information can be used to mark the start of the next cycle drive control. Therefore, it can be seen that the moment the current cycle reference clock number is counted is considered the starting point of the next cycle. At the same time, the current cycle reference clock number is updated to obtain the next cycle reference clock number after the update.

[0034] It should be understood that after counting the updated reference clock number of the next cycle, the currently updated reference clock number of the next cycle becomes the reference clock number of the current cycle. When updating the reference clock number of the next cycle, the reference clock number of the next cycle should be calculated based on the driving target frequency. Specifically, if the driving target frequency is 21.5kHz and the reference digital clock frequency is 16MHz, the method for calculating the reference clock number of the next cycle can be: 16M / 21.5k=744, that is, the calculated reference clock number of the next cycle is 744. For other calculations, please refer to the description here and will not be repeated. Specifically, the calculation here can be performed using a clock number calculator. The frequency processing counter and the clock number calculator can adopt existing commonly used forms, based on the requirements of counting and calculation.

[0035] It can be seen from the above description that after the reference clock number of the next cycle is updated, the above counting of the reference clock of the current cycle will be repeated, that is, after receiving the driving target frequency, the frequency processing unit will repeat the above counting of the reference clock number of the current cycle - generating the reference start signal of the next cycle - updating the processing process of obtaining the reference clock number of the next cycle, so as to realize the required driving control of the solenoid valve.

[0036] After the frequency processing unit generates the next-cycle reference start signal, it should load the next-cycle reference start signal into the phase scheduling unit. The phase scheduling unit typically stores the preset operating phase for each solenoid valve. Therefore, upon receiving the next-cycle reference start signal, the next-cycle channel drive start signal and clock number generation request information can be generated based on the preset operating phase. It should be understood that the number of next-cycle channel drive start signals generated should be consistent with the number of solenoid valves. For example, if there are six solenoid valves in an application scenario, six next-cycle channel drive start signals should be generated, and these six next-cycle channel drive start signals should meet the preset operating phase. For example, the preset operating phase can be 40 clocks apart from the drive control phase of each solenoid valve. In this case, after receiving the next-cycle reference start signal, the next-cycle channel drive start signals corresponding to the six solenoid valves are generated sequentially after 0 clocks, 40 clocks, 80 clocks, 120 clocks, 160 clocks, and 200 clocks, respectively. For other preset operating phases, please refer to the corresponding instructions here.

[0037] It should be noted that the number of clocks of the above-mentioned phase interval can be obtained from the above-mentioned reference digital clock frequency. Therefore, the number of intervals during phase scheduling can be determined according to the reference digital clock frequency and the state of phase scheduling.

[0038] Furthermore, when the phase scheduling unit generates the corresponding next-cycle channel drive start signal, it should also output clock number generation request information and load the generated clock number generation request information into the drive clock number generation unit. As can be seen from the above description, the generated next-cycle channel drive start signal should be loaded into the drive signal generation circuit. Therefore, it can be seen that during drive control, the drive control of different solenoid valves will have a phase delay. In this case, on the one hand, better EMC characteristics can be obtained, and on the other hand, it is convenient for the drive clock number generation unit to generate the next-cycle channel drive clock number corresponding to different solenoid valves, thereby realizing resource scheduling and achieving the purpose of reducing the area and power consumption during drive control.

[0039] The clock number generation request information generated by the phase scheduling unit is generally related to the type of the solenoid valve, which is described in detail below.

[0040] In one embodiment of the present invention, the clock number generation request information includes a plurality of generation processing sub-requests, each generation processing sub-request corresponds to a solenoid valve and a solenoid valve driving circuit for driving and controlling the solenoid valve, wherein: When a solenoid valve is a digital solenoid valve, the corresponding generation processing sub-request includes the channel number corresponding to the current solenoid valve and the PWM ratio acquisition request corresponding to the current solenoid valve drive circuit, and the drive status information corresponding to the current solenoid valve is the channel PWM ratio information, where: When generating the channel drive clock number for the next cycle, based on the PWM ratio acquisition request, the channel PWM ratio information of the current solenoid valve drive circuit is obtained. Thereafter, based on the channel PWM ratio information and the reference clock number for the next cycle, the corresponding channel drive clock number for the next cycle is generated; When one solenoid valve is a current-type solenoid valve, the corresponding generation processing sub-request includes the channel number corresponding to the current solenoid valve and the PWM ratio calculation request corresponding to the current solenoid valve drive circuit, and the drive status information of the current solenoid valve drive circuit is at least the channel current, wherein, When generating the channel drive clock number for the next cycle, the corresponding channel current is obtained based on the PWM ratio calculation request, and the corresponding channel PWM ratio information is calculated based on the obtained channel current. Thereafter, the corresponding channel drive clock number for the next cycle is generated based on the channel PWM ratio information and the reference clock number for the next cycle.

[0041] In a specific implementation, the clock number generation request information should include multiple generation processing sub-requests, each generation processing sub-request corresponding to a solenoid valve and the solenoid valve drive circuit corresponding to the solenoid valve, that is, the generation processing sub-request and the solenoid valve are in a one-to-one correspondence. Generally, the solenoid valve can be a digital solenoid valve or a current-type solenoid valve. The use of a digital solenoid valve or a current-type solenoid valve can be consistent with the existing technology. It should be noted that in a multi-way solenoid valve, the types of solenoid valves in different channels can be the same or different. That is, the solenoid valves in the multi-way solenoid valve can be of the same type, such as all the solenoid valves are digital solenoid valves or current-type solenoid valves. Alternatively, the solenoid valves in the multi-way solenoid valve can be of different types, such as some solenoid valves are digital solenoid valves and some are current-type solenoid valves. Of course, the types of different solenoid valves in the multi-way solenoid valve can be selected according to actual needs to meet the actual application requirements.

[0042] Specifically, in order to achieve accurate correspondence with multi-way solenoid valves, each solenoid valve should be transformed, that is, when each solenoid valve and the corresponding solenoid valve drive circuit are used as a channel, they will correspond to a unique channel number. Therefore, each channel number can correspond to a solenoid valve and a solenoid valve drive circuit for driving the solenoid valve. The form of the channel number can be selected according to needs, so as to uniquely identify the corresponding solenoid valve and solenoid valve drive circuit.

[0043] In one embodiment of the present invention, when a solenoid valve is a digital solenoid valve, the corresponding generation processing sub-request includes a channel number corresponding to the current solenoid valve and a PWM ratio acquisition request corresponding to the current solenoid valve drive circuit. At this time, the channel number and the PWM ratio acquisition request are associated, and the drive state information corresponding to the current solenoid valve is the channel PWM ratio information, wherein the channel PWM ratio information specifically refers to the PWM ratio used by the solenoid valve drive circuit when driving the digital solenoid valve. Generally, the channel PWM ratio information used by the solenoid valve drive circuit when driving the digital solenoid valve can be directly obtained, such as Figure 1 shown.

[0044] In a specific implementation, for a PWM ratio acquisition request, the driving clock number generation unit may obtain corresponding channel PWM ratio information based on the channel number associated with the PWM ratio acquisition request. Thereafter, based on the channel PWM ratio information and the reference clock number of the next cycle, the corresponding channel driving clock number of the next cycle is generated. When generating the channel driving clock number of the next cycle, one feasible method is: When calculating the number of channel driving clocks for the next cycle, we have:

[0045] in, The number of channel driving clocks for the next cycle, is the channel PWM duty cycle information, is the maximum duty cycle, The reference clock number for the next cycle.

[0046] Specifically, the maximum duty cycle It can be predetermined according to the demand for driving and controlling the solenoid valve. In a specific design, the maximum duty cycle value can generally be determined by the range of the channel target current value and the value range of the PID operation coefficient information used when performing the PID operation below. In specific implementation, according to the range of the channel target current value and the PID operation coefficient information used when performing the PID calculation below, the range of the output quantity in the equilibrium state is obtained through PID operation, so as to determine the corresponding maximum duty cycle value. In one embodiment of the present invention, the maximum duty cycle value can be set to 1023.

[0047] It should be noted that for a digital solenoid valve, the maximum duty cycle reflects the control accuracy of the digital solenoid valve. For example, if 1023 is used as the maximum duty cycle, then the minimum control granularity is 1 / 1023=0.098%. Therefore, in specific implementation, when the solenoid valve is a digital solenoid valve, the maximum duty cycle can adopt the maximum duty cycle determined by the following current type electronic valve.

[0048] In addition, other calculation methods can be used to calculate the channel driving clock number of the next cycle. From the description here, it can be seen that the driving clock number generation unit mainly realizes the conversion of the channel PWM duty cycle into the corresponding driving clock number. Therefore, it can be seen that the driving clock number generation unit should at least include Figure 1 The channel PWM duty cycle conversion clock number unit in the channel PWM duty cycle conversion clock number unit can complete the above calculation to generate the calculation of the channel driving clock number of the next cycle and output it.

[0049] It should be understood that, for any solenoid valve using a digital solenoid valve, the drive clock number generating unit can use the above method to generate the corresponding channel drive clock number for the next cycle.

[0050] When one solenoid valve is a current-type solenoid valve, the generated processing sub-request should be the corresponding channel number and the corresponding PWM ratio calculation request. In other words, unlike the solenoid valve being a digital solenoid valve, the channel PWM ratio information of the current-type solenoid valve should be obtained through calculation, which means that the corresponding channel PWM ratio information cannot be directly obtained. Generally, the calculated channel PWM ratio information and the obtained channel PWM ratio information are both numerical values ​​representing the PWM ratio. When calculating the channel PWM ratio information, the drive status information of the current solenoid valve drive circuit is at least the channel current. Generally, the solenoid valve drive circuit is mostly in the form of an analog circuit, and the channel current in the drive status information is generally an analog current value.

[0051] As can be seen from the above description, the PMW ratio calculation request and the channel number are also associated. Therefore, for any PWM ratio calculation request, based on the channel number corresponding to the PWM ratio calculation request, the driving clock number generation unit can obtain the corresponding channel current. Thereafter, the driving clock number generation unit should calculate the corresponding channel PWM ratio information based on the channel current. Thereafter, the same method can be used to calculate the channel driving clock number for the next cycle, such as through Figure 1 The channel PWM duty cycle clock number unit generates the corresponding channel drive clock number for the next cycle. Figure 1 The calculation and generation of channel PWM ratio information is described in detail.

[0052] In one embodiment of the present invention, the calculation of channel PWM ratio information includes: Performing AD conversion on the acquired channel current to generate a channel quantized current value corresponding to the channel current; A PID operation is performed on the generated channel quantized current value to generate corresponding channel PWM ratio information after the PID operation.

[0053] Figure 1FIG2 shows an embodiment of calculating the channel PWM ratio information. As can be seen from the figure, when calculating the channel PWM ratio information, the driving clock number generation unit should include an ADC module and a PID operation module. For any PWM ratio acquisition request, the ADC module can obtain the channel current corresponding to the channel number associated with the PWM ratio request, such as Figure 1 As shown, thereafter, the acquired channel current can be AD-converted through the ADC module, and the corresponding channel quantized current value can be obtained after AD conversion. The method of performing AD conversion on the channel current and obtaining the channel quantized current value can be consistent with the existing technology and will not be repeated here.

[0054] After obtaining the channel quantized current value, the PID operation module can be used to perform PID operation, so that the channel PWM ratio information can be calculated after the PID operation. When performing the PID calculation, the channel target current value corresponding to the current channel code should be set, that is, the channel target current value should be related to the drive control state of the solenoid valve. Therefore, after determining the drive control state of the current-type solenoid valve, the corresponding channel target current value can be determined. Thereafter, the channel target current value is used as a reference value and the channel quantized current is used as an input value. Based on the channel quantized current value and the channel target current value, the corresponding channel PWM ratio information can be calculated using the existing commonly used PID operation method.

[0055] It should be understood that when performing PID operation, the proportional coefficient, integral coefficient and / or differential coefficient used in the PID operation should be determined. During specific implementation, the corresponding proportional coefficient, integral coefficient and / or differential coefficient can be determined by preliminary testing, trial and error, etc. The method for determining the corresponding proportional coefficient, integral coefficient and / or differential coefficient can be consistent with the existing technology and will not be repeated here.

[0056] As can be seen from the above description, when the solenoid valve is a current-type solenoid valve, the drive clock number generation unit should also include an ADC module and a PID operation module. It is understood that the ADC module may include one or more ADC submodules, and the PID operation module may include one or more PID operation submodules. When multiple ADC submodules and multiple PID operation submodules are present, a single ADC submodule and PID operation submodule can be used to perform the aforementioned ADC conversion and PID operation for one solenoid valve.

[0057] In order to further optimize resource scheduling, further reduce the area and power consumption during drive control, and thus reduce the drive control cost of multi-way solenoid valves, in one embodiment of the present invention, when generating the corresponding channel drive clock number for the next cycle for the multi-way solenoid valves, a drive clock number generation unit is configured based on the channel number of each solenoid valve to generate the corresponding channel drive clock number for the next cycle in a pipeline manner. Figure 1 , an embodiment using a pipeline method is shown. In this case, in the driving clock number generating unit, there is only one ADC sub-module in the ADC module, and there is only one PID operation sub-module in the PID operation module.

[0058] When the pipeline method is adopted, the driving clock number generation unit should obtain the above-mentioned channel PWM ratio information or calculate the channel PWM ratio information according to the channel number, that is, it can select and execute the above-mentioned corresponding process according to the channel number to achieve the state of multiplexing the ADC module, PID operation module and channel PWM duty cycle conversion clock number unit.

[0059] During specific implementation, the channel target current values ​​and PID operation coefficient information of different solenoid valves can be associated with the channel number and stored, so that after obtaining the corresponding channel number, the corresponding channel target current value and PID operation coefficient information can be read and configured in the PID operation module to realize the corresponding PID operation. Specifically, the PID operation coefficient information is the above-mentioned proportional coefficient, integral coefficient and / or differential coefficient.

[0060] In order to accurately realize the drive control of the solenoid valve, Figure 1 An embodiment of the present invention for following and transmitting the channel number is shown in FIG. , that is, when performing the above-mentioned data processing, it is necessary to bind with the corresponding channel number, so that the PWM drive information can be accurately loaded into the solenoid valve drive circuit of the corresponding channel number.

[0061] In one embodiment of the present invention, the driving signal generating circuit includes a plurality of mutually independent channel PWM driving signal generating units, wherein: A channel PWM drive signal generating unit is adaptively connected to a solenoid valve drive circuit, and each channel PWM drive signal generating unit receives the corresponding channel drive clock number of the next cycle and the channel drive start signal of the next cycle; Based on the received next cycle channel driving clock number and the next cycle channel driving start signal, the channel PWM driving signal generating unit generates a corresponding channel PWM driving signal and loads the generated channel PWM driving signal to the connected solenoid valve driving circuit.

[0062] In order to generate multiple PWM drive signals and load them to the corresponding solenoid valve drive circuits respectively, in one embodiment of the present invention, the drive signal generating circuit may include multiple independent channel PWM drive signal generating units. As can be seen from the above description, Figure 1The term "channel PWM drive signal generation unit" (plurality) refers to a plurality of channel PWM drive signal generation units. Specifically, the number of channel PWM drive signal generation units within the drive signal generation circuit is no less than the number of solenoid valve drive circuits, so that the solenoid valve drive circuits and channel PWM drive signal generation units are connected in a one-to-one correspondence.

[0063] It can be seen from the above description that the solenoid valve drive circuit corresponds to the above-mentioned channel number. Therefore, for any channel PWM drive signal generating unit, the above-mentioned next cycle channel drive clock number and the next cycle channel drive start signal can be loaded into the current solenoid valve drive circuit. Thereafter, the current channel PWM drive signal generating unit can generate a channel PWM drive signal and load the generated channel PWM drive signal into the corresponding solenoid valve drive circuit, wherein the corresponding solenoid valve drive circuit is the solenoid valve drive circuit connected to the channel PWM drive signal generating unit.

[0064] In one embodiment of the present invention, each channel PWM drive signal generating unit generates a channel PWM drive signal, including: After receiving a valid next cycle channel drive start signal, the channel PWM drive signal is configured to be in a valid state within the counting time of the next cycle channel drive clock number.

[0065] As can be seen from the above description, each channel PWM drive signal generating unit will simultaneously receive the channel drive clock number of the next cycle and the channel drive start signal of the next cycle. Specifically, when the channel drive start signal of the next cycle is in a valid state, the channel PWM drive signal is configured to be in a valid state within the counting time of the channel drive clock number of the next cycle. Among them, when the channel PWM drive signal is in a valid state, it generally means that the channel PWM drive signal is in a high-level state. It can be understood that outside the counting time of the channel drive clock number of the next cycle, the channel PWM drive signal should be in a low-level invalid state, thereby achieving a corresponding duty cycle control state.

[0066] Specifically, when the channel PWM drive signal configuration is in a valid state, the drive of the connected solenoid valve can be controlled by the solenoid valve drive circuit, and when the channel PWM drive signal is in an invalid state, generally, when the channel PWM drive signal is in an invalid state, the solenoid valve drive circuit cannot drive and control the solenoid valve.

[0067] In one embodiment of the present invention, the drive verification of the multi-way solenoid valve includes: The drive processing circuit, the drive signal generating circuit, the multi-way solenoid valve and the solenoid valve drive circuit adapted to the multi-way solenoid valve are comprehensively modeled using the Verilog hardware description language; During drive verification, the drive state information of the multi-channel solenoid valve drive circuit in the comprehensive modeling is loaded into the drive clock number generation unit, so that the drive clock number generation unit generates the next cycle channel drive clock number corresponding to the solenoid valve drive circuit.

[0068] It should be understood that in order to verify the driving effect of multi-way solenoid valves, drive verification should generally be carried out. In traditional verification, functional verification is usually achieved based on Matlab modeling simulation or mixed analog-digital simulation. Specifically, Matlab modeling simulation has the problem of inconsistency with the real RTL logic design, which is easy to miss design problems and cause tape-out failure. Mixed analog-digital simulation has the problem of too slow simulation speed and inability to transplant FPGA accelerated verification. It is difficult to perform full coverage of functional verification in a short period of time, delaying production and delivery time.

[0069] In order to effectively realize the drive verification of multi-way solenoid valves, the present invention adopts Verilog hardware description language for comprehensive modeling, that is, the above-mentioned drive processing circuit, drive signal generating circuit, multi-way solenoid valve and multi-way solenoid valve drive circuit are modeled through Verilog hardware description language. From the characteristics of Verilog hardware description language, it can be seen that it can effectively avoid the problems of inconsistent MATLAB design, slow speed of mixed digital and analog simulation and inability to transplant FPGA, thereby realizing reliable and efficient completion of the verification process.

[0070] In specific implementation, the drive processing circuit, the drive signal generating circuit and the multi-way solenoid valve drive circuit can be located in the same digital chip. Figure 1 In the figure, an embodiment of the drive verification is shown. The electromagnetic valve can be integrated into the simulation model, specifically referring to the modeling of the electromagnetic valve. Figure 2 An embodiment of an equivalent simplified solenoid valve drive circuit and a solenoid valve is shown in FIG.

[0071] Figure 2 In the figure, Vsup and Vpre are the voltage sources provided by the solenoid valve driver circuit. Vss is grounded and has a voltage value of 0V. The PWM drive signal (high-side hs, low-side ls) controls the switching of the voltage source provided to the solenoid valve. The solenoid valve driver circuit has an equivalent internal resistance Rint from the voltage source to the chip port. The solenoid valve can be equivalent to a series connection of resistance R and inductance L.

[0072] It should be noted that the true values ​​of both the high side and the low side follow the PWM drive signal state. The difference is that the low side is strictly equal to the PWM drive signal duration, while the high side needs to be = 1 a while before the low side = 1, and = 0 a while after the low side = 0. That is, from the time axis, the high side = 1 needs to cover the low side = 1, which is equivalent to dead zone protection.

[0073] In a specific implementation, determining the driving working state of the solenoid valve through the PWM driving signal includes: 1) High side = 1, low side = 1, at this time, Va = Vss = 0V; 2) High side = 0, low side = 0, at this time, Va = Vsup, this is generally a high positive voltage, that is, charging; 3) High side = 1, low side = 0. At this time, Va = Vpre, which is generally a negative voltage, that is, discharge.

[0074] Specifically, in the design implementation, there is no situation where the high side = 0 and the low side = 1. According to the circuit situation, the RL differential equation can be established, and then: ,in, That is Figure 2 Voltage in .

[0075] Since the PWM drive signal changes with the digital clock as the cycle, the frequency of the digital clock can be used as the minimum unit of change during discretization processing, and the corresponding Verilog hardware description language can be obtained, specifically: Va = (hs==1)?0:((ls==1) ?Vpre:Vsink); Vb =Va- I*(R+Rint); Inext = I + Vb / L; Initially, I=0. Every time the clock frequency passes, I=Inext, and the above operation is repeated.

[0076] Take the clock 16MHz, Vsup=12V, Vpre=-1V, Rint=0.1Ω, R=3.5Ω, L=5uH as an example: Va = (hs==1) ? 0 : ((ls==1)?-1_000_000 : 12_000_000); / / Unit: uV Vb = Va - I*3600; / / unit: uV Inext = I + Vb / 5000; / / unit (mA / 16_000_000) Register I is initialized to 0, connected to a 16 MHz clock, and D is connected to Inext. This allows the current value I to be implemented as a register. By modifying the smallest unit of parameters such as current, voltage, resistance, and inductance and converting them to fixed-point values, synthesizable logic can be implemented for FPGA simulation.

[0077] In summary, a drive control method suitable for a multi-way solenoid valve can be obtained. In one embodiment of the present invention, the multi-way solenoid valve to be driven and controlled is driven and controlled by the required drive control digital circuit.

[0078] Specifically, the driving control method of the multi-way solenoid valve can refer to the above description, and the specific method is based on whether the multi-way solenoid valve can be driven and controlled as required, which will not be repeated here.

Claims

1. A digital circuit for driving and controlling multi-way solenoid valves, characterized in that: Used to drive and control multiple solenoid valves, the drive control digital circuit includes: The driving processing circuit receives the driving operation information, generates the next cycle driving control information corresponding to the driving operation information, and loads the generated next cycle driving control information into the driving signal generating circuit, wherein: The driving operation information at least includes the driving target frequency and the driving state information when each solenoid valve driving circuit drives the corresponding solenoid valve; The next cycle driving control information at least includes the next cycle driving clock information and the next cycle driving regulation information; The next cycle driving clock information includes the next cycle channel driving clock number corresponding to each solenoid valve; The next cycle driving control information includes the next cycle channel driving start signal corresponding to each solenoid valve; The drive signal generating circuit generates a channel PWM drive signal corresponding to each solenoid valve based on the received next cycle drive control information, so as to configure the solenoid valve drive circuit based on the channel PWM drive signal to drive and control the connected solenoid valve, wherein: When generating the channel PWM drive signal corresponding to each solenoid valve, the next cycle channel drive clock number and the next cycle channel drive start signal corresponding to the current solenoid valve are obtained. Thereafter, the corresponding channel PWM drive signal is generated based on the obtained next cycle channel drive clock number and the next cycle channel drive start signal.

2. The drive control digital circuit for multi-way solenoid valves according to claim 1 is characterized in that: The driving processing circuit includes a frequency processing unit, a phase scheduling unit and a driving clock number generating unit, wherein: The frequency processing unit processes the driving target frequency and generates a next cycle reference clock number and a next cycle reference start signal corresponding to the driving target frequency, and loads the generated next cycle reference clock number to the driving clock number generating unit; Based on the next cycle reference start signal and the preset working phase of each solenoid valve, the phase scheduling unit generates the next cycle channel drive start signal and clock number generation request information corresponding to each solenoid valve, and loads all the next cycle channel drive start signals to the drive signal generation circuit; Based on the clock number, request information is generated, and the driving status information of each solenoid valve is collected in sequence. Based on the collected driving status information, at least the channel PWM proportion information corresponding to each solenoid valve driving circuit is determined. Thereafter, based on the corresponding channel PWM proportion information and the next cycle reference clock number, the driving clock number generation unit generates the next cycle channel driving clock number corresponding to each solenoid valve.

3. The digital circuit for driving and controlling a multi-way solenoid valve according to claim 2, characterized in that: The clock number generation request information includes a plurality of generation processing sub-requests, each generation processing sub-request corresponds to a solenoid valve and a solenoid valve driving circuit for driving and controlling the solenoid valve, wherein: When a solenoid valve is a digital solenoid valve, the corresponding generation processing sub-request includes the channel number corresponding to the current solenoid valve and the PWM ratio acquisition request corresponding to the current solenoid valve drive circuit, and the drive status information corresponding to the current solenoid valve is the channel PWM ratio information, where: When generating the channel drive clock number for the next cycle, based on the PWM ratio acquisition request, the channel PWM ratio information of the current solenoid valve drive circuit is obtained. Thereafter, based on the channel PWM ratio information and the reference clock number for the next cycle, the corresponding channel drive clock number for the next cycle is generated; When one solenoid valve is a current-type solenoid valve, the corresponding generation processing sub-request includes the channel number corresponding to the current solenoid valve and the PWM ratio calculation request corresponding to the current solenoid valve drive circuit, and the drive status information of the current solenoid valve drive circuit is at least the channel current, wherein, When generating the channel drive clock number for the next cycle, the corresponding channel current is obtained based on the PWM ratio calculation request, and the corresponding channel PWM ratio information is calculated based on the obtained channel current. Thereafter, the corresponding channel drive clock number for the next cycle is generated based on the channel PWM ratio information and the reference clock number for the next cycle.

4. The driving control digital circuit suitable for multi-way solenoid valves according to claim 3 is characterized in that: Calculation of channel PWM ratio information includes: Performing AD conversion on the acquired channel current to generate a channel quantized current value corresponding to the channel current; A PID operation is performed on the generated channel quantized current value to generate corresponding channel PWM ratio information after the PID operation.

5. The digital circuit for driving and controlling multi-way solenoid valves according to claim 2, characterized in that: For multi-way solenoid valves, when generating the corresponding channel drive clock number for the next cycle, based on the channel number of each solenoid valve, a drive clock number generation unit is configured to generate the corresponding channel drive clock number for the next cycle in a pipeline manner, wherein: When calculating the number of channel driving clocks for the next cycle, we have: in, The number of channel driving clocks for the next cycle, is the channel PWM duty cycle information, is the maximum duty cycle, The reference clock number for the next cycle.

6. The driving control digital circuit for multi-way solenoid valves according to any one of claims 1 to 5, characterized in that: The driving signal generating circuit includes a plurality of independent channel PWM driving signal generating units, wherein: A channel PWM drive signal generating unit is adaptively connected to a solenoid valve drive circuit, and each channel PWM drive signal generating unit receives the corresponding channel drive clock number of the next cycle and the channel drive start signal of the next cycle; Based on the received next cycle channel driving clock number and the next cycle channel driving start signal, the channel PWM driving signal generating unit generates a corresponding channel PWM driving signal and loads the generated channel PWM driving signal to the connected solenoid valve driving circuit.

7. The driving control digital circuit for multi-way solenoid valves according to claim 6, characterized in that: When each channel PWM drive signal generating unit generates a channel PWM drive signal, it includes: After receiving a valid next cycle channel drive start signal, the channel PWM drive signal is configured to be in a valid state within the counting time of the next cycle channel drive clock number.

8. The driving control digital circuit for multi-way solenoid valves according to any one of claims 2 to 5, characterized in that: The frequency processing unit processes the driving target frequency, including: Counting the number of reference clocks of the current cycle, and generating a next cycle reference start signal when counting the number of reference clocks of the current cycle is completed, and when generating the next cycle reference start signal, updating the next cycle reference clock number, wherein, When the next starting reference clock number is updated, the next cycle reference clock number is calculated first. When calculating the next cycle reference clock number, the reference digital clock frequency in the frequency processing unit is obtained, and the result value of dividing the reference digital clock frequency by the driving target frequency is configured as the next cycle reference clock number.

9. The driving control digital circuit for multi-way solenoid valves according to any one of claims 2 to 5, characterized in that: The drive verification of multi-way solenoid valves includes: The drive processing circuit, the drive signal generating circuit, the multi-way solenoid valve and the solenoid valve drive circuit adapted to the multi-way solenoid valve are comprehensively modeled using the Verilog hardware description language; During drive verification, the drive state information of the multi-channel solenoid valve drive circuit in the comprehensive modeling is loaded into the drive clock number generation unit, so that the drive clock number generation unit generates the next cycle channel drive clock number corresponding to the solenoid valve drive circuit.

10. A drive control method suitable for a multi-way solenoid valve, characterized in that: The multi-way solenoid valve to be driven and controlled is driven and controlled by the drive control digital circuit described in any one of claims 1 to 9.

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