Intelligent fault processing FA logic test device and method

Abstract

The invention provides an intelligent fault processing FA logic test device and method, the intelligent fault processing FA logic test device comprises a master control MCU, three feeder terminals, a relay protection instrument and a connection circuit, the master control MCU simulates two-way section switches and one-way interconnection switch in a three-section three-interconnection line by using software, the three feeder terminals are accessed at the same time, the feeder terminals control the master control MCU through control signals, and the relay protection instrument is connected with the master control MCU. And the intelligent fault processing FA logic is tested by simulating the on and off states of the switch and recording the moments of voltage, no voltage and switch displacement. The device can simulate all switches participating in FA logic on a real 10kV three-section three-tie line, can simulate a time-delay opening and closing working scene of a field switch, provides multiple feedback points, and provides good support for field installation test work of a feeder terminal carrying an intelligent fault processing FA.

Description

Technical Field

[0001] The present application belongs to the field of power grid control technology, and specifically relates to an intelligent fault processing FA logic testing device and method. Background Art

[0002] Intelligent fault handling FA is an algorithm used on 10kV feeder terminals (FTUs). Its purpose is to solve the problems of automatic disconnection of faulty lines and switching power supply to non-faulty lines in a 10kV power grid with a three-segment and three-connection structure.

[0003] The intelligent fault handling algorithm is an improvement on the conventional "voltage-time" FA algorithm. Based on the conventional "voltage-time" algorithm, it is optimized to "no tripping upon voltage loss, only tripping upon incoming power detection." The sectionalizer's voltage-loss tripping function is eliminated, and features such as "delayed tripping with forward blocking upon incoming power detection" and "tripping with reverse blocking upon short-duration incoming power detection" are added. For transient faults, a single reclosing action after protection action restores normal operation. For permanent faults, a single reclosing action, coordinated with the line breaker, rapidly isolates the fault and transfers power.

[0004] The intelligent fault handling (FA) algorithm operates on a three-segment, three-connection 10kV line. During operation, the three feeder terminals—section switch 1, section switch 2, and the connecting switch—must cooperate with each other to complete the operation. Traditional testing uses a relay to apply a characteristic signal to a single feeder terminal, which cannot meet the requirements of joint testing of three feeder terminals. Summary of the Invention

[0005] The present application provides an intelligent fault handling FA logic testing device and method to solve or partially solve the problems raised in the above background technology.

[0006] The present application provides an intelligent fault handling FA logic test device, comprising: a main control MCU, three feeder terminals, a relay protection instrument and a connection circuit;

[0007] Main control MCU, providing 3-way analog switch;

[0008] Relay protection instrument, output voltage, current, simulate line operation:

[0009] Feeder terminals correspond one-to-one with the 3-way analog switches of the main control MCU;

[0010] Connect the circuit, connect the main control MCU, relay protection device and feeder terminal:

[0011] The main control MCU uses software to simulate two section switches and one tie switch in the three-segment three-tie line, and is connected to three feeder terminals at the same time. The feeder terminals control the main control MCU through control signals to simulate the on and off states of the switches, thereby testing the intelligent fault handling FA logic.

[0012] Preferably, the main control MCU is integrated with a liquid crystal display to display the switch state and the interval time between two state switches as the test result.

[0013] Preferably, the 3-way analog switch of the main control MCU is set with two control access points of switch on and switch off and two feedback access points of switch on state and switch off state. Each state of the switch state feedback access point can output multiple groups of feedback signals for accessing the feeder terminal and the relay protection instrument.

[0014] Preferably, the connection circuit includes a voltage sampling input circuit, an opening and closing output circuit, and an opening and closing input circuit, wherein:

[0015] The voltage sampling input circuit connects the current and voltage input terminals of the feeder terminal to the current and voltage output terminals of the relay protection instrument to simulate the on-site line environment. The main control MCU uses a voltage transformer to monitor the input voltage and current of the feeder terminal. The voltage transformer of the main control MCU is connected in parallel with the voltage transformer of the feeder terminal, and the voltage transformer signal is converted into a digital signal by the AD conversion peripheral inside the MCU. After being processed by the main control MCU, the overvoltage and undervoltage of the feeder terminal are recorded.

[0016] The switch-on / off output circuit connects the switch-on control signal and switch-off control signal of the feeder terminal to the switch-on input point and switch-off input point of the main control MCU corresponding to the analog switch position respectively;

[0017] For the opening and closing input circuit, the closing feedback output terminal and the opening feedback output terminal of the main control MCU analog switch are connected to the feeder terminal and the switch status input terminal of the relay protection instrument respectively. The opening and closing signal of the feeder terminal is a 24V active input signal. In order to protect the test equipment, an optocoupler is added for protection before the signal is input to the MCU.

[0018] Preferably, the main control MCU sets the opening delay time and closing delay time of the 3-way simulated switch according to the type of real switch to be simulated. Specifically, the closing delay time of the hydraulic column-mounted switch circuit breaker is set to 60-120ms, and the opening delay time is set to 25-75ms. The closing delay time of the spring-operated column-mounted switch circuit breaker is set to 50-100ms, and the opening delay time is set to 50-70ms.

[0019] Preferably, the main control MCU is STM32F103, and the liquid crystal display is JLXK12864G-086 dot matrix screen.

[0020] The present application also provides an intelligent fault handling FA logic testing method, comprising the following steps:

[0021] Step 1: Set the protection parameter settings of the three-way analog switch and the state sequence of the relay protection instrument;

[0022] Step 2: The relay outputs state 1 and outputs normal voltage on both sides to switch positions 1, 2, and 3. The main control MCU generates event record 1 {all switches 1 have voltage}, event record 2 {all switches 2 have voltage}, and event record 3 {all switches 3 have voltage}, and records the time when the event occurs.

[0023] Step 3: The relay maintains the first time threshold T1 in state 1 and switches to state 2, simulating the tripping of the outgoing line switch fault. The output voltage to switch positions 1 and 2 is 0 at the same time, and the reverse output voltage to switch position 3 is normal. The main control MCU generates event record 4 {all switches 1 lose voltage}, event record 5 {all switches 2 lose voltage}, and event record 6 {switch 3 has reverse voltage}, and records the time of occurrence of the event.

[0024] Step 4: The relay maintains state 2 at T1 and switches to state 3, simulating the reclosing of the outgoing line switch. Normal voltage is output to both sides of switches 1 and 3, and normal voltage plus overcurrent is output to switch 2. The main control MCU generates event record 7 {all switches 1 have voltage}, event record 8 {all switches 2 have voltage}, and event record 9 {all switches 3 have voltage}, and records the time when the event occurs.

[0025] Step 5: After the No. 1 feeder terminal detects an overcurrent, it triggers the "incoming fault detection delay tripping and forward locking function". The feeder terminal outputs a tripping signal to the main control MCU. After receiving the tripping signal, the main control MCU controls the solid-state relay to open after the tripping delay. The switch tripping signal is fed back to the relay protection instrument and the feeder terminal. At the same time, the main control MCU generates event record 10 {Switch No. 1 is open};

[0026] Step 6: After receiving the feedback of the opening of switch No. 1, the relay protection instrument switches to state 4, simulates the state after the opening of switch No. 1, outputs the normal voltage on the positive side to switch No. 1, and the main control MCU generates event record 11 {switch No. 1 has positive pressure}, the output on both sides of switch No. 2 is no pressure, and the main MCU generates event record 12 {switch No. 2 has no pressure}, the output on the negative side of switch No. 3 is negative, and the main MCU generates event record 13 {switch No. 3 has negative pressure};

[0027] Step 7: When a short-term call on the No. 2 feeder terminal is within the short-term call time threshold T2, the "short-term call detection trip reverse blocking function" is triggered. The No. 2 feeder terminal sends a trip signal to the main control MCU. After receiving the trip signal, the test device opens the solid-state relay after the trip delay, and generates event record 14 {Switch No. 2 is open}.

[0028] Step 8: After step 6, the No. 3 feeder terminal detects that the short-term incoming call is not within the short-term incoming call blocking time threshold T3, and the feeder terminal sends a closing signal. After receiving the closing signal, the main control MCU closes the solid-state relay after the closing delay, and the signal is fed back to the feeder terminal and the relay protection device, and event record 15 {No. 3 switch closed} is generated at the same time;

[0029] Step 9: After the relay receives the closing feedback signal of switch No. 3, it switches to state 5, simulating the state after the delayed transfer of power by the tie switch, and outputs a normal voltage on one side in the forward direction to section switch No. 1. Since it is consistent with the output of state 4, the main control MCU does not generate an event record. It outputs a single-side voltage to switch No. 2, and the main control MCU generates event record 16 {switch No. 2 has reverse voltage}. It outputs a double-side voltage to switch No. 3, and the main control MCU generates event record 17 {switch No. 3 has full voltage}.

[0030] If, in a set of tests, the sequence of events and the intervals between events generated by the master MCU are consistent with the presets, it proves that the FA algorithm is effective and can be used on site. If they are inconsistent, it proves that the FA algorithm is invalid.

[0031] Preferably, in step 1, the protection parameter constants specifically include: the closing mechanical delay time, opening mechanical delay time, short-time power supply time threshold T2, locked transfer short-time power supply time threshold T3, fault detection opening delay T4, and delayed transfer time T5 of each analog switch.

[0032] Preferably, the interval between events is preset as follows:

[0033] When the relay is in state 1, simulating the initial state, the test device generates event records 1, 2, and 3 simultaneously, with the occurrence time being 0;

[0034] When the relay is in state 2, it simulates the opening of the outgoing line switch, and the test device simultaneously generates event records 4, 5, and 6, with the occurrence time being T1;

[0035] When the relay is in state 3, it simulates the reclosing of the outgoing breaker. The test device simultaneously generates event records 7, 8, and 9, which occur at intervals T1 and T5 compared to the previous group. Immediately afterwards, the No. 1 feeder terminal trips due to the "incoming power fault detection trip". The test device generates event 10, which occurs at an interval T4 and T6 compared to the previous group of events.

[0036] When the relay is in state 4, simulating the state after the No. 1 feeder terminal is tripped, the test device generates event records 11, 12, and 13 simultaneously with the previous set of events.

[0037] Then the No. 2 feeder terminal executes "Short-time incoming power trip", generating event record 14, which is the trip mechanical delay time between the previous event and the last event.

[0038] Feeder 3 terminal detects that the short-term incoming call time is not within the short-term incoming call time threshold T3 for blocking and transferring, and delays closing. The test device generates event record 15. The interval between events 11, 12, and 13 is the delayed transfer time T5 + closing mechanical delay time;

[0039] The relay protection instrument switches to state 5, simulating the state after delayed power transfer. The test device simultaneously generates event records 16 and 17, and the generation time is consistent with the previous set of time.

[0040] Compared with the prior art, this application has the following beneficial effects:

[0041] The intelligent fault handling FA logic testing method and device proposed in this application can simulate all switches participating in the FA logic on a real 10kV three-segment three-interconnection line, can simulate the delayed opening and closing working scenarios of the on-site switches, and provide multiple feedback points, which provides good support for the on-site installation and testing of feeder terminals equipped with intelligent fault handling FA. Compared with the traditional use of relay protection instruments to test a single switch, the device can simulate all switches (2 section switches, 1 interconnection switch) running the logic algorithm. The simulated switch can set the delayed opening and closing time according to the type of on-site switch, which effectively improves the authenticity of the test. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The present application is further described below with reference to the accompanying drawings and examples.

[0043] Figure 1 This is the logic diagram of the section switch power failure detection delay opening and forward locking function.

[0044] Figure 2 This is the logic diagram of the reverse blocking function of the sectionalizer when detecting short-time incoming power.

[0045] Figure 3 Automatically transfer logic diagram for contact switches,

[0046] Figure 4 This is a three-section three-connection line structure diagram.

[0047] Figure 5 This is the schematic diagram of the voltage sampling input circuit.

[0048] Figure 6This is the schematic diagram of the opening and closing output circuit.

[0049] Figure 7 This is the schematic diagram of the opening and closing input circuit.

[0050] Figure 8 This is a schematic diagram of the main control MCU interface. DETAILED DESCRIPTION

[0051] For example, certain words are used in the specification and claims to refer to specific components. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. This specification and claims do not use differences in names as a way to distinguish components, but use differences in the functions of the components as the criteria for distinction. For example, "including" mentioned throughout the specification and claims is an open term, so it should be interpreted as "including but not limited to". "Approximately" means that within an acceptable error range, those skilled in the art can solve the technical problem within a certain error range and basically achieve the technical effect.

[0052] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "horizontal", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings and are only used to facilitate the description of the present application and simplify the description. They do not indicate or imply that the devices or elements referred to must have a specific direction, be constructed and operate in a specific direction. Therefore, they should not be understood as limiting the present application.

[0053] In this application, unless otherwise specified or limited, the terms "mounted," "connected," "connect," "fixed," etc. should be understood broadly. For example, they can refer to fixed connection, detachable connection, or integral connection; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0054] Example 1

[0055] like Figures 1 to 8 As shown, the present application provides an intelligent fault handling FA logic test device, including: a main control MCU, three feeder terminals, a relay and a connecting circuit;

[0056] The main control MCU provides 3-way analog switches, including two segment switches and one tie switch;

[0057] Relay protection instrument, output voltage, current, simulate line operation:

[0058] Feeder terminals correspond one-to-one with the 3-way analog switches of the main control MCU;

[0059] Connect the circuit, connect the main control MCU, relay protection device and feeder terminal.

[0060] The main control MCU of this application is connected to three feeder terminals at the same time. The feeder terminal controls the main control MCU through a control signal to simulate the on and off states of the switch, and can notify the setting of the delay time when it makes a state switch to simulate the mechanical delay time of the switch. The main control MCU feeds back the switch state to the feeder terminal and the relay through a feedback signal.

[0061] like Figure 4 The figure shows the structure of the three-segment three-connection line for the intelligent fault handling FA logic application. In the figure, CB1 to CB4 are outgoing line switches, FB1 to FB2 are segment switches, and LS1 to LS3 are contact switches. The main control MCU of this application simulates the segment switches FB1, FB2 and the contact switch LS1. The three-segment three-connection line is a high-reliability wiring mode applied to the power distribution network. It optimizes the fault handling capability and improves the power supply continuity through segmentation and contact design. The distribution line is divided into three independent sections, and each section is isolated by a segment switch (controlled by the feeder terminal). A total of two segment switches are set. After segmentation, the fault can be quickly located and isolated, reducing the scope of the power outage. Contact switches are set at three key nodes of the line and connected with other distribution lines to form a redundant power supply path. In the event of a fault, the contact switch can switch the power supply to realize load transfer.

[0062] Specifically, the protection actions of the section switch are as follows:

[0063] (1) The function of delaying the tripping and positive locking when the power is detected. After the switch is closed and the power is cut off, if the power is detected and the fault still exists, the forward locking is directly performed after the delay tripping to isolate the front end of the fault section. At the same time, it provides a short-term power time judgment criterion for the rear-end sectional switch of the fault. The action logic is as follows: Figure 1 As shown;

[0064] (2) Short-time incoming call detection time trip and reverse locking function. After the switch is closed and the power is cut off, if a short-time incoming call is detected and meets the preset time parameters, the switch will automatically trip and reverse lock to achieve fault rear-end isolation. The pressure and no-pressure setting values ​​are the same as the incoming call detection fault delay trip and forward locking function. The action logic is as follows: Figure 2 shown.

[0065] Specifically, the protection actions of the tie switch are as follows:

[0066] After the voltage is lost on one side of the tie switch, a short-term power supply is sensed within the fault handling time window, and the short-term power supply time meets the fault characteristics of non-adjacent sections, and the power transfer delay timer is started. When the timer ends, the circuit breaker is automatically closed and the power supply is transferred. The action logic is as follows: Figure 3 shown.

[0067] Specifically, the main control MCU is integrated with a liquid crystal display to display the switch status and the interval time between two state switches as the test results.

[0068] Specifically, the 3-way analog switch of the main control MCU is set with two control access points of switch on and switch off and two feedback access points of switch on state and switch off state, and the mechanical delay of the switch is simulated by software.

[0069] Furthermore, each state of the switch state feedback access point of the analog switch of the main control MCU can output multiple groups of feedback signals for accessing the feeder terminal and the relay protection instrument.

[0070] Furthermore, according to the type of real switch to be simulated, the opening mechanical delay time and closing delay time of the 3-way simulated switch are set. Specifically, the closing delay time of the hydraulic pole-mounted switch circuit breaker is generally set to 60-120ms, and the opening delay time is generally set to 25-75ms. The closing delay time of the spring-operated pole-mounted switch circuit breaker is generally set to 50-100ms, and the opening delay time is generally set to 50-70ms.

[0071] Specifically, the connection circuit includes a voltage sampling input circuit, an opening and closing output circuit, and an opening and closing input circuit, wherein:

[0072] Voltage sampling input circuit, such as Figure 5 As shown in the figure, the current and voltage input terminals of the feeder terminal are connected to the current and voltage output terminals of the relay protection instrument to simulate the on-site line environment. The main control MCU uses a voltage transformer to monitor the input voltage and current of the feeder terminal. The voltage transformer of the main control MCU is connected in parallel with the voltage transformer of the feeder terminal, and the voltage transformer signal is converted into a digital signal by the AD conversion peripheral inside the MCU. After being processed by the main control MCU, the overvoltage, undervoltage, overcurrent and loss of current of the feeder terminal are recorded.

[0073] Opening and closing output circuit, such as Figure 6 As shown, the switch closing control signal and switch opening control signal of the feeder terminal are connected to the switch closing input point and switch opening input point of the main control MCU corresponding to the analog switch position respectively;

[0074] Opening and closing input circuit, such as Figure 7 As shown in the figure, the switch closing feedback output terminal and the switch opening feedback output terminal of the main control MCU analog switch are connected to the feeder terminal and the switch status input terminal of the relay protection instrument respectively. The feeder terminal opening and closing signal is a 24V active input signal. In order to protect the test equipment, an optocoupler is added for protection before the signal is input to the MCU.

[0075] The feeder terminal voltage is three-phase three-wire access, with phase B as the common point. If AB and BC are energized in a double transformer environment, there is pressure on both sides (all are energized). AB alone is energized for forward pressure, and BC alone is energized for reverse pressure.

[0076] This application uses software simulation and connection circuits to perfectly simulate the two-way section switches and one-way interconnection switch in the three-segment three-interconnection line. It can completely simulate the FA logic, link the test site switches to delay opening and closing working scenarios, and provide multiple feedback points, providing good support for the on-site installation and testing of feeder terminals equipped with intelligent fault handling FA.

[0077] Specifically, the main control MCU is STM32F103 and the LCD screen is JLXK12864G-086 dot matrix screen.

[0078] Example 2

[0079] Based on the intelligent fault handling FA logic testing device of Example 1, the present application also provides an intelligent fault handling FA logic testing method, which specifically includes the following steps:

[0080] Step 1: Set the protection parameter settings of the three-way analog switch and the state sequence of the relay protection instrument;

[0081] Step 2: The relay outputs state 1 and outputs normal voltage on both sides to switch positions 1, 2, and 3. The main control MCU generates event record 1 {all switches 1 have voltage}, event record 2 {all switches 2 have voltage}, and event record 3 {all switches 3 have voltage}, and records the time when the event occurs.

[0082] Step 3: The relay maintains the first time threshold T1 in state 1 and switches to state 2, simulating the tripping of the outgoing line switch fault. The output voltage to switch positions 1 and 2 is 0 at the same time, and the reverse output voltage to switch position 3 is normal. The main control MCU generates event record 4 {all switches 1 lose voltage}, event record 5 {all switches 2 lose voltage}, and event record 6 {switch 3 has reverse voltage}, and records the time of occurrence of the event.

[0083] Step 4: The relay maintains state 2 at T1 and switches to state 3, simulating the reclosing of the outgoing line switch. Normal voltage is output to both sides of switches 1 and 3, and normal voltage plus overcurrent is output to switch 2. The main control MCU generates event record 7 {all switches 1 have voltage}, event record 8 {all switches 2 have voltage}, and event record 9 {all switches 3 have voltage}, and records the time when the event occurs.

[0084] Step 5: After the No. 1 feeder terminal detects an overcurrent, it triggers the "incoming fault detection delay tripping and forward locking function". The feeder terminal outputs a tripping signal to the main control MCU. After receiving the tripping signal, the main control MCU controls the solid-state relay to open after the tripping delay. The switch tripping signal is fed back to the relay protection instrument and the feeder terminal. At the same time, the main control MCU generates event record 10 {Switch No. 1 is open};

[0085] Step 6: After receiving the feedback of the opening of switch No. 1, the relay protection instrument switches to state 4, simulates the state after the opening of switch No. 1, outputs the normal voltage on the positive side to switch No. 1, and the main control MCU generates event record 11 {switch No. 1 has positive pressure}, the output on both sides of switch No. 2 is no pressure, and the main MCU generates event record 12 {switch No. 2 has no pressure}, the output on the negative side of switch No. 3 is negative, and the main MCU generates event record 13 {switch No. 3 has negative pressure};

[0086] Step 7: When a short-term call on the No. 2 feeder terminal is within the short-term call time threshold T2, the "short-term call detection trip reverse blocking function" is triggered. The No. 2 feeder terminal sends a trip signal to the main control MCU. After receiving the trip signal, the test device opens the solid-state relay after the trip delay, and generates event record 14 {Switch No. 2 is open}.

[0087] Step 8: After step 6, the No. 3 feeder terminal detects that the short-term incoming call is not within the short-term incoming call blocking time threshold T3, and the feeder terminal sends a closing signal. After receiving the closing signal, the main control MCU closes the solid-state relay after the closing delay, and the signal is fed back to the feeder terminal and the relay protection device, and event record 15 {No. 3 switch closed} is generated at the same time;

[0088] Step 9: After the relay receives the closing feedback signal of switch No. 3, the relay switches to state 5, simulating the state after the delayed transfer of power by the interconnecting switch, and outputs normal positive single-side voltage to section switch No. 1. Since it is consistent with the output of state 4, the main control MCU does not generate an event record. It outputs single-side pressure to switch No. 2, and the main control MCU generates event record 16 {switch No. 2 has reverse pressure}. It outputs double-side pressure to switch No. 3, and the main control MCU generates event record 17 {switch No. 3 has full pressure}.

[0089] At this point, the FA logic of the three feeder terminals has been fully executed. When the relay is in state 1, it simulates the initial state, and the test device simultaneously generates event records 1, 2, and 3, with the occurrence time being 0.

[0090] When the relay is in state 2, it simulates the opening of the outgoing line switch, and the test device simultaneously generates event records 4, 5, and 6, with the occurrence time being T1;

[0091] When the relay is in state 3, it simulates the reclosing of the outgoing breaker. The test device simultaneously generates event records 7, 8, and 9, which occur at intervals T1 and T5 compared to the previous group. Immediately afterwards, the No. 1 feeder terminal trips due to the "incoming power fault detection trip". The test device generates event 10, which occurs at an interval T4 and T6 compared to the previous group of events.

[0092] The fault detection trip delay is the time it takes to delay tripping after a fault is detected in the FA logic. The trip mechanical delay is the time it takes for the switch to trip due to the electrical and mechanical connections between the switch branches and the trip action.

[0093] When the relay is in state 4, simulating the state after the No. 1 feeder terminal is tripped, the test device generates event records 11, 12, and 13 simultaneously with the previous set of events.

[0094] Then the No. 2 feeder terminal executes "Short-time incoming power trip", generating event record 14, which is the trip mechanical delay time between the previous event and the last event.

[0095] When the No. 3 feeder terminal detects that the short-term power supply time is not within the short-term power supply lock transfer time threshold T3, it delays closing. The test device generates event record 15. The interval between events 11, 12, and 13 is the delayed power supply time T5 + closing mechanical delay time;

[0096] The relay protection instrument switches to state 5, simulating the state after delayed power transfer. The test device simultaneously generates event records 16 and 17, and the generation time is consistent with the previous set of time.

[0097] If, in a set of tests, the sequence of events and the intervals between events generated by the master MCU are consistent with the presets, it proves that the FA algorithm is effective and can be used on site. If they are inconsistent, it proves that the FA algorithm is invalid and cannot be used on site.

[0098] In step 1, the analog switches corresponding to the two section switches are numbered as switch No. 1 and switch No. 2, the analog switch corresponding to the tie switch is numbered as switch No. 3, and the feeder terminals corresponding to switch No. 1, switch No. 2, and switch No. 3 are numbered as feeder terminal No. 1, feeder terminal No. 2, and feeder terminal No. 3, respectively.

[0099] In step 1, the protection parameter constants specifically include: the closing mechanical delay time, opening mechanical delay time, short-time power supply time threshold T2, locking transfer short-time power supply time threshold T3, fault detection opening delay T4, and delayed power supply time T5 of each analog switch. The first time threshold T1 is also a preset time parameter.

[0100] Typically, the first time threshold T1 is set to 3s, the short-time call time threshold T2 is set to 0.27-0.4s, the locking and transfer short-time call time threshold T3 is set to 0.14-0.27s, the fault detection and tripping delay T4 is set to 0.27s, and the delayed transfer time T5 is set to 10s.

[0101] In step 1, the state sequence of the relay device refers to various preset output state (voltage, current) combinations of the relay device, including state 1 to state 5.

[0102] The above describes the implementation methods of the present application in detail in conjunction with the accompanying drawings, but the present application is not limited to the above implementation methods. Various changes can be made within the scope of knowledge possessed by ordinary technicians in the relevant technical field without departing from the purpose of the present application.

Claims

1. An intelligent fault handling FA logic test device, characterized in that: include: Main control MCU, 3 feeder terminals, relay protection device and connecting circuits; Main control MCU, providing 3-way analog switch; Relay protection instrument, output voltage simulates line operation: Feeder terminals correspond one-to-one with the 3-way analog switches of the main control MCU; Connect the circuit, connect the main control MCU, relay protection device and feeder terminal: The main control MCU uses software to simulate two section switches and one tie switch in the three-segment three-tie line, and is connected to three feeder terminals at the same time. The feeder terminals control the main control MCU through control signals to simulate the on and off states of the switches, and record the moments of pressure, no pressure, and switch position change to test the intelligent fault handling FA logic.

2. The intelligent fault handling FA logic test device according to claim 1, characterized in that: The main control MCU is integrated with a liquid crystal display to display the switch status and the interval time between two state switches as the test results.

3. The intelligent fault handling FA logic test device according to claim 1, characterized in that: The 3-way analog switch of the main control MCU is set with two control access points of switch on and switch off, and two feedback access points of switch on state and switch off state. Each state of the switch state feedback access point can output multiple groups of feedback signals for accessing the feeder terminal and the relay protection instrument.

4. The intelligent fault handling FA logic test device according to claim 3, characterized in that: The connection circuit includes a voltage sampling input circuit, an opening and closing output circuit, and an opening and closing input circuit, wherein: The voltage sampling input circuit connects the current and voltage input terminals of the feeder terminal to the current and voltage output terminals of the relay protection instrument to simulate the on-site line environment. The main control MCU uses a voltage transformer to monitor the input voltage and current of the feeder terminal. The voltage transformer of the main control MCU is connected in parallel with the voltage transformer of the feeder terminal, and the voltage transformer signal is converted into a digital signal by the AD conversion peripheral inside the MCU. After being processed by the main control MCU, the overvoltage and undervoltage of the feeder terminal are recorded. The switch-on / off output circuit connects the switch-on control signal and switch-off control signal of the feeder terminal to the switch-on input point and switch-off input point of the main control MCU corresponding to the analog switch position respectively; For the opening and closing input circuit, the closing feedback output terminal and the opening feedback output terminal of the main control MCU analog switch are connected to the feeder terminal and the switch status input terminal of the relay protection instrument respectively. The opening and closing signal of the feeder terminal is a 24V active input signal. In order to protect the test equipment, an optocoupler is added for protection before the signal is input to the MCU.

5. The intelligent fault handling FA logic test device according to claim 3, characterized in that: The main control MCU sets the opening and closing mechanical delay times of the three-way simulated switches according to the type of real switch to be simulated. The closing mechanical delay time of the hydraulic column-mounted switch circuit breaker is set to 60-120ms, and the opening mechanical delay time is set to 25-75ms. The closing mechanical delay time of the spring-operated column-mounted switch circuit breaker is set to 50-100ms, and the opening mechanical delay time is set to 50-70ms.

6. The intelligent fault handling FA logic test device according to claim 2, characterized in that: The main control MCU is STM32F103, and the LCD screen is JLXK12864G-086 dot matrix screen.

7. An intelligent fault handling FA logic testing method, characterized in that: The steps include: Step 1: Set the protection parameter settings of the three-way analog switch and the state sequence of the relay protection instrument; Step 2: The relay outputs state 1 and outputs normal voltage on both sides to switch positions 1, 2, and 3. The main control MCU generates event record 1 {all switches 1 have voltage}, event record 2 {all switches 2 have voltage}, and event record 3 {all switches 3 have voltage}, and records the time when the event occurs. Step 3: The relay maintains the first time threshold T1 in state 1 and switches to state 2, simulating the tripping of the outgoing line switch fault. The output voltage to switch positions 1 and 2 is 0 at the same time, and the reverse output voltage to switch position 3 is normal. The main control MCU generates event record 4 {all switches 1 lose voltage}, event record 5 {all switches 2 lose voltage}, and event record 6 {switch 3 has reverse voltage}, and records the time of occurrence of the event. Step 4: The relay maintains state 2 at T1 and switches to state 3, simulating the reclosing of the outgoing line switch. Normal voltage is output to both sides of switches 1 and 3, and normal voltage plus overcurrent is output to switch 2. The main control MCU generates event record 7 {all switches 1 have voltage}, event record 8 {all switches 2 have voltage}, and event record 9 {all switches 3 have voltage}, and records the time when the event occurs. Step 5: After the No. 1 feeder terminal detects an overcurrent, it triggers the "incoming fault detection delayed tripping and forward blocking function". The feeder terminal outputs a trip signal to the main control MCU. After receiving the trip signal, the main control MCU controls the solid-state relay to open after the trip delay. The switch trip signal is fed back to the relay protection device and the feeder terminal. At the same time, the main control MCU generates event record 10 {Switch No. 1 is open}; Step 6: After receiving the feedback of the opening of switch No. 1, the relay protection instrument switches to state 4, simulates the state after the opening of switch No. 1, outputs the normal voltage on the positive side to switch No. 1, and the main control MCU generates event record 11 {switch No. 1 has positive pressure}, the output on both sides of switch No. 2 is no pressure, and the main MCU generates event record 12 {switch No. 2 has no pressure}, the output on the negative side of switch No. 3 is negative, and the main MCU generates event record 13 {switch No. 3 has negative pressure}; Step 7: When a short-term call on feeder 2 falls within the short-term call time threshold T2, the "short-term call detection trip reverse blocking function" is triggered. Feeder 2 sends a trip signal to the main control MCU. Upon receiving the trip signal, the test device opens the solid-state relay after the trip delay, and generates event record 14 {Switch 2 open}. Step 8: After step 6, the No. 3 feeder terminal detects that the short-term incoming call is not within the short-term incoming call blocking time threshold T3, and the feeder terminal sends a closing signal. After receiving the closing signal, the main control MCU closes the solid-state relay after the closing delay, and the signal is fed back to the feeder terminal and the relay protection device, and event record 15 {No. 3 switch closed} is generated at the same time; Step 9: After the relay receives the closing feedback signal of switch No. 3, it switches to state 5, simulating the state after the delayed transfer of power by the tie switch, and outputs a normal voltage on one side in the forward direction to section switch No.

1. Since it is consistent with the output of state 4, the main control MCU does not generate an event record. It outputs a single-side voltage to switch No. 2, and the main control MCU generates event record 16 {switch No. 2 has reverse voltage}. It outputs a double-side voltage to switch No. 3, and the main control MCU generates event record 17 {switch No. 3 has full voltage}. If, in a set of tests, the sequence of events and the intervals between events generated by the master MCU are consistent with the presets, it proves that the FA algorithm is effective and can be used on site. If they are inconsistent, it proves that the FA algorithm is invalid.

8. The intelligent fault handling FA logic testing method according to claim 7, characterized in that: In step 1, the protection parameter constants specifically include: the closing mechanical delay time, opening mechanical delay time, short-time power supply time threshold T2, locking transfer short-time power supply time threshold T3, fault detection opening delay T4, and delayed transfer time T5 of each analog switch.

9. The intelligent fault handling FA logic testing method according to claim 8, characterized in that: The interval between events is preset as follows: When the relay is in state 1, simulating the initial state, the test device generates event records 1, 2, and 3 simultaneously, with the occurrence time being 0; When the relay is in state 2, it simulates the opening of the outgoing line switch, and the test device simultaneously generates event records 4, 5, and 6, with the occurrence time being T1; When the relay is in state 3, it simulates the reclosing of the outgoing breaker. The test device simultaneously generates event records 7, 8, and 9, which occur at intervals T1 and 15 respectively. Immediately thereafter, the No. 1 feeder terminal trips due to the "incoming power fault detection trip" event. The test device generates event 10, which occurs at intervals T4 and 15 respectively, which are longer than the previous event interval. When the relay is in state 4, simulating the state after the No. 1 feeder terminal is tripped, the test device generates event records 11, 12, and 13 simultaneously with the previous set of events. Then, the No. 2 feeder terminal executes "Short-time incoming power detection trip", generating event record 14, which is the tripping mechanical delay time between the previous event and the previous event. Feeder 3 terminal detects that the short-time incoming call time is not within the short-time incoming call time threshold T3 for blocking and transferring, and delays closing. The test device generates event record 15. The interval between events 11, 12, and 13 is the delayed transfer time T5 + closing mechanical delay time; The relay protection instrument switches to state 5, simulating the state after delayed power transfer. The test device simultaneously generates event records 16 and 17, and the generation time is consistent with the previous set of time.

Images