Verification method and system for maximum likelihood sequence detection chip

Abstract

The application provides a verification method and system of a maximum likelihood sequence detection chip, the verification method comprises creating a random environment, and a random model is created in the random environment; a verification environment is created, a reference model is run in the verification environment, and a device to be tested is run in the verification environment; the random environment is run, random configuration information is generated from the random environment and is sent to the reference model; the reference model forms a test signal according to the received configuration information, and inputs the test signal to the device to be tested; the reference model generates reference data according to the configuration information and outputs the reference data to a checker, the device to be tested generates running data after running according to the test signal and outputs the running data to the checker, and the checker compares the reference data with the running data and generates a verification result. The application also provides a verification system for realizing the above method. The application can realize decoupling of generation of configuration information and the verification environment, and improves the accuracy of chip verification.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip testing, in particular to a verification method of a maximum likelihood sequence detection chip based on SerDes and a verification system for implementing the verification method. BACKGROUND

[0002] A SerDes chip is a chip that converts parallel data into high-speed serial data or restores serial data into parallel data. With the increase of the communication rate of the SerDes chip, such as to 56Gbps or even 112Gbps, the signal will produce inter-symbol interference in channel transmission due to path loss, reflection, crosstalk and other reasons. The traditional simple threshold detection or DFE method cannot well compensate for channel damage. Therefore, it is necessary to introduce a maximum likelihood sequence detection (MLSD) algorithm in the SerDes chip, which is called a maximum likelihood sequence detection chip. Since the implementation of the maximum likelihood sequence detection chip has the problem of high complexity, it is necessary to verify the chip to ensure that the designed chip meets the preset requirements.

[0003] The existing chip verification method is to send a fixed-length test signal to the chip to be tested by a verification device. Usually, in order to verify the performance of the device to be tested, noise is added in the test signal. Then, the verification device receives the response data returned by the device to be tested, and judges whether the device to be tested meets the pre-set requirements according to the received response data.

[0004] However, the test signal input to the device to be tested by the traditional test method is often fixed, and it is often difficult to comprehensively test the problems of the device to be tested, resulting in that the verification of the chip is not comprehensive and accurate. The Chinese patent application for invention with publication number CN119203174A discloses a verification method of a chip encryption module. The method first acquires random input data, determines a first calculation result according to the random input data and the device to be tested, and determines a random detection result corresponding to the random input data according to the random input data and a pre-set detection model. Then, the first verification result corresponding to the device to be tested is determined according to the random detection result and the first calculation result.

[0005] The above method inputs random data to the device to be tested by the driving module during the test, so that the excitation signal input to the device to be tested is not a fixed sequence, but a randomly generated sequence, which can detect more hidden problems of the chip. However, since the driving module is also a module running under the test device and belongs to the verification environment, although the random data output by the driving module is a random test vector randomly generated within a certain constraint range, the constraint range is not managed separately, and in the case that the driving module itself is a module in the verification environment, there will be an implicit coupling between the configuration information input to the verification environment and the verification environment, which limits the coverage and affects the accuracy and comprehensiveness of the verification. In addition, the test method only generates random test vectors, and does not generate random configuration information for the coverage points for testing. Since the random test vectors often cannot cover a large number of coverage points, there will still be test blind spots that cannot be covered for chip verification, which affects the accuracy of the test. SUMMARY

[0006] The first object of the present application is to provide a verification method of a maximum likelihood sequence detection chip capable of improving verification coverage and verification accuracy.

[0007] The second object of the present application is to provide a verification system of a maximum likelihood sequence detection chip for implementing the above verification method.

[0008] To achieve the first object of the present application, the verification method of a maximum likelihood sequence detection chip provided by the present application comprises creating a random environment, creating a random model in the random environment; creating a verification environment, a reference model running in the verification environment, and a device to be tested running in the verification environment; running the random environment, generating random configuration information from the random environment and sending it to the reference model, the configuration information generated by the random environment including the running configuration information of the reference model and / or the configuration information of the registers of the device to be tested; the reference model forms a test signal according to the received configuration information and inputs it to the device to be tested; the reference model generates reference data according to the configuration information and outputs it to the checker, the device to be tested generates running data after running according to the test signal and outputs it to the checker, and the checker compares the reference data with the running data and generates a verification result.

[0009] From the above scheme can be seen, the present application creates a random environment and verification environment, from the random environment generates random configuration information and sends to the reference model, that is, the configuration information is not randomly generated by the drive module running in the verification environment, but is generated by the pre-created random environment according to the actual application scenario of the chip, so that the random configuration information generated by the random model can realize the decoupling of the generation and verification environment of the configuration information, effectively avoid the existence of implicit coupling between the configuration information and the verification environment, and can cover a wider range of chip running conditions, and the verification of the chip is more accurate.

[0010] In addition, since the present application is based on the pre-set configuration parameters to randomly generate configuration information, therefore, the configuration information is randomly generated, and the verification environment is tested by the test signal based on the configuration information. The configuration information of the present application includes the running configuration information of the reference model, the configuration information of the register of the device to be tested, and the like, so the configuration information actually sets the running conditions of the reference model and the configuration conditions of the device to be tested. The running conditions under different running conditions are simulated by randomly generating these configuration conditions. Therefore, the test signal of the present application is not a group of vectors randomly generated, but a test signal generated based on the randomly generated configuration information, so that the device to be tested can be tested under random configuration conditions during the verification process. Compared with the random test signal composed of random vectors, the present application can cover more running conditions, that is, the present application can cover more coverage points, and the verification of the chip is more comprehensive and accurate.

[0011] A preferred scheme is that before creating the random environment, the class of the random model is set, and the configuration parameters of the class are defined; when creating the random environment, the random model is created based on the class.

[0012] As can be seen, by creating a new class to define the random model, the creation of the random model is facilitated, and the problem of defining the random model by itself every time the random environment is created can be avoided, thereby improving the creation efficiency of the random environment.

[0013] A further scheme is that when defining the configuration parameters of the class of the random model, the configuration parameters are constrained based on the application scenario parameters of the device to be tested.

[0014] A further scheme is that when the random environment generates the configuration information, the configuration information is randomly generated within the constraint condition range of the configuration parameters.

[0015] As can be seen, since the configuration parameters of the class of the random model are constrained based on the application scenario parameters of the device to be tested, the configuration parameters will not exceed the boundary of the constraint condition, thereby avoiding the generation of unexpected configuration information and affecting the accuracy of the chip verification.

[0016] Further, the reference model determines the signal value of the test signal in each clock cycle and sends the corresponding signal value to the device under test in each clock cycle.

[0017] Thus, the test signal is input to the device under test according to the actual situation in each clock cycle, so that the device under test can accurately receive the test signal in each clock cycle, and accurate data is provided for subsequent verification.

[0018] Further, when determining the signal value of the test signal in each clock cycle, the signal value corresponding to each clock cycle is determined according to the delay of the test signal in multiple clock cycles.

[0019] Thus, the delay is considered when sending the test signal, so that the device under test can receive the corresponding test signal at the accurate time, avoiding the influence of the inaccuracy of the test signal receiving time on the accuracy of chip verification.

[0020] Further, the reference model sends the reference data to the checker according to the clock cycle, and the device under test sends the running data to the checker according to the clock cycle, and the checker compares the consistency of the reference data and the running data in each clock cycle.

[0021] Thus, the checker compares the reference data and the running data according to the clock cycle, so that the abnormal result of the device under test in which clock cycle can be accurately found, and the position of the abnormal device under test can be accurately judged, so that the test personnel can quickly find the abnormal reason.

[0022] Further, the device under test includes a data module and an adaptive module, and the data module and the adaptive module both receive the test signal from the reference model; the checker includes a data checker and an adaptive checker, the data checker receives the running data output by the data module and compares it with the reference data output by the reference model, and the adaptive checker receives the running data output by the adaptive module and compares it with the reference data output by the reference model.

[0023] Thus, the corresponding checker is set for the data module and the adaptive module, that is, the data checker and the adaptive checker are set, the running data output by the data module is compared with the reference data output by the reference model through the data checker, and the running data output by the adaptive module is compared with the reference data output by the reference model through the adaptive checker, so that the problems existing in the data module and the adaptive module can be checked respectively, and the accuracy of verification is improved.

[0024] Further, the data module and the adaptive module are independently operated and generate respective operation data.

[0025] Further, the data module also receives the data output by the adaptive module and generates corresponding operation data; and the adaptive module also receives the data output by the data module and generates corresponding operation data.

[0026] Therefore, when the data module and the adaptive module are independently operated and tested, the accuracy of the operation of the data module and the adaptive module can be verified respectively, and when the data module and the adaptive module are connected and verified, whether the data interaction between the two modules is correct can be verified, and through the above two verification modes, the separate operation and the data interaction of the two modules can be accurately verified, thereby covering complete operation scenarios.

[0027] To achieve the above second object, the verification system of the maximum likelihood sequence detection chip provided by the application includes a random environment, a random model is run in the random environment, and the random environment is used to generate random configuration information, which includes the operation configuration information of the reference model and / or the configuration information of the registers of the device to be tested; a verification environment, the reference model is run in the verification environment, and the device to be tested is run in the verification environment, the reference model is used to receive the configuration information generated by the random environment, and form a test signal according to the configuration information, and input the test signal to the device to be tested; the verification environment is also provided with an inspector, the inspector receives the reference data generated by the reference model according to the configuration information and the operation data generated by the device to be tested according to the test signal, compares the reference data with the operation data and generates a verification result.

[0028] As can be seen from the above scheme, the configuration information input to the reference model is generated by the random environment, specifically, by the random model running in the random environment. Since the configuration parameters of the random model are constrained based on the application scenario parameters of the device to be tested, the configuration information generated by running the random environment can avoid the potential implicit coupling of the configuration parameters and the verification environment, thereby covering more verification scenarios and improving the coverage and accuracy of chip verification.

[0029] A preferred scheme is that the device to be tested includes a data module and an adaptive module, the inspector includes a data inspector and an adaptive inspector, the data inspector is used to receive the operation data output by the data module and compare with the reference data output by the reference model, and the adaptive inspector is used to receive the operation data output by the adaptive module and compare with the reference data output by the reference model.

[0030] Therefore, using the data checker and the adaptive checker respectively to verify the data module and the adaptive module respectively can more accurately realize the respective verification of the two modules and improve the accuracy of the verification. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 is a structural block diagram of the verification system of the maximum likelihood sequence detection chip in the first verification state.

[0032] Figure 2 is a structural block diagram of the verification system of the maximum likelihood sequence detection chip in the second verification state.

[0033] Figure 3 is a flow chart of the verification method embodiment of the maximum likelihood sequence detection chip.

[0034] The application will be further described below in combination with the drawings and embodiments. DETAILED DESCRIPTION

[0035] The verification method of the maximum likelihood sequence detection chip is used for verifying a device to be tested, in particular a chip to be tested. The application generates configuration information by creating a random environment running a random model, and outputs the configuration information to a reference model in a verification environment, so as to verify the device to be tested, so that the configuration parameters can cover a wider running environment, and the accuracy of chip verification is improved.

[0036] Verification system embodiment of the maximum likelihood sequence detection chip:

[0037] The verification system of this embodiment is used for verifying a maximum likelihood sequence detection (MLSD) chip based on a serializer / deserializer (Serdes), and random configuration information is generated by a random environment to a verification environment, a test sequence is generated by the verification environment based on the configuration information and sent to a device to be tested, and whether the device to be tested meets the expected design requirements is verified by comparing the difference between the data returned by the device to be tested and reference data.

[0038] Reference Figure 1The verification system of the embodiment includes a random environment 10 and a verification environment 20, the random environment 10 runs a random model 11, the verification environment 20 runs a reference model 21, and a device to be tested also runs in the verification environment 20. The random environment 10 is mainly used to generate random configuration information to the verification environment 20, and the verification environment 20 verifies the device to be tested based on the received configuration information. For this purpose, a checker needs to be set in the verification environment 20, which is used to receive the running data output by the device to be tested. In addition, the reference model 21 also generates reference data according to the received configuration information, and the checker compares the received reference data with the running data output by the device to be tested, for example, compares the reference data and the running data in each clock cycle according to the clock cycle, so as to judge whether the device to be tested meets the preset design requirements.

[0039] In the embodiment, the device to be tested is a chip implementing a maximum likelihood sequence detection algorithm, for example, the device to be tested includes a data module (MLSD_DATA) 23 and an adaptive module (MLSD_ADAPT) 26, each of which implements its own function, and the two modules also transmit data to each other, for example, the data module 23 is used to calculate the values of branch metrics, path accumulation and decision values, and the adaptive module 26 is used to calculate the score threshold (level value) of the maximum likelihood sequence detection algorithm.

[0040] In order to verify the data module 23 and the adaptive module 26 respectively, the checker includes a data checker 24 and an adaptive checker 27, the data checker 24 receives the reference data output by the reference model 21 and the running data output by the data module 23, and compares the reference data output by the reference model 21 with the running data output by the data module 23, so as to judge whether the data module 23 has incorrect running. The adaptive checker 27 receives the reference data output by the reference model 21 and the running data output by the adaptive module 26, and compares the reference data output by the reference model 21 with the running data output by the adaptive module 26, so as to judge whether the adaptive module 26 has incorrect running.

[0041] In the process of verifying the device to be tested, the reference model 21 receives the configuration information output from the random environment 10, and generates the correct result that the data module 23 should output according to the configuration information, that is, the reference data of the data module 23, which is output to the data checker 24. In addition, the reference model 21 also generates the correct result that the adaptive module 26 should output according to the configuration information, that is, the reference data of the adaptive module 26, which is output to the adaptive checker 27.

[0042] On the other hand, the reference model 21 generates a test signal required to be output to the data module 23 according to the received configuration information, and the test signal is output to the data module 23 through the data signal input module 22. Meanwhile, the reference model 21 also generates a test signal required to be output to the adaptive module 26, and the test signal is output to the adaptive module 26 through the adaptive signal input module 25.

[0043] Since the data module 23 and the adaptive module 26 can be operated independently, that is, operated without data interaction between each other, and the data module 23 and the adaptive module 26 can also be operated in association, that is, the data module 23 and the adaptive module 26 perform data interaction during operation. In the case of independent operation of the data module 23 and the adaptive module 26, the correctness of the respective operation of the data module 23 and the adaptive module 26 can be verified, and in the case of associated operation of the data module 23 and the adaptive module 26, whether the data interaction between the data module 23 and the adaptive module 26 is correct can be verified. The contents of the verification under the two operation conditions are not the same, and therefore, it is usually necessary to perform the above two verification operations respectively, that is, it is necessary to verify whether the data module 23 and the adaptive module 26 are respectively correct, and it is also necessary to verify whether the data interaction between the data module 23 and the adaptive module 26 is correct.

[0044] In Figure 1 Under the connection mode shown, there is no data interaction between the data module 23 and the adaptive module 26, and in this state, the data module 23 and the adaptive module 26 will be operated independently, and the data module 23 will output the result of independent operation, that is, the operation data generated during independent operation, to the data checker 24, and the data checker 24 will judge whether an abnormal condition occurs when the data module 23 is operated independently. Moreover, the adaptive module 26 will also output the result of independent operation, that is, the operation data generated during independent operation, to the adaptive checker 27, and the adaptive checker 27 will judge whether an abnormal condition occurs when the adaptive module 26 is operated independently.

[0045] In Figure 2Under the connection mode shown, data module 23 and adaptive module 26 interact with each other in data, for example, data module 23 needs to output the decision value obtained by operation to adaptive module 26, while adaptive module 26 outputs the score threshold obtained by operation to data module 23. In this way, data module 23 performs subsequent calculation based on the obtained score threshold and outputs running data, and correspondingly, adaptive module 26 also performs subsequent calculation based on the obtained decision value and outputs corresponding running data. The running data output by data module 23 is also output to data checker 24, and the running data output by adaptive module 26 is also output to adaptive checker 27. It should be noted that in the case of mutual data interaction between data module 23 and adaptive module 26, the running data output by data module 23 is different from the running data output by data module 23 in the case of independent running, therefore, reference model 21 needs to generate corresponding reference data according to the condition of whether data module 23 and adaptive module 26 are independently running or associated running, to ensure that data checker 24 can accurately judge the true running condition of data module 23.

[0046] Verification method for maximum likelihood sequence detection chip

[0047] The following will be combined Figure 3 The working method of the above verification system is introduced. First, step S1 is executed, and the class of the random model is set. For example, a class named RandModel is defined, the matlab model is defined in the class, and the configuration required by the target algorithm is performed, that is, the setting of the configuration parameters. In this embodiment, the device to be tested is a chip implementing maximum likelihood sequence detection algorithm, therefore, the configuration parameters include channel insertion loss, implementation code of optimized continuous time linear equalizer (CTLE_code), dc_noise, mode of adaptation, gain, seed number of simulation, register configuration, etc. When setting the configuration parameters, the configuration parameters need to be constrained. For example, the application scenario parameters derived from the actual product constrain each configuration parameter by accurately modeling various configuration requirements under the actual application conditions, so that the values of each configuration parameter are within the pre-set constraint range, thereby ensuring that the subsequently randomly generated configuration information can fully cover the real working state and boundary conditions of the chip.

[0048] Then, step S2 is executed, and an independent random environment is created, in which the random model runs. It should be noted that the random environment runs independently of the verification environment, that is, the running of the random environment is not disturbed by the verification environment, and the running of the random environment also does not depend on the data output by the verification environment. In this way, the random model in the random environment is completely created based on the RandModel class defined in step S1.

[0049] The process of creating the random model is also the process of instantiating the random model, specifically, a specific object is created according to the class defined in step S1, and the object is the created random model. Since the configuration parameters of the class of RandModel have been constrained in step S1, the configuration parameters of the random model are randomly selected within the set constraint range when instantiated, so the configuration parameters of the random model generated each time are not the same, and the generated configuration information is also not the same, thereby avoiding the problem of outputting fixed configuration information to the verification environment.

[0050] The random environment generates random configuration information after running. In order to verify the rationality of the configuration information, the configuration information can be functionally sampled, for example, the configuration information output by the random model is obtained, and it is judged whether the output configuration information meets the expected requirements, for example, whether the configuration information exceeds the pre-set constraint range. If it does not exceed the pre-set constraint range, it is considered that the configuration information is reasonable, and if it exceeds the pre-set constraint range, it indicates that the configuration information generation is abnormal, and the configuration parameters need to be redefined and the configuration information needs to be regenerated. Of course, if the content of the configuration information needs to be increased subsequently, the configuration parameters of the class of the random model can be redefined to increase new configuration parameters, so that the random model can generate new configuration information. And sampling the configuration information can also facilitate the subsequent analysis and supplement of the coverage of the configuration information.

[0051] Then, step S3 is performed to create a verification environment, and a data transmission interface is defined in the verification environment for signal transmission. The random environment and the verification environment can realize data transmission through the data transmission interface, for example, the random environment outputs the configuration information to the verification environment through the data transmission interface. The created verification environment includes a reference model, a checker, etc., and the device under test also runs on the verification model.

[0052] In this embodiment, the device under test includes a data module and an adaptive module, and correspondingly, the checker includes a data checker and an adaptive checker. After creating the verification environment, the data module, the adaptive module and the data transmission interface need to be instantiated, and the connection between the modules is realized. For example, the data transmission interface can be connected to the reference model, the reference model receives the configuration information output by the random environment, the data module can be connected to the data checker, and the adaptive module can be connected to the adaptive checker, etc. In addition, clock signals and reset signals also need to be generated in the verification environment. The reference model, the data module, the adaptive module, the data checker and the adaptive checker all need to work under the same clock signal, so as to facilitate subsequent verification of the running data output by the data module and the adaptive module according to the clock signal.

[0053] Then, step S4 is performed, and the random environment is run, for example, the VCS simulator is started to run the random environment alone. After the random environment is run, the random model will generate configuration information, which is the configuration information randomly generated within the constraint condition of the configuration parameters. The configuration information generated by the random environment includes the running configuration information of the reference model and the configuration information of the registers of the device to be tested. Specifically, part of the configuration information is used to control the running of the matlab reference model, such as the random generation of the noise of matlab controlled by the random seed number, and part of the configuration information is used to control the register configuration of the device to be tested, for example, the gain of the adaptive module. The greater the gain of the adaptive module, the slower the adaptive tracking speed, but the stability is better. The smaller the gain, the faster the tracking speed, but the stability is poor. Since the random model can randomly generate configuration information, the gain of the adaptive module is also randomly generated within the constraint range. The configuration information output to the device to be tested is not the same and has randomness, so the running status of the adaptive module under different gains can be verified, so as to judge whether the device to be tested meets the running requirements under different gains. Since the embodiment randomly generates configuration information and verifies the device to be tested based on the configuration information, different configuration information actually verifies different performance of the device to be tested, so the embodiment can cover more coverage points of the device to be tested, so as to more comprehensively and accurately verify the device to be tested.

[0054] Of course, the configuration information can also be specified by the tester through the plusarg command. In this way, the tester can specify specific configuration information according to the actual test needs, so as to avoid the problem that the random generation of configuration information does not completely cover the specific test conditions, so that the verification of the device to be tested can cover all blind spots, and the accuracy of the verification is improved.

[0055] Since the test signal of the embodiment is not a simple random vector, but a test signal generated based on the randomly generated configuration information, and the configuration information includes the running configuration information of the reference model and the configuration information of the registers of the device to be tested, the running conditions of the reference model and the configuration conditions of the device to be tested are randomized, so the embodiment can simulate the running conditions under different running conditions by randomly generating these configuration conditions. Compared with the way of using only random vectors to constitute a random test signal in the prior art, the embodiment can cover more running conditions, that is, more coverage points, and the verification of the chip is more comprehensive and accurate.

[0056] Then, step S5 is performed to run the verification environment, for example, to start the VCS simulation tool to run the verification environment. After the reference model is run, the reference model receives the configuration information from the random model through the data transmission interface, and generates the test signals required by the device under test according to the configuration information. Since the device under test contains the data module and the adaptive module, the test signals required by the data module and the adaptive module need to be generated respectively, and these test signals are output according to each clock cycle.

[0057] In the verification environment, the data signal input module and the adaptive signal input module are also run, and the test signals required by the data module generated by the reference model are first output to the data signal input module, and then output to the data module by the data signal input module according to each clock cycle. In addition, the test signals required by the adaptive module generated by the reference model are first output to the adaptive signal input module, and then output to the adaptive module by the adaptive signal input module according to each clock cycle. Since the reference model, the data signal input module, the data module, the data checker, and the adaptive signal output module, the adaptive module, and the adaptive checker all receive the same clock signal and work based on the unified clock signal, the reference model outputs the corresponding test signals in turn according to the working timing requirements of the data module and the adaptive module. Specifically, when the reference model sends the test signals, it needs to determine the signal value of the test signal under each clock cycle, and send the corresponding signal value to the data module and the adaptive module in each clock cycle. Since the test signals sent to the data module and the adaptive module are different, the reference model needs to generate corresponding test signals respectively and send them to the data module and the adaptive module according to each clock cycle.

[0058] In addition, since signal transmission delay may occur during the operation of the device under test, a reasonable delay needs to be set in the test signal. Therefore, when determining the signal value of the test signal under each clock cycle, the signal value corresponding to each clock cycle is determined according to the delay of the test signal under multiple clock cycles, so that the test signals sent to the data module and the adaptive module contain the delay, thereby verifying whether the data module and the adaptive module can correctly output the corresponding data under the corresponding delay respectively.

[0059] Then, step S6 is performed, and after the data module receives the test signals, it runs according to the received test signals and forms running data, and outputs the running data to the data checker. At the same time, the adaptive module also runs according to the received test signals and forms corresponding running data, and outputs the running data to the adaptive checker.

[0060] In addition, while the data module and the adaptive module output running data, the reference model also sends reference data to the checker according to the clock cycle. Specifically, the reference model applies the received configuration information to run and generates corresponding running results, including the running results of the data module and the running results of the adaptive module. The running results are the reference data. The parameter data corresponding to the data module is sent to the data checker, and the reference data corresponding to the adaptive module is sent to the adaptive checker.

[0061] Finally, step S7 is performed. The data checker compares the running data output by the data module and the reference data output by the reference model and generates a verification result therefrom. Specifically, since the data module receives the test signal according to the clock cycle, it also outputs running data according to the clock cycle. The reference model also outputs reference data according to the clock cycle. Therefore, the data checker can receive the reference data and the running data under each clock cycle and compare the reference data and the running data in units of clock cycles, thereby quickly analyzing the clock cycle in which the running data output by the data module is incorrect and further quickly determining the cause of the running error of the data module, such as which part of the data module is incorrect in design.

[0062] Similarly, the adaptive checker compares the running data output by the adaptive module and the reference data output by the reference model and generates a verification result therefrom. Specifically, since the adaptive module receives the test signal according to the clock cycle, it also outputs running data according to the clock cycle. The reference model also outputs reference data according to the clock cycle. Therefore, the adaptive checker can receive the reference data and the running data under each clock cycle and compare the reference data and the running data in units of clock cycles, thereby quickly analyzing the clock cycle in which the running data output by the adaptive module is incorrect and further quickly determining the cause of the running error of the adaptive module.

[0063] It should be noted that when performing step S6 and performing step S7, two cases of testing can be divided, that is, the data module and the adaptive module run independently, and the data module and the adaptive module are associated with running. In the case of independent running of the data module and the adaptive module, the data module does not send data to the adaptive module, and the adaptive module does not send data to the data module. The data module only receives test signals from the reference model and runs based on the test signals, thereby outputting running data. Correspondingly, the reference model also generates corresponding reference data under the condition of independent running of the data module. Therefore, the verification result generated by the data checker is a verification result under the condition of independent running of the data module. Similarly, when the adaptive module runs independently, the verification result generated by the adaptive checker is a verification result under the condition of independent running of the adaptive module. In this case, it can be verified whether the data module itself runs abnormally, and whether the adaptive module itself runs abnormally.

[0064] In the case of associated running of the data module and the adaptive module, the data module receives not only test signals from the reference model but also data output from the adaptive module during the running process. The data module runs based on the test signals and the data output from the adaptive module, thereby generating running data. Correspondingly, the reference model also generates corresponding reference data under the condition of associated running of the data module and the adaptive module. Therefore, the verification result generated by the data checker is a verification result under the condition of associated running of the data module and the adaptive module. Similarly, when the data module and the adaptive module are associated with running, the verification result generated by the adaptive checker is a verification result under the condition of associated running of the data module and the adaptive module. In this case, it can be verified whether the data interaction between the data module and the adaptive module is abnormal.

[0065] Generally, when verifying a chip, not only the running conditions of each module itself need to be verified, but also the data interaction between the modules needs to be verified. Therefore, both cases need to be tested, and the tests of the two cases are complementary. For example, first, the running conditions of each module itself are verified to determine whether each module itself has design abnormalities. If each module itself does not have design abnormalities, it is still necessary to verify whether the data exchange between each module is abnormal. Therefore, verification can be performed first in the case of independent running of each module, and then verification can be performed in the case of associated running of each module.

[0066] Since the random model of the random environment can generate random configuration information each time, through multiple verifications, multiple configuration information can cover more random scenarios, which can avoid the coverage blind area caused by using fixed configuration information in the verification process, so that the verification result of the chip is more accurate.

[0067] In addition, since the configuration information received by the reference model is from the random model running in a random environment, and the random model is run independently of the verification environment, that is, the verification environment does not interfere with the running of the random model, and will not cause any interference to the configuration information generated by the random model. Compared with the verification method of generating random numbers in the verification environment through the driving module, the present application can realize the decoupling of the generation and verification process of the configuration information, that is, the generation of the configuration information is not associated with the verification environment, which can effectively prevent the implicit coupling existing in the verification environment and the configuration information generation process. Moreover, since the class of the random model is defined in advance, and the configuration parameters of the class are constrained, that is, the generation of the configuration information is managed independently of the verification environment, thereby ensuring the independence of the configuration information, so that the generation of the configuration information is not disturbed by the verification environment, further preventing the implicit coupling existing in the verification environment and the configuration information generation process.

[0068] In addition, when generating the configuration information, in addition to generating random configuration information through the random model, manual setting by the tester is also allowed, for example, for the case not covered by the random configuration information, the manual setting of the configuration information is used to cover the conditions not verified, thereby improving the coverage of the verification.

[0069] In addition, the test signal generated by the embodiment can be periodically changed, so that the parameter data generated by the reference model should also be periodically changed, and if the device to be tested can run correctly, the output data should also be periodically changed. Therefore, the checker can further judge whether the data module and the adaptive module are abnormal by judging whether the data output by the device to be tested is periodically changed, and the accuracy of the verification of the device to be tested can be further improved.

[0070] Finally, it should be emphasized that the above is only the preferred embodiment of the present application, and is not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications, any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method of verifying a maximum likelihood sequence detection chip, characterized by, The method comprises: creating a random environment, and creating a random model in the random environment; creating a verification environment, wherein a reference model runs in the verification environment, and a device to be tested runs in the verification environment; running the random environment, generating random configuration information by the random environment and sending the configuration information to the reference model, wherein the configuration information generated by the random environment comprises running configuration information of the reference model and / or configuration information of registers of the device to be tested; the reference model forms test signals according to the received configuration information, and inputs the test signals to the device to be tested; the reference model generates reference data according to the received configuration information and outputs the reference data to a checker, the device to be tested generates running data according to the test signals and outputs the running data to the checker, and the checker compares the reference data with the running data and generates a verification result; wherein the random environment runs independently of the verification environment, and the running of the random environment does not depend on data output by the verification environment; before creating the random environment, setting a class of the random model, defining configuration parameters of the class, and creating the random model based on the class when creating the random environment; when defining the configuration parameters of the class of the random model, the configuration parameters are constrained based on application scenario parameters of the device to be tested; when the random environment generates the configuration information, the configuration information is randomly generated within the constraint condition range of the configuration parameters.

2. The verification method of the maximum likelihood sequence detection chip according to claim 1, wherein: when the reference model inputs the test signals to the device to be tested, the signal values of the test signals in each clock cycle are determined, and the corresponding signal values in each clock cycle are sent to the device to be tested; the reference model sends the reference data to the checker according to clock cycles, the device to be tested sends the running data to the checker according to clock cycles, and the checker compares the consistency of the reference data and the running data in each clock cycle.

3. The verification method of the maximum likelihood sequence detection chip according to claim 2, wherein: when the signal values of the test signals in each clock cycle are determined, the signal values corresponding to each clock cycle are determined according to the delay conditions of the test signals in multiple clock cycles.

4. The verification method of the maximum likelihood sequence detection chip according to any one of claims 1 to 3, wherein: the device to be tested comprises a data module and an adaptive module, and the data module and the adaptive module both receive test signals from the reference model; the checker comprises a data checker and an adaptive checker, the data checker receives running data output by the data module and compares the running data with reference data output by the reference model, and the adaptive checker receives running data output by the adaptive module and compares the running data with reference data output by the reference model.

5. The verification method of the maximum likelihood sequence detection chip according to claim 4, wherein: The data module and the adaptive module are independently operated and generate respective operation data. 6.The verification method of a maximum likelihood sequence detection chip according to claim 4, characterized in that: The data module further receives data output by the adaptive module and generates corresponding operation data, and the adaptive module further receives data output by the data module and generates corresponding operation data.

7. A verification system for maximum likelihood sequence detection chips, characterized by Comprise: A random environment in which a random model is operated, the random environment is used to generate random configuration information, the configuration information generated by the random environment comprises operation configuration information of a reference model and / or configuration information of a register of a device to be tested; A verification environment in which a reference model is operated, the device to be tested is operated in the verification environment, the reference model is used to receive the configuration information generated by the random environment, and form a test signal according to the configuration information, and input the test signal to the device to be tested; The verification environment is further provided with an inspector, the inspector receives reference data generated by the reference model according to the configuration information and operation data generated by the device to be tested according to the test signal, compares the reference data with the operation data and generates a verification result; Wherein, the random environment is independently operated from the verification environment, and the operation of the random environment does not depend on the data output by the verification environment; Before creating the random environment, a class of the random model is set, and configuration parameters of the class are defined, and when the random environment is created, the random model is created based on the class; When defining the configuration parameters of the class of the random model, the configuration parameters are constrained based on application scenario parameters of the device to be tested; When the random environment generates the configuration information, the configuration information is randomly generated within the constraint condition range of the configuration parameters. 8.The verification system of a maximum likelihood sequence detection chip according to claim 7, characterized in that: The device to be tested comprises a data module and an adaptive module, the inspector comprises a data inspector and an adaptive inspector, the data inspector is used to receive operation data output by the data module and compare with reference data output by the reference model, and the adaptive inspector is used to receive operation data output by the adaptive module and compare with reference data output by the reference model.

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