Array substrate, display panel and display device

Abstract

The invention provides an array substrate, a display panel and a display device, a plurality of control signal lines in the array substrate are distributed at intervals along a first direction, and a plurality of data lines are distributed at intervals along a second direction and are spatially intersected with the control signal lines. The orthographic projections of the plurality of control signal lines on the substrate and the orthographic projections of the plurality of data lines on the substrate are enclosed to form a plurality of sub-pixel areas. The first connecting part comprises a first sub-connecting part and a second sub-connecting part, and the sub-pixel area comprises a pixel electrode. At least one sub-pixel region comprises a first thin film transistor and a second thin film transistor, a first electrode of the first thin film transistor is electrically connected with the first sub-connecting part, a first electrode of the second thin film transistor is electrically connected with the second sub-connecting part, and the first sub-connecting part and the second sub-connecting part are electrically connected to the same pixel electrode; the second electrode of the first thin film transistor and the second electrode of the second thin film transistor are electrically connected with the data line through the same second connecting part.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] In a display panel, a large overlapping area is easily generated between the routing structure for transmitting data signals and the routing structure for transmitting scanning signals. The larger overlapping area often leads to a larger parasitic capacitance, which causes a delay in the transmission of the data signal, resulting in insufficient charging of the pixel circuit, affecting the normal display effect of the display panel. Summary of the Invention

[0003] Embodiments of the present application provide an array substrate, a display panel, and a display device, which can improve display reliability.

[0004] In a first aspect, embodiments of the present application provide an array substrate, comprising a substrate, a plurality of control signal lines, a plurality of data lines, a first connecting portion, a second connecting portion, a pixel electrode, a first thin-film transistor, and a second thin-film transistor. The control signal lines are disposed on the substrate and spaced apart along a first direction. The data lines are disposed on the substrate and spaced apart along a second direction and spatially intersecting with the control signal lines. The first direction, the second direction, and the thickness direction of the array substrate intersect with each other. The orthographic projections of the plurality of control signal lines and the orthographic projections of the plurality of data lines on the substrate enclose a plurality of sub-pixel regions.

[0005] The first connection portion includes a first sub-connection portion and a second sub-connection portion, the pixel electrode is disposed on the substrate, and the sub-pixel region includes the pixel electrode. The first thin-film transistor and the second thin-film transistor are disposed on the substrate, and at least one sub-pixel region includes the first thin-film transistor and the second thin-film transistor. The first electrode of the first thin-film transistor is electrically connected to the first sub-connection portion, the first electrode of the second thin-film transistor is electrically connected to the second sub-connection portion, the first sub-connection portion and the second sub-connection portion are electrically connected to the same pixel electrode, and the second electrode of the first thin-film transistor and the second electrode of the second thin-film transistor are electrically connected to the data line via the same second connection portion.

[0006] In a second aspect, an embodiment of the present application provides a display panel, which includes the display array substrate in any of the aforementioned embodiments.

[0007] In a third aspect, an embodiment of the present application provides a display device, which includes the display panel in any of the aforementioned embodiments.

[0008] Embodiments of the present application provide an array substrate, a display panel, and a display device, wherein multiple thin-film transistors are provided within at least one sub-pixel region, thereby reducing the size W of a single thin-film transistor. Furthermore, a first connecting portion and a second connecting portion are further provided within the array substrate. The first connecting portion enables electrical connection between the multiple thin-film transistors and the pixel electrode, and the second connecting portion enables electrical connection between the multiple thin-film transistors and the data line, thereby meeting the operational requirements of the pixel circuit. Furthermore, with this design, a smaller overlap area can be provided between the second connecting portion and the control signal line, thereby reducing parasitic capacitance, lowering the effect of parasitic capacitance on data signal transmission delays, and improving the charging capacity of the pixel circuit and the display reliability of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0010] Figure 1 This is a structural diagram of an array substrate in related technology;

[0011] Figure 2 This is a schematic structural diagram of an array substrate provided in an embodiment of the present application;

[0012] Figure 3 yes Figure 2 Schematic diagram of the enlarged structure at the middle area Q;

[0013] Figure 4 yes Figure 3 Schematic diagram of the cross-sectional structure at AA in the middle;

[0014] Figure 5 This is a structural diagram of another array substrate provided in an embodiment of the present application;

[0015] Figure 6 yes Figure 5 Schematic diagram of the cross-sectional structure at the middle BB;

[0016] Figure 7 This is a structural diagram of another array substrate provided in an embodiment of the present application;

[0017] Figure 8 This is a structural diagram of another array substrate provided in an embodiment of the present application;

[0018] Figure 9 yes Figure 8 Schematic diagram of the cross-section structure at CC;

[0019] Figure 10is a schematic cross-sectional structural diagram of another array substrate provided in an embodiment of the present application;

[0020] Figure 11 This is a structural diagram of another array substrate provided in an embodiment of the present application;

[0021] Figure 12 yes Figure 11 Schematic diagram of the cross-sectional structure at the middle BB;

[0022] Figure 13 is a structural diagram of a display panel provided in an embodiment of the present application;

[0023] Figure 14 It is a structural schematic diagram of a display device provided in an embodiment of the present application.

[0024] Marking Description:

[0025] 100, array substrate; 200, display panel; 300, display device;

[0026] 10. Substrate;

[0027] 20. Control signal line; 21. First sub-segment; 22. Second sub-segment; 23. Third sub-segment;

[0028] 30. Data cable; 31. Part I;

[0029] 41. First connection part; 411. First sub-connection part; 412. Second sub-connection part; 42. Second connection part; 43. Third connection part;

[0030] 51. pixel electrode; 52. common electrode;

[0031] 61, first thin film transistor; 611, first active structure; 62, second thin film transistor; 621, second active structure;

[0032] 70. Liquid crystal layer;

[0033] 80. Color film substrate;

[0034] 30', data signal line; 20', scanning signal line;

[0035] A1, sub-pixel area;

[0036] J1, first pole; J2, second pole; J3, control end;

[0037] X, first direction; Y, second direction; Z, thickness direction. DETAILED DESCRIPTION

[0038] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0039] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0040] There are many types of display panels, such as liquid crystal display panels, organic light emitting display panels, and micro-luminescent display panels. Taking the liquid crystal display panel as an example, the liquid crystal display panel includes an array substrate, a color filter substrate, and a liquid crystal layer located between the array substrate and the color filter substrate. The array substrate includes multiple scanning signal lines and data signal lines. Two adjacent scanning signal lines and two adjacent data signal lines together form a sub-pixel area. The sub-pixel area is usually provided with a part of the common electrode structure, the pixel electrode, the liquid crystal capacitor C LC , storage capacitor C ST and thin film transistors as switching devices.

[0041] Liquid crystal capacitor C LC It is composed of pixel electrodes and common electrodes, and is used to control the deflection angle of liquid crystal molecules, thereby changing the transmittance of light to present different brightness. Storage capacitor C ST There are many forms, such as storage capacitor C ST It can be composed of scanning lines and pixel electrodes, or storage capacitors C ST It can be composed of a common electrode line and a pixel electrode, wherein the common electrode line is used to provide a corresponding voltage signal to the common electrode. ST Used to maintain the liquid crystal capacitor C LC When the thin film transistor has leakage problems due to its own characteristics, the storage capacitor CST Can timely adjust the liquid crystal capacitor C LC Recharge.

[0042] For some products, such as low-resolution display panels, the size of the pixel electrode becomes larger due to the increase in the size of the sub-pixel area A1. The larger the size of the pixel electrode, the greater the current it requires. Therefore, the overcurrent capacity of the thin film transistor needs to be improved accordingly, which leads to the need to increase the corresponding size W of the thin film transistor. Among them, the size W refers to the width of the channel region in the thin film transistor. Further, as Figure 1 As shown, the increase in size W easily leads to a larger overlapping area between the data signal line 30' and the scanning signal line 20', which in turn leads to an increase in parasitic capacitance, a delay in the transmission of the data signal, and insufficient charging of the pixel circuit, affecting the normal display effect of the display panel.

[0043] Regarding the above issues, please refer to Figures 2 to 4 An embodiment of the present application provides an array substrate 100, comprising a substrate 10, a plurality of control signal lines 20, a plurality of data lines 30, a first connecting portion 41, a second connecting portion 42, a pixel electrode 51, a first thin-film transistor 61, and a second thin-film transistor 62. The control signal lines 20 are disposed on the substrate 10 and are spaced apart along a first direction X. The data lines 30 are disposed on the substrate 10 and are spaced apart along a second direction Y and spatially intersect with the control signal lines 20. The first direction X, the second direction Y, and the thickness direction Z of the array substrate 100 intersect with each other. The orthographic projections of the plurality of control signal lines 20 and the plurality of data lines 30 on the substrate 10 enclose a plurality of sub-pixel areas A1.

[0044] The first connection portion 41 includes a first sub-connection portion 411 and a second sub-connection portion 412. The pixel electrode 51 is disposed on the substrate 10, and the sub-pixel area A1 includes the pixel electrode 51. A first thin-film transistor 61 and a second thin-film transistor 62 are disposed on the substrate 10. At least one sub-pixel area A1 includes the first thin-film transistor 61 and the second thin-film transistor 62. The first electrode J1 of the first thin-film transistor 61 is electrically connected to the first sub-connection portion 411, and the first electrode J1 of the second thin-film transistor 62 is electrically connected to the second sub-connection portion 412. The first sub-connection portion 411 and the second sub-connection portion 412 are electrically connected to the same pixel electrode 51. The second electrode J2 of the first thin-film transistor 61 and the second electrode J2 of the second thin-film transistor 62 are electrically connected to the data line 30 via the same second connection portion 42.

[0045] The array substrate 100 is used to form the display panel 200. The embodiment of the present application does not limit the specific type of the display panel 200. Optionally, the array substrate 100 can be used to form a liquid crystal display panel 200. The substrate 10 is a film layer structure used to support and bear the load in the array substrate 100. Other film layer structures and device structures are stacked in sequence on the substrate 10. The stacking arrangement mentioned here means that the other film layer structures and device structures are arranged in sequence along the thickness direction Z of the substrate 10. Among them, the thickness direction Z of the substrate 10 is usually consistent with the thickness direction Z of other film layers and the thickness direction Z of the array substrate 100. For ease of understanding, the embodiment of the present application illustrates the thickness direction Z of the substrate 10, the thickness direction Z of the array substrate 100, and the thickness direction Z of other film layers in the same direction.

[0046] The control signal lines 20 are used to transmit scanning signals, and a plurality of control signal lines 20 are spaced apart in a first direction X. The data lines 30 are used to transmit data signals, and a plurality of data lines 30 are spaced apart in a second direction Y. The plurality of data lines 30 are spatially intersecting with the control signal lines 20. The term "spatially intersecting" herein means that the extension directions of the data lines 30 and the control signal lines 20 intersect, and the orthographic projections of the plurality of data lines 30 on the substrate 10 overlap with the orthographic projection of the same control signal line 20 on the substrate 10.

[0047] In some optional embodiments, the first direction X, the second direction Y, and the thickness direction Z are perpendicular to each other, the control signal line 20 extends along the second direction Y, and the data line 30 extends along the first direction X. The "control signal line 20 extends along the second direction Y" mentioned here means that the control signal line 20 as a whole has a tendency to extend along the second direction Y. The control signal line 20 can be a straight line structure parallel to the second direction Y, or the control signal line 20 can also intersect with the second direction Y at some positions, for example, in a wavy or broken line shape in part or as a whole, as long as the control signal line 20 as a whole has a tendency to extend along the second direction Y. Similarly, "the data line 30 extends along the first direction X" means that the data line 30 as a whole has a tendency to extend in the first direction X.

[0048] The sub-pixel area A1 is defined by the control signal lines 20 and the data lines 30. Specifically, two adjacent control signal lines 20 in the first direction X and two adjacent data lines 30 in the second direction Y enclose a sub-pixel area A1. In the subsequently formed display panel 200, the sub-pixel areas A1 correspond one to one with sub-pixels. A sub-pixel is the smallest unit used by the display panel 200 to implement the display function. Multiple adjacent sub-pixels can form a pixel unit. Multiple pixel units are arranged in an array. A pixel unit is the smallest repeating unit used by the display panel 200 to implement the display function.

[0049] In some optional embodiments, the display device 300 formed by the array substrate 100 further includes a source driver chip and a gate driver chip. The source driver chip is used to provide data signals to the data lines 30, and the gate driver chip is used to provide scan signals to the control signal lines 20. The source driver chip and the gate driver chip can be integrated into one driver chip. Further optionally, the array substrate 100 includes a display area and a frame area surrounding the display area. The multiple sub-pixel areas A1 are all located in the display area, and the source driver chip and the gate driver chip are both located in the frame area.

[0050] The pixel electrode 51 is located within the array substrate 100. There are multiple pixel electrodes 51, and the multiple pixel electrodes 51 are located in multiple sub-pixel areas A1 and are spaced apart from each other. The pixel electrode 51 can form an electric field structure together with the common electrode 52 to drive the deflection of liquid crystal molecules, thereby changing the transmittance of light and presenting different brightness. The common electrode can have various positions. For example, the common electrode can be located within the array substrate so that the pixel electrode 51 and the common electrode are located on the same side of the liquid crystal layer 70 in the thickness direction Z. Alternatively, the common electrode 52 can also be located within the color filter substrate so that the liquid crystal layer is sandwiched between the pixel electrode 51 and the common electrode.

[0051] In addition to the above structure, the array substrate 100 further includes a first thin film transistor 61 and a second thin film transistor 62. At least one sub-pixel area A1 includes the first thin film transistor 61 and the second thin film transistor 62. The first thin film transistor 61 and the second thin film transistor 62 both include a first electrode J1, a second electrode J2, and a control terminal J3. One of the first electrode J1 and the second electrode J2 is a source electrode, and the other is a drain electrode. The control terminal J3 is used to control whether the first electrode J1 and the second electrode J2 are conductive.

[0052] The second electrode J2 of the first thin-film transistor 61 and the second electrode J2 of the second thin-film transistor 62 are electrically connected to the data line 30 via the same second connection portion 42. In other words, the second connection portion 42 can transmit data signals, and a single second connection portion 42 can be electrically connected to both the first thin-film transistor 61 and the second thin-film transistor 62 within a single sub-pixel area A1. The specific relationship between the second connection portion 42 and the data line 30 is not limited in this embodiment of the present application. For example, the second connection portion 42 can be a partial structure within the data line 30, or the second connection portion 42 can be located outside the data line 30 and electrically connected to the data line 30.

[0053] As for the first electrode J1 of the first thin-film transistor 61 and the first electrode J1 of the second thin-film transistor 62, they are electrically connected to the first sub-connection portion 411 and the second sub-connection portion 412, respectively, and the first sub-connection portion 411 and the second sub-connection portion 412 are electrically connected to the same pixel electrode 51. In other words, the first electrode J1 of the first thin-film transistor 61 and the first electrode J1 of the second thin-film transistor 62 are electrically connected to the same pixel electrode 51 through different connection structures. As a result, the switching element in at least one sub-pixel area A1 is not composed of a single thin-film transistor, but is composed of at least two thin-film transistors. The first sub-connection portion 411 and the second sub-connection portion 412 can be electrically connected to the pixel electrode 51 separately, or they can be electrically connected to each other through other connection portions and electrically connected to the pixel electrode 51 through these connection portions.

[0054] It should be noted that part of the structure in the control signal line 20 is reused as the control terminal J3 of the thin film transistor. Specifically, the part of the structure on the control signal line 20 that overlaps with the active structure in the thin film transistor is the control terminal J3 of the thin film transistor. The active structure includes a source region, a drain region, and a channel region, and the channel region is located between the source region and the drain region. The source region and the drain region can be electrically connected to the first electrode J1 and the second electrode J2 of the thin film transistor respectively through vias, or the first electrode J1 and the second electrode J2 can be directly overlapped with the source region and the drain region respectively, or the source region and the drain region can be directly reused as the first electrode J1 and the second electrode J2 of the thin film transistor.

[0055] The active structure can have a variety of material types. For example, the active structure can include one of low-temperature polysilicon, amorphous silicon, and metal oxide. When the active structure includes low-temperature polysilicon, the thin film transistor usually adopts a top-gate structure, that is, the control terminal J3 is located on the side of the active structure facing away from the substrate 10. Furthermore, an insulating layer is provided between the active structure and the control terminal J3, and a via is provided in the insulating layer. In this case, the first electrode J1 and the second electrode J2 need to pass through the insulating layer in the form of a via to achieve electrical connection with the source region and the drain region. In addition, an inorganic layer is often provided on the side of the first electrode J1 and the second electrode J2 facing away from the substrate 10 to meet insulation requirements. When the active structure includes amorphous silicon, the thin film transistor usually adopts a bottom-gate structure, that is, the control terminal J3 is located on the side of the active structure facing the substrate 10. Furthermore, there is no insulating layer between the first electrode J1 and the second electrode J2 relative to the active structure. In this case, the first electrode J1 and the second electrode J2 are directly overlapped with the source region and the drain region respectively. In addition, an inorganic layer is often provided on the side of the first electrode J1 and the second electrode J2 facing away from the substrate 10 to meet insulation requirements.

[0056] When the active structure includes a metal oxide, the thin film transistor can adopt a bottom-gate structure or a bottom-gate structure. Taking the case where the active structure includes a metal oxide and the thin film transistor has a bottom-gate structure as an example, the control terminal J3 is located on the side of the active structure facing the substrate 10. Furthermore, there is no insulating layer between the first electrode J1 and the second electrode J2 relative to the active structure. In this case, the first electrode J1 and the second electrode J2 are directly connected to the source region and the drain region, respectively. In addition, an organic layer is often provided on the side of the first electrode J1 and the second electrode J2 facing away from the substrate 10 to meet insulation requirements.

[0057] Taking the example of an active structure comprising a metal oxide and a top-gate thin-film transistor, the control terminal J3 is located on the side of the active structure facing away from the substrate 10. Furthermore, an insulating layer is provided between the first electrode J1 and the second electrode J2 relative to the active structure, and a via is provided in the insulating layer. In this case, the first electrode J1 and the second electrode J2 need to pass through the insulating layer via the via to achieve electrical connection with the source and drain regions. Furthermore, an organic layer is often provided on the side of the first electrode J1 and the second electrode J2 facing away from the substrate 10 to meet insulation requirements.

[0058] It should be noted that the first thin film transistor 61 and the second thin film transistor 62 in the embodiment of the present application may be a bottom gate structure or a top gate structure, and the active structures of both may include low temperature polysilicon, amorphous silicon, or metal oxide, which are not limited in the embodiment of the present application. Figure 4 , the active structure includes metal oxide and the first thin film transistor 61 and the second thin film transistor 62 are bottom-gate structures.

[0059] The control terminal J3 of the first thin film transistor 61 and the control terminal J3 of the second thin film transistor 62 may correspond to the same control signal line 20 or may correspond to different control signal lines 20. This embodiment of the present application does not limit this. Figure 3 , the control terminal J3 of the first thin film transistor 61 and the control terminal J3 of the second thin film transistor 62 correspond to the same control signal line 20. When the two correspond to different control signal lines 20, the two control signal lines 20 corresponding to the first thin film transistor 61 and the second thin film transistor 62 need to have the same control timing so that the first thin film transistor 61 and the second thin film transistor 62 can be turned on and off at the same time.

[0060] In the related art, the switching element in the sub-pixel area A1 only includes a single thin-film transistor. However, in the case where the pixel electrode 51 has a larger size, the thin-film transistor needs to have a correspondingly larger size W to provide a larger current to the pixel electrode 51. This design causes the overlapping area between the data signal line and the scanning signal line to become larger, affecting the transmission reliability of the data signal.

[0061] However, in the embodiment of the present application, the switch element in at least one sub-pixel region A1 does not include only a single thin film transistor, but includes at least two thin film transistors, thereby reducing the size W corresponding to a single thin film transistor, thereby reducing parasitic capacitance and improving the transmission reliability of data signals. Specifically, the driving current I ds The formula is as follows:

[0062]

[0063] Wherein, L is the length of the channel region in the thin film transistor, W is the width of the channel region in the thin film transistor, μ is the electron mobility; ε is the dielectric constant of the gate insulating layer; d is the thickness of the gate insulating layer; Vg is the voltage of the control terminal J3; and Vth is the threshold voltage.

[0064] Combined with the above formula, it can be seen that the driving current I of the thin film transistor is ds Affected by parameters W, L, μ, ε, d, Vg, and Vth. On this basis, taking the case where the switch element in the related art only includes the third thin film transistor, and the parameters of the first thin film transistor 61, the second thin film transistor 62, and the third thin film transistor are all kept consistent except for the size W, in the related art, since only the third thin film transistor exists, it is necessary to increase the size W of the third thin film transistor to increase the driving current I of the third thin film transistor. ds , thereby providing a larger current to the pixel electrode 51. However, in the embodiment of the present application, since the switch element includes both the first thin film transistor 61 and the second thin film transistor 62, and both are electrically connected to the pixel electrode 51, the current received by the pixel electrode 51 is the driving current I ds and the driving current I of the second thin film transistor 62 ds The current formed by the confluence is that the current required by the pixel electrode 51 is shared by the first thin film transistor 61 and the second thin film transistor 62 .

[0065] In view of this, the driving current I of the first thin film transistor 61 ds and the driving current I of the second thin film transistor 62 ds are all less than the driving current I of the third thin film transistor ds, thus the size W of the first thin film transistor 61 and the size W of the second thin film transistor 62 can both be smaller than the size W of the third thin film transistor. The size W of the first thin film transistor 61 and the size W of the second thin film transistor 62 can be the same or different. Optionally, the size W of the first thin film transistor 61 and the size W of the second thin film transistor 62 are the same, and both are equal to half the size W of the third thin film transistor.

[0066] Furthermore, as can be seen from the accompanying drawings, the second connection portion 42 for transmitting data signals overlaps with the control signal line 20, generating corresponding parasitic capacitance. The extension direction of the second connection portion 42 is often parallel to the direction corresponding to dimension W, and the overlap dimension between the second connection portion 42 and the control signal line 20 along the extension direction of the second connection portion 42 is also positively correlated with dimension W.

[0067] On this basis, because both the first thin-film transistor 61 and the second thin-film transistor 62 have a relatively small size W, the overlapping area between the second connecting portion 42 and the control signal line 20 can be reduced, thereby reducing the magnitude of the parasitic capacitance. This design can reduce the effect of parasitic capacitance on the delay of data signal transmission, improve the charging capability of the pixel circuit, and enhance the display reliability of the display panel 200.

[0068] It should be noted that, depending on actual needs, each sub-pixel area A1 may include a first thin film transistor 61 and a second thin film transistor 62, or some sub-pixel areas A1 may include a first thin film transistor 61 and a second thin film transistor 62, while other sub-pixel areas A1 may include only a single thin film transistor. The embodiments of the present application do not limit this.

[0069] In summary, in the embodiment of the present application, multiple thin-film transistors are provided in at least one sub-pixel area A1, thereby reducing the size W of a single thin-film transistor. On this basis, a first connecting portion 41 and a second connecting portion 42 are further provided in the array substrate 100. The first connecting portion 41 is used to electrically connect the multiple thin-film transistors to the pixel electrode 51, and the second connecting portion 42 is used to electrically connect the multiple thin-film transistors to the data line 30, thereby meeting the operating requirements of the pixel circuit. Furthermore, under this design, the second connecting portion 42 and the control signal line 20 can have a smaller overlapping area, thereby reducing parasitic capacitance, reducing the delay effect caused by parasitic capacitance on data signal transmission, and improving the charging capacity of the pixel circuit and the display reliability of the display panel 200.

[0070] The specific position relationship of the film layer where the above structure is located is not limited in the present embodiment. Figure 4As shown, the control signal line 20 is located on the side of the active structure of the first thin-film transistor 61 facing the substrate 10, that is, the first thin-film transistor 61 has a bottom-gate structure. Similarly, the control signal line 20 is located on the side of the active structure of the second thin-film transistor 62 facing the substrate 10, that is, the second thin-film transistor 62 has a bottom-gate structure. As for the data line 30 and the pixel electrode 51, both are located on the side of the active structure of the first thin-film transistor 61 facing away from the substrate 10, and the pixel electrode 51 is located on the side of the data line 30 facing away from the substrate 10.

[0071] In some embodiments, see Figure 5 and Figure 6 The first thin film transistor 61 includes a first active structure 611, and the second thin film transistor 62 includes a second active structure 621. The first active structure 611 and the second active structure 621 are arranged at intervals, and the orthographic projection of the first active structure 611 on the substrate 10 and the orthographic projection of the second active structure 621 on the substrate 10 both at least partially overlap with the orthographic projection of the same second connecting portion 42 on the substrate 10.

[0072] The first active structure 611 includes a semiconductor material and is an active structure in the first thin film transistor 61. The partial structure of the control signal line 20 overlapping with the first active structure 611 is reused as the control terminal J3 of the first thin film transistor 61. The partial structure of the first active structure 611 overlapping with the first sub-connection portion 411 is the source region of the first active structure 611. The partial structure of the first active structure 611 overlapping with the second connection portion 42 is the drain region of the first active structure 611. The partial structure of the first active structure 611 located between the first sub-connection portion 411 and the second connection portion 42 is the channel region of the first active structure 611.

[0073] The second active structure 621 includes a semiconductor material and is an active structure in the second thin film transistor 62. The partial structure of the control signal line 20 overlapping with the second active structure 621 is reused as the control terminal J3 of the second thin film transistor 62. The partial structure of the second active structure 621 overlapping with the second sub-connection portion 412 is the source region of the second active structure 621. The partial structure of the second active structure 621 overlapping with the second connection portion 42 is the drain region of the second active structure 621. The partial structure of the second active structure 621 located between the second sub-connection portion 412 and the second connection portion 42 is the channel region of the second active structure 621.

[0074] The first active structure 611 and the second active structure 621 are spaced apart, that is, they are not connected as one. In some optional embodiments, the first active structure 611 and the second active structure 621 can be arranged in the same layer and include the same semiconductor material, so that the first active structure 611 and the second active structure 621 can be prepared together in the same process. Or in other optional embodiments, the first active structure 611 and the second active structure 621 can also be arranged in different layers and include different semiconductor materials. Figure 6 FIG. 6 shows a case where the first active structure 611 and the second active structure 621 are in the same layer and include the same semiconductor material.

[0075] Furthermore, the first active structure 611 and the second active structure 621 are overlapped with each other relative to the same second connecting portion 42. On this basis, as shown in FIG. Figure 6 As shown, when the active structure includes a metal oxide and the first thin film transistor 61 and the second thin film transistor 62 have a bottom-gate structure, the single second connection portion 42 can be disposed overlappingly with both the first active structure 611 and the second active structure 621. Alternatively, when an insulating layer is provided between the first active structure 611 and the second connection portion 42, since the second connection portion 42 is disposed overlappingly with both active structures, the single second connection portion 42 can be connected to both the first active structure 611 and the second active structure 621 through a via.

[0076] In the embodiment of the present application, the first active structure 611 of the first thin-film transistor 61 and the second active structure 621 of the second thin-film transistor 62 are two independent active structures. On this basis, by overlapping the first active structure 611 and the second active structure 621 relative to the same second connecting portion 42, the second electrode J2 of the first thin-film transistor 61 and the second electrode J2 of the second thin-film transistor 62 can be directly connected or connected to the same second connecting portion 42 through a via. With this design, the data signal line only needs to use a single second connecting portion 42 to transmit the data signal to the first thin-film transistor 61 and the second thin-film transistor 62 respectively. This reduces the number of second connecting portions 42 in the array substrate 100 and reduces the difficulty of the wiring layout of the array substrate 100.

[0077] In some embodiments, as Figure 3 and Figure 4As shown, the first thin film transistor 61 includes a first active structure 611, and the second thin film transistor 62 includes a second active structure 621. The first active structure 611 and the second active structure 621 are connected to form an integrated structure, and along the intersection direction of the side-by-side arrangement direction of the first active structure 611 and the second active structure 621, the orthographic projection of the first connecting portion 41 on the substrate 10 exceeds the orthographic projection of the first active structure 611 on the substrate 10 and the orthographic projection of the second active structure 621 on the substrate 10.

[0078] The first active structure 611 and the second active structure 621 are connected and arranged as a whole. In the figure, the boundary between the first active structure 611 and the second active structure 621 is indicated by a dotted line. The first active structure 611 and the second active structure 621 can have various positions. For example, Figure 3 and Figure 4 As shown, the first active structure 611 and the second active structure 621 can be arranged side by side and connected as a whole in the first direction X. Alternatively, the first active structure 611 and the second active structure 621 can also be arranged side by side and connected as a whole in the second direction Y.

[0079] The orthographic projection of the second connecting portion 42 corresponds to an orthographic projection extending beyond the first active structure 611 and the second active structure 621. Specifically, if the first active structure 611 and the second active structure 621 are arranged side by side in the first direction X, then the second direction Y is a direction intersecting the direction in which the two active structures are arranged side by side, and the second connecting portion 42 can be arranged beyond the first active structure 611 and the second active structure 621 in the second direction Y. If the first active structure 611 and the second active structure 621 are arranged side by side in the second direction Y, then the first direction X is a direction intersecting the direction in which the two active structures are arranged side by side, and the second connecting portion 42 can be arranged beyond the first active structure 611 and the second active structure 621 in the first direction X.

[0080] In the embodiment of the present application, the first active structure 611 and the second active structure 621 are arranged in the same layer and connected as one body, so that the two can be made of the same material and formed together in the same process, thereby simplifying the process and reducing costs. On this basis, the embodiment of the present application also sets the second connecting portion 42 to extend beyond the first active structure 611 and the second active structure 621 in a specific direction, so that the second connecting portion 42 can have a larger overlapping area relative to the first active structure 611 and the second active structure 621. This design can be used in Figure 4When the active structure shown includes metal oxide and the first thin-film transistor 61 and the second thin-film transistor 62 have a bottom-gate structure, the overlap effect of the second connecting portion 42 relative to the first active structure 611 and the second active structure 621 is improved. Alternatively, when an insulating layer is provided between the first active structure 611 and the second connecting portion 42, this design can improve the reliability of the via connection between the second connecting portion 42 and the first active structure 611 and the second active structure 621.

[0081] In some embodiments, the data line 30 extends along the first direction X, and the first connection portion 41 and the second connection portion 42 extend along the second direction Y.

[0082] The data line 30 and the second connecting portion 42 are electrically connected, and their corresponding extension directions intersect. Therefore, the data line 30 and the second connecting portion 42 have different structures. The data line 30 and the second connecting portion 42 can be arranged on the same layer and connected as one piece, so that they are composed of the same material and formed together in the same process, simplifying the manufacturing process and reducing costs. Alternatively, the data line 30 and the second connecting portion 42 can be arranged on different layers and electrically connected to each other through vias or other adapters, which is not limited in this embodiment of the present application.

[0083] The first connecting portion 41 and the second connecting portion 42 have the same extension direction, both extending along the second direction Y. On this basis, the first connecting portion 41 and the second connecting portion 42 can be arranged side by side in the first direction X so that the orthographic projections of the first connecting portion 41 and the second connecting portion 42 on the substrate 10 are staggered, reducing the risk of contact interference between the first connecting portion 41 and the second connecting portion 42. Optionally, the first connecting portion 41 and the second connecting portion 42 are arranged on the same layer, so that the first connecting portion 41 and the second connecting portion 42 can be made of the same material and formed together in the same process, simplifying the process and reducing costs. Further optionally, the first connecting portion 41, the second connecting portion 42 and the data line 30 are all arranged on the same layer.

[0084] It should be noted that the first connection portion 41 includes a first sub-connection portion 411 and a second sub-connection portion 412. The embodiment of the present application does not limit the specific positional relationship between the first sub-connection portion 411 and the second sub-connection portion 412 relative to the second connection portion 42. For example, the first sub-connection portion 411 and the second sub-connection portion 412 can be located on the same side of the second connection portion 42 in the first direction X, or the second connection portion 42 can be located between the first sub-connection portion 411 and the second sub-connection portion 412 in the first direction X.

[0085] In the embodiment of the present application, the first connection portion 41 and the second connection portion 42 both extend along the second direction Y, so that the first sub-connection portion 411 and the second sub-connection portion 412 can be arranged side by side in the first direction X. On this basis, the first thin film transistor 61 and the second thin film transistor 62 are arranged side by side in the first direction X, and the width direction of the channel region in the two thin film transistors is the second direction Y. Therefore, this design helps to reduce the size of the first active structure 611 and the second active structure 621 in the second direction Y, and reduce the size of the control terminal J3 of the two thin film transistors in the second direction Y, thereby reducing the overlapping size of the second connection portion 42 relative to the control terminal J3 of the two thin film transistors in the second direction Y, reducing the overlapping area between the second connection portion 42 and the control signal line 20, reducing the generation of parasitic capacitance, and improving the charging capacity of the pixel circuit and the display reliability of the display panel 200.

[0086] It should be noted that the embodiment of the present application does not impose any restrictions on the size of the second connection portion 42 in the second direction Y. Since the first active structure 611 and the second active structure 621 are often relatively small in the second direction Y, the second connection portion 42 corresponding to the two thin-film transistors does not need to be excessively large in the second direction Y. In view of this, the size of the second connection portion 42 in the second direction Y can optionally be determined by the minimum size achievable by the manufacturing process. This design helps reduce the transmission delay of the data signal.

[0087] In some embodiments, as Figure 3 and Figure 4 As shown, the first thin film transistor 61 and the second thin film transistor 62 are arranged in the first direction X. In the first direction X, the second connection portion 42 is located between the first sub-connection portion 411 and the second sub-connection portion 412, and the orthographic projection of the data line 30 on the substrate 10 and the orthographic projection of the first thin film transistor 61 on the substrate 10 are spaced apart in the second direction Y.

[0088] The first thin-film transistor 61 and the second thin-film transistor 62 are arranged in the first direction X, and the first electrode J1 of the first thin-film transistor 61 is located on the side of the second electrode J2 away from the second thin-film transistor 62, while the first electrode J1 of the second thin-film transistor 62 is located on the side of the second electrode J2 away from the first thin-film transistor 61. As a result, the first electrode J1 of the first thin-film transistor 61 and the first electrode J1 of the second thin-film transistor 62 can be relatively close to each other in the first direction X. Furthermore, by positioning the second connecting portion 42 between the first sub-connecting portion 411 and the second sub-connecting portion 412, the second connecting portion 42 can be electrically connected to both the first electrode J1 of the first thin-film transistor 61 and the first electrode J1 of the second thin-film transistor 62. Consequently, only a single second connecting portion 42 is required to write data signals corresponding to the first thin-film transistor 61 and the second thin-film transistor 62, simplifying the wiring layout of the array substrate 100.

[0089] The parallel arrangement direction of the first thin film transistor 61 and the second thin film transistor 62 is the same as the extending direction of the data line 30, and the data line 30 is spaced apart from the first thin film transistor 61 and the second thin film transistor 62 in the second direction Y, that is, the data line 30 does not overlap with the two thin film transistors. Figure 1 and Figure 3 It can be seen that in the embodiment of the present application, the control signal line 20 does not need to be widened in the area where it overlaps with the data line 30. This reduces the overlap between the data line 30 and the control signal line 20 in the first direction X, thereby reducing the parasitic capacitance between the two. With this design, the total parasitic capacitance generated by the data line 30 and the second connecting portion 42 relative to the control signal line 20 can be smaller than the parasitic capacitance generated by the data signal line and the scanning signal line in the related art, thereby improving the display reliability of the display panel 200.

[0090] Furthermore, in the embodiment of the present application, since the data line 30 and the control signal line 20 have a relatively small overlap in the first direction X, a relatively small parasitic capacitance exists between them. Therefore, in some alternative embodiments, the width of the data line 30 can be adaptively increased, that is, the dimension of the data line 30 in the second direction Y can be increased to reduce the resistance of the data line 30. This design has a relatively small impact on the parasitic capacitance and helps improve the reliability of data signal transmission.

[0091] In some embodiments, see Figure 7 and Figure 4The control signal line 20 includes a first subsegment 21, a second subsegment 22, and a third subsegment 23. In the second direction Y, the first subsegment 21 and the third subsegment 23 are respectively connected to the two ends of the second subsegment 22. The orthographic projection of the first subsegment 21 on the substrate 10 overlaps with the orthographic projection of the first active structure 611 in the first thin-film transistor 61 on the substrate 10. The orthographic projection of the second subsegment 22 on the substrate 10 overlaps with the orthographic projection of the data line 30 on the substrate 10. The width of the second subsegment 22 is smaller than the width of the third subsegment 23.

[0092] The first subsegment 21, the second subsegment 22, and the third subsegment 23 are arranged sequentially in the second direction Y. The second subsegment 22 is integrally connected to the first subsegment 21 and the third subsegment 23 at both ends in the second direction Y. The first subsegment 21 overlaps with the first active structure 611 and the second active structure 621. The first sub-connection portion 411, the second sub-connection portion 412, and the second connection portion 42 all overlap with the first subsegment 21. The second subsegment 22 overlaps with the data line 30, and its orthographic projection on the substrate 10 is outside the orthographic projections of the first and second thin-film transistors 61 and 62. The orthographic projection of the third subsegment 23 on the substrate 10 is outside both the orthographic projections of the data line 30 and the orthographic projections of the first and second thin-film transistors 61 and 62.

[0093] On this basis, the embodiment of the present application further adjusts the width of the second sub-segment 22 to be smaller than the width of the third sub-segment 23. The "width of the second sub-segment 22" referred to herein refers to the average size of the second sub-segment 22 in the first direction X. Similarly, the "width of the third sub-segment 23" refers to the average size of the third sub-segment 23 in the first direction X. In other words, the embodiment of the present application adaptively reduces the size of the second sub-segment 22 in the first direction X to be smaller than the size of the third sub-segment 23 in the first direction X. This reduces the overlap between the data line 30 and the second sub-segment 22 in the first direction X, thereby reducing the overlapping area between the two. This design can further reduce parasitic capacitance, mitigate the impact of parasitic capacitance on data signal transmission delays, improve the charging capability of the pixel circuit, and enhance the display reliability of the display panel 200.

[0094] In some embodiments, see Figure 8 and Figure 9 The data line 30 , the first connecting portion 41 and the second connecting portion 42 are all extended along the first direction X.

[0095] The data line 30, the first connection portion 41, and the second connection portion 42 have the same extension direction. On this basis, the data line 30 and the second connection portion 42 can have various relationships. For example, the data line 30 and the second connection portion 42 have different structures and are spaced apart in the second direction Y. In this case, the data line 30 and the second connection portion 42 need to be electrically connected with other connection portions. Alternatively, the second connection portion 42 can be located within the data line 30, that is, part of the structure of the data line 30 is reused as the second connection portion 42. Figure 8 FIG. 4 shows a case where a part of the structure of the data line 30 is reused as the second connection portion 42 .

[0096] In the embodiment of the present application, the first connection portion 41 and the second connection portion 42 both extend along the first direction X, so that the first sub-connection portion 411 and the second sub-connection portion 412 can be arranged side by side in the second direction Y. On this basis, the first thin film transistor 61 and the second thin film transistor 62 are arranged side by side in the second direction Y, and the width direction of the channel region in the two thin film transistors is both in the first direction X. Therefore, this design helps to reduce the size of the first active structure 611 and the second active structure 621 in the first direction X, and reduce the size of the control terminals J3 of the two thin film transistors in the first direction X, thereby reducing the overlapping size of the second connection portion 42 relative to the control terminals J3 of the two thin film transistors in the first direction X, reducing the overlapping area between the second connection portion 42 and the control signal line 20, reducing the generation of parasitic capacitance, and improving the charging capacity of the pixel circuit and the display reliability of the display panel 200.

[0097] In addition to the array substrate 100, the display panel 200 typically includes a liquid crystal layer 70 and a color filter substrate 80 located on the side of the liquid crystal layer 70 facing away from the array substrate 100. A shielding layer is provided within the color filter substrate 80. The shielding layer includes a shielding portion that can cover the control signal lines 20, the data lines 30, and the thin-film transistors, and a light-shielding opening formed by the shielding portion and corresponding to the plurality of sub-pixel areas A1. On this basis, since the thin-film transistors in the embodiment of the present application have a relatively small size in the first direction X, the shielding portion used to shield the thin-film transistors and the control signal lines 20 can have a relatively small size in the first direction X. This increases the size of the light-shielding opening in the first direction X, thereby improving the display brightness of the display panel 200.

[0098] In some embodiments, as Figure 8 and Figure 9 As shown, the data line 30 includes a plurality of first portions 31 and a plurality of second connection portions 42 , and adjacent first portions 31 are connected via the second connection portions 42 .

[0099] The data line 30 includes a second connecting portion 42, which is a portion of the structure of the data line 30 that serves as the second connecting portion 42. In addition to the second connecting portion 42, the data line 30 also includes a first portion 31. The first portion 31 and the second connecting portion 42 are connected to each other and can be provided on the same layer, that is, they can be made of the same material and formed together in the same process. There can be multiple first portions 31 and multiple second connecting portions 42, and the multiple first portions 31 and the multiple second connecting portions 42 can be arranged alternately in the first direction X. In other words, there is a second connecting portion 42 between two adjacent first portions 31, and there is a first portion 31 between two adjacent second connecting portions 42.

[0100] In the embodiment of the present application, a portion of the structure of the data line 30 is reused as the second connection portion 42. In this case, only the second connection portion 42 of the data line 30 overlaps with the control signal line 20, while the orthographic projection of the first portion 31 on the substrate 10 is located outside the orthographic projection of the control signal line 20 on the substrate 10. Furthermore, because the switching transistor arrangement within at least one sub-pixel area A1 includes multiple thin-film transistors, the active structure and control terminal J3 of a single thin-film transistor can have a smaller size in the first direction X. This helps reduce the overlap size of the data line 30 and the control signal line 20 in the first direction X, thereby reducing parasitic capacitance, improving the charging capability of the pixel circuit, and improving the display reliability of the display panel 200.

[0101] In some embodiments, the first thin film transistor 61 and the second thin film transistor 62 are arranged in the second direction Y, and the orthographic projection of the data line 30 on the substrate 10 overlaps with the orthographic projection of the first thin film transistor 61 on the substrate 10. In the second direction Y, the data line 30 is located between the first sub-connection portion 411 and the second sub-connection portion 412.

[0102] The arrangement direction of the first thin film transistor 61 and the second thin film transistor 62 intersects with the extension direction of the data line 30, while the extension directions of the first sub-connection portion 411 and the second sub-connection portion 412 are parallel to the extension direction of the data line 30, and the data line 30 is located between the first sub-connection portion 411 and the second sub-connection portion 412. The first sub-connection portion 411, the second sub-connection portion 412, and the data line 30 can be provided in the same layer, such that the three are composed of the same material and formed together in the same process. Alternatively, the data line 30 can be provided in a different layer relative to the first sub-connection portion 411 and the second sub-connection portion 412, and this embodiment of the present application is not limited thereto.

[0103] In the embodiment of the present application, it can be seen from the accompanying drawings that the first active structure 611 in the first thin film transistor 61 and the second active structure 621 in the second thin film transistor 62 can be arranged in the second direction Y and connected as an integral unit. On the one hand, this allows the two active structures to include the same material and be formed together in the same process, thereby simplifying the process and reducing costs. On the other hand, the integral structure formed by connecting the two active structures has a smaller size in the first direction X, so that the portion of the structure where the control signal line 20 overlaps with the active structure has a smaller size in the first direction X, thereby reducing the overlapping area between the data line 30 and the control signal line 20, reducing parasitic capacitance, and improving the charging capacity of the pixel circuit and the display reliability of the display panel 200.

[0104] In some embodiments, the dimension of the data line 30 along its width direction is greater than or equal to the dimension of the second connecting portion 42 along its width direction. The "dimension of the data line 30 along its width direction" mentioned herein refers to the maximum width dimension of the data line 30. Similarly, the "dimension of the second connecting portion 42 along its width direction" mentioned herein refers to the maximum width dimension of the second connecting portion 42.

[0105] by Figure 3 Taking the structure shown as an example, the second connection portion 42 is located outside the data line 30. The dimension of the data line 30 along its width direction is the maximum dimension of the data line 30 in the second direction Y, and the dimension of the second connection portion 42 along its width direction is the maximum dimension of the second connection portion 42 in the first direction X. In this case, changes in the size and shape of the second connection portion 42 will not significantly affect the transmission of signals within the data line 30. In view of this, the dimension of the second connection portion 42 along its width direction can optionally be smaller than the dimension of the second connection portion 42 along its width direction. This can reduce the overlapping area between the second connection portion 42 and the control signal line 20 while not affecting the transmission of signals within the data line 30, thereby reducing parasitic capacitance.

[0106] by Figure 8 Taking the structure shown as an example, a portion of the structure of the data line 30 is reused as the second connecting portion 42. The dimension of the data line 30 along its width direction is the maximum dimension of the data line 30 in the second direction Y, and the dimension of the second connecting portion 42 along its width direction is the maximum dimension of the second connecting portion 42 in the second direction Y. In this case, the size and shape of the second connecting portion 42 will affect the transmission of signals within the data line 30. In view of this, the dimension of the data line 30 along its width direction is optionally equal to the dimension of the second connecting portion 42 along its width direction. Furthermore, the first portion 31 and the second connecting portion 42 have the same width dimension. This design can not only improve the reliability of signal transmission within the data line 30, but also reduce parasitic capacitance, thereby improving the display reliability of the display panel 200.

[0107] In summary, in the embodiment of the present application, the width dimension of the second connecting portion 42 is limited by design, and the dimension of the second connecting portion 42 along its own width direction is set to be no larger than the dimension of the data line 30 along its own width direction, so as to reduce the overlapping area between the second connecting portion 42 and the control signal line 20, thereby reducing the parasitic capacitance and improving the display reliability of the display panel 200.

[0108] In some embodiments, the first sub-connecting portion 411 and the second sub-connecting portion 412 are arranged in parallel.

[0109] In different situations, the first sub-connection portion 411 and the second sub-connection portion 412 have different extension directions. Specifically, taking the structure shown in the figure as an example, the first sub-connection portion 411 and the second sub-connection portion 412 can both extend along the second direction Y and be arranged in an array in the first direction X. Taking the structure shown in the figure as an example, the first sub-connection portion 411 and the second sub-connection portion 412 can both extend along the first direction X and be arranged in an array in the second direction Y.

[0110] In the embodiment of the present application, the first sub-connection portion 411 and the second sub-connection portion 412 are both arranged to extend in the same direction, thereby reducing the risk of contact and interference between the first sub-connection portion 411 and the second sub-connection portion 412 along their own extension paths, and improving the layout reliability of the internal wiring of the array substrate 100. Furthermore, optionally, the first sub-connection portion 411, the second sub-connection portion 412, and the second connection portion 42 are all arranged in parallel, thereby helping to reduce the risk of contact and interference between the first sub-connection portion 411 and the second sub-connection portion 412 relative to the second connection portion 42.

[0111] In some embodiments, as Figure 3 and Figure 8 As shown, the first sub-connection portion 411 and the second sub-connection portion 412 are connected to the pixel electrode 51 through a third connection portion 43 .

[0112] The third connection portion 43 is used to realize the electrical connection between the first sub-connection portion 411 and the second sub-connection portion 412 relative to the pixel electrode 51. Specifically, the first sub-connection portion 411 and the second sub-connection portion 412 are not directly connected to the pixel electrode 51, but are connected to the third connection portion 43, and the third connection portion 43 is connected to the pixel electrode 51.

[0113] The embodiments of the present application do not limit the specific positional relationship of the third connection part 43 relative to the first sub-connection part 411 and the second sub-connection part 412. For example, the third connection part 43 can be arranged at the same layer relative to at least one of the first sub-connection part 411 and the second sub-connection part 412, or the third connection part 43 can also be arranged at different layers relative to the first sub-connection part 411 and the second sub-connection part 412.

[0114] In the embodiment of the present application, a third connection portion 43 is additionally provided in the array substrate 100, and the first sub-connection portion 411 and the second sub-connection portion 412 are connected to the pixel electrode 51 through a third connection portion 43. In this way, the pixel electrode 51 only needs to use a via structure to connect to the third connection portion 43, which can meet the electrical connection requirements of the first sub-connection portion 411 and the second sub-connection portion 412 relative to the third connection portion 43, thereby reducing the number of via structures corresponding to the pixel electrode 51, thereby improving the morphological flatness of the pixel electrode 51, and further helping to improve the operating reliability of the pixel electrode 51 and the display accuracy of the display panel 200.

[0115] In some embodiments, as Figure 3 As shown, the orthographic projection of the third connection portion 43 on the substrate 10 at least partially does not overlap with the orthographic projection of the active structure of at least one of the first thin film transistor 61 and the second thin film transistor 62 on the substrate 10 .

[0116] It can be seen from the accompanying drawings that the morphological dimensions of the partial structure of the control signal line 20 that overlaps with the active structure generally match the shape dimensions of the active structure. In view of this, the embodiment of the present application adjusts the position and extension direction of the third connection portion 43, and sets the orthographic projection of the third connection portion 43 on the substrate 10 to be at least partially located outside the orthographic projection of the active structure of the two thin film transistors on the substrate 10, so that the orthographic projection of at least part of the structure in the third connection portion 43 on the substrate 10 is located outside the orthographic projection of the control signal line 20 on the substrate 10, thereby helping to reduce the overlapping area between the third connection portion 43 and the control signal line 20, reduce parasitic capacitance, and improve the display reliability of the display panel 200.

[0117] In some embodiments, as Figure 3 and Figure 4 As shown, the first connection portion 41 and the third connection portion 43 are both provided in the same layer as the data line 30 , and the extension direction of the third connection portion 43 is parallel to the extension direction of the data line 30 .

[0118] by Figure 3Taking the structure shown as an example, in the case where the second connection portion 42 is located outside the data line 30, the data line 30 and the third connection portion 43 both extend along the first direction X, the first sub-connection portion 411 and the second sub-connection portion 412 both extend along the second direction Y, and the data line 30 and the third connection portion 43 can be located on either side of the first sub-connection portion 411 and the second sub-connection portion 412 in the second direction Y. In this design, the orthographic projection of the third connection portion 43 on the substrate 10 can be located outside the orthographic projection of the data line 30 on the substrate 10. Therefore, even if the first connection portion 41 and the third connection portion 43 are both provided on the same layer as the data line 30, there will be no contact interference between the third connection portion 43 and the data line 30, thereby ensuring the reliability of their respective signal transmission.

[0119] In the embodiment of the present application, the position and extension direction of the third connection portion 43 are adjusted, and the extension direction of the third connection portion 43 is set to be parallel to the extension direction of the data line 30. On this basis, the first connection portion 41 and the third connection portion 43 can be set in the same layer as the data line 30. Therefore, the first connection portion 41, the third connection portion 43 and the data line 30 can include the same material and be formed together in the same process, thereby simplifying the process and reducing costs.

[0120] In some embodiments, see Figures 8 to 10 The first connection portion 41 and the data line 30 are provided on the same layer, the third connection portion 43 and the data line 30 are provided on different layers, and the first connection portion 41 and the third connection portion 43 are connected through a via.

[0121] by Figure 8 Taking the structure shown as an example, in the case where part of the structure of the data line 30 is reused as the second connection portion 42, the first sub-connection portion 411, the second sub-connection portion 412, and the data line 30 all extend along the first direction X, and the first sub-connection portion 411 and the second sub-connection portion 412 are respectively arranged on either side of the data line 30 along the second direction Y. On this basis, the orthographic projection of the third connection portion 43 used to connect the first sub-connection portion 411 and the second sub-connection portion 412 on the substrate 10 overlaps with the orthographic projection of the data line 30 on the substrate 10. Therefore, if the third connection portion 43 and the data line 30 are arranged on the same layer, contact interference will occur between the third connection portion 43 and the data line 30, affecting the reliability of signal transmission between the two. In view of this, in the embodiment of the present application, the third connection portion 43 and the data line 30 are arranged on different layers, and the first connection portion 41 and the third connection portion 43 are connected through a via.

[0122] It should be noted that the specific film position and form of the third connecting portion 43 are not limited in this embodiment of the present application. Figure 9 As shown, the third connection portion 43 can be provided on the same layer as the control signal line 20, that is, the third connection portion 43 is located on the side of the data line 30 facing the substrate 10. Figure 10 As shown, the third connection portion 43 may also be located on the side of the data line 30 facing away from the substrate 10 . In this case, part of the structure in the pixel electrode 51 may be reused as the third connection portion 43 .

[0123] In an embodiment of the present application, in a scenario where the orthographic projection of the third connection portion 43 on the substrate 10 overlaps with the orthographic projection of the data line 30 on the substrate 10, the third connection portion 43 and the data line 30 are arranged on different layers, thereby reducing the risk of contact interference between the third connection portion 43 and the data line 30 and improving the reliability of signal transmission.

[0124] Furthermore, the embodiment of the present application does not limit the electrical connection method between the first connecting portion 41 and the active structure. Figure 9 and Figure 10 As shown, when the active structure includes metal oxide and the first thin film transistor 61 and the second thin film transistor 62 have a bottom-gate structure, the first connecting portion 41 and the second active structure 621 can be directly overlapped. Alternatively, when an insulating layer is provided between the second active structure 621 and the first connecting portion 41, the first connecting portion 41 and the second active structure 621 can be connected through a via.

[0125] In some embodiments, see Figure 11 and Figure 12 The array substrate 100 also includes a common electrode 52, which is located on the side of the data line 30 away from the substrate 10, and the pixel electrode 51 is located on the side of the common electrode 52 away from the substrate 10, and the common electrode 52 covers at least part of the data line 30, and the pixel electrode 51 is connected to the first connecting portion 41 through a via.

[0126] The pixel electrode 51 and the common electrode 52 can work together to form an electric field structure that drives liquid crystal deflection to achieve display function. The pixel electrode 51 and the common electrode 52 are both located within the array substrate 100. That is, in the display panel 200, the pixel electrode 51 and the common electrode 52 are located on the same side of the liquid crystal layer 70. Based on this, the lateral electric field between the pixel electrode 51 and the common electrode 52 passes through the liquid crystal layer 70 and drives the liquid crystal to deflect.

[0127] Furthermore, the embodiment of the present application adjusts the specific positional relationship between the pixel electrode 51 and the common electrode 52, and sets the common electrode 52 between the data line 30 and the pixel electrode 51, and sets the common electrode 52 to cover at least a portion of the data line 30, thereby achieving signal shielding between the pixel electrode 51 and the data line 30 with the help of a constant voltage signal inside the common electrode 52, thereby improving the reliability of the signal transmission between the two and improving the display reliability of the display panel 200.

[0128] Second, see Figure 13, an embodiment of the present application provides a display panel 200 , and the display panel 200 includes the array substrate 100 in any of the aforementioned embodiments.

[0129] The display panel 200 may be a liquid crystal display panel 200. In addition to the array substrate 100, the display panel 200 further includes a liquid crystal layer 70 and a color filter substrate 80. The liquid crystal layer 70 is sandwiched between the color filter substrate 80 and the array substrate 100. The display panel 200 provided in the embodiment of the present application has the beneficial effects of the array substrate 100 in any of the aforementioned embodiments. For details, please refer to the aforementioned description of the beneficial effects of the array substrate 100, which will not be repeated in this embodiment of the present application.

[0130] Thirdly, please refer to Figure 14 , an embodiment of the present application provides a display device 300, and the display device 300 includes the display panel 200 in any of the aforementioned embodiments.

[0131] Although the embodiments disclosed in this application are as described above, the contents described are merely embodiments adopted to facilitate understanding of this application and are not intended to limit the present invention. Any person skilled in the art to which this application belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application. However, the scope of protection of this application shall still be based on the scope defined by the appended claims.

[0132] The above description is only a specific embodiment of the present application. Those skilled in the art will clearly understand that for the convenience and brevity of description, the replacement of other connection methods described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. It should be understood that the scope of protection of the present application is not limited to this. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the scope of protection of this application.

Claims

1. An array substrate, characterized in that: include: substrate; A plurality of control signal lines are provided on the substrate, and the plurality of control signal lines are spaced apart and distributed along a first direction; a plurality of data lines disposed on the substrate, wherein the plurality of data lines are spaced apart along a second direction and spatially intersect with the control signal lines, and the first direction, the second direction, and the thickness direction of the array substrate intersect with each other; The orthographic projections of the plurality of control signal lines on the substrate and the orthographic projections of the plurality of data lines on the substrate enclose a plurality of sub-pixel areas; a first connecting portion and a second connecting portion, wherein the first connecting portion includes a first sub-connecting portion and a second sub-connecting portion; A pixel electrode is provided on the substrate, and the sub-pixel area includes the pixel electrode; A first thin film transistor and a second thin film transistor are arranged on the substrate; at least one sub-pixel area includes the first thin film transistor and the second thin film transistor, the first electrode of the first thin film transistor is electrically connected to the first sub-connection portion, the first electrode of the second thin film transistor is electrically connected to the second sub-connection portion, the first sub-connection portion and the second sub-connection portion are electrically connected to the same pixel electrode, and the second electrode of the first thin film transistor and the second electrode of the second thin film transistor are electrically connected to the data line through the same second connection portion.

2. The array substrate according to claim 1, wherein: The first thin film transistor includes a first active structure, and the second thin film transistor includes a second active structure. The first active structure and the second active structure are arranged at intervals, and the orthographic projection of the first active structure on the substrate and the orthographic projection of the second active structure on the substrate both at least partially overlap with the orthographic projection of the same second connecting portion on the substrate.

3. The array substrate according to claim 1, wherein: The first thin film transistor includes a first active structure, and the second thin film transistor includes a second active structure. The first active structure and the second active structure are connected to form an integral structure, and along the intersection direction of the side-by-side arrangement direction of the first active structure and the second active structure, the orthographic projection of the second connecting portion on the substrate exceeds the orthographic projection of the first active structure on the substrate and the orthographic projection of the second active structure on the substrate.

4. The array substrate according to claim 1, wherein: The data line is extended along the first direction, and the first connecting portion and the second connecting portion are both extended along the second direction.

5. The array substrate according to claim 4, wherein: The first thin film transistor and the second thin film transistor are arranged in the first direction, and in the first direction, the second connection portion is located between the first sub-connection portion and the second sub-connection portion; An orthographic projection of the data line on the substrate and an orthographic projection of the first thin film transistor on the substrate are spaced apart in the second direction.

6. The array substrate according to claim 5, wherein: The control signal line includes a first subsegment, a second subsegment, and a third subsegment. In the second direction, the first subsegment and the third subsegment are respectively connected to two ends of the second subsegment. The orthographic projection of the first subsegment on the substrate overlaps with the orthographic projection of the first active structure in the first thin film transistor on the substrate. The orthographic projection of the second subsegment on the substrate overlaps with the orthographic projection of the data line on the substrate. The width of the second sub-segment is smaller than the width of the third sub-segment.

7. The array substrate according to claim 1, wherein: The data line, the first connecting portion, and the second connecting portion are all extended along the first direction.

8. The array substrate according to claim 7, wherein: The data line includes a plurality of first portions and a plurality of second connection portions, and adjacent first portions are connected via the second connection portions.

9. The array substrate according to claim 7, wherein: The first thin film transistor and the second thin film transistor are arranged in the second direction, and the orthographic projection of the data line on the substrate overlaps with the orthographic projection of the first thin film transistor on the substrate; In the second direction, the data line is located between the first sub-connection portion and the second sub-connection portion.

10. The array substrate according to any one of claims 1 to 9, characterized in that: The size of the data line along its own width direction is greater than or equal to the size of the second connecting portion along its own width direction.

11. The array substrate according to claim 1, wherein: The first sub-connection portion and the second sub-connection portion are arranged in parallel.

12. The array substrate according to claim 11, wherein: The first sub-connection portion and the second sub-connection portion are connected to the pixel electrode through a third connection portion.

13. The array substrate according to claim 12, wherein: An orthographic projection of the third connecting portion on the substrate at least partially does not overlap with an orthographic projection of an active structure of at least one of the first thin film transistor and the second thin film transistor on the substrate.

14. The array substrate according to claim 12, wherein: The first connecting portion and the third connecting portion are both provided in the same layer as the data line, and an extending direction of the third connecting portion is parallel to an extending direction of the data line.

15. The array substrate according to claim 12, wherein: The first connection portion and the data line are provided in the same layer, the third connection portion and the data line are provided in a different layer, and the first connection portion and the third connection portion are connected through a via hole.

16. The array substrate according to claim 1, wherein: The array substrate further includes a common electrode, which is located on a side of the data line away from the substrate. The pixel electrode is located on a side of the common electrode away from the substrate, and the common electrode covers at least a portion of the data line. The pixel electrode is connected to the first connecting portion through a via.

17. A display panel, characterized in that: include: The array substrate according to any one of claims 1 to 16.

18. A display device, characterized in that: include: The display panel as claimed in claim 17.

Images