Low-power soc optimization method and system

Abstract

The application provides a low-power SOC optimization method and system. The interface states of multiple interfaces are periodically sampled; the joint weight is periodically determined, the joint weight is used to indicate the relevance between the interfaces; the relevance between the interfaces and behaviors is determined based on the correspondence between the historical interface states of the multiple interfaces and the actual behaviors; the predicted behaviors in the current period are determined based on the relevance between the interfaces and behaviors, the interface states in the current period, and the joint weight in the current period; the target clock domain and the target power domain are determined based on the predicted behaviors in the current period, the first correspondence and the second correspondence, and the control strategy of the power and the clock is triggered based on the target clock domain and the target power domain. In different working modes, the power, the clock and the data storage strategy of the multi-module are dynamically coordinated to realize system-level power optimization, and the fast wake-up and data integrity are ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of SOC, in particular to a low-power SOC optimization method and system. BACKGROUND

[0002] In embedded systems and mobile devices, multi-module collaborative work (such as CPU, DDR, SRAM, peripherals, etc.) leads to the complication of power management. Existing technologies usually adopt independent strategies: for example, reducing dynamic power consumption through clock gating, or closing inactive modules through power domain management, or reducing storage unit power supply through data compression. However, these methods all have the problem of low resource utilization: for example, a dedicated bus is only used for a specific task and is not deeply integrated with other low-power strategies (such as clock gating, power domain management), and cannot maximize energy efficiency. SUMMARY

[0003] The purpose of the embodiments of the present application is to provide a low-power SOC optimization method and system to improve resource utilization.

[0004] In a first aspect, the present application provides a low-power SOC optimization method, the SOC includes a plurality of clock domains and a plurality of power domains; the SOC maintains a first correspondence relationship between the clock domains and behaviors and a second correspondence relationship between the power domains and behaviors, the SOC includes a plurality of interfaces, and the interfaces include GPIO interfaces; the method includes:

[0005] Periodically sampling interface states of a plurality of the interfaces;

[0006] Periodically determining a joint weight, the joint weight being used to indicate the relevance between each of the interfaces;

[0007] Determining the relevance between the interfaces and the behaviors based on the correspondence relationship between the historical interface states of a plurality of the interfaces and the actual behaviors;

[0008] Determining a predicted behavior of a current period based on the relevance between the interfaces and the behaviors, the interface states of the current period, and the joint weight of the current period;

[0009] Determining a target clock domain and a target power domain based on the predicted behavior of the current period, the first correspondence relationship, and the second correspondence relationship, and triggering a power and clock control strategy based on the target clock domain and the target power domain.

[0010] In a second aspect, the present application provides a low-power SOC optimization system, the SOC includes a plurality of clock domains and a plurality of power domains; the SOC maintains a first correspondence relationship between the clock domains and behaviors and a second correspondence relationship between the power domains and behaviors, the SOC includes a plurality of interfaces, and the interfaces include GPIO interfaces; the optimization system includes:

[0011] a collection module configured to periodically sample interface states of a plurality of interfaces;

[0012] a first determination module configured to periodically determine a joint weight, the joint weight being used to indicate a relevance between the interfaces;

[0013] a second determination module configured to determine a relevance between an interface and a behavior based on a correspondence between historical interface states of the plurality of interfaces and actual behaviors;

[0014] a prediction module configured to determine a predicted behavior of a current period based on the relevance between the interface and the behavior, the interface states of the current period, and the joint weight of the current period;

[0015] a control module configured to determine a target clock domain and a target power domain based on the predicted behavior of the current period, the first correspondence, and the second correspondence, and trigger a control strategy of a power supply and a clock based on the target clock domain and the target power domain.

[0016] The embodiments of the present application provide a low-power-consumption SOC optimization method and system. The interface states of a plurality of interfaces are periodically sampled. A joint weight is periodically determined, the joint weight being used to indicate a relevance between the interfaces. A relevance between an interface and a behavior is determined based on a correspondence between historical interface states of the plurality of interfaces and actual behaviors. A predicted behavior of a current period is determined based on the relevance between the interface and the behavior, the interface states of the current period, and the joint weight of the current period. A target clock domain and a target power domain are determined based on the predicted behavior of the current period, the first correspondence, and the second correspondence, and a control strategy of a power supply and a clock is triggered based on the target clock domain and the target power domain. In different working modes, the power supply, the clock, and the data storage strategy of a plurality of modules are dynamically coordinated, system-level power consumption optimization is achieved, and meanwhile, fast wake-up and data integrity are ensured. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor based on these drawings.

[0018] Figure 1 A low-power-consumption SOC optimization method flowchart provided by the embodiments of the present application;

[0019] Figure 2 A low-power-consumption SOC optimization system structure schematic diagram provided by the embodiments of the present application. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

[0021] Figure 1 A low-power SOC optimization method provided in the embodiments of the present application is shown in a flowchart. The SOC includes multiple clock domains and multiple power domains. The power domains and the clock domains each include parent domains and child domains, each parent domain corresponds to one or more child domains, each parent domain corresponds to a total switch, and each child domain corresponds to a sub-switch; the parent power domains include a core computing domain, a storage domain, a communication domain, a sensor domain, and a display domain; and the parent clock domains include a main clock domain, a storage clock domain, a communication clock domain, and a sensor clock domain.

[0022] The core computing domain includes a CPU and a GPU (high power consumption, dynamic frequency adjustment is required).

[0023] The storage domain includes a DDR and an SRAM (medium power consumption, on-demand retention self-refresh is required).

[0024] The sensor domain includes a GPIO and an I2C (low power consumption, monitoring is required).

[0025] Examples:

[0026] User interaction behavior: the core domain is boosted to 1.0V, and the storage domain is reduced to 0.7V.

[0027] Idle behavior: the GPU is turned off, and the storage domain enters self-refresh (0.7V).

[0028] Clock domain division:

[0029] The main clock domain includes a CPU and a GPU (high frequency, such as 2.0GHz).

[0030] The communication clock domain includes a UART and an SPI (medium frequency, such as 100MHz).

[0031] The sensor clock domain includes a GPIO and an ADC (low frequency, such as 10MHz).

[0032] Examples:

[0033] Predicted behavior: user interaction: the CPU frequency is increased to 2.0GHz, and the screen refresh rate is set to 60Hz.

[0034] Predicted behavior: idle: the main clock is reduced to 200MHz, and the sensor clock is gated (only periodic sampling).

[0035] The SOC maintains a first correspondence relationship between the clock domains and behaviors and a second correspondence relationship between the power domains and behaviors, and the SOC includes multiple interfaces, including a GPIO interface.

[0036] The second correspondence can be described as in Table 1 below:

[0037] Table 1

[0038] Power parent domain Power sub-domain Default state Behavior association Core compute domain CPU, GPU, NPU Active (1.0V) User interaction, high-performance tasks Storage domain DDR, low-power SRAM Retention (0.7V) Data access requirements Communication domain I2C, SPI, UART Active (1.0V) Sensor data transceiving, peripheral control Sensor domain GPIO (keys, environmental sensors) Low-Power (0.9V) Environmental monitoring, wake-up detection Display domain Screen driving, backlight Off (0V) User active interaction

[0039] The first correspondence can be described as in Table 2 below:

[0040] Table 2

[0041] Clock domain Contains modules Default frequency Behavior association Main clock domain CPU, GPU 2.0GHz User interaction, compute-intensive tasks Storage clock domain DDR controller, SRAM 1.2GHz Data access operations Communication clock domain I2C, SPI, UART 100MHz Peripheral data transmission Sensor clock domain GPIO interface, ADC 10MHz Sensor sampling

[0042] As shown in Figure 1 , the method comprises:

[0043] S110, periodically sampling interface states of a plurality of interfaces.

[0044] The interface state can refer to an active or idle state of the interface.

[0045] An active interface is generally transmitting data (e.g., a GPIO button is pressed, a UART receives data).

[0046] An idle interface is generally an interface without data transmission (e.g., a sensor is not triggered, a screen is not operated).

[0047] The sampling period can refer to a time interval at which the system detects the interface state periodically (e.g., sampling once every 100 ms).

[0048] The sampling process can be that when the interface state changes (e.g., a GPIO edge trigger), an interrupt service program (ISR) is triggered, the state is recorded and the register is updated. For example, when a user presses a GPIO button, the ISR changes the interface state from 0 to 1.

[0049] The interface register state can also be read periodically by a timer (e.g., querying an I2C sensor whether it returns data once every 100 ms). For example, the I2C interface state of a temperature and humidity sensor is read once every second.

[0050] S120, periodically determining a joint weight, the joint weight being used to indicate the relevance between the interfaces.

[0051] In specific implementation, the determination of the joint weight can be based on historical interaction data between the interfaces. For example, if two interfaces are frequently active at the same time in multiple behaviors, the joint weight between them is high, indicating that there is a strong relevance between the two interfaces. This relevance can be used to predict the active state of the interface in future behaviors, thereby optimizing the management of power and clock.

[0052] To determine the joint weight more accurately, the time decay effect between interfaces can also be considered. That is, if two interfaces are not co-active for a long time, their relevance between them can be weakened. This time decay effect can be simulated by introducing parameters such as time decay weight and decay rate.

[0053] The joint weight W can be determined based on the following formula, which combines the time decay effect and the recent co-occurrence pattern, ensuring real-time and low overhead requirements, which can quickly reduce the weight of interfaces that have not cooperated for a long time, avoiding the interference of outdated data on prediction, where, ij (t), which combines the time decay effect and the recent co-occurrence pattern, ensures real-time and low overhead requirements, which can quickly reduce the weight of interfaces that have not cooperated for a long time, avoiding the interference of outdated data on prediction, where, The larger the weight is, the smaller the weight is, the sliding window co-occurrence term, which is used to capture the recent co-occurrence pattern of interface pairs, and the higher the frequency of co-occurrence is, the higher the weight is, in order to adapt to short-term behavior pattern changes:

[0054] ;

[0055] where, : time decay weight;

[0056] : decay rate; it can control the decay rate and efficiently handle time-sensitive problems (such as = 0.1 slow decay, = 1.0 fast decay).

[0057] : the period when interface i and j last co-activated;

[0058] T: total period number, which can be determined according to actual needs; it can balance real-time and noise suppression (T large, strong noise suppression; T small, fast response).

[0059] (relevant to time decay effect) to give dynamic weight to historical events, indicating that the longer the time from the last co-activation, the more obvious the weight decay;

[0060] (relevant to recent co-occurrence pattern) to count the frequency of interface i and j being active at the same time in the past T periods, indicating the strength of their recent association.

[0061] By and balance the weight of historical decay and recent statistics.

[0062] The combination that maximizes prediction accuracy on the validation set can be selected by grid search or Bayesian optimization.

[0063] S130, based on the correspondence between the interface state of a plurality of interfaces and the actual behavior, determines the relevance of the interface and the behavior.

[0064] Correlation coefficient The correlation coefficient can be determined based on the following formula

[0065] ;

[0066] Correlation coefficient The correlation coefficient can also be determined based on the following formula:

[0067] ;

[0068] Wherein:

[0069] i, j represent the interface number index;

[0070] : the kth behavior, m is the number of behaviors, k∈m;

[0071] p ijk represents the conditional probability that interfaces i and j are simultaneously active and trigger behavior in the history T period;

[0072] N is the total number of statistical periods (recommended value range 100-1000 sampling periods);

[0073] d ijk is the decay factor (value range 0.9-0.99), used to reduce the weight of early history data;

[0074] T interval represents the interval coefficient of the current period and the reference period (when the sliding window mechanism is adopted, T interval = current period number-window start period number);

[0075] The formula dynamically adjusts the correlation strength in two dimensions: in the time dimension, the progressive forgetting mechanism of the historical data is realized through the exponential decay factor d ijk , ensuring that the system can adapt to changes in usage patterns; in the spatial dimension, the cooperative activation mode between interfaces is captured through the conditional probability p ijk . For example, when the GPIO button (interface i=5) and the SPI screen interface (j=8) present a high correlation of p 5,8,1 =0.93 in the user interaction scenario (k=1), it indicates that the linkage of these two interfaces can be used as an important feature to predict user interaction behavior.

[0076] In specific implementation, the correlation coefficient matrix can be constructed by the following steps:

[0077] Initialize the three-dimensional matrix C[m][n][n], and set the initial weight according to the mapping relationship between the interface number and the parent domain (such as the sensor domain interface group S={9, 10, 11}, the display domain interface group D={7, 8}).

[0078] Statistical interface state joint active events in sliding time window (suggested length 50-200 cycles):

[0079] When interfaces i and j are simultaneously in the Active state and the system performs behavior Bk, the counter CT ijk +=1; when any interface is individually active but does not trigger behavior, the counter CT ijk =0.5 (penalty term);

[0080] Recalculate p calibrate and d ijk every T ijk period (suggested 10-20 cycles):

[0081] p ijk =CT ijk / Σ(CT::k);

[0082] d ijk =1-(current epoch -last activeepochijk ) / N decay ;

[0083] Where N decay is the decay cycle constant (default 100);

[0084] Normalize the coefficient matrix to ensure ΣC::k∈[0,1];

[0085] p ijk represents the proportion of a certain value, which is obtained by comparing the local value CT ijk with the sum of the overall value, used to measure the weight of the local in the global.

[0086] CT ijk is a local value.

[0087] Σ(CT::k) represents the sum of the counter values.

[0088] d ijk represents a time-varying decay value, used to measure the freshness or activity of a certain event or state.

[0089] current epoch represents the current time point or timestamp, used to dynamically calculate time-related variables.

[0090] N decay represents the decay factor, which controls the speed of time decay. The larger the value, the slower the decay; the smaller the value, the faster the decay.

[0091] Application example: In user interaction scenarios, when the C signal of the GPIO button interface (i=5) and the SPI screen interface (j=8) is detected... 5,8,1 =0.87, and the joint weight W 5,8 When (t)=0.92, the linkage of these two interfaces will significantly improve the prediction probability of user interaction behavior. However, in idle scenarios, if the C of the temperature sensor interface (i=12) and the GPU status interface (j=3) is... 12,3,idle =0.05, indicating that the active state of these two interfaces is negatively correlated with idle behavior.

[0092] Next, the system will dynamically adjust the weight of each interface in predicting user behavior based on the calculated correlation coefficient matrix. For highly correlated interface combinations, the system will assign higher weights to more accurately predict user behavior. Simultaneously, the system will continuously refine the correlation coefficient matrix based on updates to historical data to adapt to changes in usage patterns.

[0093] In practice, the system also considers other factors, such as user habits and contextual information, to further improve prediction accuracy. For example, when a user frequently performs a specific operation, the system will prioritize interface combinations related to that operation, thereby improving prediction accuracy.

[0094] S140, based on the correlation between the interface and the behavior, the interface status of the current period, and the joint weight of the current period, determine the predicted behavior for the current period.

[0095] If the probability of the target behavior occurring in the current period is greater than a first threshold and the difference between the probability of the target behavior and the probability of other behaviors occurring in the current period is greater than a second threshold, then the predicted behavior for the current period is determined to be the target behavior.

[0096] The probability of each action in the current cycle can be determined based on the following formula:

[0097] ;

[0098] in, : The k-th action, where m is the number of actions, k∈m;

[0099] : The state of the interface in the current period t; where S(t) = [s1(t), s2(t), ..., s n (t)];

[0100] Behavior B k In the current period t, behavior B k The probability of occurrence;

[0101] : behavior B k Correlation coefficient of interface i and interface j, n is the number of interfaces, i∈n, i∈n;

[0102] : joint weight of interface i and interface j in current period t.

[0103] The parameters α, β, T, θ k As the action space of reinforcement learning, a Markov decision process is constructed to optimize the parameters.

[0104] The state space of the Markov decision process is the interface active frequency, power consumption level, temperature, and remaining power.

[0105] In some embodiments, the SOC includes a temperature sensor.

[0106] The second threshold Δθ can be determined based on the following formula:

[0107] ;

[0108] Where μ is the mean of all behaviors, and σ is the standard deviation of all behaviors.

[0109] S150, based on the predicted behavior of the current period, the first correspondence relationship, the second correspondence relationship, determines the target clock domain and the target power domain, and triggers the control strategy of the power and the clock based on the target clock domain and the target power domain.

[0110] Where the first correspondence relationship can be used to map the predicted behavior to the target clock domain, and the mapping can be achieved based on the first correspondence relationship through a lookup table or a lookup algorithm. At the same time, the second correspondence relationship is used to map the predicted behavior to the target power domain, and the mapping can also be achieved based on the first correspondence relationship through a lookup table or a lookup algorithm.

[0111] After the target clock domain and the target power domain are determined, the corresponding power and clock control strategy can be triggered, such as adjusting the output frequency of the clock generator, switching the power state of the power management unit (PMU), adjusting the voltage level, etc. Throughout the process, the power and clock adjustment is coordinated to avoid timing problems or performance degradation.

[0112] For example, the interface feature of the predicted behavior user interaction can be: GPIO key high level + SPI screen data flow > 10KB / s. Based on the first correspondence relationship and the second correspondence relationship, the target clock domain and the target power domain corresponding to the predicted behavior are determined. The following strategy actions can be performed on the target clock domain and the target power domain:

[0113] Power: core computing domain boosted to 1.0V, display domain turned on.

[0114] Clock: CPU frequency boosted to 2.0 GHz, screen refresh rate 60 Hz.

[0115] The interface feature monitored by the predicted behavior sensor can be a + GPIO interrupt pulse triggered every 2 seconds for an I2C temperature and humidity sensor. Based on the first correspondence and the second correspondence, the target clock domain and the target power domain corresponding to the predicted behavior are determined. The following policy actions can be performed on the target clock domain and the target power domain:

[0116] Power: communication domain remains 0.9V, sensor domain is bucked to 0.8V.

[0117] Clock: SPI frequency is reduced to 50MHz, GPIO clock gating is enabled for 10MHz sampling.

[0118] The interface feature of the predicted behavior of idling can be no activity within 5 minutes for all interfaces. Based on the first correspondence and the second correspondence, the target clock domain and the target power domain corresponding to the predicted behavior are determined. The following policy actions can be performed on the target clock domain and the target power domain:

[0119] Power: storage domain is bucked to 0.7V, core computing domain is turned off.

[0120] Clock: DDR enters self-refresh mode (1.2GHz→200MHz), sensor clock gating.

[0121] After implementing the power and clock control strategy, the power consumption and performance of the system are monitored to ensure that the power consumption is optimized under the premise of meeting the behavior requirements. If the system power consumption exceeds the preset threshold or the performance is lower than expected, the control strategy is adjusted, the target clock domain and power domain are re-determined, and the balance between power consumption and performance is achieved.

[0122] As the user behavior pattern changes, the activity state of the interface and the relevance will also be adjusted. The system needs to continuously monitor the interface state, including the transition of active interfaces, the change of collaborative mode between interfaces, and the migration of behavior patterns. For example, when the user interaction mode changes to idle mode, the interface state will change from high-frequency activity to low-frequency or no activity state.

[0123] When a significant change in interface state or behavior pattern is detected, the system needs to re-evaluate the relevance of interfaces and behaviors (such as recalculating the relevance coefficient C ijk and the joint weight W ij (t). This can ensure that the prediction model can capture changes in user behavior in real time and avoid interference from outdated data on prediction results.

[0124] Based on the updated relevance and weight, the system needs to re-determine the target clock domain and power domain, and trigger the corresponding power and clock control strategy. For example, if the user behavior changes from data-intensive tasks to simple environmental monitoring, the system needs to reduce the voltage and frequency of the core computing domain, and at the same time, turn off unnecessary interface power to maximize the saving of power consumption.

[0125] Through continuous monitoring and dynamic adjustment, the system can ensure that the real-time optimization of power consumption and performance is realized under the premise of meeting the user behavior demand, and the overall energy efficiency is improved.

[0126] The system periodically repeats the above steps to adjust the power management and clock configuration in real time according to the dynamic changes of user behavior, to adapt to different use scenarios and realize the dual protection of low power consumption and high performance.

[0127] In addition, the SOC also has adaptive learning ability, which can continuously optimize the relevance evaluation model and behavior prediction algorithm between interfaces according to the user's usage habits, improve the prediction accuracy and response speed, and provide users with a smoother and energy-saving use experience.

[0128] In the embodiment, the SOC has been successfully applied to low-power intelligent terminals such as smartphones, tablets, and wearable devices, effectively prolonging the device's battery life while ensuring smooth user experience. In the future, with the continuous optimization of algorithms and the upgrading of hardware technology, the performance and power consumption of the SOC will be further improved, providing strong support for the development of the Internet of Things, edge computing and other fields.

[0129] In order to perform the corresponding steps in the above embodiments and various possible ways, the following is an implementation of a low-power SOC optimization device, which can optionally use the device structure of the electronic device shown in the above Figure 2 . Further, please refer to Figure 2 , Figure 2 The function module diagram of a low-power SOC optimization device provided by the embodiment of the present application. It should be noted that the low-power SOC optimization device provided by the embodiment has the same basic principles and technical effects as the above-mentioned embodiments. For brevity, some parts of this embodiment are not mentioned, and the corresponding content of the above-mentioned embodiments can be referred to. The low-power SOC optimization device includes:

[0130] Figure 2 The low-power SOC optimization system structure schematic diagram provided by the embodiment of the present application. The SOC includes a plurality of clock domains, a plurality of power domains; the SOC maintains a first correspondence relationship between the clock domain and the behavior and a second correspondence relationship between the power domain and the behavior, the SOC includes a plurality of interfaces, and the interface includes a GPIO interface; the optimization system includes:

[0131] The collection module 201 is configured to periodically sample interface states of a plurality of interfaces;

[0132] The first determination module 202 is configured to periodically determine a joint weight, which is used to indicate the relevance between the interfaces.

[0133] The second determination module 203 is configured to determine the relevance between the interfaces and the behaviors based on a historical correspondence between the interface states of the plurality of interfaces and the actual behaviors.

[0134] The prediction module 204 is configured to determine a predicted behavior of a current period based on the relevance between the interfaces and the behaviors, the interface state of the current period, and the joint weight of the current period.

[0135] The control module 205 is configured to determine a target clock domain and a target power domain based on the predicted behavior of the current period, the first correspondence, and the second correspondence, and trigger a control strategy of the power and the clock based on the target clock domain and the target power domain.

[0136] In some embodiments, the SOC further includes a temperature sensor.

[0137] In some embodiments, the power domain and the clock domain each include a parent domain and a child domain, each parent domain corresponds to one or more child domains, each parent domain corresponds to a total switch, and each child domain corresponds to a sub-switch; the parent power domain includes a core computing domain, a storage domain, a communication domain, a sensor domain, and a display domain; and the parent clock domain includes a main clock domain, a storage clock domain, a communication clock domain, and a sensor clock domain.

[0138] Optionally, the above modules can be stored in the memory in the form of software or firmware (Firmware) or solidified in the low-power SOC-optimized operating system (Operating System, OS), and can be executed by the processor. Meanwhile, the data, program codes, and the like required for executing the above modules can be stored in the memory.

[0139] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can also be implemented by other manners. The apparatus embodiments described above are merely illustrative, for example, the flowcharts and block diagrams in the drawings show the possible implementation architecture, function and operation of the apparatus, method and computer program product according to the embodiments of the present application. In this regard, each block in the flowchart or block diagram can represent a module, a program segment or a part of code, which contains one or more executable instructions for implementing the specified logic function. It should also be noted that in some alternative implementation manners, the functions noted in the blocks can also occur in different order from that noted in the drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and sometimes they can also be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for executing the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0140] In addition, each functional module in the embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0141] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application can be embodied in the form of a software product, and the computer software product is stored in a storage medium, and includes a number of instructions for causing a computer device (which can be a personal computer, an electronic device, or a network device, etc.) to execute all or part of the steps of the methods described in the embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0142] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A low-power SOC optimization method, characterized in that, The SOC comprises a plurality of clock domains and a plurality of power domains; the SOC maintains a first correspondence relationship between the clock domains and behaviors and a second correspondence relationship between the power domains and behaviors, the SOC comprises a plurality of interfaces, and the interfaces comprise GPIO interfaces; and the method comprises: periodically sampling interface states of the plurality of interfaces; periodically determining joint weights, the joint weights being used to indicate correlations between the interfaces; determining correlations between the interfaces and behaviors based on historical correspondence relationships between the interface states of the plurality of interfaces and actual behaviors; determining predicted behaviors of a current period based on the correlations between the interfaces and behaviors, the interface states of the current period and the joint weights of the current period; determining target clock domains and target power domains based on the predicted behaviors of the current period, the first correspondence relationship and the second correspondence relationship, and triggering a control strategy of power and clocks based on the target clock domains and the target power domains; if a probability that a target behavior occurs in the current period is greater than a first threshold value and a difference between probabilities that the target behavior and other behaviors occur in the current period is greater than a second threshold value, determining that the predicted behaviors of the current period are the target behaviors; determining probabilities of the behaviors of the current period based on the following formula: ； wherein, : kth behavior, m is the number of behaviors, k e m; : state of interface for current cycle t; : Probability of occurrence of behavior B in current period t k : Probability of occurrence of behavior B in current period t : Action B k Correlation coefficient of the lower interface i and interface j, n is the number of interfaces, i ∈ n; : current period t joint weight of interface i and interface j.

2. The method of claim 1, wherein, W is determined based on the following equation ij (t): ； wherein : time decay weight; : decay rate; : period when interfaces i and j were last jointly active; T: total period quantity; To count the frequency of simultaneous activity of interfaces i and j in the past T periods.

3. The method of claim 2, wherein, The parameters α, β, T, θ k As the action space of reinforcement learning, a Markov decision process is constructed to optimize the parameters.

4. The method of claim 3, wherein, a state space of the Markov decision process is interface active frequency, power consumption level, temperature and remaining power.

5. The method of claim 4, wherein, The SOC comprises a temperature sensor.

6. The method of claim 1, wherein, determining the second threshold value Δθ based on the following formula: ； wherein μ is a mean value of all behaviors, and σ is a standard deviation of all behaviors.

7. The method of claim 1, wherein, The power domains and the clock domains each comprise parent domains and child domains, each parent domain corresponding to one or more child domains, each parent domain corresponding to a total switch, and each child domain corresponding to a child switch; the parent power domains comprise core computing domains, storage domains, communication domains, sensor domains and display domains; and the parent clock domains comprise main clock domains, storage clock domains, communication clock domains and sensor clock domains.

8. A low power SOC optimization system, characterized in that, The SOC comprises a plurality of clock domains and a plurality of power domains; the SOC maintains a first correspondence relationship between the clock domains and behaviors and a second correspondence relationship between the power domains and behaviors, the SOC comprises a plurality of interfaces, and the interfaces comprise GPIO interfaces; and the optimization system comprises: a collection module, configured to periodically sample interface states of the plurality of interfaces; a first determination module, configured to periodically determine joint weights, the joint weights being used to indicate correlations between the interfaces; a second determination module, configured to determine correlations between the interfaces and behaviors based on historical correspondence relationships between the interface states of the plurality of interfaces and actual behaviors; a prediction module, configured to determine predicted behaviors of a current period based on the correlations between the interfaces and behaviors, the interface states of the current period and the joint weights of the current period; a control module, configured to determine target clock domains and target power domains based on the predicted behaviors of the current period, the first correspondence relationship and the second correspondence relationship, and trigger a control strategy of power and clocks based on the target clock domains and the target power domains. if a probability of the target behavior occurring in the current period is greater than a first threshold and a difference between the probability of the target behavior and probabilities of other behaviors occurring in the current period is greater than a second threshold, determining the predicted behavior of the current period as the target behavior; the probabilities of the respective behaviors in the current period are determined based on the following formula: ； wherein, : kth behavior, m is the number of behaviors, k e m; : state of interface for current cycle t; : action B k probability of occurrence of action B in the current period t k the current period t : Action B k Correlation coefficient of the lower interface i and interface j, n is the number of interfaces, i ∈ n; : current period t joint weight of interface i and interface j.

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