Instruction jump prediction method and device, computer equipment, readable storage medium and program product

Abstract

The invention relates to an instruction jump prediction method and device, computer equipment, a readable storage medium and a program product. The method comprises the following steps: acquiring a to-be-processed instruction obtained by decoding, and acquiring structure behavior information corresponding to a conditional jump instruction under the condition that the to-be-processed instruction is identified as the conditional jump instruction; performing feature extraction based on the structural behavior information to obtain structural features; obtaining a sensor corresponding to the condition jump instruction; and inputting the structural features into the sensor, and performing jump prediction to obtain a predicted jump result. By adopting the method, the instruction jump prediction accuracy can be improved, so that the instruction execution conflict is reduced, and the waste of computer resources is reduced.

Description

Technical Field

[0001] The present application relates to the field of artificial intelligence technology, and in particular to an instruction jump prediction method, apparatus, computer equipment, readable storage medium, and program product. Background Art

[0002] In order to improve the efficiency of computer instruction execution, pipeline technology was introduced. Pipeline technology splits a task into multiple instructions and staggers their execution time to achieve the effect of improving execution efficiency. However, the pipeline data is very large, and there are situations where instruction execution conflicts occur. In order to avoid instruction execution conflicts, it is necessary to predict the execution path of instructions in advance.

[0003] However, the prediction mechanisms in traditional technologies (such as BHT and TAGE) usually rely on historical behavior or PC templates. Without the model's historical behavior or PC template, the accuracy of the predicted instruction execution path is very low, which will lead to instruction execution conflicts. This requires a large number of clock cycles to compensate, wasting a lot of computing resources. Summary of the Invention

[0004] Based on this, it is necessary to provide an instruction jump prediction method, device, computer equipment, readable storage medium and program product that can improve the accuracy of instruction jump prediction, thereby reducing instruction execution conflicts and reducing the waste of computer resources to address the above technical problems.

[0005] In a first aspect, the present application provides an instruction jump prediction method, the method comprising:

[0006] Get the decoded instructions to be processed;

[0007] When the instruction to be processed is identified as a conditional jump instruction, obtaining structural behavior information corresponding to the conditional jump instruction;

[0008] Performing feature extraction based on the structural behavior information to obtain structural features;

[0009] obtaining a perceptron corresponding to the conditional jump instruction;

[0010] The structural features are input into the perceptron to perform jump prediction to obtain a predicted jump result.

[0011] In one embodiment, the structural behavior information includes at least one of the number of loops recorded by the loop counter, the proportion of zero values ​​in the current tensor corresponding to the instruction, the proportion of target instructions in the historical target number of instructions, and the instruction storage location; the structural features include at least one of the critical jump point features obtained based on the number of loops, the sparsity features obtained based on the proportion of zero values ​​in the current tensor corresponding to the instruction and the jump threshold, the instruction type features obtained based on the proportion of target instructions in the historical target number of instructions and the distribution threshold, and the hash features obtained by hashing the instruction storage location.

[0012] In one embodiment, the structural feature includes a multi-level coded feature for characterizing jump probability; inputting the structural feature into the perceptron to perform jump prediction to obtain a predicted jump result includes:

[0013] Inputting the structural features into the perceptron to obtain a jump probability;

[0014] The jump probability is used as the predicted jump result.

[0015] In one embodiment, inputting the structural features into the perceptron to perform jump prediction to obtain a predicted jump result includes:

[0016] Get the weight vector and bias vector of the perceptron;

[0017] Calculating a dot product result based on the structural feature, the weight vector, and the bias vector;

[0018] A predicted jump result is obtained based on the dot product result.

[0019] In one embodiment, the method further comprises:

[0020] When the predicted jump result is different from the actual jump result, the weight vector is corrected based on the dot product result and the structural feature so that the dot product result of the structural feature is close to the dot product corresponding to the actual jump result, and the bias vector is corrected based on the dot product result to adjust the classification boundary.

[0021] In one embodiment, the method further comprises:

[0022] If the sensor satisfies a correction condition, correcting the sensor;

[0023] The correction condition includes at least one of the following conditions:

[0024] The number of times that the predicted jump result of the sensor differs from the actual jump result is greater than a number threshold;

[0025] or, no conditional jump instruction corresponding to the sensor is identified within a preset time period;

[0026] Alternatively, the sensor is an invalid sensor;

[0027] Alternatively, overflow occurs when the weight vector and bias vector of the perceptron are updated.

[0028] In one embodiment, obtaining a perceptron corresponding to the conditional jump instruction includes:

[0029] Calculating a hash value corresponding to the storage address of the conditional jump instruction;

[0030] A perceptron corresponding to the conditional jump instruction is queried based on the hash value.

[0031] In one embodiment, obtaining a perceptron corresponding to the conditional jump instruction includes:

[0032] In the case where the processor is a multi-core processor, calculating a hash value corresponding to the storage address of the conditional jump instruction;

[0033] Performing an XOR operation on the hash value and the identifier of the core corresponding to the conditional jump instruction to obtain a perceptron index;

[0034] A perceptron corresponding to the conditional jump instruction is searched based on the perceptron index.

[0035] In one embodiment, the method further comprises:

[0036] Get the number of effective perceptrons corresponding to each kernel;

[0037] The perceptrons of the kernel whose number of effective perceptrons is smaller than the effective threshold are replaced with the perceptrons of the kernel whose number of effective perceptrons is larger than the effective threshold.

[0038] In one embodiment, the method further comprises:

[0039] In the event of a primary branch predictor failure, continuing with the step of identifying a conditional jump instruction; or

[0040] A prediction result of the primary branch predictor obtained in parallel with the predicted jump result is obtained, and a target jump result is obtained based on the prediction result of the primary branch predictor and the predicted jump result.

[0041] In a second aspect, the present application further provides an instruction branch prediction device, the device comprising:

[0042] An instruction acquisition module is used to acquire the decoded instructions to be processed;

[0043] an identification module, configured to obtain structural behavior information corresponding to a conditional jump instruction when the instruction to be processed is identified as a conditional jump instruction;

[0044] A feature extraction module, configured to extract features based on the structural behavior information to obtain structural features;

[0045] a perceptron acquisition module, configured to acquire a perceptron corresponding to the conditional jump instruction;

[0046] The prediction module is used to input the structural features into the perceptron to perform jump prediction to obtain a predicted jump result.

[0047] In a third aspect, the present application further provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method in any one of the above embodiments when executing the computer program.

[0048] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the method in any one of the above-mentioned embodiments when the computer program is executed by a processor.

[0049] In a fifth aspect, the present application also provides a computer program product, comprising a computer program, which implements the steps of the method in any one of the above embodiments when executed by a processor.

[0050] The above-mentioned instruction jump prediction method, device, computer equipment, readable storage medium and program product obtain the decoded instruction to be processed, and when the instruction to be processed is identified as a conditional jump instruction, obtain the structural behavior information corresponding to the conditional jump instruction; perform feature extraction based on the structural behavior information to obtain structural features; obtain a perceptron corresponding to the conditional jump instruction; input the structural features into the perceptron, perform jump prediction to obtain a predicted jump result, and thus, since each structural layer has a definite start and end pattern, feature extraction based on the structural behavior information can greatly improve the accuracy of jump prediction, thereby reducing instruction execution conflicts and reducing the waste of computer resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments of the present application or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying any creative work.

[0052] Figure 11. A diagram illustrating an application environment of an instruction jump prediction method according to an embodiment;

[0053] Figure 2 1 is a flow chart of an instruction jump prediction method according to an embodiment;

[0054] Figure 3 1 is a flow chart of an instruction jump prediction method according to another embodiment;

[0055] Figure 4 is a structural block diagram of an instruction jump prediction device in one embodiment;

[0056] Figure 5 FIG. 1 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0058] It should be noted that the terms "including" and "having" and any variations thereof used in this application are intended to cover non-exclusive inclusions. The term "plurality" used in this application refers to two or more.

[0059] The instruction jump prediction method provided in the embodiment of the present application can be applied to Figure 1 In the application environment shown, the instruction decoder decodes the input instruction to obtain a pending instruction, and then inputs the pending instruction into the jump predictor, which predicts whether to jump. The jump predictor is used to optimize loop exit and layer boundary prediction in neural network model inference. In this way, because each structural layer has a definite start and end pattern, feature extraction based on structural behavior information can significantly improve jump prediction accuracy, thereby reducing instruction execution conflicts and reducing the waste of computer resources.

[0060] In other embodiments, a primary branch predictor may also be included. This jump predictor serves as an auxiliary path to the primary branch predictor. The primary branch predictor uses existing prediction mechanisms (such as BHT and TAGE) to perform jump prediction based on historical behavior or PC templates. The jump predictor performs jump prediction based on structural features to improve the accuracy of overall jump prediction.

[0061] After the jump prediction result is obtained, instruction scheduling is performed based on the jump prediction result to avoid conflicts during instruction execution, thereby improving the efficiency of instruction execution.

[0062] It should be noted that the instruction jump prediction method of the present application can be applied to the jump prediction of the structure of each neural network layer in the AI ​​program, and can also be applied to ordinary programs. No specific restrictions are made here. In this application, the above-mentioned instruction jump prediction method is applied to the jump prediction of the structure of each neural network layer in the AI ​​program.

[0063] In an exemplary embodiment, Figure 2 As shown, an instruction jump prediction method is provided, which is applied to Figure 1 The jump predictor in FIG. 1 is taken as an example to illustrate the method, which includes the following steps S202 to S210. In which:

[0064] S202: Obtain the decoded instruction to be processed.

[0065] The instruction decoding unit decodes the input instruction to obtain an instruction to be processed. The decoding process may include instruction addressing and / or decoding process, which is not specifically limited here.

[0066] S204: When the instruction to be processed is identified as a conditional jump instruction, structural behavior information corresponding to the conditional jump instruction is obtained.

[0067] The conditional jump instruction is decoded by the instruction decoding unit. The instruction decoding unit can identify the instruction type to determine whether the instruction is a conditional jump instruction. Optionally, the instruction decoding unit can also output the jump PC (Program Counter, which stores the memory address of the next instruction to be executed to ensure continuous operation of the instruction pipeline) to the feature extractor and perceptron.

[0068] In some optional embodiments, the structural behavior information includes at least one of the number of loops recorded by the loop counter, the proportion of zero values ​​in the current tensor corresponding to the instruction, the proportion of target instructions in the historical target number of instructions, and the instruction storage location.

[0069] Each layer of the neural network model has a definite start and end pattern. For example, the convolutional layer executes a fixed number of iterations in a loop, activation functions such as ReLU usually appear in specific locations, and the execution includes a large number of CMP operations. In quantized or sparse models, some layers have a high zero value ratio (sparsity), and the program execution address (PC) exhibits a stage-by-stage clustering feature. In other words, there are clear jumps at these structural jump points. To this end, structural behavior information is obtained, which includes the number of loops recorded by the loop counter, the proportion of zero values ​​in the current tensor corresponding to the instruction, the proportion of target instructions in the historical target number of instructions, and at least one of the instruction storage locations.

[0070] When a layer structure is expanded through a for loop, a jump usually occurs at the end of the loop. Therefore, the number of loops recorded by the loop counter can be used as structural behavior information.

[0071] Some model structure layers, such as deep convolution or pruned MLP layers, have sparse input tensors. Jumps may occur when the proportion of zero values ​​is higher than a threshold. Therefore, the proportion of zero values ​​in the current tensor corresponding to the instruction can be used as structural behavior information.

[0072] Different structural layers in a neural network model have different instruction types. For example, activation layers (such as ReLU) often feature a significant proportion of comparison instructions like CMP and MAX. These changes in instruction type can serve as implicit signals of structural transitions, predicting whether a particular stage is currently being entered or about to be exited. Therefore, the proportion of target instructions within the historical target number of instructions can be used as information about structural behavior.

[0073] The low bits of the instruction address can distinguish the structural blocks. For example, different Conv layers have different instruction locations, so the instruction storage location can be used as structural behavior information.

[0074] S206: Extract features based on the structural behavior information to obtain structural features.

[0075] The structural features are obtained by processing structural behavior information through a feature extractor. The structural features include at least one of a critical jump point feature based on the number of loops, a sparsity feature based on the proportion of zero values ​​in the current tensor corresponding to the instruction and a jump threshold, an instruction type feature based on the proportion of target instructions in the historical target number of instructions and a distribution threshold, and a hash feature obtained by hashing the instruction storage location.

[0076] Specifically, a conditional jump instruction corresponds to a set of counters that record the number of for-loop executions, such as 4, 5, 6, 7, 8, etc. In this way, the loop count value can be obtained based on the number of loops in the counter, and then the corresponding critical jump point feature can be obtained. Optionally, the width of the counter can include 8, so the critical jump point feature can be expressed as .

[0077] The sparsity feature can be obtained by comparing the zero value ratio in the current tensor with a jump threshold, wherein the jump threshold can be preset. In some optional embodiments, since the jump thresholds of different model structure layers are different, the sparsity feature can be obtained by multi-level encoding.

[0078] An instruction type signature is derived based on the proportion of target instructions within a historical target number of instructions and a distribution threshold. For example, the proportion of CMP and / or ACT type instructions within a historical target number of instructions is calculated and compared with the distribution threshold to obtain the instruction type signature. In some optional embodiments, because the distribution thresholds for different model structure layers are different, the instruction type signature can be derived through multi-level encoding.

[0079] Based on the hash features obtained by hashing the instruction storage location, in actual neural network execution, especially when running the model on a CPU or general AI accelerator, each neural network layer will be compiled / generated into a specific code block (such as loop, matrix multiplication, activation function, etc.):

[0080]

[0081] Although these layers have similar semantic behaviors, the addresses of conditional jump instructions are completely different. Using a traditional branch predictor (such as TAGE) requires maintaining independent state for each address, lacking generalization. However, using instruction hash values ​​allows the perceptron to map different addresses into a unified structural behavior prediction, achieving semantically generalized prediction across layers.

[0082] In this application, structural feature extraction is integrated into the processor, and structural features are extracted in real time during the pipeline stage.

[0083] S208: Obtain the perceptron corresponding to the conditional jump instruction.

[0084] S210: Input the structural features into the perceptron to perform jump prediction to obtain a predicted jump result.

[0085] Each conditional jump instruction corresponds to a unique perceptron. When a conditional jump instruction is identified, in order to predict whether a jump will be performed, the structural features are input into the perceptron, and a jump prediction is performed to obtain a predicted jump result.

[0086] Among them, the perceptron is a single-layer perceptron, each perceptron includes a weight vector and a bias vector. In addition, each perceptron may also include a perceptron identifier, and the perceptron identifier may be a hash value based on the storage address of the conditional jump instruction. The hash value is used as the index of the perceptron array, so that after the conditional jump instruction is identified, the storage address of the conditional jump instruction can be obtained based on the program counter of the conditional jump instruction, and then the hash value is calculated, and then the corresponding perceptron is obtained based on the hash value.

[0087] The perceptron includes a weight vector and a bias vector, so jump prediction can be performed based on structural features, the weight vector and the bias vector to obtain a predicted jump result.

[0088] It's also important to note that after a predicted jump result is obtained, subsequent instruction execution can be scheduled based on the predicted jump result to avoid instruction conflicts, thereby reducing the extra computer resources consumed by instruction conflicts and improving resource utilization. Furthermore, by predicting instruction jumps in advance, the corresponding storage registers can be allocated in advance for instruction execution, reducing the resource waste caused by fixed register allocation.

[0089] The above-mentioned instruction jump prediction method obtains the instruction to be processed obtained by decoding, and when the instruction to be processed is identified as a conditional jump instruction, obtains the structural behavior information corresponding to the conditional jump instruction; performs feature extraction based on the structural behavior information to obtain structural features; obtains a perceptron corresponding to the conditional jump instruction; inputs the structural features into the perceptron, performs jump prediction to obtain a predicted jump result, and thus, since each structural layer has a definite start and end pattern, feature extraction based on the structural behavior information can greatly improve the accuracy of jump prediction, thereby reducing instruction execution conflicts and reducing the waste of computer resources.

[0090] In one optional embodiment, the structural features are input into a perceptron to perform jump prediction to obtain a predicted jump result, including: obtaining a weight vector and a bias vector of the perceptron; calculating a dot product result based on the structural features, the weight vector, and the bias vector; and obtaining a predicted jump result based on the dot product result.

[0091] The dot product result z=w·x+b is the predicted jump result , where the sign operator is used to return the sign of an integer, that is The value is ±1.

[0092] Take the loop count value as an example: 8 bits ( ), where x=[+1,+1,+1,+1,+1,+1,+1,-1], w=[+2,+1,0,-1,-1,0,+1,-2], b=-5, so z=4+(-5)=-1, so =-1, where -1 means no jump and +1 means jump.

[0093] In some optional embodiments, the method also includes: when the predicted jump result is different from the actual jump result, correcting the weight vector based on the dot product result and the structural features so that the dot product result of the structural features is close to the dot product corresponding to the actual jump result, and correcting the bias vector based on the dot product result to adjust the classification boundary.

[0094] Among them, if the prediction is wrong (i.e. y≠ ), the online updated perceptron weight is w+y·x, and the updated bias weight is b+y.

[0095] Still using the above example, if the actual result is y = +1 (should jump but predicted not to jump), then update w to [+3, +2, +1, 0, 0, +1, +2, -3] and update b to -4.

[0096] The weight vector is updated based on the dot product results and structural features. If the prediction is incorrect, it indicates a deviation in the dot product direction. To address this, y·x is added to w to shift the direction of future dot products of x closer to y. This strengthens the weight of features in the "correct direction" and weakens the weight of features in the "misleading direction." Updates to the bias weights are used to adjust the overall classification boundary. If the jump behavior fluctuates near the boundary, b will gradually shift toward the correct classification.

[0097] When a layer structure is expanded through a for loop, a jump usually occurs at the end of the loop. For example, take i=254 as the jump critical point:

[0098]

[0099] The perceptron uses this feature to gradually learn to identify the structural jump conditions at the loop termination point. Through weight accumulation and bias adjustment, the perceptron can capture critical points during training.

[0100] Some layers, such as depthwise convolution or pruned MLP layers, have sparse input tensors, and jumps may occur when the proportion of zero values ​​is above a threshold:

[0101]

[0102] This feature participates in the prediction through the sparsity of the input data in the structure layer (such as the proportion of zero values), which can assist the perceptron in identifying the behavioral characteristics that may cause structural jumps in the pruning and sparse stages. To simplify the hardware implementation, the current version uses Indicates whether the sparsity threshold (e.g. 60%) is exceeded; the perceptron will learn the correlation between the sparse phase and the jump behavior.

[0103] Different structural layers in a neural network model have different instruction types. For example, activation layers (such as ReLU) often have a significant proportion of comparison instructions like CMP and MAX. These changes in instruction type can serve as implicit signals of structural transitions, predicting whether a particular stage is currently being entered or about to be exited.

[0104]

[0105] This feature indicates whether the current structural layer is in the activation or comparison phase. During training, the perceptron automatically learns the correlation between these phase changes and jump behavior. In some cases, this feature alone can identify jump trends, making it suitable for determining structural boundaries.

[0106] The low bit of the jump instruction address can distinguish the structural blocks. For example, different Conv layers have different instruction locations and use PC[7:4] to get the value:

[0107]

[0108] This feature serves as a lightweight indicator of program execution semantics, distinguishing different structural locations through hashing. Although the jump instruction PC address is program-local, the perceptron can generalize across layers using this hash feature. That is, if the structural behaviors corresponding to different addresses are similar, the perceptron will obtain a consistent response through weight training.

[0109] In the above embodiment, low-overhead hardware logic can be used to perform real-time reasoning and training in the instruction decoding or pre-jump detection path to achieve online learning of jump behavior, and even for a new model, accurate prediction can be achieved after several training sessions.

[0110] In addition, to facilitate understanding, when multiple structural features participate in the judgment together, the semantic expression ability of the perceptron can be improved. For example, when the structural features of the input include:

[0111]

[0112] Merged input vector: x=[+1,+1,+1,+1,+1,+1,+1,-1,+1,+1,+1,+1,-1,+1], initial state of weight vector: w=[+3,+2,+1,0,0,+1,+2,3,+1,0,+2,-2,0,0], bias vector b=-5.

[0113] Perform dot product calculation: the first 8 dot products are: 3+2+1+0+0+1+2+(-3)=6, the last 6 dot products are: +1+0+2-2+0+0=+1, the bias vector is -5, z=6+1-5=2, so = + 1. In other embodiments, the dot product calculation may also be calculated together without distinguishing between the first 8 terms and the last 6 terms.

[0114] If the prediction is wrong (actual y=-1): then update: w is wx (subtract item by item), b is b-1, update example (first 3 items):

[0115]

[0116] A total of 14 bits are updated. By fusing multi-source structural features, the perceptron can capture structural jump patterns in real time. It has fast online training convergence and low hardware implementation cost, making it suitable for AI model structure prediction. Furthermore, if the perceptron has weight overflow or a high number of misjudgments, a replacement or zeroing management strategy is implemented. The details of the replacement or zeroing management strategy can be found below. In this application, the perceptron update frequency is controlled to converge within 5 to 10 mispredictions, which can adapt to structural behavior changes at different stages of the neural network.

[0117] In some optional embodiments, the structural features include multi-level encoded features for characterizing jump probability; the structural features are input into a perceptron to perform jump prediction to obtain a predicted jump result, including: inputting the structural features into the perceptron to obtain the jump probability; and using the jump probability as the predicted jump result.

[0118] Among them, in order to improve the accuracy of structural features in this application, the jump probability is represented by multi-level coding. For example, in the sparsity feature, if higher expression ability is required, multi-level sparsity hierarchical coding can be introduced. This can adapt to the sparsity features of different model structure layers. For example, the sparsity jump point of a certain model structure layer is 50%, and that of a certain model is 75%. In this way, multiple different levels of sparsity features can be introduced, such as using 2-bit to represent four levels: low, medium-low, medium-high, and high, to enhance the ability to distinguish jump boundaries and support a more refined weight learning process. In other embodiments, other numbers of levels can also be introduced, not limited to 2 bits.

[0119] For instruction type features, if higher expressive power is required, multi-scale hierarchical encoding can be introduced, for example, 2-bit represents four levels: low, medium-low, medium-high, and high. In other embodiments, other numbers of levels can also be introduced, not limited to 2 bits.

[0120] In this way, in this embodiment, the structural features of the multi-level coding can be calculated and then processed by the perceptron to obtain the jump probability, thereby improving the accuracy of the jump prediction.

[0121] In some optional embodiments, the method further includes: correcting the perceptron if the perceptron satisfies a correction condition; wherein the correction condition includes at least one of the following conditions: the number of times the predicted jump result of the perceptron differs from the actual jump result is greater than a threshold number; or, the conditional jump instruction corresponding to the perceptron is not recognized within a preset time period; or, the perceptron is an invalid perceptron; or, there is an overflow when updating the weight vector and bias vector of the perceptron.

[0122] The modification conditions include replacement conditions and / or clearing conditions, which are used to replace the perceptron and / or clear the values ​​of corresponding registers in the perceptron. The corresponding registers in the perceptron may include a loop counter, a weight vector, and a bias vector. Clearing the perceptron requires clearing the values ​​of these registers. Replacing a perceptron requires clearing the perceptron and updating its state and identifier (e.g., the aforementioned hash value).

[0123] In order to control resource consumption, this application also uses a sensor pool to manage each sensor. Each sensor in the sensor pool includes a sensor state, an identifier, a loop counter, a weight vector, a bias vector, and a usage frequency. The sensor state is used to indicate whether the sensor is valid, the identifier is the above-mentioned hash value, and the usage frequency is indicated by the failure to identify the conditional jump instruction corresponding to the sensor within a preset time length.

[0124] The total resource estimation can be done based on the perceptron array, number, and bit width, where the size of the perceptron array is 2 k , k is determined by the hash bit width of the conditional jump instruction. For example, PC[7:4] corresponds to 16 perceptrons, where the perceptron array includes 16 perceptrons, and the number of perceptrons is 16 (PC Hash = 4 bits). The total resources are: 16 groups * (16 (weight) × (5 bits) + 5 bits (bias) + 4 bits (PC hash)) ≈ 1.4KB. For ease of understanding, an embodiment of weights is given, where the feature vector x = [Loop8, Sparsity2, Instr2, PCHash4], that is, the feature vector has a total of 16 bits ± 1, and the weight vector also has 16 bits, corresponding to the number of bits in the feature vector. If more feature dimensions or the hash bit width of the conditional jump instruction is required (such as 32 or 64 perceptrons), there will be a linear increase. In other embodiments, the number of perceptrons in the perceptron array can be dynamically adjusted, for example, to support 16, 32, or 64 perceptron instances, etc., which is not specifically limited here.

[0125] The loop counter in the perceptron is incremented by 1 when a jump return is executed. It is reset to 0 when the jump offset is no longer jumped or the predictor misses. Optionally, a maximum counter can be set to prevent overflow, and the maximum counter value can be 255.

[0126] For the sparsity in the perceptron, which is a dynamic detection feature, real-time sampling is performed each time the structural block is executed; there is no need to retain the last state, only whether the current round exceeds the threshold; the instruction type feature is based on a sliding window (such as 64 items) and is updated once per cycle.

[0127] Among them, when the above correction conditions are met, the corresponding state is cleared or the sensor is replaced.

[0128] In order to illustrate the clearing and replacement of perceptrons, an embodiment is given. In this embodiment, after a conditional jump instruction is identified, the perceptron corresponding to the conditional jump instruction is obtained. If the perceptron is not obtained, the existing perceptron in the perceptron pool is replaced. For example, it is determined whether the existing perceptron in the perceptron pool triggers the replacement condition (the replacement condition is the above-mentioned correction condition). If one of the perceptrons is selected for replacement, the replacement process can be referred to above. In this way, the perceptron corresponding to the conditional jump instruction is obtained, and then a jump prediction is performed, and the actual jump situation is recorded. If the two are inconsistent, the number of failures is recorded. If the number of failures is greater than a number threshold, the perceptron can be cleared. In addition, if the weight overflows during the perceptron update process, the perceptron can also be cleared.

[0129] In other embodiments, the sensor pool may independently execute a management thread to periodically determine whether the sensors in the sensor pool meet the aforementioned correction conditions, and if so, clear or replace the sensors accordingly.

[0130] In some optional embodiments, obtaining a perceptron corresponding to a conditional jump instruction includes: calculating a hash value corresponding to a storage address of the conditional jump instruction; and querying the perceptron corresponding to the conditional jump instruction based on the hash value.

[0131] When the instruction to be processed is identified as a conditional jump instruction, a hash value, that is, the identifier of the sensor, is calculated based on the storage address of the conditional jump instruction, so that the corresponding sensor can be queried based on the identifier.

[0132] If a conditional jump instruction corresponding to a perceptron is not recognized within a preset time period, the perceptron may be replaced. For example, if a corresponding perceptron is not found based on a hash value query, a replacement operation may be triggered to replace the perceptron for which a conditional jump instruction corresponding to the perceptron was not recognized within a preset time period. The replacement process requires clearing the corresponding vector, counter state, hash value, etc.

[0133] In some optional embodiments, obtaining a perceptron corresponding to a conditional jump instruction includes: when the processor is a multi-core processor, calculating a hash value corresponding to a storage address of the conditional jump instruction; performing an XOR operation on the hash value and an identifier of a core corresponding to the conditional jump instruction to obtain a perceptron index; and querying the perceptron corresponding to the conditional jump instruction based on the perceptron index.

[0134] In the case where multiple cores share a perceptron pool, the perceptron index is determined by combining the perceptron identifier and the core identifier.

[0135] Multi-core processors can share a common perceptron for centralized training. Each core's perceptron access is XORed with the core's ID, so that the same hash value on different cores maps to different entries, preventing conflicts. Cross-core migration is supported, which involves inserting the perceptron contents of the current core into the shared perceptron without changing the contents. The identifier (hash value) of the conditional adjustment instruction is XORed with the core's ID.

[0136] In some optional embodiments, the method further includes: obtaining the number of valid perceptrons corresponding to each core; and replacing the perceptrons of the cores whose number of valid perceptrons is greater than the valid threshold with the perceptrons of the cores whose number of valid perceptrons is less than the valid threshold.

[0137] In this application, due to limited resources, the number of shared common perceptrons occupied by different cores can be managed. For example, each core can retain a maximum of M valid perceptrons, and if the number exceeds the threshold, the perceptrons are replaced. For example, the perceptrons of the core whose number of valid perceptrons is less than the valid threshold are used to replace the perceptrons of the core whose number of valid perceptrons is greater than the valid threshold. This can balance the number of perceptrons corresponding to each core, thereby ensuring the prediction efficiency of each core.

[0138] In some optional embodiments, the method further includes: in the event of a failure of the primary branch predictor, continuing to execute the step of identifying the conditional jump instruction; or obtaining a prediction result of the primary branch predictor obtained in parallel with the predicted jump result, and obtaining a target jump result based on the prediction result of the primary branch predictor and the predicted jump result.

[0139] In this embodiment, the jump predictor is deployed in parallel with the main branch predictor, and can also serve as a backup prediction when the main branch predictor fails. When deployed in parallel, the prediction result of the main branch predictor and the predicted jump result are integrated to obtain the target jump result to improve the prediction accuracy.

[0140] For ease of understanding, combined Figure 3 As shown, Figure 3 This is a flowchart of instruction jump prediction in another embodiment. First, the instruction decoding unit decodes to obtain the instruction to be processed, and then detects whether the instruction to be processed is a conditional jump instruction. If so, the program counter is output to the feature extractor and the perceptron selection module. The feature extractor determines the structural behavior information corresponding to the conditional jump instruction based on the program counter, and then performs feature extraction on the structural behavior information to obtain structural features. The perceptron selection module determines the perceptron corresponding to the conditional jump instruction based on the program counter, inputs the structural features into the determined perceptron to obtain a jump prediction result, and obtains the actual jump result. If the two are inconsistent, the perceptron is updated.

[0141] It should be understood that, although the various steps in the flowcharts involved in the above embodiments are displayed in sequence according to the instructions of the arrows, these steps are not necessarily performed in sequence in the order indicated by the arrows. Unless clearly stated herein, the execution of these steps is not strictly limited in order, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with at least a portion of the steps or stages in other steps or other steps. It is understandable that the various steps in different embodiments can be freely combined as needed, and the various non-contradictory schemes formed by the combination all fall within the scope of protection of this application.

[0142] Based on the same inventive concept, embodiments of the present application further provide an instruction jump prediction device for implementing the aforementioned instruction jump prediction method. The implementation solution provided by this device is similar to the implementation solution described in the aforementioned method. Therefore, the specific limitations of one or more instruction jump prediction device embodiments provided below can be found in the limitations of the instruction jump prediction method above and will not be repeated here.

[0143] In an exemplary embodiment, Figure 4 As shown, an instruction jump prediction device is provided, comprising: an instruction acquisition module 401, a recognition module 402, a feature extraction module 403, a perceptron acquisition module 404 and a prediction module 405, wherein:

[0144] The instruction acquisition module 401 is used to acquire the decoded instruction to be processed;

[0145] Identification module 402, for obtaining structural behavior information corresponding to the conditional jump instruction when the instruction to be processed is identified as a conditional jump instruction;

[0146] Feature extraction module 403, used to extract features based on structural behavior information to obtain structural features;

[0147] a perceptron acquisition module 404 for acquiring a perceptron corresponding to a conditional jump instruction;

[0148] The prediction module 405 is used to input the structural features into the perceptron to perform jump prediction to obtain a predicted jump result.

[0149] In some optional embodiments, the structural behavior information includes at least one of the number of loops recorded by the loop counter, the proportion of zero values ​​in the current tensor corresponding to the instruction, the proportion of target instructions in the historical target number of instructions, and the instruction storage location; the structural features include at least one of the critical jump point features obtained based on the number of loops, the sparsity features obtained based on the proportion of zero values ​​in the current tensor corresponding to the instruction and the jump threshold, the instruction type features obtained based on the proportion of target instructions in the historical target number of instructions and the distribution threshold, and the hash features obtained by hashing the instruction storage location.

[0150] In some optional embodiments, the structural features include multi-level encoded features for characterizing jump probability; the above-mentioned prediction module 405 is specifically used to input the structural features into the perceptron to obtain the jump probability; and the jump probability is used as the predicted jump result.

[0151] In some optional embodiments, the prediction module 405 is specifically configured to obtain a weight vector and a bias vector of the perceptron; calculate a dot product result based on the structural features, the weight vector, and the bias vector; and obtain a predicted jump result based on the dot product result.

[0152] In some optional embodiments, the above-mentioned device also includes: a training module, which is used to correct the weight vector based on the dot product result and the structural feature when the predicted jump result is different from the actual jump result, so that the dot product result of the structural feature is close to the dot product corresponding to the actual jump result, and correct the bias vector based on the dot product result to adjust the classification boundary.

[0153] In some optional embodiments, the apparatus further comprises: a correction module configured to correct the perceptron if the perceptron satisfies a correction condition; wherein the correction condition comprises at least one of the following conditions: the number of times the predicted jump result of the perceptron differs from the actual jump result is greater than a threshold number; or, the conditional jump instruction corresponding to the perceptron is not recognized within a preset time period; or, the perceptron is an invalid perceptron; or, an overflow occurs when the weight vector and bias vector of the perceptron are updated.

[0154] In some optional embodiments, the sensor acquisition module 404 is specifically configured to calculate a hash value corresponding to a storage address of a conditional jump instruction; and query a sensor corresponding to the conditional jump instruction based on the hash value.

[0155] In some optional embodiments, the above-mentioned perceptron acquisition module 404 is specifically used to calculate the hash value corresponding to the storage address of the conditional jump instruction when the processor is a multi-core processor; perform an XOR operation on the hash value and the identifier of the core corresponding to the conditional jump instruction to obtain a perceptron index; and query the perceptron corresponding to the conditional jump instruction based on the perceptron index.

[0156] In some optional embodiments, the apparatus further includes: a management module configured to obtain the number of valid sensors corresponding to each core; and replace the sensors of the cores whose number of valid sensors is greater than the valid threshold with the sensors of the cores whose number of valid sensors is less than the valid threshold.

[0157] In some optional embodiments, the above-mentioned device also includes: a result determination module, which is used to continue executing the step of identifying conditional jump instructions in the event of a failure of the main branch predictor; or obtain the prediction result of the main branch predictor obtained in parallel with the predicted jump result, and obtain the target jump result based on the prediction result of the main branch predictor and the predicted jump result.

[0158] Each module in the aforementioned instruction jump prediction device can be implemented in whole or in part through software, hardware, or a combination thereof. Each module can be embedded in hardware within a processor in a computer device or independent of it. Alternatively, in a multi-core processor, a separate auxiliary core can execute the program corresponding to the instruction jump prediction method of the target core.

[0159] In an exemplary embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as shown in FIG. Figure 5 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, abbreviated as I / O) and a communication interface. The processor, memory and input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the computer device is used to store structural behavior information and sensors, etc. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, an instruction jump prediction method is implemented.

[0160] Those skilled in the art will understand that Figure 5 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0161] In one embodiment, a computer device is further provided, including a memory and a processor. The memory stores a computer program, and the processor implements the steps in the above method embodiments when executing the computer program.

[0162] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0163] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0164] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0165] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. In particular, any reference to memory, database, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The databases involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the various embodiments provided herein may be, but are not limited to, general-purpose processors, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), programmable logic devices (PLDs), quantum computing-based data processing logic devices, artificial intelligence (AI) processors, and the like.

[0166] The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0167] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. An instruction jump prediction method, characterized in that: The method comprises: Get the decoded instructions to be processed; When the instruction to be processed is identified as a conditional jump instruction, obtaining structural behavior information corresponding to the conditional jump instruction; Performing feature extraction based on the structural behavior information to obtain structural features; obtaining a perceptron corresponding to the conditional jump instruction; The structural features are input into the perceptron to perform jump prediction to obtain a predicted jump result.

2. The method according to claim 1, characterized in that The structural behavior information includes at least one of the number of loops recorded by the loop counter, the proportion of zero values ​​in the current tensor corresponding to the instruction, the proportion of target instructions in the historical target number of instructions, and the instruction storage location; the structural features include at least one of the critical jump point features obtained based on the number of loops, the sparsity features obtained based on the proportion of zero values ​​in the current tensor corresponding to the instruction and the jump threshold, the instruction type features obtained based on the proportion of target instructions in the historical target number of instructions and the distribution threshold, and the hash features obtained by hashing the instruction storage location.

3. The method according to claim 1 or 2, characterized in that The structural features include multi-level coded features for characterizing jump probability; Inputting the structural features into the perceptron to perform jump prediction to obtain a predicted jump result includes: Inputting the structural features into the perceptron to obtain a jump probability; The jump probability is used as the predicted jump result.

4. The method according to claim 1 or 2, characterized in that Inputting the structural features into the perceptron to perform jump prediction to obtain a predicted jump result includes: Get the weight vector and bias vector of the perceptron; Calculating a dot product result based on the structural feature, the weight vector, and the bias vector; A predicted jump result is obtained based on the dot product result.

5. The method according to claim 4, characterized in that The method further comprises: When the predicted jump result is different from the actual jump result, the weight vector is corrected based on the dot product result and the structural feature so that the dot product result of the structural feature is close to the dot product corresponding to the actual jump result, and the bias vector is corrected based on the dot product result to adjust the classification boundary.

6. The method according to claim 5, characterized in that The method further comprises: If the sensor satisfies a correction condition, correcting the sensor; The correction condition includes at least one of the following conditions: The number of times that the predicted jump result of the sensor differs from the actual jump result is greater than a number threshold; or, no conditional jump instruction corresponding to the sensor is identified within a preset time period; Alternatively, the sensor is an invalid sensor; Alternatively, overflow occurs when the weight vector and bias vector of the perceptron are updated.

7. The method according to claim 1 or 2, characterized in that The acquiring of a perceptron corresponding to the conditional jump instruction includes: Calculating a hash value corresponding to the storage address of the conditional jump instruction; A perceptron corresponding to the conditional jump instruction is queried based on the hash value.

8. The method according to claim 1 or 2, characterized in that The acquiring of a perceptron corresponding to the conditional jump instruction includes: In the case where the processor is a multi-core processor, calculating a hash value corresponding to the storage address of the conditional jump instruction; Performing an XOR operation on the hash value and the identifier of the core corresponding to the conditional jump instruction to obtain a perceptron index; A perceptron corresponding to the conditional jump instruction is searched based on the perceptron index.

9. The method according to claim 8, characterized in that The method further comprises: Get the number of effective perceptrons corresponding to each kernel; The perceptrons of the kernel whose number of effective perceptrons is smaller than the effective threshold are replaced with the perceptrons of the kernel whose number of effective perceptrons is larger than the effective threshold.

10. The method according to claim 1 or 2, characterized in that The method further comprises: In the event of a primary branch predictor failure, continuing with the step of identifying a conditional jump instruction; or A prediction result of the primary branch predictor obtained in parallel with the predicted jump result is obtained, and a target jump result is obtained based on the prediction result of the primary branch predictor and the predicted jump result.

11. An instruction branch prediction device, characterized in that: The device comprises: An instruction acquisition module is used to acquire the decoded instructions to be processed; an identification module, configured to obtain structural behavior information corresponding to a conditional jump instruction when the instruction to be processed is identified as a conditional jump instruction; A feature extraction module, configured to extract features based on the structural behavior information to obtain structural features; a perceptron acquisition module, configured to acquire a perceptron corresponding to the conditional jump instruction; The prediction module is used to input the structural features into the perceptron to perform jump prediction to obtain a predicted jump result.

12. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 10 are implemented.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 10 are implemented.

14. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 10 are implemented.

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