Graphics processor hardware acceleration device performance testing method and system

Abstract

The application provides a kind of graphics processor hardware acceleration equipment performance test method and system. Among them, the method first obtains device node information and collects encoding, decoding channel running index data, ensures data validity through format verification, if format error, record error and retry;Subsequently, detect whether relevant process exists, if missing, automatically restart, if existing, compare current frame number with last frame number to judge running state, if frame number is not increased, restart process and record error;In the whole process, through error counting control, when error accumulation exceeds threshold value, automatically terminate abnormal process, finally, the channel index collected is statistically analyzed and visual chart is generated, so as to realize the stability and performance of GPU hardware acceleration equipment Automatic test.The technical scheme provided by the application improves the automation degree and visualization level of virtualized GPU test, reduces the burden of manual operation and maintenance, and facilitates timely discovery and positioning of system abnormalities.

Description

Technical Field

[0001] The present invention relates to the technical field of hardware acceleration device performance testing, and in particular to a method and system for testing the performance of a graphics processor hardware acceleration device. Background Art

[0002] With the continuous improvement of graphics processing unit (GPU) hardware acceleration capabilities, its application in scenarios such as image processing and rendering is becoming increasingly widespread. The deployment and execution of GPU-accelerated tasks in virtual machine environments has also become commonplace. This is especially true during image processing-related testing, where the scheduling and management of GPU hardware resources are crucial. However, existing GPU-accelerated image processing testing methods primarily rely on traditional manual intervention or script control to complete testing tasks, resulting in low automation, inefficient data feedback, and cumbersome operations and maintenance.

[0003] The current common testing process usually includes: obtaining relevant information about tasks running on virtual machine nodes through the host machine's hardware query tool, and compiling and generating test reports; during the test process, mainly relying on manual inspection of printed information to identify abnormal nodes, and then logging into the target virtual machine to view logs and manually perform restart operations, or remotely executing query and restart commands through scripts. This type of method lacks the ability to automatically manage the entire life cycle of test tasks, is prone to response delays, missed exceptions, and other problems, and is inefficient. In addition, for different types of hardware status indicators, it is often necessary to execute different commands or manually extract the required information from large amounts of data. There is a lack of a unified, easy-to-use and intuitive way to view performance indicators, making it difficult to meet the debugging and performance evaluation needs in complex scenarios.

[0004] In order to improve testing efficiency and intelligence, some existing technologies have attempted to introduce automated testing methods.

[0005] For example, Chinese patent CN202311604763.2 "A new Android automated testing method and system based on wireless drive" proposes to adopt a new Android automated testing method based on wireless drive, establish local communication with the Android system service through the monitoring application in the Android test host, receive operation commands from the PC and automatically enable the relevant permissions required for the test, realize wireless connection between the Android test host and the PC, automate control identification and testing, and perform automated testing on multiple devices at the same time, thereby improving the efficiency of automated testing. The patented technical solution also has a clear architectural layered design, in which multiple test machines and the PC can be approximately regarded as having two layers through wireless connection, but it does not involve the life cycle processing of specific test items and data visualization during the test process; Chinese patent CN202510108322.6 "A method, device, equipment and medium for automated testing" creates configuration files according to each test item of the server, so that customers can test the system automatically. The client can test and generate test files according to the test conditions of each test item in the configuration file, determine the test sequence and execute the test, thereby improving the test flexibility and test efficiency. The patented technical solution generates a test report in sequence according to the test items, but there is no system indicator chart demonstration during operation. It also does not mention exception handling of test items and data processing of test reports; Chinese patent CN202010986837.3 "A virtual machine stress / performance testing method and system" creates virtual machines containing test programs and agent programs in batches on the host machine. The daemon waits for client requests, executes and stops test tasks, and realizes automated testing of virtual machine stress / performance. The test results are sent to the client that issues the test instructions through the daemon in the host machine, realizing the reception and feedback of test tasks, and improving the batch processing capability of virtual machine performance testing. However, the test report generated by the patented technical solution also fails to display the various indicators of the system during operation in real time, nor does it mention the visualization of data.

[0006] It can be seen from this that the above-mentioned existing technologies do not propose a special solution for the software lifecycle management of recoverable exceptions in GPU hardware-accelerated image processing scenarios: when the test software crashes, deadlocks, and other exceptions occur in the virtual machine, the existing methods can often only remotely execute scripts or manually shut down and restart, and lack an automated self-healing mechanism; at the same time, there is also a lack of real-time and intuitive display of the running status of the GPU hardware after virtualization. Common methods usually only output a static test report after the test is completed, which cannot meet the needs of quickly locating problems and dynamically evaluating performance.

[0007] Therefore, there is an urgent need to provide a testing solution that can realize automatic management of the entire life cycle of tasks, automatic response processing of exceptions, and can intuitively display multi-dimensional hardware performance indicators in a unified interface to make up for the shortcomings of existing technologies. Summary of the Invention

[0008] In view of this, the present invention provides a method and system for testing the performance of a graphics processor hardware acceleration device, so as to solve the above-mentioned technical problems in the prior art.

[0009] According to one aspect of the present invention, a method for testing the performance of a graphics processor hardware acceleration device is provided, wherein the method comprises:

[0010] Hardware acceleration device node initialization: obtain the node information of the hardware acceleration device;

[0011] Obtaining encoding and decoding channel information: Obtain encoding channel information and decoding channel information, parse encoding channel information and decoding channel information, and obtain channel indicator data;

[0012] Information format judgment: organize channel indicator data into a preset format and judge it. If the format is correct, report the channel indicator data and perform process detection. If the format is incorrect, increase the error flag value count and return to execute codec channel information acquisition;

[0013] Process detection: Check whether the corresponding encoding or decoding process exists. If it does, perform encoding and decoding frame number comparison. If it does not exist, restart the process and return to execute encoding and decoding channel information acquisition;

[0014] Comparison of codec frame numbers: Compare the current frame number of encoding or decoding with the previous frame number. If the frame number increases after comparison, return to execute codec channel information acquisition. If the frame number stops increasing after comparison, terminate and restart the process, increase the error flag value count, and then return to execute codec channel information acquisition.

[0015] Data collection and analysis: collect and analyze reported channel indicator data and generate visual charts;

[0016] When the error flag value count exceeds a preset threshold, the process is automatically terminated and the codec channel information acquisition is returned to be executed.

[0017] According to another aspect of the present invention, a graphics processor hardware acceleration device performance testing system is provided, wherein the system includes:

[0018] A hardware acceleration device node initialization module is configured to obtain node information of the hardware acceleration device;

[0019] The encoding and decoding channel information acquisition module is configured to obtain encoding channel information and decoding channel information, parse the encoding channel information and decoding channel information, and obtain channel indicator data;

[0020] The information format judgment module is configured to organize the channel indicator data into a preset format and judge it. If the format is correct, the channel indicator data is reported and the process detection is performed. If the format is incorrect, the error flag value count is increased and the codec channel information acquisition module is returned to execute;

[0021] The process detection module is configured to detect whether the corresponding encoding or decoding process exists. If so, it performs a codec frame number comparison. If not, it restarts the process and returns to the codec channel information acquisition module.

[0022] The codec frame number comparison module is configured to compare the current frame number of encoding or decoding with the previous frame number. If the frame number is found to have increased after comparison, the module returns to execute the codec channel information acquisition module. If the frame number is found to have stopped increasing after comparison, the module terminates and restarts the process, increases the error flag value count, and then returns to execute the codec channel information acquisition module.

[0023] A data collection and analysis module is configured to collect and analyze reported channel indicator data and generate visual charts;

[0024] When the error flag value count exceeds a preset threshold, the process is automatically terminated and the codec channel information acquisition module is returned to execute.

[0025] According to yet another aspect of the present invention, an electronic device is provided, comprising: one or more processors and a memory, wherein the memory is used to store executable instructions; and the one or more processors are configured to implement the above method via the executable instructions.

[0026] According to yet another aspect of the present invention, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the processor executes the above method.

[0027] It can be seen from the above technical solutions that the technical solution provided by the present invention has at least the following advantages:

[0028] 1. Fully automate the testing process and reduce manual intervention costs: By comprehensively monitoring and analyzing the GPU's operating status and the execution of codecs / rendering programs, intelligent lifecycle management of hardware call programs is achieved, effectively improving the stability and continuity of GPU image processing performance testing. Even if the test cycle may last for several weeks, as long as the hardware does not experience unrecoverable anomalies, video codec tasks can continue to run stably for a long time without manual intervention, significantly improving test efficiency and reliability while significantly reducing operation and maintenance costs and the risk of human interference.

[0029] 2. Enhanced visualization and controllability of performance monitoring: Relying on the data collection and display capabilities of the containerized service cluster monitoring tool, by reporting preliminarily processed system operation status information and generating a dynamically updated performance dashboard, the specific performance indicators of all virtual hardware acceleration nodes can be intuitively displayed, enabling real-time visual monitoring of all virtual hardware acceleration nodes, thereby fully understanding the system operation status and improving the efficiency of anomaly detection and resource scheduling capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are used to provide a further understanding of the technical solution of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the technical solution of the present invention, but do not constitute a limitation to the technical solution of the present invention.

[0031] Figure 1 A flow chart showing a method provided by an exemplary embodiment of the present invention is shown;

[0032] Figure 2 shows a structural diagram of a system provided by an exemplary embodiment of the present invention;

[0033] Figure 3 shows a structural diagram of a system provided by another exemplary embodiment of the present invention;

[0034] Figure 4 shows an overall architecture diagram of a system provided by an exemplary embodiment of the present invention;

[0035] Figure 5 A structural block diagram of an electronic device provided by an exemplary embodiment of the present invention is shown. DETAILED DESCRIPTION

[0036] Various exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is not intended to limit the invention, its application, or use. The present invention can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to make this disclosure thorough and complete and to fully convey the scope of the invention to those skilled in the art.

[0037] Unless explicitly stated, if the number of an element is not specifically limited, the element may be one or more. The term "plurality" means two or more, the term "based on" should be interpreted as "based at least in part on," and the terms "and / or" and "at least one of..." encompass any and all possible combinations of the listed items. Furthermore, terms such as "first," "second," and the like are for descriptive purposes only and do not indicate or imply relative importance or implicitly specify the number of the technical features being referred to.

[0038] Please refer to Figure 1 , which shows a flow chart of a method provided by an exemplary embodiment of the present invention.

[0039] According to one aspect of the present invention, a method for testing the performance of a graphics processor hardware acceleration device is provided. The method can not only manage the life cycle of the test software based on the hardware operation information and the test software operation status, so that the test software can continue to execute as long as the hardware does not have an unrecoverable exception; it can also aggregate and process the queried hardware performance data into a chart and display it to the user in real time, so that the user can view the performance indicator data of GPU encoding, decoding and rendering tasks in real time and perform task operation management.

[0040] Specifically, the method provided by the present invention includes:

[0041] Hardware acceleration device node initialization: obtain the node information of the hardware acceleration device;

[0042] Obtaining encoding and decoding channel information: Obtain encoding channel information and decoding channel information, parse encoding channel information and decoding channel information, and obtain channel indicator data;

[0043] Information format judgment: organize channel indicator data into a preset format and judge it. If the format is correct, report the channel indicator data and perform process detection. If the format is incorrect, increase the error flag value count and return to execute codec channel information acquisition;

[0044] Process detection: Check whether the corresponding encoding or decoding process exists. If it does, perform encoding and decoding frame number comparison. If it does not exist, restart the process and return to execute encoding and decoding channel information acquisition;

[0045] Comparison of codec frame numbers: Compare the current frame number of encoding or decoding with the previous frame number. If the frame number increases after comparison, return to execute codec channel information acquisition. If the frame number stops increasing after comparison, terminate and restart the process, increase the error flag value count, and then return to execute codec channel information acquisition.

[0046] Data collection and analysis: Collect and analyze reported channel indicator data and generate visual charts; when the error flag value count exceeds the preset threshold, the process is automatically terminated and returns to execute codec channel information acquisition.

[0047] In an exemplary embodiment, the preset threshold is 36, and the error flag value count is cleared after the restart process.

[0048] In one exemplary embodiment, if the acquisition of the hardware acceleration device's node information fails, a prompt message is printed to inform the user that the hardware or driver is not correctly installed. If the channel indicator data does not exist or is formatted incorrectly, an error log is printed, and the missing data is reported with the default value.

[0049] In an exemplary embodiment, the channel indicator data includes the board serial number, physical node number, virtual node number, current channel number, codec format, codec frame rate, number of frames entering the encoder or decoder, number of frames exiting the encoder or decoder, video width and height, and pixel format.

[0050] In one exemplary embodiment, the visualization charts provided by the present invention are presented as a visualization dashboard within a containerized service cluster, which can be dynamically updated via a webpage and accessed from multiple terminals. However, the present invention is not limited to this. For example, the visualization dashboard within the containerized service cluster can also be replaced with other existing data visualization tools (e.g., Grafana, Apache Superset, FineVis), as long as they can meet the needs of charting the collected data according to specific requirements to facilitate user viewing of system hardware performance.

[0051] The following section of this article will describe the execution process of the method provided by the present invention in more detail in stages.

[0052] 1. Device node initialization phase

[0053] After the acceleration device is started, the node information of the hardware acceleration device is read from the driver. If the node information of the hardware acceleration device is not correctly obtained, a prompt message is printed to prompt the user that the hardware or driver is not installed correctly.

[0054] 2. Codec channel detection and analysis stage

[0055] Call external commands to obtain encoding channel information and decoding channel information, and parse out the board serial number, physical node number, virtual node number, current channel number, video codec format (such as H.264 / H.265 / AV1, etc.), encoding / decoding frame rate, number of frames entering the encoder / decoder, number of frames exiting the encoder / decoder, encoding / decoding, video width and height, pixel format and other information.

[0056] If the information parsing is successful, the information parsing module will extract data such as the board number, physical node number, virtual node number, channel number, codec format, frame rate, running task number, resolution and pixel format from the encoding channel information and decoding channel information, organize the parsed data into a preset format, and then report this data to the data collection module of the containerized service cluster through the network.

[0057] If the data format is incorrect or there is no relevant information after information parsing, an error log will be printed and missing values ​​will be reported with the default value.

[0058] 3. Encoding / decoding process management stage

[0059] Use Python's psutil API to detect whether a process name corresponding to encoding / decoding exists.

[0060] If there is no process name corresponding to the encoding / decoding process, the Windows subprocess interface is used to call "taskkill / F / T / PID" to restart the corresponding process, and then the encoding / decoding frame count is checked to see if it has increased. If the encoding / decoding frame count has not increased, the subprocess interface is called to forcefully terminate the process before restarting it, and the error flag value count is incremented. When the error flag value accumulates to 36, the restart step is executed. This method reduces the possibility of process abnormalities caused by the accumulation of small errors. At this point, the entire guard process is completed, and the codec channel detection and parsing phase is returned to re-acquire the encoding and decoding channel information and report it.

[0061] 4. Performance data display stage

[0062] When there is reported data, the time series data storage and management module in the containerized service cluster will collect and analyze the reported data. Then, based on the user's specific needs, the visualization module can plot information such as frame rate, resolution, encoding / decoding format, and running nodes into charts and display them on the web dashboard for users to view.

[0063] Please refer to Figure 2 , which shows a structural diagram of a system provided by an exemplary embodiment of the present invention.

[0064] According to another aspect of the present invention, a graphics processor hardware acceleration device performance testing system is provided. The main functions of the system include three parts: video encoding and decoding task lifecycle management function, video encoding and decoding performance data acquisition and upload function, and video encoding and decoding performance data collection, analysis and display function.

[0065] Specifically, the system includes the following modules:

[0066] A hardware acceleration device node initialization module is configured to obtain node information of the hardware acceleration device;

[0067] The encoding and decoding channel information acquisition module is configured to obtain encoding channel information and decoding channel information, parse the encoding channel information and decoding channel information, and obtain channel indicator data;

[0068] The information format judgment module is configured to organize the channel indicator data into a preset format and judge it. If the format is correct, the channel indicator data is reported and the process detection is performed. If the format is incorrect, the error flag value count is increased and the codec channel information acquisition module is returned to execute;

[0069] The process detection module is configured to detect whether the corresponding encoding or decoding process exists. If so, it performs a codec frame number comparison. If not, it restarts the process and returns to the codec channel information acquisition module.

[0070] The codec frame number comparison module is configured to compare the current frame number of encoding or decoding with the previous frame number. If the frame number is found to have increased after comparison, the module returns to execute the codec channel information acquisition module. If the frame number is found to have stopped increasing after comparison, the module terminates and restarts the process, increases the error flag value count, and then returns to execute the codec channel information acquisition module.

[0071] A data collection and analysis module is configured to collect and analyze reported channel indicator data and generate visual charts;

[0072] When the error flag value count exceeds a preset threshold, the process is automatically terminated and the codec channel information acquisition module is returned to execute.

[0073] It should be understood that Figure 2 The system shown in the figure may correspond to the method described above in this specification. Thus, the operations, features, and advantages described above for the method are also applicable to the system provided by the present invention and the modules included therein, and the operations, features, and advantages described above for the system and the modules included therein are also applicable to the method provided by the present invention. For the sake of brevity, certain operations, features, and advantages will not be described in detail.

[0074] Furthermore, those skilled in the art will appreciate that, although specific functions have been discussed above with reference to specific modules, it should be noted that the functions of each module in the technical solution of the present invention may also be implemented by dividing it into multiple modules, and / or at least some functions of multiple modules may be combined into a single module for implementation. The manner in which a specific module in the technical solution of the present invention performs an action includes the specific module itself performing the action, or being called or otherwise accessed by the specific module to perform the action (or performing the action in conjunction with the specific module). Therefore, the specific module that performs the action may include the specific module itself that performs the action and / or another module that is called or otherwise accessed by the specific module to perform the action.

[0075] For example, in an exemplary embodiment, the main functions of the system in the technical solution of the present invention can also be implemented by dividing into multiple modules. Figure 3 , which shows a structural diagram of a system provided by another exemplary embodiment of the present invention. Detailed description is as follows.

[0076] 1. Lifecycle management function of video encoding and decoding process

[0077] This function consists of a process status monitoring module, an encoding and decoding frame count status determination module, and a process protection and exception handling module, capable of independently managing the lifecycle of the encoding and decoding processes. All three modules include exception handling and logging capabilities, enabling monitoring and safeguarding of encoding and decoding tasks. As long as there are no unrecoverable hardware exceptions, encoding and decoding tasks can continue to execute.

[0078] (1) Process status monitoring module

[0079] The process status monitoring module calls an external command to execute the hardware query tool and parses the hardware card's serial number, device number, physical node number, virtual node number, video codec channel, video codec node, and other information. If the above information cannot be obtained, a prompt will be printed indicating that the acceleration hardware or driver is not properly installed. If some information does not meet the preset range, an error prompt will be reported.

[0080] (2) Codec frame number status judgment module

[0081] The codec frame count status determination module first calls external commands to obtain encoding and decoding channel information. It then parses this information to determine data such as the board serial number, physical node number, virtual node number, current codec channel number, encoding format, encoding / decoding frame rate, number of frames entering the encoder / decoder, number of frames exiting the encoder / decoder, encoding / decoding, video width and height, and pixel format. It then checks this data for anomalies, reporting an error if any. If no anomalies are found, it further determines whether the current frame count has increased reasonably compared to the previous query. If the frame count stops increasing or other anomalies occur, the currently running task is restarted.

[0082] (3) Process protection and exception handling module

[0083] The process protection and exception handling module first checks the system interface to see if the corresponding decoding and encoding processes exist. If no corresponding processes exist, the current task process is directly restarted. If a corresponding process exists, it further checks to determine whether the frame rate is normal. If the frame rate is abnormal, the current task process is restarted. If the frame rate is normal, it checks the error count. If the error count exceeds 36, the current task process is restarted.

[0084] The lifecycle management function of the video encoding and decoding process combines process status detection and frame count analysis to make comprehensive judgments. It also checks the existence of the process identifier (PID) and frame count changes to avoid false positives of zombie processes, thus implementing the core process management function of the video encoding and decoding daemon.

[0085] 2. Video encoding and decoding performance data acquisition and upload function

[0086] This function consists of a PCIe device information acquisition module, an encoding / decoding channel indicator processing module, and a monitoring data reporting pipeline module.

[0087] (1) PCIe device information acquisition module

[0088] The PCIe device information acquisition module obtains hardware configuration information, such as the board serial number, physical node number, and virtual node number, by calling the hardware acceleration device query module, and organizes this information into a specific data structure to be uploaded to the timing data storage and management module through the API of the custom indicator collection module.

[0089] (2) Index processing module of encoding / decoding channel

[0090] The indicator processing module of the encoding / decoding channel is used to organize the information such as the board serial number, physical node number, virtual node number, current channel number, encoding format, encoding / decoding frame rate, number of frames entering the encoder / decoder, number of frames exiting the encoder / decoder, encoding / decoding, video width and height, pixel format, etc., which are parsed by the encoding / decoding frame number status judgment module, into the data structure required by the time series data storage and management module in the containerized service.

[0091] (3) Monitoring data reporting pipeline module

[0092] The monitoring data reporting pipeline module regularly uploads the data organized in the previous step to the time series data storage and management module of the containerized service cluster through a custom API interface. It supports the construction of multi-dimensional label indicators and encrypted data upload, and can perform the next step of mapping and display.

[0093] If multiple data channels exist, they are merged and their structures aligned. The monitoring data reporting pipeline utilizes multi-process reporting, automatically populates default values ​​for instances, and automatically captures and logs exceptions. The monitoring data reporting module utilizes the Python API of the Data Storage and Management module. This functionality implements a complete data pipeline from the hardware layer to the monitoring layer, enabling real-time monitoring and reporting of the hardware and software operating status and performance data for multiple video codecs.

[0094] 3. Video encoding and decoding performance data collection and display function

[0095] The container-based service set integrated with container index collection, host index collection, custom index collection, time series data storage and management, data visualization and alarm notification modules, and the like, integrates functions such as a time series database, a push acceptor of transient tasks and batch tasks, alarm management, visualized indexes, a host index collector, a reverse proxy and a basic authentication provider, can collect performance data information such as frame rate, resolution, encoding / decoding format, CPU utilization and memory in real time, and display the indexes to users through an intuitive and convenient visualized dashboard.

[0096] Please refer to Figure 4 which shows the overall architecture diagram of the system provided by the exemplary embodiment of the present application.

[0097] The architecture of the system provided by the present application is divided into three layers from top to bottom, namely a virtualized resource layer, a containerized monitoring layer and a user interface layer. The following sections will describe the architecture of the system in layers.

[0098] 1. Virtualized resource layer

[0099] The virtualized resource layer is composed of a cloud computer cluster (a virtual machine running a video encoding / video decoding playback task) built by a server configured with hardware resources.

[0100] The cloud computer cluster realizes hardware resource isolation based on central processing unit (CPU) virtualization, single root I / O virtualization (SR-IOV) and input / output memory management unit (IOMMU) technology, and each virtual machine is independently allocated CPU, GPU and storage resources. The GPU hardware provides hardware acceleration computing power for encoding and decoding.

[0101] Four GPU hardware acceleration cards are inserted into the peripheral component interconnect express (PCIe) slots of a medium / large server, each hardware acceleration card can be divided into four independent running nodes, and each independent running node can be virtualized into seven virtual acceleration nodes, so a total of 112 hardware acceleration nodes can be provided.

[0102] The server runs the Libvirt daemon service, creating and running 112 Windows virtual machines. Each VM is configured with four CPU cores, 4GB of RAM, 128GB of storage, and one hardware acceleration node. The hardware acceleration tasks running on the VMs are divided into two categories: video encoding and decoding. Details are described below.

[0103] (1) Hardware-accelerated video encoding: Provide users with a desktop that can be accessed remotely. That is, through a video encoding program, the desktop image of the virtual machine is compressed into a video stream with a lower bit rate, and then quickly transmitted to the remote desktop software on the user side through the network, achieving real-time and clear remote desktop display and control effects on the remote desktop client software.

[0104] (2) Hardware-accelerated video decoding: This provides users with video playback services. This involves configuring video players or browsers, which can play videos, to hardware acceleration mode on a Windows virtual machine. Videos can then be played using this type of video playback software (supporting encoding formats such as H264 / HEVC / AV1). The computing resources used for decoding and rendering are provided by the GPU hardware acceleration device, which consumes almost no CPU computing resources, thereby ensuring the efficient operation of the virtual machine in image data encoding, decoding, and rendering tasks.

[0105] 2. Containerized Monitoring Layer

[0106] The services provided by the containerized monitoring layer include six modules: container indicator collection module, host indicator collection module, custom indicator collection module, time series data storage and management module, data visualization module, and alarm notification module.

[0107] The container indicator collection module is a resource monitoring tool that is dedicated to collecting container runtime indicators; the host indicator collection module is a host-layer indicator collector that can monitor the status of physical / virtual machine hardware and operating system (Operating System, OS); the custom indicator collection module can upload self-defined indicators through the API, such as frame rate, frame number, etc.; the time series data storage and management module can actively pull the data collected by the container indicator collection module, host indicator collection module, and custom indicator collection module, and store it in the time series database, which can support real-time data query, filtering and calculation; the data visualization module can intuitively display the indicator data stored in the time series data storage and management module in charts; the alarm notification module processes alarm notifications in the time series database and routes and distributes them.

[0108] Dynamic IP address allocation (DHCP) technology and distributed switching strategies are used between the cloud computer clusters of the containerized monitoring layer and the virtualized resource layer to optimize traffic paths, achieve secure communication between virtual machines and host machines in the same local area network and the containerized service cluster, and provide users with a web display interface.

[0109] 3. User interface layer

[0110] Users can use their own devices to access the client of the containerized service cluster through a browser. The client supports remote connection from multiple terminals (PC / mobile devices) and uses an intuitive and easy-to-use interface to display encoding and decoding operation indicators such as frame rate, CPU utilization, video resolution, video codec format and running node.

[0111] Virtualized resources are hosted on servers equipped with GPU hardware accelerators. Leveraging virtualization and GPU hardware acceleration, they provide hardware acceleration for video encoding, decoding, and playback. Hardware performance data is obtained using existing tools that directly print hardware operating status. After analysis, the performance information generated by these tools is formatted for upload. Performance data is reported using the Python API of the custom metric collection module, which supports multi-dimensional tag-based metric construction and encrypted data upload. The time series data storage and management module collects, manages, and analyzes performance metrics for encoding and decoding. The alarm notification module provides alerts for values ​​outside preset ranges. The visualization module renders visual performance data charts for users. Network devices such as wireless routers and switches provide network services between the various layers, connecting the servers equipped with virtualized resources with devices at the user interface layer, such as mobile phones, tablets, laptops, and desktop computers. Users at the user interface layer can access the containerized service cluster client from their devices and, by configuring the required display options, access a convenient graphical dashboard to view hardware performance metrics, understand hardware operating status, and assess test results.

[0112] In an exemplary embodiment, four GPU hardware acceleration cards are inserted into the PCIe slots of a medium or large server. Each hardware acceleration card can be divided into four physical operating nodes, and each physical operating node can be virtualized into seven virtual acceleration nodes, providing a total of 112 hardware acceleration nodes.

[0113] The server runs the Libvirt daemon service, and a script is used to batch-create and run 112 Windows virtual machines. Each VM is configured with four CPU cores, 4GB of RAM, one virtual acceleration node, and 128GB of storage. The hardware acceleration tasks running on these VMs fall into two categories: video encoding (on the remote desktop server) and decoding and playback (on PotPlayer video playback). Details are as follows.

[0114] 1. The specific business of hardware-accelerated encoding is to provide users with a remotely accessible desktop: after obtaining the desktop image of a virtual machine, the image is compressed into a video stream with a smaller bit rate by a video encoding program, which can be quickly transmitted to the user's end through the network. The remote desktop software on the remote desktop software can achieve clear remote desktop display and real-time control effect. Since the bandwidth and CPU occupation of control operations (mouse movement, click and keyboard input) are much smaller than the resources occupied by video encoding and decoding, the CPU resources and network occupied by control operations are not considered.

[0115] 2. The specific business of hardware-accelerated decoding is to provide video playback services for users: a video player or browser-based video playback software can be configured on a Windows virtual machine to run in hardware acceleration mode, and then the video playback software can call hardware resources to play videos, supporting H264 / HEVC / AV1 and other encoding formats. The computing resources used for playback are provided by GPU hardware acceleration devices, which almost do not occupy CPU computing resources, thereby ensuring the efficient operation of the virtual machine on image data compression and decompression tasks.

[0116] By deploying the life cycle management program of the encoding and decoding task, the hardware video encoding and playback program can be automatically controlled. The life cycle management function regularly monitors and queries the state of the encoding, decoding and playback program and the hardware execution state, and judges whether each program and hardware is running normally by combining process state detection and hardware execution state, to decide whether to restart or other operations for a certain program. This function realizes the core management function of the daemon program of hardware video encoding and decoding and playback, and as long as the hardware has no unrecoverable exception, the encoding and decoding task can be executed all the time.

[0117] The containerized service set calls existing modules: the container metric collection module monitors container-related resources and is dedicated to collecting container runtime metrics. The host metric collection module collects performance metrics at the host layer, monitoring the physical machine / virtual machine hardware and OS state. The custom metric collection module can upload its own defined metrics, such as frame rate, frame count, etc. The time series data storage and management module actively pulls the data collected by the aforementioned three collection modules and stores it in the time series database. The data stored in the time series database supports real-time data query, filtering and calculation. The data visualization module can visually display the metric data stored by the time series data storage and management module in charts. The alarm notification module processes alarm notifications in the time series database and routes and distributes them, which can be sent in the form of email or SMS.

[0118] When there is data reporting, the web page can view the frame rate, resolution, encoding / decoding format and running node, etc. Other information such as system load, CPU utilization, running memory, etc. can also be displayed by changing the configuration.

[0119] In addition to the above technical solutions, the present invention also provides an electronic device, which includes one or more processors and a memory for storing executable instructions. The one or more processors are configured to implement the above method via executable instructions. The present invention also provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by the processor, the processor executes the above method. In the following part of this specification, Figure 5 To describe illustrative examples of the aforementioned electronic device and computer-readable storage medium.

[0120] Figure 5 An example configuration of an electronic device 300 that can be used to implement the methods described herein is shown. The technical solutions of the present invention can also be implemented in whole or in part by electronic device 300 or similar devices / systems. Electronic device 300 can be a variety of different types of devices. Examples of electronic devices 300 include, but are not limited to, desktop computers, server computers, laptop or netbook computers, mobile devices, wearable devices, entertainment devices, televisions or other display devices, and automotive computers.

[0121] The electronic device 300 may include at least one processor 302, memory 304, communication interface(s) 309, a display device 301, other input / output (I / O) devices 310, and one or more mass storage devices 303, all capable of communicating with each other via a system bus 311 or other appropriate connections.

[0122] The processor 302 may be a single or multiple processing units, all of which may include a single or multiple computing units or multiple cores. The processor 302 may be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, state machines, logic circuits, and / or any device that manipulates signals based on operational instructions. Among other capabilities, the processor 302 may be configured to retrieve and execute computer-readable instructions stored in the memory 304, mass storage device 303, or other computer-readable media, such as program code of an operating system 305, application programs 306, or other programs 307.

[0123] Memory 304 and mass storage device 303 are examples of computer-readable storage media for storing instructions that are executed by processor 302 to implement the various functions described above. For example, memory 304 may generally include both volatile memory and non-volatile memory. In addition, mass storage device 303 may generally include a hard drive, a solid-state drive, removable media, including external and removable drives, memory cards, flash memory, floppy disks, optical disks, storage arrays, network attached storage, storage area networks, etc. Memory 304 and mass storage device 303 may be collectively referred to as memory or computer-readable storage media in the present invention and may be non-transitory media capable of storing computer-readable, processor-executable program instructions as computer program code that may be executed by processor 302 as a specific machine configured to implement the operations and functions described in the examples of the present invention.

[0124] A plurality of programs may be stored on the mass storage device 303. These programs include an operating system 305, one or more application programs 306, other programs 307, and program data 308, and they may be loaded into the memory 304 for execution. Examples of such applications or program modules may include, for example, computer program logic (e.g., computer program code or instructions) for implementing the following components / functions: the methods provided by the present invention (including any suitable steps of the methods) and / or other embodiments described herein.

[0125] Although Figure 5 Although shown as being stored in the memory 304 of the electronic device 300, the modular operating system 305, application programs 306, other programs 307, and program data 308, or portions thereof, may be implemented using any form of computer-readable media accessible by the electronic device 300. Here, a computer-readable medium may be any available computer-readable storage medium or communication medium accessible to a computer. Communication media include media such as communication signals for transmitting computer-readable instructions, data structures, program modules, or other data from one system to another. Communication media may include guided transmission media as well as wireless media capable of propagating energy waves. Computer-readable instructions, data structures, program modules, or other data may be embodied as, for example, modulated data signals in a wireless medium.

[0126] For example, computer-readable storage media can include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. For example, computer-readable storage media includes, but is not limited to, volatile memory, such as random access memory (RAM), DRAM, SRAM; and non-volatile memory, such as flash memory, various read-only memories (ROM, PROM, EPROM, EEPROM), magnetic and ferromagnetic / ferroelectric memories (MRAM, FeRAM), and magnetic and optical storage devices (hard disk, tape, CD, DVD); or other known media or developed in the future that is capable of storing computer readable information / data for use with a computer system.

[0127] One or more communication interfaces 309 are used to exchange data with other devices over, for example, a network, a direct connection, etc. This communication interface can be one or more of: any type of network interface, wired or wireless (e.g., WLAN) interface, Wi-MAX interface, Ethernet interface, USB interface, cellular network interface, Bluetooth interface, NFC interface, etc. The communication interface 309 can facilitate communication within a variety of network and protocol types, including wired and wireless networks, the Internet, etc. The communication interface 309 can also provide communication with external storage devices (not shown in the figures), such as storage arrays, network attached storage, storage area networks, etc.

[0128] In some examples, a display device 301, e.g., a monitor, can be included for displaying information and images to a user. Other I / O devices 310 can be devices that receive user input and provide output to a user, and can include touch / gesture input devices, cameras, keyboards, remote controls, mice, audio input / output devices, etc.

[0129] The technical solutions described in the present application can be supported by these various configurations of the electronic device 300, and are not limited to the specific examples of the technical solutions described in the present application. The foregoing description and the accompanying drawings of the present application are not limiting, and it is obvious to those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, and the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the scope of the present application claimed is defined by the claims, not the above description, and all variations falling within the meaning and scope of the equivalent elements of the claims are included in the scope of protection of the present application.

Claims

1. A method for testing the performance of a graphics processor hardware acceleration device, characterized in that: The method comprises: Hardware acceleration device node initialization: obtain the node information of the hardware acceleration device; Obtaining encoding and decoding channel information: Obtaining encoding channel information and decoding channel information, parsing the encoding channel information and decoding channel information, and obtaining channel indicator data; Information format judgment: organize the channel indicator data into a preset format and judge it. If the format is correct, report the channel indicator data and perform process detection. If the format is incorrect, increase the error flag value count and return to execute codec channel information acquisition; Process detection: Check whether the corresponding encoding or decoding process exists. If it does, perform encoding and decoding frame number comparison. If it does not exist, restart the process and return to execute encoding and decoding channel information acquisition; Comparison of codec frame numbers: Compare the current frame number of encoding or decoding with the previous frame number. If the frame number increases after comparison, return to execute codec channel information acquisition. If the frame number stops increasing after comparison, terminate and restart the process, increase the error flag value count, and then return to execute codec channel information acquisition. Data collection and analysis: collect and analyze the reported channel indicator data and generate visual charts; When the error flag value count exceeds a preset threshold, the process is automatically terminated and the codec channel information acquisition is returned to be executed.

2. The method according to claim 1, characterized in that The method further comprises: If obtaining the node information of the hardware acceleration device fails, a prompt message is printed to inform the user that the hardware or driver is not installed correctly.

3. The method according to claim 1, characterized in that The method further comprises: If the channel indicator data does not exist or is in an incorrect format, an error log is printed and the missing data is reported with the default value.

4. The method according to claim 1, wherein The visual chart is dynamically updated through the web page and supports multi-terminal access.

5. The method according to claim 1, wherein The channel indicator data includes the board serial number, physical node number, virtual node number, current channel number, codec format, codec frame rate, number of frames entering the encoder or decoder, number of frames exiting the encoder or decoder, video width and height, and pixel format.

6. The method according to claim 1, characterized in that The preset threshold is 36, and the error flag value count is cleared after the restart process.

7. The method according to claim 1, characterized in that If multiple channel indicator data exist, the multiple channel indicator data are merged and the data structures are aligned.

8. A graphics processor hardware acceleration device performance testing system, characterized in that: The system comprises: A hardware acceleration device node initialization module is configured to obtain node information of the hardware acceleration device; The encoding and decoding channel information acquisition module is configured to acquire encoding channel information and decoding channel information, parse the encoding channel information and decoding channel information, and obtain channel indicator data; An information format determination module is configured to organize the channel indicator data into a preset format and determine whether the format is correct. If the format is correct, the channel indicator data is reported and a process check is performed. If the format is incorrect, an error flag value count is increased and the module returns to execute the codec channel information acquisition module. The process detection module is configured to detect whether the corresponding encoding or decoding process exists. If so, it performs a codec frame number comparison. If not, it restarts the process and returns to the codec channel information acquisition module. The codec frame number comparison module is configured to compare the current frame number of encoding or decoding with the previous frame number. If the frame number is found to have increased after comparison, the module returns to execute the codec channel information acquisition module. If the frame number is found to have stopped increasing after comparison, the module terminates and restarts the process, increases the error flag value count, and then returns to execute the codec channel information acquisition module. A data collection and analysis module is configured to collect and analyze the reported channel indicator data and generate a visual chart; When the error flag value count exceeds a preset threshold, the process is automatically terminated and the codec channel information acquisition module is returned to execute.

9. An electronic device, characterized in that: The electronic device comprises: one or more processors; a memory for storing executable instructions; The one or more processors are configured to implement the method of any one of claims 1 to 7 via the executable instructions. 10 . A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the processor is caused to perform the method according to claim 1 .

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