Data equalization circuit and chip

Abstract

The invention provides a data equalization circuit and a chip, and belongs to the field of analog integrated circuits. The data equalization circuit comprises a data transmission circuit used for receiving a first analog differential signal at a current moment through a channel and outputting a digital signal at the current moment based on the first analog differential signal at the current moment and a feedback signal at a previous moment; and the intersymbol interference elimination circuit is used for converting the digital signal at the current moment into a second analog differential signal at the current moment, and generating a feedback signal at the current moment based on the second analog differential signal at the current moment. The output digital signal is firstly converted into the analog signal through the intersymbol interference elimination circuit, and then the feedback signal is generated based on the analog signal, so that the digital signal output by the data transmission circuit is not directly coupled with the data transmission circuit, and the digital signal is prevented from being directly fed to the data transmission circuit; and therefore, the reduction of the elimination effect of the inter-symbol interference caused by the feed-through effect can be avoided, and the elimination effect of the inter-symbol interference can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of analog integrated circuits, and in particular to a data equalization circuit and chip. Background Art

[0002] In high-speed serial communication scenarios within the analog integrated circuit field, due to the limited channel bandwidth, high-speed serial signals are subject to inter-symbol interference (ISI) during transmission, resulting in increased bit error rates and reduced communication quality. ISI refers to the effect of a previously transmitted signal on the currently transmitted signal. For example, if the previously transmitted signal was a logic "1," the presence of ISI will cause the currently transmitted signal to also be a logic "1" (even if the signal should be a logic "0"), leading to bit errors.

[0003] Therefore, at the receiving end of the high-speed serial signal, a data equalization circuit needs to be provided to reduce inter-symbol interference. Summary of the Invention

[0004] The present invention provides a data equalization circuit and chip that can reduce inter-symbol interference. The technical solution is as follows.

[0005] In one aspect, a data equalization circuit is provided, the data equalization circuit comprising: a data transmission circuit and an intersymbol interference elimination circuit;

[0006] The data transmission circuit is configured to receive a first analog differential signal at a current moment through a channel, and output a digital signal at a current moment based on the first analog differential signal at the current moment and a feedback signal at a previous moment, wherein the feedback signal at a previous moment is generated by the intersymbol interference cancellation circuit based on the digital signal at a previous moment output by the data transmission circuit;

[0007] The inter-symbol interference elimination circuit is used to convert the digital signal at the current moment into a second analog differential signal at the current moment, and generate a feedback signal at the current moment based on the second analog differential signal, and the feedback signal at the current moment is used to reduce the interference of the digital signal at the current moment on the digital signal at the next moment.

[0008] In a possible implementation, the digital signal at the current moment includes a first signal and a second signal that are logically complementary, and the intersymbol interference cancellation circuit includes: a first differential amplifier circuit and a feedback equalization circuit;

[0009] The first differential amplifier circuit is configured to amplify and convert the first signal and the second signal to obtain and output the second analog differential signal, where the second analog differential signal matches the first analog differential signal received by the data transmission circuit at a previous moment;

[0010] The feedback equalization circuit is configured to generate the feedback signal at the current moment based on the second analog differential signal.

[0011] In a possible implementation, the second analog differential signal includes a first positive signal and a first negative signal, the feedback signal at the current moment includes the first feedback signal or the second feedback signal, and the first analog differential signal at the next moment received by the data transmission circuit includes a second positive signal and a second negative signal;

[0012] The feedback equalization circuit is configured to generate the first feedback signal when the first positive signal is at a first level and the first negative signal is at a second level, and the first feedback signal is configured to reduce the voltage of the second positive signal; and to generate the second feedback signal when the first positive signal is at a second level and the first negative signal is at a first level, and the second feedback signal is configured to reduce the voltage of the second negative signal.

[0013] In one possible implementation, the feedback equalization circuit includes a first switch circuit, a second switch circuit, and a third switch circuit, wherein the first switch circuit is connected to the transmission link of the second positive signal and the third switch circuit, respectively; the second switch circuit is connected to the transmission link of the second negative signal and the third switch circuit, respectively; and the third switch circuit is further connected to ground.

[0014] When the first positive signal is at a first level and the first negative signal is at a second level, the first switch circuit is turned on and the second switch circuit is turned off, so that the first feedback signal is generated when the third switch circuit is turned on, and the turning on or off of the third switch circuit is controlled by the first clock signal;

[0015] When the first positive signal is at the second level and the first negative signal is at the first level, the first switch circuit is turned off and the second switch circuit is turned on, so that the second feedback signal is generated when the third switch circuit is turned on.

[0016] In a possible implementation, the data transmission circuit includes: a second differential amplifier circuit, a buffer circuit, and an analog-to-digital conversion circuit;

[0017] The second differential amplifier circuit is configured to receive the first analog differential signal at a current moment through a channel, and amplify the first analog differential signal at the current moment into a third analog differential signal;

[0018] the buffer circuit being configured to output a fourth analog differential signal under the influence of the feedback signal at the previous moment and the third analog differential signal, so that the load capacitance of the second differential amplifier circuit is equal to the parasitic capacitance of the buffer circuit, and the parasitic capacitance of the buffer circuit is smaller than the sum of the input capacitance of the analog-to-digital conversion circuit and the parasitic capacitance of the intersymbol interference cancellation circuit;

[0019] The analog-to-digital conversion circuit is used to convert the fourth analog differential signal into the digital signal at the current moment.

[0020] In one possible embodiment, the buffer circuit is further connected to the power supply end and the first clock signal, respectively; the buffer circuit is configured to output a fourth analog differential signal when the first clock signal is at a first level, and a voltage value of the fourth analog differential signal is the voltage value of the power supply end; and when the first clock signal is at a second level, under the action of the feedback signal at the previous moment and the third analog differential signal, output a fourth analog differential signal, and a voltage value of the fourth analog differential signal is less than the voltage value of the power supply end.

[0021] In one possible implementation, the analog-to-digital conversion circuit includes a comparator and a trigger;

[0022] The comparator is configured to compare the positive signal and the negative signal in the fourth analog differential signal, and output a logic signal according to the comparison result;

[0023] The trigger is used to sample the logic signal and output the digital signal at the current moment according to the sampling result. The digital signal at the current moment includes a first signal and a second signal that are logically complementary. The first signal is in phase with the sampled logic signal, and the second signal is in phase with the sampled logic signal.

[0024] In one possible implementation, the trigger is used to sample the logic signal based on a trigger of a second clock signal; wherein the second clock signal is delayed compared to the first clock signal so that the comparator outputs a stable logic signal.

[0025] In a possible implementation manner, the first clock signal and the second clock signal have the same frequency, and the frequency is equal to a data rate of data transmitted by the data transmission circuit.

[0026] On the other hand, a chip is provided, comprising the data equalization circuit described in the first aspect.

[0027] In summary, the technical solutions provided by the embodiments of the present application bring at least the following beneficial effects:

[0028] The data equalization circuit provided in the embodiments of the present application generates a feedback signal corresponding to the data that has already been transmitted through the inter-symbol interference cancellation circuit, and applies it to the data currently being transmitted in the data transmission circuit to reduce the interference of the already transmitted data on the data currently being transmitted. In addition, because the inter-symbol interference cancellation circuit first converts the output digital signal into an analog signal and then generates a feedback signal based on the analog signal, the digital signal output by the data transmission circuit is not directly coupled to the data transmission circuit, thus preventing the digital signal from directly feeding through to the data transmission circuit, thereby preventing the reduction in the inter-symbol interference cancellation effect caused by the feedthrough effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0030] Figure 1 This is a structural diagram of a data equalization circuit in a related technology provided by an embodiment of the present application;

[0031] Figure 2 This is a structural diagram of a data equalization circuit provided in an embodiment of the present application;

[0032] Figure 3 is a structural diagram of another data equalization circuit provided in an embodiment of the present application;

[0033] Figure 4 This is a structural diagram of another data equalization circuit provided in an embodiment of the present application;

[0034] Figure 5 1 is a schematic structural diagram of a circuit for generating a clock signal provided in an embodiment of the present application;

[0035] Figure 6 This is a structural diagram of another data equalization circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0037] During the transmission of high-speed serial signals, data equalization circuits can reduce inter-symbol interference. Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a circuit structure of a data equalization circuit in a related technology provided by an embodiment of the present application. Figure 1As shown, the data equalization circuit includes a differential amplifier circuit, an inter-symbol interference elimination circuit, a comparator cmp1 and a D flip-flop dff1.

[0038] The input signal of the data equalization circuit is a differential high-speed serial signal Vip / Vim. After passing through the differential amplifier circuit, the signal Vip / Vim is transmitted to the nodes ip1 and im1. The signals at the nodes ip1 and im1 are differential high-speed serial signals ip1 / im1. After passing through the comparator cmp1, the signal ip1 / im1 is converted into a digital signal and transmitted to the node op. The signal at the node op is the digital signal op. The signal op is input to the D flip-flop dff1. The D flip-flop dff1 samples the signal op under the action of the clock signal clk. The positive output terminal Q of the D flip-flop dff1 outputs the digital signal t1p, and the negative output terminal Output digital signal t1m.

[0039] like Figure 1 As shown, the differential amplifier includes NMOS transistors Ma1 and Ma2, resistors R1 and R2, and a current source Ia. Signal Vip is input to the gate of Ma1, and signal Vim is input to the gate of Ma2. The sources of Ma1 and Ma2 are connected to the current source Ia, which is also connected to the ground terminal. The drains of Ma1 and Ma2 are connected to resistors R1 and R2, respectively, which are also connected to the power supply terminal VDD. Among them, the NMOS transistor is also called an N-type MOS transistor. The MOS transistor is a metal-oxide-semiconductor (MOS) field-effect transistor. The NMOS transistor is turned on when the gate voltage is high and turned off when the gate voltage is low.

[0040] Comparator cmp1 includes two inputs and one output. The two inputs are the non-inverting input "+" and the inverting input "-." Comparator cmp1 is used to compare the magnitudes of the input signals at its two inputs. When the voltage at the non-inverting input is greater than the voltage at the inverting input, the comparator outputs a high level. Conversely, when the voltage at the non-inverting input is less than the voltage at the inverting input, the comparator outputs a low level. For example, if ip1 - im1 > 0, then op = 1; if ip1 - im1 < 0, then op = 0.

[0041] The D flip-flop dff1 is a bistable element with two stable states, 0 and 1. The D flip-flop dff1 includes a data input terminal "D", a clock input terminal "Clk", a positive output terminal "Q" and an inverting output terminal The D flip-flop dff1 can store and output the input data under the control of the clock signal clk. For example, if op=1, then t1p=1, t1m=0; if op=0, then t1p=0, t1m=1.

[0042] The trigger types of the D flip-flop dff1 include, but are not limited to, edge triggering and level triggering. Edge triggering can be further divided into rising edge triggering and falling edge triggering. Taking rising edge triggering as an example, when the clock signal clk inputted by the clock input terminal Clk changes from a low level to a high level (i.e., a rising edge), the D flip-flop dff1 samples the signal at the input terminal and transmits the signal to the positive phase output terminal, and transmits the inverse of the signal to the negative phase output terminal. During other periods except the rising edge of the clock signal clk, the values ​​of the positive phase output terminal and the negative phase output terminal remain unchanged.

[0043] based on Figure 1 The data equalization circuit shown in the figure shows that for the data currently being transmitted, the values ​​of signals t1p and t1m are the data from the previous moment (i.e., the previous clk cycle). If there is no intersymbol interference cancellation circuit, when the data transmitted at the previous moment is 1, the voltage of ip1 at the previous moment is relatively large. If the data currently being transmitted is 0, the voltage of ip1 cannot drop quickly due to the intersymbol interference of the data transmitted at the previous moment, which was 1. This may cause the current ip1 to remain greater than im1, resulting in the current data being mistakenly judged as 1.

[0044] After adding the inter-symbol interference cancellation circuit, it includes NMOS transistors Mb1 and Mb2 and a current source Ib. Signal t1p is input to the gate of Mb1, and signal t1m is input to the gate of Mb2. The sources of Mb1 and Mb2 are connected to current source Ib, which is also connected to ground. The drain of Mb1 is connected to node ip1, and the drain of Mb2 is connected to node im1. Thus, the previously transmitted data is used to control the conduction and disconnection of Mb1 and Mb2. Under the action of current source Ib, the voltages at nodes ip1 and im1 are changed to offset the inter-symbol interference introduced by the previously transmitted data.

[0045] For example, since signals t1p and t1m are respectively connected to the gates of NMOS transistors Mb1 and Mb2 in the inter-symbol interference cancellation circuit, when the data transmitted at the previous moment is 1, t1p is at a high level (1), Mb1 is turned on, t1m is at a low level (0), Mb2 is turned off, and then under the action of the current source Ib, the voltage of ip1 will drop, causing ip1-im1 to decrease, thereby reducing the probability that the data transmitted at the current moment is misjudged as 1 due to the data transmitted at the previous moment being 1. Similarly, when the data transmitted at the previous moment is 0, t1p is at a low level (0), Mb1 is turned off, t1m is at a high level (1), Mb2 is turned on, and then under the action of the current source Ib, the voltage of im1 will drop, causing ip1-im1 to increase, thereby reducing the probability that the data transmitted at the current moment is misjudged as 0 due to the data transmitted at the previous moment being 0.

[0046] However, NMOS transistor Mb1 is connected between node ip1 and current source Ib, and NMOS transistor Mb2 is connected between node im1 and current source Ib. Due to the gate-drain parasitic capacitance of NMOS transistors Mb1 / Mb2, digital signal t1p / t1m is directly coupled with nodes ip1 and im1 on the data transmission link. This causes digital signal t1p / t1m to feed through to nodes ip1 / im1, creating a feedthrough effect. Feedthrough refers to the phenomenon whereby a portion of the input signal's energy is directly coupled to the output without passing through the intended signal processing path. Gate-drain parasitic capacitance refers to the equivalent capacitance between the gate and drain of an NMOS transistor. The result of digital signal t1p / t1m feeding through to nodes ip1 / im1 deviates from the expected result of inter-symbol interference (ISI) elimination. Therefore, the feedthrough effect reduces the effectiveness of ISI elimination.

[0047] For example, consider NMOS transistor Mb1. If gate input signal t1p changes from 0 to 1, Mb1 turns on. If the high voltage at t1p, which is 1, is fed through to ip1, the voltage on ip1 will also increase. However, the intended result of inter-symbol interference (ISI) elimination is to reduce the voltage on ip1. Therefore, the feedthrough effect may result in an insufficient reduction in the voltage on ip1, which in turn reduces the effectiveness of ISI elimination.

[0048] Therefore, the embodiment of the present application provides a novel data equalization circuit, which can avoid the above-mentioned feedthrough effect and improve the effect of eliminating inter-symbol interference. Figure 2 Schematic diagram of a data equalization circuit provided in an embodiment of the present application. Figure 2 As shown, the data equalization circuit includes: a data transmission circuit 01 and an inter-symbol interference cancellation circuit 02, wherein the data transmission circuit 01 is connected to the inter-symbol interference cancellation circuit 02. The connection mode includes but is not limited to electrical connection or coupling.

[0049] Data transmission circuit 01 is configured to receive a first analog differential signal at the current moment through a channel and output a digital signal at the current moment based on the first analog differential signal at the current moment and a feedback signal at the previous moment. Intersymbol interference cancellation circuit 02 is configured to convert the digital signal at the current moment into a second analog differential signal at the current moment and generate a feedback signal at the current moment based on the second analog differential signal.

[0050] The previous moment's feedback signal is generated by the intersymbol interference cancellation circuit based on the previous moment's digital signal output by the data transmission circuit. The feedback signal is used to reduce interference from previously transmitted data on currently transmitted data. Specifically, the previous moment's feedback signal reduces interference from the previous moment's digital signal on the current moment's digital signal, and the current moment's feedback signal reduces interference from the current moment's digital signal on the next moment's digital signal.

[0051] It can be understood that in the scenario where the transmitting end sends a serial signal or a high-speed serial signal to the receiving end, the data equalization circuit can be deployed in the circuit of the receiving end. The first analog differential signal can refer to a serial signal or a high-speed serial signal that is transmitted from the transmitting end to the data transmission circuit 01 of the receiving end in a differential manner through a channel. A differential signal refers to two signals with the same amplitude and opposite phases that are transmitted on a pair of coupled transmission lines. The two signals can be called a positive signal and a negative signal. Figure 2 As shown, in the embodiment of the present application, the positive signal of the first analog differential signal is represented by Vip, and the negative signal of the first analog differential signal is represented by Vim.

[0052] Therefore, in the data equalization circuit provided in the embodiment of the present application, the inter-symbol interference cancellation circuit 02 generates a feedback signal corresponding to the data that has already been transmitted, and acts on the data currently being transmitted in the data transmission circuit 01 to reduce the interference of the already transmitted data on the data currently being transmitted. In addition, because the inter-symbol interference cancellation circuit 02 first converts the output digital signal into an analog signal and then generates a feedback signal based on the analog signal, the digital signal output by the data transmission circuit 01 is not directly coupled to the data transmission circuit 01, thus preventing the digital signal from directly feeding through to the data transmission circuit 01, thereby preventing the reduction in the inter-symbol interference cancellation effect caused by the feedthrough effect.

[0053] Optionally, the digital signal output by the data transmission circuit 01 can be a single-ended digital signal or a double-ended digital signal. A single-ended digital signal transmits digital information through a signal line, uses the ground potential as a reference potential, and represents logic "0" and "1" based on the level of the signal line relative to the reference potential. A double-ended digital signal is a differential signal, which is transmitted by a pair of signal lines. The signals on the two lines have equal amplitudes and opposite phases. When the output is a single-ended digital signal, it can be converted into a double-ended digital signal, for example, by Figure 1 The D flip-flop shown converts a single-ended digital signal OP into dual-ended digital signals t1p and t1m.

[0054] Taking the digital signal output by the data transmission circuit 01 as a two-terminal digital signal as an example, the digital signal output by the data transmission circuit 01 includes a first signal and a second signal which are logically complementary. The first signal can be represented by t1p and the second signal can be represented by t1m. Figure 3 The inter-symbol interference elimination circuit 02 may include: a first differential amplifier circuit 021 and a feedback equalization circuit 022 , and the first differential amplifier circuit 021 is connected to the feedback equalization circuit 022 .

[0055] The first differential amplifier circuit 021 is configured to amplify and convert the first and second signals to generate and output a second analog differential signal. The second analog differential signal matches the first analog differential signal received by the data transmission circuit 01 at the previous moment. The second analog differential signal includes a first positive signal and a first negative signal, with the first positive signal represented by ip2 and the first negative signal represented by im2. For example, the second analog differential signal is equal to or close to the first analog differential signal received by the data transmission circuit at the previous moment. The feedback equalization circuit 022 is configured to generate a current feedback signal based on the second analog differential signal.

[0056] Optionally, the feedback signal at the current moment includes a first feedback signal or a second feedback signal, and the first analog differential signal received by the data transmission circuit at the next moment includes a second positive signal and a second negative signal. The feedback equalization circuit is configured to generate a first feedback signal when the first positive signal is at a first level and the first negative signal is at a second level, the first feedback signal being used to reduce the voltage of the second positive signal; and to generate a second feedback signal when the first positive signal is at a second level and the first negative signal is at a first level, the second feedback signal being used to reduce the voltage of the second negative signal. In an embodiment of the present application, the first level can be a high level 1 and the second level can be a low level 0; alternatively, the first level can be a low level 0 and the second level can be a high level 1.

[0057] Take the first level as high level 1 and the second level as low level 0 as an example. The first positive signal is the first level, which means that the digital signal transmitted at the last moment is 1. Figure 1 Analysis of the circuit shows that if the digital signal transmitted at the previous moment is 1, the voltage of the positive signal being transmitted at the current moment will be increased. At this time, reducing the voltage of the positive signal in the analog differential signal being transmitted at the current moment can eliminate the inter-symbol interference caused by the digital signal being 1 at the previous moment. The first negative signal is at the first level, indicating that the digital signal transmitted at the previous moment was 0. Similarly, if the digital signal transmitted at the previous moment is 0, the voltage of the negative signal being transmitted at the current moment will be increased. At this time, reducing the voltage of the negative signal in the analog differential signal being transmitted at the current moment can eliminate the inter-symbol interference caused by the digital signal being 0 at the previous moment.

[0058] In one possible implementation, feedback equalization circuit 022 includes a first switching circuit, a second switching circuit, and a third switching circuit. The first switching circuit is connected to the transmission link of the second positive signal and the third switching circuit, respectively. The second switching circuit is connected to the transmission link of the second negative signal and the third switching circuit, respectively. The third switching circuit is also connected to ground. Thus, the first and third switching circuits are used to control the connection or disconnection between the second positive signal and the ground, and the second and third switching circuits are used to control the connection or disconnection between the second negative signal and the ground.

[0059] The first switch circuit is turned on or off by a first positive signal. For example, when the first positive signal is at a first level, the first switch circuit is turned on, and when the first positive signal is at a second level, the first switch circuit is turned off. The second switch circuit is turned on or off by a first negative signal. For example, when the first negative signal is at a first level, the second switch circuit is turned on, and when the first negative signal is at a second level, the second switch circuit is turned off.

[0060] The switching circuits involved in the embodiments of the present application can be implemented by components such as transistors, MOS transistors, or thyristors, without limitation. For example, the first switching circuit is an NMOS transistor M2', the second switching circuit is an NMOS transistor M1', and the third switching circuit is an NMOS transistor M3'. The gate of the NMOS transistor M2' is connected to the first positive signal ip2 in the second analog differential signal, and the gate of the NMOS transistor M1' is connected to the first negative signal im2 in the second analog differential signal.

[0061] The on / off state of the third switch circuit is controlled by the first clock signal. For example, when the first clock signal is at a first level, the third switch circuit is on, and when the first clock signal is at a second level, the third switch circuit is off. In this embodiment of the present application, the frequency of the first clock signal can be equal to the data rate of the data transmitted by the data transmission circuit 01. The data rate refers to the amount of effective data transmitted by the data transmission circuit 01 per unit time, that is, one data is transmitted per clock cycle. The data transmitted at the previous moment is the data transmitted in the previous clock cycle, and the data transmitted at the current moment is the data transmitted in the current clock cycle.

[0062] Thus, when the first positive signal is at the first level and the first negative signal is at the second level, the first switch circuit is turned on and the second switch circuit is turned off, so that when the third switch circuit is turned on, the above-mentioned first feedback signal is generated; when the first positive signal is at the second level and the first negative signal is at the first level, the first switch circuit is turned off and the second switch circuit is turned on, so that when the third switch circuit is turned on, the above-mentioned second feedback signal is generated.

[0063] In one possible implementation, see Figure 4 The data transmission circuit 01 includes: a second differential amplifier circuit 011, a buffer circuit 012 and an analog-to-digital conversion circuit 013. The second differential amplifier circuit 011 is connected to the buffer circuit 012, the buffer circuit 012 is connected to the analog-to-digital conversion circuit 013, and the buffer circuit 012 is also connected to the inter-symbol interference elimination circuit 02. Figure 4 As shown, the buffer circuit 012 is also connected to the feedback equalization circuit 022 in the inter-symbol interference cancellation circuit 02.

[0064] The second differential amplifier circuit 011 is configured to receive the first analog differential signal at the current moment through a channel and amplify the first analog differential signal at the current moment into a third analog differential signal. The third analog differential signal includes a third positive signal and a third negative signal, with the third positive signal being denoted by ip1 and the third negative signal being denoted by im1. The buffer circuit 012 is configured to output a fourth analog differential signal under the influence of the feedback signal from the previous moment and the third analog differential signal, such that the load capacitance of the second differential amplifier circuit 011 is equal to the parasitic capacitance of the buffer circuit 012. The fourth analog differential signal includes a fourth positive signal and a fourth negative signal, with the fourth positive signal being denoted by xp and the fourth negative signal being denoted by xm. The analog-to-digital conversion circuit 013 is configured to convert the fourth analog differential signal into the current digital signal.

[0065] exist Figure 1 In the data equalization circuit shown in FIG, since the loads of nodes ip1 and im1 are the sum of the drain parasitic capacitances of Mb1 and Mb2 and the input capacitance of comparator cmp1, the loads of nodes ip1 and im1 are relatively large, that is, Figure 1 The differential amplifier circuit in the comparator is heavily loaded. Drain parasitic capacitance refers to the sum of the capacitance between the drain and all surrounding areas where electric field coupling may occur. Input capacitance refers to the parasitic capacitance of components such as transistors and diodes within comparator cmp1, as well as capacitance introduced by pins and wiring. This is the equivalent capacitance presented at the input of comparator cmp1. In high-speed serial communications, the heavy load on the differential amplifier circuit limits the overall transmission bandwidth of the data equalization circuit, thereby reducing the transmission speed of high-speed serial signals.

[0066] In this embodiment of the present application, by adding a buffer circuit 012 between the second differential amplifier circuit 011 and the analog-to-digital converter circuit 013, the loads of nodes ip1 and im1 are the parasitic capacitance of the buffer circuit. This means that the load of the second differential amplifier circuit 011 is the parasitic capacitance of the buffer circuit, which is smaller than the sum of the input capacitance of the analog-to-digital converter circuit 013 and the parasitic capacitance of the intersymbol interference cancellation circuit 02. Therefore, the data equalization circuit provided in this embodiment of the present application provides a lower load on the second differential amplifier circuit 011, thereby enabling the data equalization circuit to have a greater transmission bandwidth.

[0067] Optionally, the buffer circuit 012 is further connected to the power supply terminal and the first clock signal, respectively. The buffer circuit 012 is configured to output a fourth analog differential signal when the first clock signal is at a first level, wherein the voltage value of the fourth analog differential signal is equal to the voltage value of the power supply terminal; and to output a fourth analog differential signal when the first clock signal is at a second level, under the influence of the feedback signal at the previous moment and the third analog differential signal, wherein the voltage value of the fourth analog differential signal is less than the voltage value of the power supply terminal.

[0068] Exemplarily, the buffer circuit 012 includes a fourth switch circuit, a fifth switch circuit, a sixth switch circuit, a seventh switch circuit, and an eighth switch circuit. The fourth switch circuit and the fifth switch circuit are both connected to the power supply terminal VDD. The fourth switch circuit is connected to the sixth switch circuit and the feedback equalization circuit 022 via a first node, respectively. The fifth switch circuit is connected to the seventh switch circuit and the feedback equalization circuit 022 via a second node, respectively. The sixth switch circuit and the seventh switch circuit are also connected to the eighth switch circuit, respectively. The eighth switch circuit is also connected to ground.

[0069] The fourth and fifth switch circuits are controlled to be on or off by the inverted signal of the first clock signal, the sixth switch circuit is controlled to be on or off by the third positive signal ip1, the seventh switch circuit is controlled to be on or off by the third negative signal im1, and the eighth switch circuit is controlled to be on or off by the first clock signal. For example, the fourth switch circuit is a PMOS transistor M4, the fifth switch circuit is a PMOS transistor M5, the sixth switch circuit is an NMOS transistor M1, the seventh switch circuit is an NMOS transistor M2, and the eighth switch circuit is an NMOS transistor M3. A PMOS transistor, also known as a P-type MOS transistor, turns on when the gate voltage is low and turns off when the gate voltage is high. The specific operation of the buffer circuit 012 will be described later and will not be elaborated here.

[0070] In one possible embodiment, the analog-to-digital conversion circuit 013 includes a comparator; the comparator is used to compare the positive signal and the negative signal in the fourth analog differential signal, and output a logic signal according to the comparison result, and the logic signal is the output single-ended digital signal. Alternatively, the analog-to-digital conversion circuit 013 includes a comparator and a trigger; the comparator is used to compare the positive signal and the negative signal in the fourth analog differential signal, and output a logic signal according to the comparison result; the trigger is used to sample the logic signal, and output a two-ended digital signal according to the sampling result, and the two-ended digital signal includes a first signal and a second signal that are logically complementary. The first signal is in phase with the sampled logic signal, and the second signal is in phase with the sampled logic signal. The comparator and the trigger and their working principles can be found in Figure 1 The relevant introduction in will not be repeated here.

[0071] Optionally, the trigger is used to sample the logic signal based on the triggering of the second clock signal. The first clock signal and the second clock signal have the same frequency, and the second clock signal has a delay compared to the first clock signal, so that the comparator outputs a stable logic signal. For example, see Figure 5For example, the first clock signal, denoted by clk, is converted to its inverted signal, clkb, by inverter inv1. clkb then passes through inverter inv2 to its inverted signal, clkt. clkt is the second clock signal. clkt and clk have the same phase, and clkt is equivalent to a delayed version of clk.

[0072] For example, the switch circuit is implemented by a MOS tube. Figure 6 , Figure 6 A schematic diagram of a data equalization circuit provided in an embodiment of the present application. Figure 6 The second differential amplifier circuit 011 shown is connected to Figure 1 The differential amplifier circuit shown is identical, also consisting of NMOS transistors Ma1 and Ma2, resistors R1 and R2, and current source Ia. The input of the second differential amplifier circuit 011 is the differential high-speed serial signal Vip / Vim (corresponding to the first analog differential signal described above). After passing through the second differential amplifier circuit 011, the signal Vip / Vim is transmitted to nodes ip1 and im1. The signals at nodes ip1 and im1 are the differential high-speed serial signals ip1 / im1. That is, the output of the second differential amplifier circuit 011 is the differential high-speed serial signal ip1 / im1 (corresponding to the third analog differential signal described above).

[0073] However, in the embodiment of the present application, the node where the second differential amplifier circuit 011 outputs the signal ip1 / im1 is connected to the gate of the NMOS transistor M1 / M2 respectively. As a result, the load of the second differential amplifier circuit 011 is only the gate capacitance of the NMOS transistor M1 / M2, which is much smaller than the sum of the drain parasitic capacitance of Mb1 / Mb2 and the input capacitance of the comparator cmp1, thus being relatively low. Figure 1 The circuit shown has lower loading and thus greater transmission bandwidth.

[0074] The following explains Figure 6 How does the data equalization circuit shown in the figure achieve the function of eliminating inter-symbol interference? Wherein, clk is a clock signal, and data is sampled and transmitted at the rising or falling edge of the clock signal. Optionally, the frequency of clk can be determined based on the data rate of the transmitted high-speed serial data vip / vim. For example, the frequency of clk is equal to the data rate of the transmitted high-speed serial data vip / vim, that is, one bit of data is transmitted per clock cycle. Optionally, according to Figure 5 The circuit shown generates clock signals clk, clkb, and clkt. clk is connected to the gates of NMOS transistors M3 and M3', while clkb is connected to the gates of PMOS transistors M4 and M5. clkt is connected to the clock input of D-type flip-flop dff1 and serves as its trigger clock. clkt has a delay compared to clk, which ensures sufficient settling time for comparator cmp1.

[0075] When clk = 0 (low), NMOS transistors M3 and M3' are disconnected, PMOS transistors M4 and M5 are turned on, and the voltage at nodes xp / xm is pulled up to the high level VDD. When clk = 1 (high), NMOS transistors M3 and M3' are turned on, and PMOS transistors M4 and M5 are turned off. The voltage at nodes xp / xm decreases, with the rate of decrease determined by the gate voltages of M1, M2, M1', and M2'. Optionally, M1, M2, M1', and M2' have the same size.

[0076] The gates of NMOS transistors M1' and M2' are connected to nodes im2 and ip2, respectively. Nodes im2 and ip2 are also connected to the drains of NMOS transistors Mb1 and Mb2. The gates of NMOS transistors Mb1 and Mb2 are connected to the positive-inverting output terminal t1p and the negative-inverting output terminal t1m of the D-type flip-flop dff1, respectively. Nodes im2 and ip2 are also connected to the power supply terminal VDD through resistors Rb1 and Rb2, respectively. Based on the above analysis, when transmitting data at the current moment, the value of t1p / t1m is the same as the data transmitted at the previous moment. When the data transmitted at the previous moment was 1, t1p = 1 and t1m = 0. At this point, Mb1 is on and Mb2 is off. Under the action of current source Ib, the voltage at node im2 decreases, causing M1' to turn off, while the voltage at node ip2 increases, causing M2' to turn on. When clk=1 (high level), under the action of the turned-on M2' and M3', the voltage of the node xp drops faster, making the output data op more inclined to 0, that is, offsetting the inter-symbol interference caused by the data 1 transmitted at the previous moment.

[0077] Similarly, when the data transmitted last time was 0, t1p = 0 and t1m = 1. At this point, ports Mb1 and Mb2 are conducting. Under the action of current source Ib, the voltage at node im2 increases, turning M1` on, while the voltage at node ip2 decreases, turning M2` off. When clk = 1 (high), the voltage at node xm decreases faster due to the conduction of M1` and M3`, causing the output data op to be more inclined toward 1, thus offsetting the intersymbol interference caused by the previously transmitted data being 0.

[0078] In summary, embodiments of the present application provide a data equalization circuit. In this data equalization circuit, an intersymbol interference cancellation circuit generates a feedback signal corresponding to already transmitted data, which acts on the data currently being transmitted in the data transmission circuit to reduce interference from the already transmitted data on the currently being transmitted data. Furthermore, because the intersymbol interference cancellation circuit first converts the output digital signal into an analog signal and then generates a feedback signal based on the analog signal, the digital signal output by the data transmission circuit is not directly coupled to the data transmission circuit, thus preventing the digital signal from directly feeding through to the data transmission circuit and, in turn, preventing a reduction in the effectiveness of intersymbol interference cancellation due to the feedthrough effect.

[0079] The embodiment of the present application also provides a chip system comprising Figure 1-4 or any of the data equalization circuits shown in 6. For example, the chip can be deployed at the receiving end of a high-speed serial signal, such as a receiver (RX) chip. It is understood that the chip has substantially the same technical effects as the aforementioned data equalization circuit, so for the sake of brevity, the technical effects of the chip will not be repeated here.

[0080] It should be noted that the terms used in the embodiments of this application are used to explain the embodiments of this application and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of this application should have the common meanings understood by people with ordinary skills in the field to which this application belongs.

[0081] For example, the words “first”, “second” or “third” and similar words used in the patent application specification and claims of this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as “a” or “an” do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as “include” or “comprise” mean that the elements or objects appearing before “include” or “comprises” include the elements or objects listed after “include” or “comprises” and their equivalents, and do not exclude other elements or objects. “Up”, “down”, “left” or “right” and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. “Connected” or “coupled” refers to an electrical connection. The character “ / ” generally indicates that the objects related before and after are in an “or” relationship.

[0082] The above description is merely an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A data equalization circuit, characterized in that: The data equalization circuit includes: a data transmission circuit and an inter-symbol interference elimination circuit; The data transmission circuit is configured to receive a first analog differential signal at a current moment through a channel, and output a digital signal at a current moment based on the first analog differential signal at the current moment and a feedback signal at a previous moment, wherein the feedback signal at a previous moment is generated by the intersymbol interference cancellation circuit based on the digital signal at a previous moment output by the data transmission circuit; The inter-symbol interference elimination circuit is used to convert the digital signal at the current moment into a second analog differential signal at the current moment, and generate a feedback signal at the current moment based on the second analog differential signal, and the feedback signal at the current moment is used to reduce the interference of the digital signal at the current moment on the digital signal at the next moment.

2. The data equalization circuit according to claim 1, wherein: The digital signal at the current moment includes a first signal and a second signal that are logically complementary, and the inter-symbol interference elimination circuit includes: a first differential amplifier circuit and a feedback equalization circuit; The first differential amplifier circuit is configured to amplify and convert the first signal and the second signal to obtain and output the second analog differential signal, where the second analog differential signal matches the first analog differential signal received by the data transmission circuit at a previous moment; The feedback equalization circuit is configured to generate the feedback signal at the current moment based on the second analog differential signal.

3. The data equalization circuit according to claim 2, wherein: The second analog differential signal includes a first positive signal and a first negative signal, the feedback signal at the current moment includes the first feedback signal or the second feedback signal, and the first analog differential signal at the next moment received by the data transmission circuit includes a second positive signal and a second negative signal; The feedback equalization circuit is configured to generate the first feedback signal when the first positive signal is at a first level and the first negative signal is at a second level, and the first feedback signal is configured to reduce the voltage of the second positive signal; and to generate the second feedback signal when the first positive signal is at a second level and the first negative signal is at a first level, and the second feedback signal is configured to reduce the voltage of the second negative signal.

4. The data equalization circuit according to claim 3, wherein: The feedback equalization circuit includes a first switch circuit, a second switch circuit, and a third switch circuit, wherein the first switch circuit is connected to the transmission link of the second positive signal and the third switch circuit respectively, the second switch circuit is connected to the transmission link of the second negative signal and the third switch circuit respectively, and the third switch circuit is further connected to the ground; When the first positive signal is at a first level and the first negative signal is at a second level, the first switch circuit is turned on and the second switch circuit is turned off, so that the first feedback signal is generated when the third switch circuit is turned on, and the turning on or off of the third switch circuit is controlled by the first clock signal; When the first positive signal is at the second level and the first negative signal is at the first level, the first switch circuit is turned off and the second switch circuit is turned on, so that the second feedback signal is generated when the third switch circuit is turned on.

5. The data equalization circuit according to any one of claims 1 to 4, characterized in that: The data transmission circuit includes: a second differential amplifier circuit, a buffer circuit and an analog-to-digital conversion circuit; The second differential amplifier circuit is configured to receive the first analog differential signal at a current moment through a channel, and amplify the first analog differential signal at the current moment into a third analog differential signal; the buffer circuit being configured to output a fourth analog differential signal under the influence of the feedback signal at the previous moment and the third analog differential signal, so that the load capacitance of the second differential amplifier circuit is equal to the parasitic capacitance of the buffer circuit, and the parasitic capacitance of the buffer circuit is smaller than the sum of the input capacitance of the analog-to-digital conversion circuit and the parasitic capacitance of the intersymbol interference cancellation circuit; The analog-to-digital conversion circuit is used to convert the fourth analog differential signal into the digital signal at the current moment.

6. The data equalization circuit according to claim 5, characterized in that: The buffer circuit is further connected to the power supply terminal and the first clock signal respectively; the buffer circuit is configured to output a fourth analog differential signal when the first clock signal is at a first level, wherein the voltage value of the fourth analog differential signal is the voltage value of the power supply terminal; When the first clock signal is at the second level, under the action of the feedback signal at the previous moment and the third analog differential signal, a fourth analog differential signal is output, and the voltage value of the fourth analog differential signal is less than the voltage value of the power supply end.

7. The data equalization circuit according to claim 6, wherein: The analog-to-digital conversion circuit includes a comparator and a trigger; The comparator is configured to compare the positive signal and the negative signal in the fourth analog differential signal, and output a logic signal according to the comparison result; The trigger is used to sample the logic signal and output the digital signal at the current moment according to the sampling result. The digital signal at the current moment includes a first signal and a second signal that are logically complementary. The first signal is in phase with the sampled logic signal, and the second signal is in phase with the sampled logic signal.

8. The data equalization circuit according to claim 7, wherein: The trigger is used to sample the logic signal based on the triggering of a second clock signal; wherein the second clock signal is delayed compared to the first clock signal, so that the comparator outputs a stable logic signal.

9. The data equalization circuit according to claim 8, wherein: The first clock signal and the second clock signal have the same frequency, and the frequency is equal to a data rate of data transmitted by the data transmission circuit.

10. A chip, characterized in that: The chip includes the data equalization circuit according to any one of claims 1 to 9.

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