Method, system and device for testing performance of circuit board and storage medium

By performing feature extraction, parameter correlation analysis, and redundancy elimination on circuit board test data, combined with factor analysis and entropy weight optimization, the problem of low accuracy in circuit board performance testing is solved, achieving more efficient and accurate performance evaluation.

CN120596877APending Publication Date: 2025-09-05SHENZHEN HANLONGFU TECH CO LTD
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Patent Information

Application Number
CN202510674894.0
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-05-23
Publication Date
2025-09-05

AI Technical Summary

Technical Problem

Existing technologies are unable to flexibly adjust the weight distribution of circuit board performance test items, resulting in the potential interaction effects between electrical performance and mechanical performance not being fully considered, leading to low test accuracy.

Method used

By obtaining circuit board test data, performing feature extraction and parameter correlation analysis, building a quantitative correlation matrix, eliminating redundant parameters, performing factor analysis and entropy weight optimization, and determining a set of key performance indicators.

Benefits of technology

It improves the accuracy and repeatability of circuit board performance testing, enhances the scientific nature and computational efficiency of data analysis, and ensures the scientific nature and stability of key indicator selection.

✦ Generated by Eureka AI based on patent content.

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Abstract

The invention relates to the technical field of industrial data analysis, and discloses a circuit board performance test method, system and device and a storage medium, the method comprises the following steps: obtaining circuit board test data, and carrying out feature extraction to obtain an initial feature data set and an initial parameter set; performing parameter correlation analysis according to the initial feature data set to obtain a quantitative correlation matrix; performing redundancy analysis according to the quantitative incidence matrix and the initial parameter set to obtain a simplified parameter set; performing data cleaning on the circuit board test data according to the simplified parameter set, and performing factor analysis to obtain a factor load matrix; performing main factor extraction according to the factor load matrix, and performing parameter contribution rate analysis according to an obtained main factor set to obtain a key performance index set; and performing entropy weight optimization according to the key performance index set to obtain a final performance index set. The method can improve the performance test accuracy of the circuit board.
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Description

Technical Field

[0001] The present invention relates to the technical field of industrial data analysis, and in particular to a performance testing method, system, device and storage medium for a circuit board. Background Art

[0002] With the rapid development of the electronics manufacturing industry, circuit boards, as core components of electronic equipment, have a direct impact on the stability and reliability of the entire system. Therefore, effective performance testing of circuit boards has become particularly important. Against this backdrop, industrial data analysis has become a key technology for improving testing accuracy and efficiency. By collecting and analyzing various data from the production line, including but not limited to parameters such as temperature, humidity, and electrical characteristics, a deeper understanding of circuit board performance can be achieved. However, faced with increasingly complex production environments and diverse product demands, traditional testing methods are no longer able to meet the requirements of modern manufacturing. Especially in the context of big data, how to leverage industrial data analysis to optimize circuit board performance testing processes and improve the accuracy and repeatability of test results has become a key focus of the industry.

[0003] In one existing technique, circuit board performance testing primarily relies on a series of standardized test items, such as electrical performance testing, mechanical performance testing, and environmental adaptability testing. First, technicians determine the specific parameters to be tested based on the product's design specifications and set corresponding thresholds. Next, specialized testing equipment is used to inspect each circuit board individually, recording the actual measured values ​​for each parameter. For example, electrical performance testing examines key indicators such as the circuit board's resistance, capacitance, and signal transmission speed; mechanical performance testing assesses aspects such as impact resistance and bending strength. This test data is then aggregated and analyzed to determine whether the circuit board meets established quality standards.

[0004] In practical applications, potential interactions between electrical and mechanical properties exist. For example, the relationship between the coefficient of thermal expansion and changes in circuit impedance can lead to product failures during field use. Furthermore, in high-frequency signal processing applications, signal integrity is the most critical factor, while in some applications requiring high physical durability, mechanical performance is even more important. However, existing technologies lack the flexibility to adjust the weighting of test items and the impact of potential interactions, resulting in low accuracy in circuit board performance testing. Summary of the Invention

[0005] The present invention provides a circuit board performance testing method, system, device, electronic equipment and storage medium to solve the problem of low accuracy in performance testing of circuit boards.

[0006] In a first aspect, in order to solve the above technical problems, the present invention provides a performance testing method for a circuit board, comprising: Obtain circuit board test data and perform feature extraction to obtain an initial feature data set and an initial parameter set; Performing parameter correlation analysis based on the initial feature data set to obtain a quantitative correlation matrix; Performing redundancy analysis on the quantized correlation matrix and the initial parameter set to obtain a simplified parameter set; Performing data cleaning on the circuit board test data according to the simplified parameter set, and performing factor analysis to obtain a factor loading matrix; Extracting principal factors according to the factor loading matrix, and performing parameter contribution rate analysis based on the obtained principal factor set to obtain a set of key performance indicators; Entropy weight optimization is performed according to the key performance indicator set to obtain a final performance indicator set.

[0007] In an optional embodiment, the obtaining of circuit board test data and performing feature extraction to obtain an initial feature data set and an initial parameter set includes: Standardize the circuit board test data to obtain standardized test data; Performing covariance calculation based on the standardized test data to obtain a covariance matrix; Performing eigenvalue decomposition according to the covariance matrix to obtain eigenvalues ​​and corresponding eigenvectors; When the eigenvalue is greater than or equal to a preset eigenvalue threshold, the corresponding eigenvector is retained and added to the dimension-reduced feature matrix; When the eigenvalue is less than the eigenvalue threshold, eliminating the eigenvalue and the corresponding eigenvector; Performing matrix multiplication on the dimension-reduced feature matrix and the standardized test data to obtain an initial feature data set; An initial parameter set is formed according to the test parameters corresponding to each dimension of the initial feature data set.

[0008] In an optional implementation, performing parameter correlation analysis based on the initial feature data set to obtain a quantitative correlation matrix includes: Performing covariance calculation based on the initial feature data set to obtain feature covariance; Calculating the standard deviation of the initial feature data set to obtain a feature standard deviation; Calculate parameter correlation based on the characteristic covariance and the characteristic standard deviation to obtain a correlation coefficient; A symmetric matrix is ​​constructed according to the correlation coefficient to obtain a quantized correlation matrix.

[0009] In an optional implementation, performing redundancy analysis on the quantized correlation matrix and the initial parameter set to obtain a simplified parameter set includes: Get parameter business scenarios; When the correlation coefficient in the quantized correlation matrix is ​​greater than a preset correlation threshold, it is determined that there is a strong correlation between the parameters; Performing redundancy determination on strongly associated parameters according to the parameter business scenarios, determining strongly associated parameters with overlapping business scenarios as redundant parameters, and removing them from the initial parameter set; After completing the redundancy determination of all strongly associated parameters, the remaining parameters in the initial parameter set constitute a reduced parameter set.

[0010] In an optional implementation, the step of performing data cleaning on the circuit board test data according to the simplified parameter set and performing factor analysis to obtain a factor loading matrix includes: Traversing the circuit board test data, deleting data dimensions that are not in the simplified parameter set, and obtaining first simplified data; Eliminate outliers based on the first simplified data to obtain cleaned second simplified data; Performing principal component analysis on the second simplified data to obtain simplified eigenvalues ​​and simplified eigenvectors; The factor loading vector is calculated using the following formula: in, represents the factor loading vector, express The simplified eigenvalues, express The simplified eigenvalue corresponding to the simplified eigenvalue is The number representing the reduced eigenvalue; The factor loading matrix is ​​obtained by performing horizontal connection according to the factor loading vectors.

[0011] In an optional embodiment, the extracting of principal factors according to the factor loading matrix and the performing of parameter contribution rate analysis according to the obtained principal factor set to obtain a set of key performance indicators include: Obtain the simplified eigenvalue and the second simplified data of each column of the factor loading matrix; When the simplified eigenvalue is less than the preset main factor threshold, the corresponding factor loading vector is eliminated; When the simplified eigenvalue is greater than or equal to the main factor threshold, the corresponding factor loading vector is retained and added to the main factor set; Multiplying each factor loading vector in the main factor set by the second reduced data to obtain a main factor score; Calculating score variance based on the main factor scores; Divide the square of the main factor score by the score variance to obtain the factor contribution rate; When the factor contribution rate is greater than a preset contribution rate threshold, the parameter corresponding to the factor loading vector is included in the key performance indicator set.

[0012] In an optional implementation, performing entropy weight optimization according to the key performance indicator set to obtain a final performance indicator set includes: Calculate information entropy based on the key performance indicator set to obtain indicator information entropy; Obtain the initial weight of the indicator according to the inverse of the indicator information entropy; Performing weighted summation on each key performance indicator according to the initial weight of the indicator to obtain a comprehensive confidence level of the indicator; When the comprehensive confidence of the indicator is less than the preset confidence threshold, the corresponding performance indicator is eliminated; When the comprehensive confidence of the indicator is greater than or equal to the confidence threshold, retaining the corresponding performance indicator; After completing the traversal of all indicators, the final performance indicator set is obtained.

[0013] In a second aspect, the present invention provides a performance testing system for a circuit board, comprising: The data acquisition module is used to obtain circuit board test data and perform feature extraction to obtain an initial feature data set and an initial parameter set; A correlation analysis module, configured to perform parameter correlation analysis based on the initial feature data set to obtain a quantitative correlation matrix; a redundancy elimination module, configured to perform redundancy analysis based on the quantization correlation matrix and the initial parameter set to obtain a streamlined parameter set; A factor analysis module, configured to perform data cleaning on the circuit board test data according to the simplified parameter set, and perform factor analysis to obtain a factor loading matrix; A key indicator module is used to extract main factors according to the factor loading matrix, and perform parameter contribution rate analysis based on the obtained main factor set to obtain a key performance indicator set; The entropy weight optimization module is used to perform entropy weight optimization according to the key performance indicator set to obtain a final performance indicator set.

[0014] In a third aspect, the present invention also provides an electronic device comprising a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein when the processor executes the computer program, the performance testing method of the circuit board described in any one of the above items is implemented.

[0015] In a fourth aspect, the present invention also provides a computer-readable storage medium, which includes a stored computer program, wherein when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute any one of the circuit board performance testing methods described above.

[0016] Compared with the prior art, the present invention has the following beneficial effects: (1) Obtain circuit board test data and perform feature extraction to obtain an initial feature data set and initial parameter set. By collecting multidimensional test data from the circuit board during performance testing and extracting key features using statistical analysis and principal component analysis, a structured initial feature data set and parameter set are formed. This step provides a high-quality input foundation for subsequent data correlation analysis and optimization, improving the accuracy of data analysis.

[0017] (2) Parameter correlation analysis is performed based on the initial feature data set to obtain a quantitative correlation matrix. The Pearson correlation coefficient method is used to quantitatively evaluate the relationship between the parameters and generate a quantitative correlation matrix. This step helps to identify the dependency between parameters, reveal the potential coupling mechanism, provide a basis for subsequent redundancy analysis, and improve the scientific nature and computational efficiency of parameter screening.

[0018] (3) Redundancy analysis is performed on the quantitative association matrix and the initial parameter set to obtain a streamlined parameter set. Based on the high correlation between parameters in the quantitative association matrix and the overlap of business scenarios, duplicate or highly correlated redundant parameters are eliminated, and the most representative core parameters are retained to construct a streamlined parameter set. This method effectively reduces data dimensionality and unnecessary calculations while retaining key information, significantly improving the efficiency and accuracy of subsequent data cleaning and modeling.

[0019] (4) The circuit board test data is cleaned according to the simplified parameter set and factor analysis is performed to obtain a factor loading matrix. After performing cleaning operations such as outlier removal on the simplified parameters, factor analysis is further used to explore the potential common factors hidden behind multiple variables and construct a factor loading matrix. This step not only enhances the structure of the data, but also improves the data's interpretability, providing reliable mathematical support for subsequent principal factor extraction.

[0020] (5) Extract the principal factors based on the factor loading matrix, and perform parameter contribution analysis based on the obtained principal factor set to obtain a set of key performance indicators. By performing eigenvalue decomposition and variance contribution calculation on the factor loading matrix, the principal factors with the greatest impact on overall performance are identified, and the key performance indicator set is determined accordingly. This process achieves an efficient mapping from raw test data to core performance indicators, significantly improving the accuracy and interpretability of performance evaluation.

[0021] (6) Perform entropy weight optimization based on the key performance indicator set to obtain a final performance indicator set. Based on the entropy weight method, each key performance indicator is weighted and a confidence calculation is performed to obtain a more representative and stable final performance indicator set. This method improves the objectivity and consistency of the performance evaluation results and ensures the scientificity and effectiveness of the key indicator selection in the industrial data analysis process. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a schematic flow chart of a performance testing method for a circuit board provided by the first embodiment of the present invention; Figure 2 This is a schematic structural diagram of a circuit board performance testing system provided by the second embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0024] Reference Figure 1 A first embodiment of the present invention provides a performance testing method for a circuit board, comprising the following steps: S11, obtaining circuit board test data and performing feature extraction to obtain an initial feature data set and an initial parameter set; S12, performing parameter correlation analysis based on the initial feature data set to obtain a quantitative correlation matrix; S13, performing redundancy analysis based on the quantization correlation matrix and the initial parameter set to obtain a simplified parameter set; S14, performing data cleaning on the circuit board test data according to the simplified parameter set, and performing factor analysis to obtain a factor loading matrix; S15, extracting main factors according to the factor loading matrix, and performing parameter contribution rate analysis based on the obtained main factor set to obtain a key performance indicator set; S16, performing entropy weight optimization according to the key performance indicator set to obtain a final performance indicator set.

[0025] In step S11, circuit board test data is acquired and feature extraction is performed to obtain an initial feature data set and an initial parameter set.

[0026] It's worth noting that circuit board test data contains multidimensional information, covering electrical performance (such as voltage, current, and resistance), environmental conditions (temperature, humidity, and vibration frequency), mechanical stress (bending, folding, and tensile strength), production parameters (dimensional accuracy and soldering quality), and functional response (signal transmission stability and short / open circuit detection). Data acquisition relies on automated test equipment and sensor networks. For example, high-precision data acquisition cards monitor electrical parameters in real time, laser rangefinders and optical inspection equipment (such as AOI and X-rays) capture physical features, environmental test chambers record temperature and humidity changes, and vibration tables simulate performance under mechanical stress. Data is stored in structured databases to support real-time analysis and historical data mining. Within the industrial data mining and analysis framework, this data requires cleaning, dimensionality reduction, and feature engineering to build predictive models or optimize testing processes.

[0027] In one embodiment, the circuit board test data is standardized to obtain standardized test data; Performing covariance calculation based on the standardized test data to obtain a covariance matrix; Performing eigenvalue decomposition according to the covariance matrix to obtain eigenvalues ​​and corresponding eigenvectors; When the eigenvalue is greater than or equal to a preset eigenvalue threshold, the corresponding eigenvector is retained and added to the dimension-reduced feature matrix; When the eigenvalue is less than the eigenvalue threshold, eliminating the eigenvalue and the corresponding eigenvector; Performing matrix multiplication on the dimension-reduced feature matrix and the standardized test data to obtain an initial feature data set; An initial parameter set is formed according to the test parameters corresponding to each dimension of the initial feature data set.

[0028] It's worth noting that the normalization calculation steps are implemented using the Z-score method. First, the mean and standard deviation are calculated for each feature dimension (such as voltage or resistance). Next, the difference between the original value of each data point and the feature's mean is calculated, and this difference is divided by the feature's standard deviation to obtain the normalized value. This process normalizes all feature values ​​to a distribution with a mean of 0 and a standard deviation of 1, eliminating the impact of differences in physical dimensions and magnitude on subsequent analysis and facilitating subsequent covariance matrix calculation and dimensionality reduction.

[0029] It is worth noting that, based on the standardized test data, the covariance matrix between each feature dimension is first calculated to reflect the linear correlation between different parameters. The covariance matrix is ​​then subjected to eigenvalue decomposition to obtain a set of eigenvalues ​​and their corresponding eigenvectors sorted by importance. The larger the eigenvalue, the higher the variance contribution of the data in the direction of the eigenvector. The preset eigenvalue threshold is 1, which means that only principal components with a variance contribution greater than 1 (i.e., eigenvectors with eigenvalues ​​≥ 1) are retained. These principal components can explain the variation information in the data that exceeds the average level, while eliminating components with eigenvalues ​​< 1 can remove low-variance noise or redundant features. Finally, the filtered eigenvectors are combined into a dimensionality reduction feature matrix and matrix multiplication is performed with the standardized test data to project the original high-dimensional data into a low-dimensional space to form a compressed initial feature data set, thereby achieving data dimensionality reduction and key feature extraction.

[0030] It's worth noting that in circuit board performance testing, an example of constructing an initial parameter set is as follows: When testing a multi-layer circuit board, if the initial feature dataset includes dimensions such as on-resistance, insulation resistance, solder joint impedance, dielectric constant, and dielectric loss, the test parameters corresponding to these dimensions must be extracted and combined into a parameter set. For example, on-resistance corresponds to a key parameter in circuit connectivity testing, used to determine whether there are open or short circuits; insulation resistance reflects the insulation performance between layers or between a circuit and ground; solder joint impedance assesses soldering quality by measuring the resistance of the solder joint after reflow soldering; and dielectric constant and dielectric loss reflect the impact of the substrate on signal transmission through high-frequency signal testing (such as VNA measurements). By categorizing these parameters according to their physical properties and test objectives, an initial parameter set (e.g., {on-resistance, insulation resistance, solder joint impedance, dielectric constant, dielectric loss}) is formed, providing basic data support for subsequent redundancy analysis and key performance indicator screening.

[0031] In step S12, parameter correlation analysis is performed based on the initial feature data set to obtain a quantitative correlation matrix.

[0032] In one embodiment, a covariance calculation is performed based on the initial feature data set to obtain a feature covariance; Calculating the standard deviation of the initial feature data set to obtain a feature standard deviation; Calculate parameter correlation based on the characteristic covariance and the characteristic standard deviation to obtain a correlation coefficient; A symmetric matrix is ​​constructed according to the correlation coefficient to obtain a quantized correlation matrix.

[0033] It is worth noting that the covariance between each pair of parameters in the initial feature dataset is first calculated to reflect their linear correlation trends. Covariance is calculated by calculating the product of the deviations of each pair of parameters (e.g., on-resistance and insulation resistance) from their respective means. The sum of these products is then divided by the sample size minus one. Next, the standard deviation is calculated for each parameter individually. This is done by first taking the sum of the squares of the deviations of each observation from the mean, then taking the average and taking the square root. This measures the dispersion of the parameter. Finally, the covariance result is divided by the product of the two parameter standard deviations to obtain the standardized Pearson correlation coefficient. This coefficient ranges from -1 to 1. Values ​​closer to 1 or -1 indicate a stronger linear relationship between the parameters, while values ​​closer to 0 indicate virtually no linear correlation. This process eliminates dimension effects and transforms the raw covariance into a directly comparable correlation measure, thus providing a basis for constructing a quantitative correlation matrix.

[0034] It's worth noting that in circuit board performance testing, the core of parameter correlation analysis is to quantify the strength of the linear relationship between pairwise parameters using the Pearson correlation coefficient. To perform the calculation, the standardized feature data sets are first paired together, and their covariances and respective standard deviations are calculated. Finally, the correlation coefficient is calculated by dividing the covariance by the product of the two parameter standard deviations. When the absolute value of the correlation coefficient is ≥0.7, a strong correlation is determined between the parameters. For example, on-resistance and solder joint impedance can show a high positive correlation due to soldering process defects. The correlation coefficients of all parameter pairs are tabulated row by row to form a symmetric matrix, known as a quantitative correlation matrix (e.g., a 3×3 matrix containing three coefficients: on-resistance-insulation resistance, on-resistance-solder joint impedance, and insulation resistance-solder joint impedance). This matrix intuitively reflects the distribution of correlation strengths between parameters, providing a basis for subsequent redundant parameter elimination and key indicator screening.

[0035] In step S13, redundancy analysis is performed based on the quantization correlation matrix and the initial parameter set to obtain a simplified parameter set.

[0036] In one implementation, a parameter business scenario is obtained; When the correlation coefficient in the quantized correlation matrix is ​​greater than a preset correlation threshold, it is determined that there is a strong correlation between the parameters; Performing redundancy determination on strongly associated parameters according to the parameter business scenarios, determining strongly associated parameters with overlapping business scenarios as redundant parameters, and removing them from the initial parameter set; After completing the redundancy determination of all strongly associated parameters, the remaining parameters in the initial parameter set constitute a reduced parameter set.

[0037] It is worth noting that the correlation threshold is set at 0.7. When the correlation coefficient is greater than or equal to 0.7, it is considered a strong correlation. When it is less than 0.7, no special treatment is performed.

[0038] It is worth noting that in the performance test of circuit boards, the core of redundancy analysis is to screen strongly correlated parameters in combination with business scenarios. Specifically, the storage and retrieval of business scenarios are achieved through a preset parameter classification system. For example, in the test system, each parameter (such as on-resistance, solder joint impedance, dielectric constant Dk) is bound to its own business scenario label (such as "connectivity detection", "welding quality assessment", "high-frequency signal transmission"). For example, on-resistance and solder joint impedance both belong to the "connectivity detection" scenario, while Dk and Df belong to the "high-frequency signal transmission" scenario. These associations can be stored in database tables or metadata files, and business scenarios can be quickly matched by reading parameter labels during testing. Among them, Dk represents the dielectric constant and Df represents the dissipation factor.

[0039] It is worth noting that the overlap of business scenarios refers to the duplication of functions of multiple parameters due to measuring the same physical phenomenon or serving the same test target. For example, both on-resistance and solder joint impedance are used to evaluate line connectivity. If the correlation coefficient of the two in the quantitative correlation matrix is ​​≥0.7 (preset threshold), it means that their test results are highly consistent, reflecting the same defect (such as solder joint). At this time, redundancy needs to be further determined based on the business scenario: if both parameters belong to the "connectivity detection" scenario, then one (such as on-resistance) is retained and the other (solder joint impedance) is eliminated because of its information overlap; if the parameters belong to different scenarios (such as on-resistance belongs to "connectivity detection" and Dk belongs to "high-frequency signal transmission"), even if the correlation is high, both need to be retained because they serve different test dimensions.

[0040] It's worth noting that the elimination criteria are: 1) the parameter pair correlation coefficient ≥ a threshold (e.g., 0.7); 2) the parameter business scenarios are identical or highly overlapping; and 3) the elimination does not affect the integrity of the test objective. For example, in connectivity testing, if the on-resistance already covers both open and short circuit issues, redundant information about solder joint impedance can be eliminated. However, if solder joint impedance is also used to assess soldering process stability (e.g., reflow soldering temperature profile), it must be retained. Ultimately, the parameter set is streamlined to retain only the non-redundant key parameters (e.g., {on-resistance, Dk, Df}) that cover all business scenarios, thereby improving test efficiency and reducing data processing complexity.

[0041] In step S14, data cleaning is performed on the circuit board test data according to the simplified parameter set, and factor analysis is performed to obtain a factor loading matrix.

[0042] In one embodiment, the circuit board test data is traversed, and data dimensions that are not in the simplified parameter set are deleted to obtain first simplified data; Eliminate outliers based on the first simplified data to obtain cleaned second simplified data; Performing principal component analysis on the second simplified data to obtain simplified eigenvalues ​​and simplified eigenvectors; The factor loading vector is calculated using the following formula: in, represents the factor loading vector, express The simplified eigenvalues, express The simplified eigenvalue corresponding to the simplified eigenvalue is The number representing the reduced eigenvalue; The factor loading matrix is ​​obtained by performing horizontal connection according to the factor loading vectors.

[0043] It is worth noting that when removing outliers from the first reduced data, a median-based outlier detection method is used. The specific steps are as follows: Sort all values ​​in the first reduced data from smallest to largest and find the middle value as the median. If the total number of data points is even, take the average of the two middle values ​​as the median. The median reflects the central tendency of the data and is insensitive to extreme values. For each data point, calculate the absolute value of the difference between it and the median to form a new set of difference data. Sort the absolute values ​​of all differences again by size and find the median. This median is the mean average deviation (MAD), which measures the typical deviation of data points from the median in the dataset. Set the deviation threshold to three times the MAD. Iterate through all data points and determine if the absolute difference between a data point and the median exceeds the threshold. These outliers are removed from the first reduced data, and the remaining data constitutes the cleaned second reduced data.

[0044] It is worth noting that each variable in the second reduced data set was standardized to eliminate dimensional differences. Specifically, the mean of each variable was subtracted from its original value and then divided by its standard deviation, ensuring that all variables were compared on the same scale. The covariance matrix was then calculated using the standardized data. The covariance matrix was then input into a mathematical tool (such as a linear algebra algorithm) to calculate its eigenvalues ​​and corresponding eigenvectors. Eigenvalues ​​represent the amount of variance explained by each principal component, while eigenvectors describe the direction of the principal component. The principal components were sorted by eigenvalue, retaining the top k eigenvalues ​​and their corresponding eigenvectors (k is the dimension after dimensionality reduction) with the largest explained variance. For example, if the eigenvalues ​​of the covariance matrix, ranked from largest to smallest, were 3.2, 1.5, and 0.8, and the cumulative variance contribution (the sum of the first two eigenvalues ​​to the total variance) reached 85%, the first two eigenvalues, 3.2 and 1.5, were selected as the reduced eigenvalues, and their corresponding eigenvectors were used as the reduced eigenvectors. Finally, the selected eigenvalues ​​and eigenvectors were used as the results of the principal component analysis.

[0045] It is worth noting that factor loading vectors can be calculated by combining the reduced eigenvalues ​​and reduced eigenvectors obtained from principal component analysis. Specifically, the square root of each reduced eigenvalue is multiplied by the corresponding reduced eigenvector to produce a set of new vectors that describe the strength of the association between the original variables and the principal components. Subsequently, the factor loading vectors of all principal components are concatenated horizontally, column by column, to form a factor loading matrix. The core purpose of this process is to quantify the relationship between the principal components after data dimensionality reduction and the original variables, thereby revealing which original variables have a greater and lesser influence on the principal components. The factor loading value itself reflects the degree of correlation between the original variable and the principal component. A larger value indicates a higher weight for the variable in the corresponding principal component. This provides a more intuitive interpretation of the actual meaning of the principal components and provides a basis for subsequent data analysis, model optimization, or variable screening.

[0046] In step S15, main factors are extracted according to the factor loading matrix, and parameter contribution rate analysis is performed according to the obtained main factor set to obtain a key performance indicator set.

[0047] In one embodiment, a simplified eigenvalue and a second simplified data of each column of the factor loading matrix are obtained; When the simplified eigenvalue is less than the preset main factor threshold, the corresponding factor loading vector is eliminated; When the simplified eigenvalue is greater than or equal to the main factor threshold, the corresponding factor loading vector is retained and added to the main factor set; Multiplying each factor loading vector in the main factor set by the second reduced data to obtain a main factor score; Calculating score variance based on the main factor scores; Divide the square of the main factor score by the score variance to obtain the factor contribution rate; When the factor contribution rate is greater than a preset contribution rate threshold, the parameter corresponding to the factor loading vector is included in the key performance indicator set.

[0048] It is worth noting that the main factor threshold is 1. The contribution rate threshold is 10%.

[0049] It is worth noting that in the performance testing of printed circuit boards (PCBs / PCBAs), a set of key performance indicators (KPIs) uses factor loading matrices and contribution rate analysis to identify the core parameters that most significantly impact the functionality, reliability, or quality of the PCB, providing data support for industrial data analysis, production optimization, troubleshooting, and quality control. The specific method includes: first, extracting the principal factors based on the factor loading matrix, eliminating redundant parameters with eigenvalues ​​below a preset threshold (such as scratch depth in non-critical areas), and retaining high-contribution principal factors (such as impedance, insulation resistance, and salt spray corrosion rate). The principal factor scores and variances are then calculated, and parameter importance is determined by the factor contribution rate (the square of the principal factor score divided by the variance). Only parameters with a contribution rate above a set threshold (such as 10%) are included in the KPI set. For example, in electrical performance testing, if the "impedance value" deviates from the design range (±5%) or the "insulation resistance" leakage current exceeds 1μA, the circuit design or insulation layer process needs to be adjusted. In environmental adaptability testing, if the salt spray corrosion rate exceeds 0.1mm / year, the solder mask hardness or surface treatment process needs to be optimized. In mechanical reliability testing, if the solder joint detachment rate exceeds 1%, vibration resistance can be improved by optimizing the reflow temperature profile or adding glue fixation. Ultimately, the key performance indicator set focuses on high-contribution parameters (such as ionic contamination ≤ 6.45μg / cm² and solder joint thrust value ≥ 0.5N / mm²).

[0050] In step S16, entropy weight optimization is performed according to the key performance indicator set to obtain a final performance indicator set.

[0051] In one embodiment, information entropy is calculated based on the key performance indicator set to obtain indicator information entropy; Obtain the initial weight of the indicator according to the inverse of the indicator information entropy; Performing weighted summation on each key performance indicator according to the initial weight of the indicator to obtain a comprehensive confidence level of the indicator; When the comprehensive confidence of the indicator is less than the preset confidence threshold, the corresponding performance indicator is eliminated; When the comprehensive confidence of the indicator is greater than or equal to the confidence threshold, retaining the corresponding performance indicator; After completing the traversal of all indicators, the final performance indicator set is obtained.

[0052] It's worth noting that calculating information entropy and determining initial weights based on a set of key performance indicators (KPIs) first requires normalizing the KPI data to ensure they are consistent in dimension and range. For example, if the test data for a KPI consists of multiple sample values ​​(such as impedance or insulation resistance), these values ​​must be normalized to the interval [0, 1] to eliminate dimensional differences. Next, for each KPI, its proportion among all samples is calculated (i.e., the proportion of each sample value to the total value of that KPI), thereby forming a probability distribution. Information entropy is then calculated based on these proportions: if the sample values ​​for a particular KPI are more evenly distributed (i.e., the proportions of all samples are similar), its information entropy is higher, indicating that the KPI has weaker discriminative power for the dataset. Conversely, if the sample values ​​vary significantly (e.g., some samples have extremely high proportions), its information entropy is lower, indicating that the KPI has stronger discriminative power. Finally, the inverse of the information entropy of each KPI is used as its initial weight: indicators with lower information entropy (i.e., greater data variance) have higher inverses and greater weights; conversely, indicators with higher information entropy (i.e., more evenly distributed data) have lower inverses and lower weights. This process converts the importance of key performance indicators into calculable weight values ​​by quantifying the discreteness of the data, providing a basis for subsequent analysis or optimization.

[0053] It is worth noting that the confidence threshold is 0.85.

[0054] It's worth noting that the weighted sum is the sum of the standardized test values ​​of each key performance indicator multiplied by its initial weight. For example, if the impedance value (normalized to 0.9), insulation resistance (0.85), and solder joint thrust value (0.8) of a circuit board have weights of 0.3, 0.4, and 0.3, respectively, the combined confidence level is (0.9 × 0.3) + (0.85 × 0.4) + (0.8 × 0.3) = 0.27 + 0.34 + 0.24 = 0.85. This value reflects the combined performance of all core indicators within the overall performance, with higher values ​​indicating more reliable quality. Ultimately, if the combined confidence level falls below a preset threshold (e.g., if 0.85 < 0.85, the indicator is removed), it indicates that the indicator fails to meet quality requirements under the current process and must be removed from the set. If it reaches or exceeds the threshold (e.g., if 0.85 ≥ 0.85, it is retained), the indicator is considered valid. Through this process, the core parameters that have the greatest impact on the performance of the circuit board and meet the process requirements can be dynamically screened out to form a final set of performance indicators, providing an accurate basis for subsequent optimization.

[0055] In summary, the present invention discloses a performance testing method for a circuit board, which revolves around industrial data analysis and aims to improve the accuracy and efficiency of traditional testing methods in a multi-dimensional parameter environment. The method first collects circuit board test data and performs feature extraction to form an initial feature data set and an initial parameter set, providing a structured data basis for subsequent analysis. On this basis, industrial data analysis technology is used to quantitatively evaluate the correlation between the parameters, construct a quantitative correlation matrix, identify the dependency and coupling mechanism between the parameters, thereby improving the scientific nature and computational efficiency of parameter screening. Subsequently, redundancy analysis is performed based on the matrix to eliminate repeated or highly correlated parameters to obtain a more representative streamlined parameter set, effectively reducing the data dimension and significantly improving the efficiency of subsequent modeling and cleaning while retaining key information. Next, the streamlined parameters are processed using a factor analysis method to generate a factor loading matrix, further enhancing the structurality and explanatory power of the data and laying a mathematical foundation for extracting the main influencing factors. By performing eigenvalue decomposition and variance contribution analysis on the factor loading matrix, we extract the principal factors and calculate their contribution to overall performance. This allows us to determine a set of key performance indicators, efficiently mapping raw data to core indicators and improving the accuracy and interpretability of performance evaluation. Finally, we employ an entropy weight optimization method to assign weights and calculate confidence levels for key performance indicators, resulting in a final set of performance indicators that enhances the stability and objectivity of the evaluation results. This entire process, tightly integrated with industrial data analysis concepts, strengthens data-driven capabilities during circuit board performance testing and enhances the ability to respond to and interpret quality fluctuations in complex manufacturing environments.

[0056] Reference Figure 2 A second embodiment of the present invention provides a circuit board performance testing system, comprising: The data acquisition module is used to obtain circuit board test data and perform feature extraction to obtain an initial feature data set and an initial parameter set; A correlation analysis module, configured to perform parameter correlation analysis based on the initial feature data set to obtain a quantitative correlation matrix; a redundancy elimination module, configured to perform redundancy analysis based on the quantization correlation matrix and the initial parameter set to obtain a streamlined parameter set; A factor analysis module, configured to perform data cleaning on the circuit board test data according to the simplified parameter set, and perform factor analysis to obtain a factor loading matrix; A key indicator module is used to extract main factors according to the factor loading matrix, and perform parameter contribution rate analysis based on the obtained main factor set to obtain a key performance indicator set; The entropy weight optimization module is used to perform entropy weight optimization according to the key performance indicator set to obtain a final performance indicator set.

[0057] It should be noted that the performance testing system for a circuit board provided in an embodiment of the present invention is used to execute all the process steps of the performance testing method for a circuit board in the above embodiment. The working principles and beneficial effects of the two correspond one to one, and therefore will not be described in detail.

[0058] An embodiment of the present invention further provides an electronic device. The electronic device includes: a processor, a memory, and a computer program stored in the memory and executable on the processor, such as a data acquisition program. When the processor executes the computer program, the steps in the above-mentioned circuit board performance test method embodiments are implemented, such as Figure 1 Alternatively, when the processor executes the computer program, the functions of the modules / units in the above-mentioned device embodiments are realized, such as the data acquisition module.

[0059] Exemplarily, the computer program may be divided into one or more modules / units, which are stored in the memory and executed by the processor to implement the present invention. The one or more modules / units may be a series of computer program instruction segments capable of implementing specific functions, and the instruction segments are used to describe the execution process of the computer program in the electronic device.

[0060] The electronic device may be a computing device such as a desktop computer, notebook, PDA, or smart tablet. The electronic device may include, but is not limited to, a processor and memory. Those skilled in the art will appreciate that the aforementioned components are merely examples of electronic devices and do not constitute a limitation of the electronic device. The electronic device may include more or fewer components than those described above, or a combination of certain components, or different components. For example, the electronic device may also include input / output devices, network access devices, buses, and the like.

[0061] The processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor. The processor is the control center of the electronic device and connects various parts of the entire electronic device using various interfaces and lines.

[0062] The memory can be used to store the computer programs and / or modules. The processor implements the various functions of the electronic device by running or executing the computer programs and / or modules stored in the memory and accessing the data stored in the memory. The memory may primarily include a program storage area and a data storage area. The program storage area may store an operating system and at least one application required for a function (such as a sound playback function or an image playback function); the data storage area may store data generated based on the use of the mobile phone (such as audio data, a phone book, etc.). Furthermore, the memory may include high-speed random access memory and non-volatile memory, such as a hard disk, internal memory, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, at least one disk storage device, a flash memory device, or other volatile solid-state storage device.

[0063] If the module / unit integrated into the electronic device is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention can implement all or part of the process steps in the above-mentioned method embodiments by using a computer program to instruct the relevant hardware. The computer program can be stored in a computer-readable storage medium. When executed by a processor, the computer program can implement the steps of each of the above-mentioned method embodiments. The computer program includes computer program code, which can be in source code form, object code form, executable file, or some intermediate form. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal, and software distribution medium. It should be noted that the content of the computer-readable medium can be appropriately increased or decreased based on the requirements of legislation and patent practice in a jurisdiction. For example, in some jurisdictions, based on legislation and patent practice, computer-readable media does not include electric carrier signals and telecommunication signals.

[0064] It should be noted that the device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed across multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment. In addition, in the drawings of the device embodiments provided by the present invention, the connection relationship between the modules indicates that there is a communication connection between them, which may be specifically implemented as one or more communication buses or signal lines. A person of ordinary skill in the art can understand and implement the present invention without inventive effort.

[0065] The specific embodiments described above further illustrate the objectives, technical solutions, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A performance testing method for a circuit board, characterized in that: include: Obtain circuit board test data and perform feature extraction to obtain an initial feature data set and an initial parameter set; Performing parameter correlation analysis based on the initial feature data set to obtain a quantitative correlation matrix; Performing redundancy analysis on the quantized correlation matrix and the initial parameter set to obtain a simplified parameter set; Performing data cleaning on the circuit board test data according to the simplified parameter set, and performing factor analysis to obtain a factor loading matrix; Extracting principal factors according to the factor loading matrix, and performing parameter contribution rate analysis based on the obtained principal factor set to obtain a set of key performance indicators; Entropy weight optimization is performed according to the key performance indicator set to obtain a final performance indicator set.

2. The performance testing method of a circuit board according to claim 1, characterized in that: The circuit board test data is obtained and feature extraction is performed to obtain an initial feature data set and an initial parameter set, including: Standardize the circuit board test data to obtain standardized test data; Performing covariance calculation based on the standardized test data to obtain a covariance matrix; Performing eigenvalue decomposition according to the covariance matrix to obtain eigenvalues ​​and corresponding eigenvectors; When the eigenvalue is greater than or equal to a preset eigenvalue threshold, the corresponding eigenvector is retained and added to the dimension-reduced feature matrix; When the eigenvalue is less than the eigenvalue threshold, eliminating the eigenvalue and the corresponding eigenvector; Performing matrix multiplication on the dimension-reduced feature matrix and the standardized test data to obtain an initial feature data set; An initial parameter set is formed according to the test parameters corresponding to each dimension of the initial feature data set.

3. The performance testing method of a circuit board according to claim 1, characterized in that: The performing parameter correlation analysis based on the initial feature data set to obtain a quantitative correlation matrix includes: Performing covariance calculation based on the initial feature data set to obtain feature covariance; Calculating the standard deviation of the initial feature data set to obtain a feature standard deviation; Calculate parameter correlation based on the characteristic covariance and the characteristic standard deviation to obtain a correlation coefficient; A symmetric matrix is ​​constructed according to the correlation coefficient to obtain a quantized correlation matrix.

4. The performance testing method of a circuit board according to claim 1, characterized in that: The performing redundancy analysis based on the quantization correlation matrix and the initial parameter set to obtain a simplified parameter set includes: Get parameter business scenarios; When the correlation coefficient in the quantized correlation matrix is ​​greater than a preset correlation threshold, it is determined that there is a strong correlation between the parameters; Performing redundancy determination on strongly associated parameters according to the parameter business scenarios, determining strongly associated parameters with overlapping business scenarios as redundant parameters, and removing them from the initial parameter set; After completing the redundancy determination of all strongly associated parameters, the remaining parameters in the initial parameter set constitute a reduced parameter set.

5. The performance testing method of a circuit board according to claim 1, characterized in that: The circuit board test data is cleaned according to the simplified parameter set, and factor analysis is performed to obtain a factor loading matrix, including: Traversing the circuit board test data, deleting data dimensions that are not in the simplified parameter set, and obtaining first simplified data; Eliminate outliers based on the first simplified data to obtain cleaned second simplified data; Performing principal component analysis on the second simplified data to obtain simplified eigenvalues ​​and simplified eigenvectors; The factor loading vector is calculated using the following formula: in, represents the factor loading vector, express The simplified eigenvalues, express The simplified eigenvalue corresponding to the simplified eigenvalue is The number representing the reduced eigenvalue; The factor loading matrix is ​​obtained by performing horizontal connection according to the factor loading vectors.

6. The performance testing method of a circuit board according to claim 1, characterized in that: The principal factors are extracted according to the factor loading matrix, and parameter contribution rate analysis is performed according to the obtained principal factor set to obtain a set of key performance indicators, including: Obtain the simplified eigenvalue and the second simplified data of each column of the factor loading matrix; When the simplified eigenvalue is less than the preset main factor threshold, the corresponding factor loading vector is eliminated; When the simplified eigenvalue is greater than or equal to the main factor threshold, the corresponding factor loading vector is retained and added to the main factor set; Multiplying each factor loading vector in the main factor set by the second reduced data to obtain a main factor score; Calculating score variance based on the main factor scores; Divide the square of the main factor score by the score variance to obtain the factor contribution rate; When the factor contribution rate is greater than a preset contribution rate threshold, the parameter corresponding to the factor loading vector is included in the key performance indicator set.

7. The performance testing method of a circuit board according to claim 1, characterized in that: The entropy weight optimization is performed according to the key performance indicator set to obtain a final performance indicator set, including: Calculate information entropy based on the key performance indicator set to obtain indicator information entropy; Obtain the initial weight of the indicator according to the inverse of the indicator information entropy; Performing weighted summation on each key performance indicator according to the initial weight of the indicator to obtain a comprehensive confidence level of the indicator; When the comprehensive confidence of the indicator is less than the preset confidence threshold, the corresponding performance indicator is eliminated; When the comprehensive confidence of the indicator is greater than or equal to the confidence threshold, retaining the corresponding performance indicator; After completing the traversal of all indicators, the final performance indicator set is obtained.

8. A performance test system for a circuit board, characterized in that: include: The data acquisition module is used to obtain circuit board test data and perform feature extraction to obtain an initial feature data set and an initial parameter set; A correlation analysis module, configured to perform parameter correlation analysis based on the initial feature data set to obtain a quantitative correlation matrix; a redundancy elimination module, configured to perform redundancy analysis based on the quantization correlation matrix and the initial parameter set to obtain a streamlined parameter set; A factor analysis module, configured to perform data cleaning on the circuit board test data according to the simplified parameter set, and perform factor analysis to obtain a factor loading matrix; A key indicator module is used to extract main factors according to the factor loading matrix, and perform parameter contribution rate analysis based on the obtained main factor set to obtain a key performance indicator set; The entropy weight optimization module is used to perform entropy weight optimization according to the key performance indicator set to obtain a final performance indicator set.

9. An electronic device, characterized in that: The method comprises a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein when the processor executes the computer program, the method for testing the performance of the circuit board according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium includes a stored computer program, wherein when the computer program is executed, the device where the computer-readable storage medium is located is controlled to execute the performance testing method for the circuit board according to any one of claims 1 to 7.