Multi-fidelity micro-architecture design space optimization method based on partial order prediction

Abstract

The invention discloses a multi-fidelity micro-architecture design space optimization method based on partial order prediction, and the method comprises the following steps: selecting parameters which affect a target optimization PPA index from micro-architecture parameters, and constructing an SOC design space # imgabs0 # initialization multi-fidelity data set; constructing a non-linear multi-fidelity Gaussian agent model, and improving the final high-fidelity agent model by using the maximum expected hyper-volume; constructing and training a logistic regression function; after a new sampling design point is obtained, an EDA simulation tool is used for architecture level simulation so as to obtain low-fidelity index data, and whether the next fidelity needs to be entered or not is judged based on partial order prediction; and performing iterative optimization to obtain a Pareto optimal solution. According to the method, partial order prediction, fidelity modeling and multi-target Bayesian optimization are organically integrated, an efficient exploration system suitable for a complex micro-architecture DSE task is formed, and high practicability, universality and expandability are achieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of micro-architecture space design, and in particular relates to a multi-fidelity micro-architecture design space optimization method based on partial order prediction. Background Art

[0002] The current EDA (Electronic Design Automation) simulation process typically includes multiple stages, including the architecture, RTL (register-transfer level), and netlist levels. Simulation fidelity increases with each stage, but the time and computing resources required also increase significantly, increasing from minutes to hours or even days. While the latter stages can provide highly accurate simulation results, they are extremely time-consuming, making it difficult to fully evaluate the entire design space within a limited time budget. Early stages offer rapid evaluation, but lack accuracy, which can easily mislead target design selection and lead to missing the optimal design. Therefore, relying solely on simulation results from a single stage (whether low-fidelity or high-fidelity) struggles to balance efficiency and accuracy. Furthermore, with small sample sizes, it's difficult to effectively model design parameters and target performance metrics, resulting in inefficient and risky design space exploration.

[0003] Currently, actual development processes still rely on late-stage high-fidelity simulations to evaluate the actual performance of designs, even though this increases the time cost of the development process. Therefore, some researchers are researching multi-fidelity optimization techniques, hoping to accelerate the optimization process by leveraging early, low-fidelity data. However, existing methods lack heuristic decision logic between different fidelities, making it difficult to balance optimization accuracy and efficiency, resulting in wasted time or missed optimal solutions. For example:

[0004] (1) EffBO first introduces a nonlinear Gaussian process model to learn the complex mapping relationship between low and high fidelity, and jointly models the correlation between multiple objective functions, thereby improving the modeling accuracy. Then, the expected improvement function (EI) is used to find the next round of sampling points in the parameter space. Afterwards, based on the prediction uncertainty of the point in the current model, it is determined whether high-fidelity evaluation is needed. The main disadvantage of this method is that its multi-fidelity strategy is only based on the current model uncertainty of the sampling point, and lacks heuristic analysis of fidelity selection. At the same time, this method only achieves the optimization of a single target, which is difficult to deal with complex multi-target problems such as microarchitecture design.

[0005] (2) CorrelatMF also uses a nonlinear Gaussian model for modeling and adds the time cost of simulations at different fidelity levels as an additional weight to the acquisition function, thereby selecting fidelity while also selecting new sampling points. Although this solution takes resource consumption into account, it still has shortcomings: it only uses time cost as the fidelity weight, ignores the relationship between sorting reversal and optimization potential, and does not analyze its sorting stability under different fidelity levels.

[0006] (3) The TrustMF method directly introduces simulation fidelity as an additional input parameter into the design parameter space, constructs a unified Gaussian process model, and introduces a "trust" function as a weighted term of the sampling function to control the sampling preference for data of different fidelity. This trust represents an estimate of the accuracy of the simulation results of each fidelity, which is used to balance simulation accuracy and resource overhead. During the optimization process, TrustMF uses a fixed form function (such as the tan function) to approximate the trust, but this method has significant defects: on the one hand, the error patterns and ranking characteristics between fidelity under different problems vary greatly, and the fixed trust function lacks universality and adaptability and is prone to failure; on the other hand, this method does not explicitly determine whether the candidate design points may have a ranking reversal under different fidelity, and cannot accurately control the triggering conditions of high-fidelity simulation, which can easily lead to waste of simulation resources or misscreening of optimal solutions. Summary of the Invention

[0007] In order to make up for the shortcomings of the existing technology, the present invention provides a multi-fidelity microarchitecture design space optimization method based on partial order prediction to solve the problems existing in the current microarchitecture design space exploration, such as high simulation resource cost and insufficient inspiration of fidelity selection strategy.

[0008] The technical problems to be solved by the present invention can be achieved through the following specific solutions:

[0009] The multi-fidelity microarchitecture design space optimization method based on partial order prediction includes the following steps:

[0010] Step 1: Select parameters that affect the target optimization PPA index from the microarchitecture parameters and build the SOC (System on Chip) design space

[0011] Step 2: Initialize the multi-fidelity dataset;

[0012] Step 3: Build a nonlinear multi-fidelity Gaussian proxy model and use maximum expected hypervolume improvement on the final high-fidelity proxy model;

[0013] Step 4: Build and train the logistic regression function;

[0014] Step 5: After obtaining the new sampling design point, use EDA simulation tools to perform architecture-level simulation to obtain low-fidelity indicator data. Based on the partial order prediction, determine whether to enter the next fidelity level.

[0015] Step 6: Iterate and optimize to obtain the Pareto optimal solution.

[0016] Furthermore, in step 2, first, from the design space Randomly select design points from the dataset to form the initial low-fidelity data set X arch , use EDA simulation tools to perform architecture-level simulation and obtain low-fidelity indicator data set Y arch ; Then, from X arch Randomly select design points to form the initial medium-fidelity data set X RTL , use EDA simulation tools to perform RTL level simulation and obtain the medium fidelity index data set Y RTL ; Finally, from X RTL Randomly select design points from the dataset to form the initial high-fidelity data set X netlist , use EDA simulation tools to perform netlist level simulation and obtain high-fidelity index data set Y netlist ; and datasets of different fidelity always satisfy relationship.

[0017] Furthermore, the specific content of step 3 is: first, using the low-fidelity dataset (X arch ,Y arch ) Train a low-fidelity Gaussian proxy model GP l (.); Then, use [(X RTL ,GP l (X RTL )),Y RTL ] Train a medium-fidelity Gaussian surrogate model GP that incorporates low-fidelity data m (.); Finally, use [(X netlist ,GP m (X netlist )),Y netlist ] Train a high-fidelity Gaussian surrogate model GP that combines low- and medium-fidelity data h (.), and use this as the final fusion Gaussian proxy model; the maximum expected hypervolume improved sampling function is used on the final high-fidelity proxy model to guide the next step of exploration and select the most promising new sampling point x * , the specific sampling function is:

[0018]

[0019] Furthermore, in step 4, using (Yarch ,Y netlist ) and (Y RTL ,Y netlist ) data to construct and train the logistic regression function for the three PPA indicators, where the logistic regression function is in the form of:

[0020]

[0021] in, Represents the absolute value of the difference between the mth index of any two points in the i-th fidelity architecture. If the size of the index of the two points in the current fidelity architecture is the same as that in the high fidelity, the value of the logistic regression is 1, otherwise the output is 0.

[0022] Furthermore, in step 5, the partial order prediction judgment logic is: using the trained logistic regression function Three PPA indicators that predict the current fidelity of the new sampling point Three PPA indicators with the current Pareto point Whether there will be a reversal under high fidelity; first perform the lowest fidelity simulation, input the lowest fidelity value of the new sampling point and the value of the current Pareto point into the corresponding logistic regression model to determine whether the partial order relationship between the new sampling point and the current Pareto point will change under the current fidelity and the highest fidelity; if there is a change in the partial order relationship between the new sampling point and a current Pareto point, it is considered that the new sampling point cannot be reasonably evaluated under the current fidelity, and it is necessary to enter the next fidelity simulation, and continue the above judgment after the simulation until the highest fidelity is reached or no partial order reversal occurs; if it is judged that the new sampling point is not dominated by the current Pareto point, then the sampling point is considered to be a new Pareto point, which is a potential design point and needs to enter the next fidelity, otherwise the fidelity selection is terminated.

[0023] Furthermore, in step 6, the sampling data set is updated according to the selected fidelity level. After each iteration, it is checked whether the current sampling and optimization process has exceeded the set time budget; if not, return to step 3 and continue optimization; if it exceeds the budget, proceed to the next step; after completing sufficient optimization within the budget, the final Pareto optimal solution set is obtained.

[0024] Compared with the prior art, the present invention has the following advantages:

[0025] (1) The present invention organically integrates partial order prediction, fidelity modeling and multi-objective Bayesian optimization to form an efficient exploration system suitable for complex micro-architecture DSE tasks, which has strong practicality, versatility and scalability. Based on the nested Gaussian process, a nonlinear mapping relationship between different simulation stages (such as architecture level, RTL level, Netlist level) is constructed, and different fidelity data are integrated to form a unified proxy model to support multi-objective performance estimation and optimization guidance under the condition of incomplete high-fidelity simulation; using expected hypervolume improvement (EHVI) as a multi-objective sampling function, combined with a nonlinear proxy model, the Pareto expansion potential of unsampled design points is evaluated in each round of optimization, guiding the priority exploration of high-value points, thereby accelerating optimization convergence in multi-objective scenarios.

[0026] (2) The present invention evaluates the partial order consistency of candidate design points and the current Pareto point in each round of optimization, and dynamically decides whether to enter the high-fidelity simulation stage based on the reversal probability and boundary dominance, thereby realizing refined scheduling and conservation of simulation resources; that is, by predicting whether a candidate design point is likely to produce a reversal in order with the current Pareto solution under high-fidelity data, it decides whether to perform a more expensive high-fidelity simulation, thereby minimizing unnecessary resource overhead while ensuring the accuracy of the final result. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Flow chart of the method of the present invention;

[0028] Figure 2 This is a flow chart of the EDA tool of the present invention;

[0029] Figure 3 This is a pseudo code diagram of the partial order prediction process of the present invention;

[0030] Figure 4 This is a design space distribution diagram in an embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0032] like Figure 1 As shown, a multi-fidelity microarchitecture design space optimization method based on partial order prediction includes the following steps:

[0033] Step 1: Select parameters that affect the target optimization PPA index from the microarchitecture parameters and build the SOC (System on Chip) design space

[0034] Based on prior engineering experience, we select important parameters that have an impact on the target optimization PPA (power, area, performance) indicators from a large number of microarchitecture parameters. For example, in the BOOM microarchitecture design optimization problem, we select 20 parameters including FetchWidth and DecodeWidth, and determine the candidate range of each parameter as the design space for subsequent optimization exploration.

[0035] This application uses the BOOM (Berkeley Out-of-Order Machine) microarchitecture as the experimental object, with the goal of exploring its multi-objective optimal design configuration, including performance (cycle count), power consumption, and area, under a limited simulation budget. Due to the limited overall simulation time budget, the architecture level, RTL level, and netlist level in the VLSI process are selected as the three fidelity levels for research. The specific EDA tool process is as follows Figure 2 shown.

[0036] Step 2: Initialize the multi-fidelity dataset.

[0037] In one embodiment, first, from the design space Randomly select 30 design points from the dataset to form the initial low-fidelity data set X arch , use EDA simulation tools to perform architecture-level simulation and obtain low-fidelity indicator data set Y arch ; Then, from X arch Randomly select 15 design points to form the initial medium-fidelity data set X RTL , use EDA simulation tools to perform RTL level simulation and obtain the medium fidelity index data set Y RTL ; Finally, from X RTL Randomly select 2 design points from the dataset to form the initial high-fidelity data set X netlist , use EDA simulation tools to perform netlist level simulation and obtain high-fidelity index data set Y netlist . Note that datasets of different fidelity always satisfy relationship.

[0038] Step 3: Build a nonlinear multi-fidelity Gaussian proxy model and use maximum expected hypervolume improvement on the final high-fidelity proxy model.

[0039] First, using a low-fidelity dataset (X arch ,Y arch ) Train a low-fidelity Gaussian proxy model GP l (.); Afterwards, use [(X RTL ,GP l (X RTL )),Y RTL] Train a medium-fidelity Gaussian surrogate model GP that incorporates low-fidelity data m (.); Finally, use [(X netlist ,GP m (X netlist )),Y netlist ] Train a high-fidelity Gaussian surrogate model GP that combines low- and medium-fidelity data h (.), and use it as the final fusion Gaussian proxy model. Note that when using this proxy model, for the unknown design point x, first use GP l (.) Predict the low-fidelity index and then add it to the design parameters and input it to GP m (.) Predict the medium-fidelity index, and then perform the same operation to predict the final high-fidelity index.

[0040] The maximum expected hypervolume is used on the final high-fidelity proxy model to improve the sampling function to guide the next exploration and select the most promising new sampling point x * , the specific sampling function is:

[0041]

[0042] Step 4: Build and train the logistic regression function.

[0043] Utilize(Y arch ,Y netlist ) and (Y RTL ,Y netlist ) data to construct and train the logistic regression function for the three PPA indicators, where the logistic regression function is in the form of:

[0044]

[0045] in, Represents the absolute value of the difference between the mth index of any two points in the i-th fidelity architecture. If the size of the index of the two points in the current fidelity architecture is the same as that in the high fidelity, the value of the logistic regression is 1, otherwise the output is 0.

[0046] Step 5: After obtaining the new sampling design point, use the EDA simulation tool to perform architecture-level simulation to obtain low-fidelity indicator data, and determine whether it is necessary to enter the next fidelity based on partial order prediction.

[0047] The logic of partial order prediction is: using the trained logistic regression function Three PPA indicators that predict the current fidelity of the new sampling point Three PPA indicators with the current Pareto point Will there be a reversal at high fidelity? First, perform the lowest fidelity simulation, input the lowest fidelity value of the new sampling point and the value of the current Pareto point into the corresponding logistic regression model to determine whether the partial order relationship between the new sampling point and the current Pareto point will change at the current fidelity and the highest fidelity. If there is a change in the partial order relationship between the new sampling point and a current Pareto point, it is considered that the new sampling point cannot be reasonably evaluated at the current fidelity, and it is necessary to enter the next fidelity simulation and continue the above judgment after the simulation until the highest fidelity is reached or no partial order reversal occurs. If it is determined that the new sampling point is not dominated by the current Pareto point, it is considered that the sampling point is a new Pareto point, which is a potential design point and needs to enter the next fidelity, otherwise the fidelity selection is terminated. The detailed process code is as follows: Figure 3 shown.

[0048] Step 6: Iterate and optimize to obtain the Pareto optimal solution.

[0049] Update the sampled dataset based on the selected fidelity level to facilitate further surrogate model building, logistic regression function training, and analysis. Repeat steps 3-6 until the timeout is exhausted and the currently explored Pareto front set is obtained.

[0050] Example

[0051] This example uses the BOOM (Berkeley Out-of-Order Machine) microarchitecture as the experimental object. The goal is to explore its multi-objective optimal design configuration, including performance (number of cycles), power consumption, and area, under a limited simulation budget. Due to the limited overall simulation time budget, the architecture level, RTL level, and netlist level in the VLSI process are selected as the three fidelity levels for research. The specific EDA tool process is as follows: Figure 3 This embodiment includes 20 adjustable parameters, covering the value unit (Fetchwidth), execution unit (Issue / ALU type), register configuration, LSU size, cache size, etc.; 3,153 parameter combinations are selected as the design space for exploration, with a total of 4423 CPU simulation hours. The overall design space distribution is as follows Figure 4As shown. The simulation platform and tool chain include architecture-level evaluation, RTL-level evaluation and Netlist-level evaluation. The architecture-level evaluation uses Gem5 to obtain the number of cycles and McPAT to estimate the power consumption and area. The RTL-level evaluation generates Verilog based on Chipyard and uses Synopsys VCS and Cadence Joules to obtain the PPA of the RTL. The Netlist-level evaluation uses Cadence Genus for synthesis and outputs the final high-fidelity power consumption and area. The total simulation time in the optimization process is limited to 600 minutes. Therefore, the specific steps of the multi-fidelity microarchitecture design space optimization method based on partial order prediction are as follows:

[0052] (1) Initialization phase: 30 design points are randomly selected for architecture fidelity simulation, 15 points are selected for RTL fidelity simulation, and 2 points are selected for netlist fidelity simulation to construct an initial multi-fidelity data set.

[0053] (2) Training model: Train the multi-fidelity Gaussian process model and logistic regression prediction model based on the sampled data.

[0054] (3) Iterative optimization: The subsequent iterative process of Bayesian optimization is carried out. Each time, the EHVI acquisition function is used on the multi-fidelity Gaussian process model to select the new sampling point with the greatest potential and simulate the architecture layer. Then, the logistic regression model is used to predict whether the partial order relationship between the low-fidelity indicator and the current Pareto point of the point will be reversed at high fidelity, so as to determine whether it is necessary to enter the next fidelity simulation. After each determination, the newly sampled point and the corresponding multi-fidelity data are added to the data set to update the fusion multi-fidelity proxy model and the logistic regression prediction model.

[0055] (4) Results converge: The final Pareto solution set is obtained within the 600-minute budget.

[0056] (5) Method comparison: The present invention is compared with other multi-fidelity optimization methods on the BOOM and Rocket datasets. The following are the comparison results on the hypervolume and ADRS indicators.

[0057] TABLE II Comparisons against previous works.

[0058]

[0059] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-fidelity microarchitecture design space optimization method based on partial order prediction, characterized in that: The following steps are involved: Step 1: Select parameters that affect the target optimization PPA index from the microarchitecture parameters and build the SOC design space Step 2: Initialize the multi-fidelity dataset; Step 3: Build a nonlinear multi-fidelity Gaussian proxy model and use maximum expected hypervolume improvement on the final high-fidelity proxy model; Step 4: Build and train the logistic regression function; Step 5: After obtaining the new sampling design point, use EDA simulation tools to perform architecture-level simulation to obtain low-fidelity indicator data. Based on the partial order prediction, determine whether to enter the next fidelity level. Step 6: Iterate and optimize to obtain the Pareto optimal solution.

2. The multi-fidelity microarchitecture design space optimization method based on partial order prediction according to claim 1, characterized in that: In step 2, first, from the design space Randomly select design points from the dataset to form the initial low-fidelity data set X arch , use EDA simulation tools to perform architecture-level simulation and obtain low-fidelity indicator data set Y arch ; Then, from X arch Randomly select design points to form the initial medium-fidelity data set X RTL , use EDA simulation tools to perform RTL level simulation and obtain the medium fidelity index data set Y RTL ; Finally, from X RTL Randomly select design points from the dataset to form the initial high-fidelity data set X netlist , use EDA simulation tools to perform netlist level simulation and obtain high-fidelity index data set Y netlist ; and datasets of different fidelity always satisfy relationship.

3. The multi-fidelity microarchitecture design space optimization method based on partial order prediction according to claim 2, characterized in that: The specific content of step 3 is: first, using the low-fidelity dataset (X arch ,Y arch ) Train a low-fidelity Gaussian proxy model GP l (.); Then, use [(X RTL ,GP l (X RTL )),Y RTL ] Train a medium-fidelity Gaussian surrogate model GP that incorporates low-fidelity data m (.); Finally, use [(X netlist ,GP m (X netlist )),Y netlist ] Train a high-fidelity Gaussian surrogate model GP that combines low- and medium-fidelity data h (.), and use this as the final fusion Gaussian proxy model; the maximum expected hypervolume improved sampling function is used on the final high-fidelity proxy model to guide the next step of exploration and select the most promising new sampling point x * , the specific sampling function is:

4. The multi-fidelity microarchitecture design space optimization method based on partial order prediction according to claim 3, characterized in that: In the step 4, using (Y arch ,Y netlist ) and (Y RTL ,Y netlist ) data to construct and train the logistic regression function for the three PPA indicators, where the logistic regression function is in the form of: in, Represents the absolute value of the difference between the mth index of any two points in the i-th fidelity architecture. If the size of the index of the two points in the current fidelity architecture is the same as that in the high fidelity, the value of the logistic regression is 1, otherwise the output is 0.

5. The method for optimizing multi-fidelity microarchitecture design space based on partial order prediction according to claim 4, wherein: In step 5, the partial order prediction judgment logic is: using the trained logistic regression function Three PPA indicators that predict the current fidelity of the new sampling point Three PPA indicators with the current Pareto point Will the order relationship between the new sampling point and the current Pareto point change under the current fidelity and the highest fidelity? If the partial order relationship between the new sampling point and the current Pareto point changes, it is considered that the new sampling point cannot be reasonably evaluated at the current fidelity, and it is necessary to enter the next fidelity simulation and continue the above judgment after the simulation until the highest fidelity is reached or no partial order reversal occurs; If it is determined that the new sampling point is not dominated by the current Pareto point, then the sampling point is considered to be a new Pareto point, a potential design point, and needs to enter the next fidelity. Otherwise, the fidelity selection ends.

6. The multi-fidelity microarchitecture design space optimization method based on partial order prediction according to claim 5, characterized in that: In step 6, the sampling dataset is updated according to the selected fidelity level, and after each iteration, it is checked whether the current sampling and optimization process has exceeded the set time budget; If it does not exceed, return to step 3 and continue optimization; If the budget is exceeded, proceed to the next step; after completing sufficient optimization within the budget, the final Pareto optimal solution set is obtained.

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